MSP430ISelLowering.cpp revision b78e214274d397407b6167a293b7cd7c3b526dde 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430TargetMachine.h"
19#include "MSP430Subtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/ADT/VectorExtras.h"
36using namespace llvm;
37
38MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39  TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
40
41  // Set up the register classes.
42  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
43  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
44
45  // Compute derived properties from the register classes
46  computeRegisterProperties();
47
48  // Provide all sorts of operation actions
49
50  // Division is expensive
51  setIntDivIsCheap(false);
52
53  // Even if we have only 1 bit shift here, we can perform
54  // shifts of the whole bitwidth 1 bit per step.
55  setShiftAmountType(MVT::i8);
56
57  setStackPointerRegisterToSaveRestore(MSP430::SPW);
58  setBooleanContents(ZeroOrOneBooleanContent);
59  setSchedulingPreference(SchedulingForLatency);
60
61  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
62  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
65  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
66
67  // We don't have any truncstores
68  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
69
70  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
71  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
72  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
73  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
74  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
75  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
76  setOperationAction(ISD::RET,              MVT::Other, Custom);
77  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
78  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
79  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
80  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
81  setOperationAction(ISD::BR_CC,            MVT::Other, Expand);
82  setOperationAction(ISD::BRCOND,           MVT::Other, Custom);
83  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
84  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
85  setOperationAction(ISD::SELECT_CC,        MVT::Other, Expand);
86  setOperationAction(ISD::SELECT,           MVT::i8,    Custom);
87  setOperationAction(ISD::SELECT,           MVT::i16,   Custom);
88  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
89
90  // FIXME: Implement efficiently multiplication by a constant
91  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
92  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
93  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
94  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
95  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
96}
97
98SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
99  switch (Op.getOpcode()) {
100  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
101  case ISD::SHL: // FALLTHROUGH
102  case ISD::SRL:
103  case ISD::SRA:              return LowerShifts(Op, DAG);
104  case ISD::RET:              return LowerRET(Op, DAG);
105  case ISD::CALL:             return LowerCALL(Op, DAG);
106  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
107  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
108  case ISD::SETCC:            return LowerSETCC(Op, DAG);
109  case ISD::BRCOND:           return LowerBRCOND(Op, DAG);
110  case ISD::SELECT:           return LowerSELECT(Op, DAG);
111  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
112  default:
113    assert(0 && "unimplemented operand");
114    return SDValue();
115  }
116}
117
118//===----------------------------------------------------------------------===//
119//                      Calling Convention Implementation
120//===----------------------------------------------------------------------===//
121
122#include "MSP430GenCallingConv.inc"
123
124SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
125                                                    SelectionDAG &DAG) {
126  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
127  switch (CC) {
128  default:
129    assert(0 && "Unsupported calling convention");
130  case CallingConv::C:
131  case CallingConv::Fast:
132    return LowerCCCArguments(Op, DAG);
133  }
134}
135
136SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
137  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
138  unsigned CallingConv = TheCall->getCallingConv();
139  switch (CallingConv) {
140  default:
141    assert(0 && "Unsupported calling convention");
142  case CallingConv::Fast:
143  case CallingConv::C:
144    return LowerCCCCallTo(Op, DAG, CallingConv);
145  }
146}
147
148/// LowerCCCArguments - transform physical registers into virtual registers and
149/// generate load operations for arguments places on the stack.
150// FIXME: struct return stuff
151// FIXME: varargs
152SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
153                                                SelectionDAG &DAG) {
154  MachineFunction &MF = DAG.getMachineFunction();
155  MachineFrameInfo *MFI = MF.getFrameInfo();
156  MachineRegisterInfo &RegInfo = MF.getRegInfo();
157  SDValue Root = Op.getOperand(0);
158  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
159  unsigned CC = MF.getFunction()->getCallingConv();
160  DebugLoc dl = Op.getDebugLoc();
161
162  // Assign locations to all of the incoming arguments.
163  SmallVector<CCValAssign, 16> ArgLocs;
164  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
165  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
166
167  assert(!isVarArg && "Varargs not supported yet");
168
169  SmallVector<SDValue, 16> ArgValues;
170  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
171    CCValAssign &VA = ArgLocs[i];
172    if (VA.isRegLoc()) {
173      // Arguments passed in registers
174      MVT RegVT = VA.getLocVT();
175      switch (RegVT.getSimpleVT()) {
176      default:
177        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
178             << RegVT.getSimpleVT()
179             << "\n";
180        abort();
181      case MVT::i16:
182        unsigned VReg =
183          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
184        RegInfo.addLiveIn(VA.getLocReg(), VReg);
185        SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
186
187        // If this is an 8-bit value, it is really passed promoted to 16
188        // bits. Insert an assert[sz]ext to capture this, then truncate to the
189        // right size.
190        if (VA.getLocInfo() == CCValAssign::SExt)
191          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
192                                 DAG.getValueType(VA.getValVT()));
193        else if (VA.getLocInfo() == CCValAssign::ZExt)
194          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
195                                 DAG.getValueType(VA.getValVT()));
196
197        if (VA.getLocInfo() != CCValAssign::Full)
198          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
199
200        ArgValues.push_back(ArgValue);
201      }
202    } else {
203      // Sanity check
204      assert(VA.isMemLoc());
205      // Load the argument to a virtual register
206      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
207      if (ObjSize > 2) {
208        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
209             << VA.getLocVT().getSimpleVT()
210             << "\n";
211      }
212      // Create the frame index object for this incoming parameter...
213      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
214
215      // Create the SelectionDAG nodes corresponding to a load
216      //from this parameter
217      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
218      ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
219                                      PseudoSourceValue::getFixedStack(FI), 0));
220    }
221  }
222
223  ArgValues.push_back(Root);
224
225  // Return the new list of results.
226  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
227                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
228}
229
230SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
231  // CCValAssign - represent the assignment of the return value to a location
232  SmallVector<CCValAssign, 16> RVLocs;
233  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
234  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
235  DebugLoc dl = Op.getDebugLoc();
236
237  // CCState - Info about the registers and stack slot.
238  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
239
240  // Analize return values of ISD::RET
241  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
242
243  // If this is the first return lowered for this function, add the regs to the
244  // liveout set for the function.
245  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
246    for (unsigned i = 0; i != RVLocs.size(); ++i)
247      if (RVLocs[i].isRegLoc())
248        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
249  }
250
251  // The chain is always operand #0
252  SDValue Chain = Op.getOperand(0);
253  SDValue Flag;
254
255  // Copy the result values into the output registers.
256  for (unsigned i = 0; i != RVLocs.size(); ++i) {
257    CCValAssign &VA = RVLocs[i];
258    assert(VA.isRegLoc() && "Can only return in registers!");
259
260    // ISD::RET => ret chain, (regnum1,val1), ...
261    // So i*2+1 index only the regnums
262    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
263                             Op.getOperand(i*2+1), Flag);
264
265    // Guarantee that all emitted copies are stuck together,
266    // avoiding something bad.
267    Flag = Chain.getValue(1);
268  }
269
270  if (Flag.getNode())
271    return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
272
273  // Return Void
274  return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
275}
276
277/// LowerCCCCallTo - functions arguments are copied from virtual regs to
278/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
279/// TODO: sret.
280SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
281                                             unsigned CC) {
282  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
283  SDValue Chain  = TheCall->getChain();
284  SDValue Callee = TheCall->getCallee();
285  bool isVarArg  = TheCall->isVarArg();
286  DebugLoc dl = Op.getDebugLoc();
287
288  // Analyze operands of the call, assigning locations to each operand.
289  SmallVector<CCValAssign, 16> ArgLocs;
290  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
291
292  CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
293
294  // Get a count of how many bytes are to be pushed on the stack.
295  unsigned NumBytes = CCInfo.getNextStackOffset();
296
297  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
298                                                      getPointerTy(), true));
299
300  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
301  SmallVector<SDValue, 12> MemOpChains;
302  SDValue StackPtr;
303
304  // Walk the register/memloc assignments, inserting copies/loads.
305  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
306    CCValAssign &VA = ArgLocs[i];
307
308    // Arguments start after the 5 first operands of ISD::CALL
309    SDValue Arg = TheCall->getArg(i);
310
311    // Promote the value if needed.
312    switch (VA.getLocInfo()) {
313      default: assert(0 && "Unknown loc info!");
314      case CCValAssign::Full: break;
315      case CCValAssign::SExt:
316        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
317        break;
318      case CCValAssign::ZExt:
319        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
320        break;
321      case CCValAssign::AExt:
322        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
323        break;
324    }
325
326    // Arguments that can be passed on register must be kept at RegsToPass
327    // vector
328    if (VA.isRegLoc()) {
329      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
330    } else {
331      assert(VA.isMemLoc());
332
333      if (StackPtr.getNode() == 0)
334        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
335
336      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
337                                   StackPtr,
338                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
339
340
341      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
342                                         PseudoSourceValue::getStack(),
343                                         VA.getLocMemOffset()));
344    }
345  }
346
347  // Transform all store nodes into one single node because all store nodes are
348  // independent of each other.
349  if (!MemOpChains.empty())
350    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
351                        &MemOpChains[0], MemOpChains.size());
352
353  // Build a sequence of copy-to-reg nodes chained together with token chain and
354  // flag operands which copy the outgoing args into registers.  The InFlag in
355  // necessary since all emited instructions must be stuck together.
356  SDValue InFlag;
357  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
358    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
359                             RegsToPass[i].second, InFlag);
360    InFlag = Chain.getValue(1);
361  }
362
363  // If the callee is a GlobalAddress node (quite common, every direct call is)
364  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
365  // Likewise ExternalSymbol -> TargetExternalSymbol.
366  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
367    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
368  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
369    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
370
371  // Returns a chain & a flag for retval copy to use.
372  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
373  SmallVector<SDValue, 8> Ops;
374  Ops.push_back(Chain);
375  Ops.push_back(Callee);
376
377  // Add argument registers to the end of the list so that they are
378  // known live into the call.
379  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
380    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
381                                  RegsToPass[i].second.getValueType()));
382
383  if (InFlag.getNode())
384    Ops.push_back(InFlag);
385
386  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
387  InFlag = Chain.getValue(1);
388
389  // Create the CALLSEQ_END node.
390  Chain = DAG.getCALLSEQ_END(Chain,
391                             DAG.getConstant(NumBytes, getPointerTy(), true),
392                             DAG.getConstant(0, getPointerTy(), true),
393                             InFlag);
394  InFlag = Chain.getValue(1);
395
396  // Handle result values, copying them out of physregs into vregs that we
397  // return.
398  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
399                 Op.getResNo());
400}
401
402/// LowerCallResult - Lower the result values of an ISD::CALL into the
403/// appropriate copies out of appropriate physical registers.  This assumes that
404/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
405/// being lowered. Returns a SDNode with the same number of values as the
406/// ISD::CALL.
407SDNode*
408MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
409                                      CallSDNode *TheCall,
410                                      unsigned CallingConv,
411                                      SelectionDAG &DAG) {
412  bool isVarArg = TheCall->isVarArg();
413  DebugLoc dl = TheCall->getDebugLoc();
414
415  // Assign locations to each value returned by this call.
416  SmallVector<CCValAssign, 16> RVLocs;
417  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
418
419  CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
420  SmallVector<SDValue, 8> ResultVals;
421
422  // Copy all of the result registers out of their specified physreg.
423  for (unsigned i = 0; i != RVLocs.size(); ++i) {
424    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
425                               RVLocs[i].getValVT(), InFlag).getValue(1);
426    InFlag = Chain.getValue(2);
427    ResultVals.push_back(Chain.getValue(0));
428  }
429
430  ResultVals.push_back(Chain);
431
432  // Merge everything together with a MERGE_VALUES node.
433  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
434                     &ResultVals[0], ResultVals.size()).getNode();
435}
436
437SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
438                                          SelectionDAG &DAG) {
439  unsigned Opc = Op.getOpcode();
440  SDNode* N = Op.getNode();
441  MVT VT = Op.getValueType();
442  DebugLoc dl = N->getDebugLoc();
443
444  // We currently only lower shifts of constant argument.
445  if (!isa<ConstantSDNode>(N->getOperand(1)))
446    return SDValue();
447
448  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
449
450  // Expand the stuff into sequence of shifts.
451  // FIXME: for some shift amounts this might be done better!
452  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
453  SDValue Victim = N->getOperand(0);
454
455  if (Opc == ISD::SRL && ShiftAmount) {
456    // Emit a special goodness here:
457    // srl A, 1 => clrc; rrc A
458    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
459    ShiftAmount -= 1;
460  }
461
462  while (ShiftAmount--)
463    Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
464                         dl, VT, Victim);
465
466  return Victim;
467}
468
469SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
470  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
471  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
472
473  // Create the TargetGlobalAddress node, folding in the constant offset.
474  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
475  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
476                     getPointerTy(), Result);
477}
478
479SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
480                                                  SelectionDAG &DAG) {
481  DebugLoc dl = Op.getDebugLoc();
482  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
483  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
484
485  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
486}
487
488
489MVT MSP430TargetLowering::getSetCCResultType(MVT VT) const {
490  return MVT::i8;
491}
492
493SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
494  assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
495  SDValue LHS = Op.getOperand(0);
496  SDValue RHS = Op.getOperand(1);
497  DebugLoc dl = Op.getDebugLoc();
498  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
499
500  // FIXME: Handle bittests someday
501  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
502
503  // FIXME: Handle jump negative someday
504  unsigned TargetCC = 0;
505  switch (CC) {
506  default: assert(0 && "Invalid integer condition!");
507  case ISD::SETEQ:
508    TargetCC = MSP430::COND_E;  // aka COND_Z
509    break;
510  case ISD::SETNE:
511    TargetCC = MSP430::COND_NE; // aka COND_NZ
512    break;
513  case ISD::SETULE:
514    std::swap(LHS, RHS);        // FALLTHROUGH
515  case ISD::SETUGE:
516    TargetCC = MSP430::COND_HS; // aka COND_C
517    break;
518  case ISD::SETUGT:
519    std::swap(LHS, RHS);        // FALLTHROUGH
520  case ISD::SETULT:
521    TargetCC = MSP430::COND_LO; // aka COND_NC
522    break;
523  case ISD::SETLE:
524    std::swap(LHS, RHS);        // FALLTHROUGH
525  case ISD::SETGE:
526    TargetCC = MSP430::COND_GE;
527    break;
528  case ISD::SETGT:
529    std::swap(LHS, RHS);        // FALLTHROUGH
530  case ISD::SETLT:
531    TargetCC = MSP430::COND_L;
532    break;
533  }
534
535  SDValue Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16, LHS, RHS);
536  return DAG.getNode(MSP430ISD::SETCC, dl, MVT::i8,
537                     DAG.getConstant(TargetCC, MVT::i8), Cond);
538}
539
540SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
541  SDValue Chain = Op.getOperand(0);
542  SDValue Cond  = Op.getOperand(1);
543  SDValue Dest  = Op.getOperand(2);
544  DebugLoc dl = Op.getDebugLoc();
545  SDValue CC;
546
547  // Lower condition if not lowered yet
548  if (Cond.getOpcode() == ISD::SETCC)
549    Cond = LowerSETCC(Cond, DAG);
550
551  // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
552  // setting operand in place of the MSP430ISD::SETCC.
553  if (Cond.getOpcode() == MSP430ISD::SETCC) {
554    CC = Cond.getOperand(0);
555    Cond = Cond.getOperand(1);
556  } else
557    assert(0 && "Unimplemented condition!");
558
559  return DAG.getNode(MSP430ISD::BRCOND, dl, Op.getValueType(),
560                     Chain, Dest, CC, Cond);
561}
562
563SDValue MSP430TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
564  SDValue Cond   = Op.getOperand(0);
565  SDValue TrueV  = Op.getOperand(1);
566  SDValue FalseV = Op.getOperand(2);
567  DebugLoc dl    = Op.getDebugLoc();
568  SDValue CC;
569
570  // Lower condition if not lowered yet
571  if (Cond.getOpcode() == ISD::SETCC)
572    Cond = LowerSETCC(Cond, DAG);
573
574  // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
575  // setting operand in place of the MSP430ISD::SETCC.
576  if (Cond.getOpcode() == MSP430ISD::SETCC) {
577    CC = Cond.getOperand(0);
578    Cond = Cond.getOperand(1);
579    TrueV = Cond.getOperand(0);
580    FalseV = Cond.getOperand(1);
581  } else {
582    CC = DAG.getConstant(MSP430::COND_NE, MVT::i16);
583    Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16,
584                       Cond, DAG.getConstant(0, MVT::i16));
585  }
586
587  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
588  SmallVector<SDValue, 4> Ops;
589  Ops.push_back(TrueV);
590  Ops.push_back(FalseV);
591  Ops.push_back(CC);
592  Ops.push_back(Cond);
593
594  return DAG.getNode(MSP430ISD::SELECT, dl, VTs, &Ops[0], Ops.size());
595}
596
597SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
598                                               SelectionDAG &DAG) {
599  SDValue Val = Op.getOperand(0);
600  MVT VT      = Op.getValueType();
601  DebugLoc dl = Op.getDebugLoc();
602
603  assert(VT == MVT::i16 && "Only support i16 for now!");
604
605  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
606                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
607                     DAG.getValueType(Val.getValueType()));
608}
609
610const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
611  switch (Opcode) {
612  default: return NULL;
613  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
614  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
615  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
616  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
617  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
618  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
619  case MSP430ISD::BRCOND:             return "MSP430ISD::BRCOND";
620  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
621  case MSP430ISD::SETCC:              return "MSP430ISD::SETCC";
622  case MSP430ISD::SELECT:             return "MSP430ISD::SELECT";
623  }
624}
625
626//===----------------------------------------------------------------------===//
627//  Other Lowering Code
628//===----------------------------------------------------------------------===//
629
630MachineBasicBlock*
631MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
632                                                  MachineBasicBlock *BB) const {
633  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
634  DebugLoc dl = MI->getDebugLoc();
635  assert((MI->getOpcode() == MSP430::Select16) &&
636         "Unexpected instr type to insert");
637
638  // To "insert" a SELECT instruction, we actually have to insert the diamond
639  // control-flow pattern.  The incoming instruction knows the destination vreg
640  // to set, the condition code register to branch on, the true/false values to
641  // select between, and a branch opcode to use.
642  const BasicBlock *LLVM_BB = BB->getBasicBlock();
643  MachineFunction::iterator I = BB;
644  ++I;
645
646  //  thisMBB:
647  //  ...
648  //   TrueVal = ...
649  //   cmpTY ccX, r1, r2
650  //   jCC copy1MBB
651  //   fallthrough --> copy0MBB
652  MachineBasicBlock *thisMBB = BB;
653  MachineFunction *F = BB->getParent();
654  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
655  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
656  BuildMI(BB, dl, TII.get(MSP430::JCC))
657    .addMBB(copy1MBB)
658    .addImm(MI->getOperand(3).getImm());
659  F->insert(I, copy0MBB);
660  F->insert(I, copy1MBB);
661  // Update machine-CFG edges by transferring all successors of the current
662  // block to the new block which will contain the Phi node for the select.
663  copy1MBB->transferSuccessors(BB);
664  // Next, add the true and fallthrough blocks as its successors.
665  BB->addSuccessor(copy0MBB);
666  BB->addSuccessor(copy1MBB);
667
668  //  copy0MBB:
669  //   %FalseValue = ...
670  //   # fallthrough to copy1MBB
671  BB = copy0MBB;
672
673  // Update machine-CFG edges
674  BB->addSuccessor(copy1MBB);
675
676  //  copy1MBB:
677  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
678  //  ...
679  BB = copy1MBB;
680  BuildMI(BB, dl, TII.get(MSP430::PHI),
681          MI->getOperand(0).getReg())
682    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
683    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
684
685  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
686  return BB;
687}
688