MSP430ISelLowering.cpp revision bf8ef3f29de28529b5d65970af9015c41f7c809b 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430TargetMachine.h"
19#include "MSP430Subtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/ADT/VectorExtras.h"
36using namespace llvm;
37
38MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39  TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
40
41  // Set up the register classes.
42  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
43  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
44
45  // Compute derived properties from the register classes
46  computeRegisterProperties();
47
48  // Provide all sorts of operation actions
49
50  // Division is expensive
51  setIntDivIsCheap(false);
52
53  // Even if we have only 1 bit shift here, we can perform
54  // shifts of the whole bitwidth 1 bit per step.
55  setShiftAmountType(MVT::i8);
56
57  setStackPointerRegisterToSaveRestore(MSP430::SPW);
58  setBooleanContents(ZeroOrOneBooleanContent);
59  setSchedulingPreference(SchedulingForLatency);
60
61  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
62  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
65  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
66
67  // We don't have any truncstores
68  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
69
70  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
71  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
72  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
73  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
74  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
75  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
76  setOperationAction(ISD::RET,              MVT::Other, Custom);
77  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
78  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
79  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
80  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
81  setOperationAction(ISD::BR_CC,            MVT::Other, Expand);
82  setOperationAction(ISD::BRCOND,           MVT::Other, Custom);
83  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
84  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
85  setOperationAction(ISD::SELECT_CC,        MVT::Other, Expand);
86  setOperationAction(ISD::SELECT,           MVT::i8,    Custom);
87  setOperationAction(ISD::SELECT,           MVT::i16,   Custom);
88
89  // FIXME: Implement efficiently multiplication by a constant
90  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
91  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
92  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
93  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
94  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
95}
96
97SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
98  switch (Op.getOpcode()) {
99  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
100  case ISD::SHL: // FALLTHROUGH
101  case ISD::SRL:
102  case ISD::SRA:              return LowerShifts(Op, DAG);
103  case ISD::RET:              return LowerRET(Op, DAG);
104  case ISD::CALL:             return LowerCALL(Op, DAG);
105  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
106  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
107  case ISD::SETCC:            return LowerSETCC(Op, DAG);
108  case ISD::BRCOND:           return LowerBRCOND(Op, DAG);
109  case ISD::SELECT:           return LowerSELECT(Op, DAG);
110  default:
111    assert(0 && "unimplemented operand");
112    return SDValue();
113  }
114}
115
116//===----------------------------------------------------------------------===//
117//                      Calling Convention Implementation
118//===----------------------------------------------------------------------===//
119
120#include "MSP430GenCallingConv.inc"
121
122SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
123                                                    SelectionDAG &DAG) {
124  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
125  switch (CC) {
126  default:
127    assert(0 && "Unsupported calling convention");
128  case CallingConv::C:
129  case CallingConv::Fast:
130    return LowerCCCArguments(Op, DAG);
131  }
132}
133
134SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
135  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
136  unsigned CallingConv = TheCall->getCallingConv();
137  switch (CallingConv) {
138  default:
139    assert(0 && "Unsupported calling convention");
140  case CallingConv::Fast:
141  case CallingConv::C:
142    return LowerCCCCallTo(Op, DAG, CallingConv);
143  }
144}
145
146/// LowerCCCArguments - transform physical registers into virtual registers and
147/// generate load operations for arguments places on the stack.
148// FIXME: struct return stuff
149// FIXME: varargs
150SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
151                                                SelectionDAG &DAG) {
152  MachineFunction &MF = DAG.getMachineFunction();
153  MachineFrameInfo *MFI = MF.getFrameInfo();
154  MachineRegisterInfo &RegInfo = MF.getRegInfo();
155  SDValue Root = Op.getOperand(0);
156  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
157  unsigned CC = MF.getFunction()->getCallingConv();
158  DebugLoc dl = Op.getDebugLoc();
159
160  // Assign locations to all of the incoming arguments.
161  SmallVector<CCValAssign, 16> ArgLocs;
162  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
163  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
164
165  assert(!isVarArg && "Varargs not supported yet");
166
167  SmallVector<SDValue, 16> ArgValues;
168  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
169    CCValAssign &VA = ArgLocs[i];
170    if (VA.isRegLoc()) {
171      // Arguments passed in registers
172      MVT RegVT = VA.getLocVT();
173      switch (RegVT.getSimpleVT()) {
174      default:
175        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
176             << RegVT.getSimpleVT()
177             << "\n";
178        abort();
179      case MVT::i16:
180        unsigned VReg =
181          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
182        RegInfo.addLiveIn(VA.getLocReg(), VReg);
183        SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
184
185        // If this is an 8-bit value, it is really passed promoted to 16
186        // bits. Insert an assert[sz]ext to capture this, then truncate to the
187        // right size.
188        if (VA.getLocInfo() == CCValAssign::SExt)
189          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
190                                 DAG.getValueType(VA.getValVT()));
191        else if (VA.getLocInfo() == CCValAssign::ZExt)
192          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
193                                 DAG.getValueType(VA.getValVT()));
194
195        if (VA.getLocInfo() != CCValAssign::Full)
196          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
197
198        ArgValues.push_back(ArgValue);
199      }
200    } else {
201      // Sanity check
202      assert(VA.isMemLoc());
203      // Load the argument to a virtual register
204      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
205      if (ObjSize > 2) {
206        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
207             << VA.getLocVT().getSimpleVT()
208             << "\n";
209      }
210      // Create the frame index object for this incoming parameter...
211      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
212
213      // Create the SelectionDAG nodes corresponding to a load
214      //from this parameter
215      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
216      ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
217                                      PseudoSourceValue::getFixedStack(FI), 0));
218    }
219  }
220
221  ArgValues.push_back(Root);
222
223  // Return the new list of results.
224  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
225                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
226}
227
228SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
229  // CCValAssign - represent the assignment of the return value to a location
230  SmallVector<CCValAssign, 16> RVLocs;
231  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
232  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
233  DebugLoc dl = Op.getDebugLoc();
234
235  // CCState - Info about the registers and stack slot.
236  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
237
238  // Analize return values of ISD::RET
239  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
240
241  // If this is the first return lowered for this function, add the regs to the
242  // liveout set for the function.
243  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
244    for (unsigned i = 0; i != RVLocs.size(); ++i)
245      if (RVLocs[i].isRegLoc())
246        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
247  }
248
249  // The chain is always operand #0
250  SDValue Chain = Op.getOperand(0);
251  SDValue Flag;
252
253  // Copy the result values into the output registers.
254  for (unsigned i = 0; i != RVLocs.size(); ++i) {
255    CCValAssign &VA = RVLocs[i];
256    assert(VA.isRegLoc() && "Can only return in registers!");
257
258    // ISD::RET => ret chain, (regnum1,val1), ...
259    // So i*2+1 index only the regnums
260    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
261                             Op.getOperand(i*2+1), Flag);
262
263    // Guarantee that all emitted copies are stuck together,
264    // avoiding something bad.
265    Flag = Chain.getValue(1);
266  }
267
268  if (Flag.getNode())
269    return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
270
271  // Return Void
272  return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
273}
274
275/// LowerCCCCallTo - functions arguments are copied from virtual regs to
276/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
277/// TODO: sret.
278SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
279                                             unsigned CC) {
280  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
281  SDValue Chain  = TheCall->getChain();
282  SDValue Callee = TheCall->getCallee();
283  bool isVarArg  = TheCall->isVarArg();
284  DebugLoc dl = Op.getDebugLoc();
285
286  // Analyze operands of the call, assigning locations to each operand.
287  SmallVector<CCValAssign, 16> ArgLocs;
288  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
289
290  CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
291
292  // Get a count of how many bytes are to be pushed on the stack.
293  unsigned NumBytes = CCInfo.getNextStackOffset();
294
295  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
296                                                      getPointerTy(), true));
297
298  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
299  SmallVector<SDValue, 12> MemOpChains;
300  SDValue StackPtr;
301
302  // Walk the register/memloc assignments, inserting copies/loads.
303  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
304    CCValAssign &VA = ArgLocs[i];
305
306    // Arguments start after the 5 first operands of ISD::CALL
307    SDValue Arg = TheCall->getArg(i);
308
309    // Promote the value if needed.
310    switch (VA.getLocInfo()) {
311      default: assert(0 && "Unknown loc info!");
312      case CCValAssign::Full: break;
313      case CCValAssign::SExt:
314        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
315        break;
316      case CCValAssign::ZExt:
317        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
318        break;
319      case CCValAssign::AExt:
320        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
321        break;
322    }
323
324    // Arguments that can be passed on register must be kept at RegsToPass
325    // vector
326    if (VA.isRegLoc()) {
327      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
328    } else {
329      assert(VA.isMemLoc());
330
331      if (StackPtr.getNode() == 0)
332        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
333
334      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
335                                   StackPtr,
336                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
337
338
339      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
340                                         PseudoSourceValue::getStack(),
341                                         VA.getLocMemOffset()));
342    }
343  }
344
345  // Transform all store nodes into one single node because all store nodes are
346  // independent of each other.
347  if (!MemOpChains.empty())
348    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
349                        &MemOpChains[0], MemOpChains.size());
350
351  // Build a sequence of copy-to-reg nodes chained together with token chain and
352  // flag operands which copy the outgoing args into registers.  The InFlag in
353  // necessary since all emited instructions must be stuck together.
354  SDValue InFlag;
355  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
356    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
357                             RegsToPass[i].second, InFlag);
358    InFlag = Chain.getValue(1);
359  }
360
361  // If the callee is a GlobalAddress node (quite common, every direct call is)
362  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
363  // Likewise ExternalSymbol -> TargetExternalSymbol.
364  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
365    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
366  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
367    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
368
369  // Returns a chain & a flag for retval copy to use.
370  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
371  SmallVector<SDValue, 8> Ops;
372  Ops.push_back(Chain);
373  Ops.push_back(Callee);
374
375  // Add argument registers to the end of the list so that they are
376  // known live into the call.
377  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
378    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
379                                  RegsToPass[i].second.getValueType()));
380
381  if (InFlag.getNode())
382    Ops.push_back(InFlag);
383
384  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
385  InFlag = Chain.getValue(1);
386
387  // Create the CALLSEQ_END node.
388  Chain = DAG.getCALLSEQ_END(Chain,
389                             DAG.getConstant(NumBytes, getPointerTy(), true),
390                             DAG.getConstant(0, getPointerTy(), true),
391                             InFlag);
392  InFlag = Chain.getValue(1);
393
394  // Handle result values, copying them out of physregs into vregs that we
395  // return.
396  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
397                 Op.getResNo());
398}
399
400/// LowerCallResult - Lower the result values of an ISD::CALL into the
401/// appropriate copies out of appropriate physical registers.  This assumes that
402/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
403/// being lowered. Returns a SDNode with the same number of values as the
404/// ISD::CALL.
405SDNode*
406MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
407                                      CallSDNode *TheCall,
408                                      unsigned CallingConv,
409                                      SelectionDAG &DAG) {
410  bool isVarArg = TheCall->isVarArg();
411  DebugLoc dl = TheCall->getDebugLoc();
412
413  // Assign locations to each value returned by this call.
414  SmallVector<CCValAssign, 16> RVLocs;
415  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
416
417  CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
418  SmallVector<SDValue, 8> ResultVals;
419
420  // Copy all of the result registers out of their specified physreg.
421  for (unsigned i = 0; i != RVLocs.size(); ++i) {
422    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
423                               RVLocs[i].getValVT(), InFlag).getValue(1);
424    InFlag = Chain.getValue(2);
425    ResultVals.push_back(Chain.getValue(0));
426  }
427
428  ResultVals.push_back(Chain);
429
430  // Merge everything together with a MERGE_VALUES node.
431  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
432                     &ResultVals[0], ResultVals.size()).getNode();
433}
434
435SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
436                                          SelectionDAG &DAG) {
437  unsigned Opc = Op.getOpcode();
438  SDNode* N = Op.getNode();
439  MVT VT = Op.getValueType();
440  DebugLoc dl = N->getDebugLoc();
441
442  // We currently only lower shifts of constant argument.
443  if (!isa<ConstantSDNode>(N->getOperand(1)))
444    return SDValue();
445
446  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
447
448  // Expand the stuff into sequence of shifts.
449  // FIXME: for some shift amounts this might be done better!
450  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
451  SDValue Victim = N->getOperand(0);
452
453  if (Opc == ISD::SRL && ShiftAmount) {
454    // Emit a special goodness here:
455    // srl A, 1 => clrc; rrc A
456    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
457    ShiftAmount -= 1;
458  }
459
460  while (ShiftAmount--)
461    Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
462                         dl, VT, Victim);
463
464  return Victim;
465}
466
467SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
468  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
469  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
470
471  // Create the TargetGlobalAddress node, folding in the constant offset.
472  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
473  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
474                     getPointerTy(), Result);
475}
476
477SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
478                                                  SelectionDAG &DAG) {
479  DebugLoc dl = Op.getDebugLoc();
480  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
481  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
482
483  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
484}
485
486
487MVT MSP430TargetLowering::getSetCCResultType(MVT VT) const {
488  return MVT::i8;
489}
490
491SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
492  assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
493  SDValue LHS = Op.getOperand(0);
494  SDValue RHS = Op.getOperand(1);
495  DebugLoc dl = Op.getDebugLoc();
496  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
497
498  // FIXME: Handle bittests someday
499  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
500
501  // FIXME: Handle jump negative someday
502  unsigned TargetCC = 0;
503  switch (CC) {
504  default: assert(0 && "Invalid integer condition!");
505  case ISD::SETEQ:
506    TargetCC = MSP430::COND_E;  // aka COND_Z
507    break;
508  case ISD::SETNE:
509    TargetCC = MSP430::COND_NE; // aka COND_NZ
510    break;
511  case ISD::SETULE:
512    std::swap(LHS, RHS);        // FALLTHROUGH
513  case ISD::SETUGE:
514    TargetCC = MSP430::COND_HS; // aka COND_C
515    break;
516  case ISD::SETUGT:
517    std::swap(LHS, RHS);        // FALLTHROUGH
518  case ISD::SETULT:
519    TargetCC = MSP430::COND_LO; // aka COND_NC
520    break;
521  case ISD::SETLE:
522    std::swap(LHS, RHS);        // FALLTHROUGH
523  case ISD::SETGE:
524    TargetCC = MSP430::COND_GE;
525    break;
526  case ISD::SETGT:
527    std::swap(LHS, RHS);        // FALLTHROUGH
528  case ISD::SETLT:
529    TargetCC = MSP430::COND_L;
530    break;
531  }
532
533  SDValue Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16, LHS, RHS);
534  return DAG.getNode(MSP430ISD::SETCC, dl, MVT::i8,
535                     DAG.getConstant(TargetCC, MVT::i8), Cond);
536}
537
538SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
539  SDValue Chain = Op.getOperand(0);
540  SDValue Cond  = Op.getOperand(1);
541  SDValue Dest  = Op.getOperand(2);
542  DebugLoc dl = Op.getDebugLoc();
543  SDValue CC;
544
545  // Lower condition if not lowered yet
546  if (Cond.getOpcode() == ISD::SETCC)
547    Cond = LowerSETCC(Cond, DAG);
548
549  // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
550  // setting operand in place of the MSP430ISD::SETCC.
551  if (Cond.getOpcode() == MSP430ISD::SETCC) {
552    CC = Cond.getOperand(0);
553    Cond = Cond.getOperand(1);
554  } else
555    assert(0 && "Unimplemented condition!");
556
557  return DAG.getNode(MSP430ISD::BRCOND, dl, Op.getValueType(),
558                     Chain, Dest, CC, Cond);
559}
560
561SDValue MSP430TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
562  SDValue Cond   = Op.getOperand(0);
563  SDValue TrueV  = Op.getOperand(1);
564  SDValue FalseV = Op.getOperand(2);
565  DebugLoc dl    = Op.getDebugLoc();
566  SDValue CC;
567
568  // Lower condition if not lowered yet
569  if (Cond.getOpcode() == ISD::SETCC)
570    Cond = LowerSETCC(Cond, DAG);
571
572  // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
573  // setting operand in place of the MSP430ISD::SETCC.
574  if (Cond.getOpcode() == MSP430ISD::SETCC) {
575    CC = Cond.getOperand(0);
576    Cond = Cond.getOperand(1);
577    TrueV = Cond.getOperand(0);
578    FalseV = Cond.getOperand(1);
579  } else {
580    CC = DAG.getConstant(MSP430::COND_NE, MVT::i16);
581    Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16,
582                       Cond, DAG.getConstant(0, MVT::i16));
583  }
584
585  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
586  SmallVector<SDValue, 4> Ops;
587  Ops.push_back(TrueV);
588  Ops.push_back(FalseV);
589  Ops.push_back(CC);
590  Ops.push_back(Cond);
591
592  return DAG.getNode(MSP430ISD::SELECT, dl, VTs, &Ops[0], Ops.size());
593}
594
595const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
596  switch (Opcode) {
597  default: return NULL;
598  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
599  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
600  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
601  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
602  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
603  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
604  case MSP430ISD::BRCOND:             return "MSP430ISD::BRCOND";
605  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
606  case MSP430ISD::SETCC:              return "MSP430ISD::SETCC";
607  case MSP430ISD::SELECT:             return "MSP430ISD::SELECT";
608  }
609}
610
611//===----------------------------------------------------------------------===//
612//  Other Lowering Code
613//===----------------------------------------------------------------------===//
614
615MachineBasicBlock*
616MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
617                                                  MachineBasicBlock *BB) const {
618  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
619  DebugLoc dl = MI->getDebugLoc();
620  assert((MI->getOpcode() == MSP430::Select16) &&
621         "Unexpected instr type to insert");
622
623  // To "insert" a SELECT instruction, we actually have to insert the diamond
624  // control-flow pattern.  The incoming instruction knows the destination vreg
625  // to set, the condition code register to branch on, the true/false values to
626  // select between, and a branch opcode to use.
627  const BasicBlock *LLVM_BB = BB->getBasicBlock();
628  MachineFunction::iterator I = BB;
629  ++I;
630
631  //  thisMBB:
632  //  ...
633  //   TrueVal = ...
634  //   cmpTY ccX, r1, r2
635  //   jCC copy1MBB
636  //   fallthrough --> copy0MBB
637  MachineBasicBlock *thisMBB = BB;
638  MachineFunction *F = BB->getParent();
639  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
640  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
641  BuildMI(BB, dl, TII.get(MSP430::JCC))
642    .addMBB(copy1MBB)
643    .addImm(MI->getOperand(3).getImm());
644  F->insert(I, copy0MBB);
645  F->insert(I, copy1MBB);
646  // Update machine-CFG edges by transferring all successors of the current
647  // block to the new block which will contain the Phi node for the select.
648  copy1MBB->transferSuccessors(BB);
649  // Next, add the true and fallthrough blocks as its successors.
650  BB->addSuccessor(copy0MBB);
651  BB->addSuccessor(copy1MBB);
652
653  //  copy0MBB:
654  //   %FalseValue = ...
655  //   # fallthrough to copy1MBB
656  BB = copy0MBB;
657
658  // Update machine-CFG edges
659  BB->addSuccessor(copy1MBB);
660
661  //  copy1MBB:
662  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
663  //  ...
664  BB = copy1MBB;
665  BuildMI(BB, dl, TII.get(MSP430::PHI),
666          MI->getOperand(0).getReg())
667    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
668    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
669
670  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
671  return BB;
672}
673