MSP430ISelLowering.cpp revision dcb802cf7be8e540e487c699f25d89c4821536ab 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430TargetMachine.h"
19#include "MSP430Subtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/ADT/VectorExtras.h"
36using namespace llvm;
37
38MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39  TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
40
41  // Set up the register classes.
42  addRegisterClass(MVT::i16, MSP430::MSP430RegsRegisterClass);
43
44  // Compute derived properties from the register classes
45  computeRegisterProperties();
46
47  setOperationAction(ISD::RET, MVT::Other, Custom);
48}
49
50SDValue MSP430TargetLowering::
51LowerOperation(SDValue Op, SelectionDAG &DAG) {
52  switch (Op.getOpcode()) {
53  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
54  case ISD::RET: return LowerRET(Op, DAG);
55  default:
56    assert(0 && "unimplemented operand");
57    return SDValue();
58  }
59}
60
61//===----------------------------------------------------------------------===//
62//                      Calling Convention Implementation
63//===----------------------------------------------------------------------===//
64
65#include "MSP430GenCallingConv.inc"
66
67SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
68                                                    SelectionDAG &DAG) {
69  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
70  switch (CC) {
71  default:
72    assert(0 && "Unsupported calling convention");
73  case CallingConv::C:
74  case CallingConv::Fast:
75    return LowerCCCArguments(Op, DAG);
76  }
77}
78
79/// LowerCCCArguments - transform physical registers into virtual registers and
80/// generate load operations for arguments places on the stack.
81// FIXME: struct return stuff
82// FIXME: varargs
83SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
84                                                SelectionDAG &DAG) {
85  MachineFunction &MF = DAG.getMachineFunction();
86  MachineFrameInfo *MFI = MF.getFrameInfo();
87  MachineRegisterInfo &RegInfo = MF.getRegInfo();
88  SDValue Root = Op.getOperand(0);
89  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
90  unsigned CC = MF.getFunction()->getCallingConv();
91  DebugLoc dl = Op.getDebugLoc();
92
93  // Assign locations to all of the incoming arguments.
94  SmallVector<CCValAssign, 16> ArgLocs;
95  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
96  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
97
98  assert(!isVarArg && "Varargs not supported yet");
99
100  SmallVector<SDValue, 16> ArgValues;
101  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
102    CCValAssign &VA = ArgLocs[i];
103    if (VA.isRegLoc()) {
104      // Arguments passed in registers
105      MVT RegVT = VA.getLocVT();
106      switch (RegVT.getSimpleVT()) {
107      default:
108        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
109             << RegVT.getSimpleVT()
110             << "\n";
111        abort();
112      case MVT::i16:
113        unsigned VReg =
114          RegInfo.createVirtualRegister(MSP430::MSP430RegsRegisterClass);
115        RegInfo.addLiveIn(VA.getLocReg(), VReg);
116        SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
117
118        // If this is an 8-bit value, it is really passed promoted to 16
119        // bits. Insert an assert[sz]ext to capture this, then truncate to the
120        // right size.
121        if (VA.getLocInfo() == CCValAssign::SExt)
122          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
123                                 DAG.getValueType(VA.getValVT()));
124        else if (VA.getLocInfo() == CCValAssign::ZExt)
125          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
126                                 DAG.getValueType(VA.getValVT()));
127
128        if (VA.getLocInfo() != CCValAssign::Full)
129          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
130
131        ArgValues.push_back(ArgValue);
132      }
133    } else {
134      // Sanity check
135      assert(VA.isMemLoc());
136      // Load the argument to a virtual register
137      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
138      if (ObjSize > 2) {
139        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
140             << VA.getLocVT().getSimpleVT()
141             << "\n";
142      }
143      // Create the frame index object for this incoming parameter...
144      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
145
146      // Create the SelectionDAG nodes corresponding to a load
147      //from this parameter
148      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
149      ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
150                                      PseudoSourceValue::getFixedStack(FI), 0));
151    }
152  }
153
154  ArgValues.push_back(Root);
155
156  // Return the new list of results.
157  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
158                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
159}
160
161SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
162  // CCValAssign - represent the assignment of the return value to a location
163  SmallVector<CCValAssign, 16> RVLocs;
164  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
165  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
166  DebugLoc dl = Op.getDebugLoc();
167
168  // CCState - Info about the registers and stack slot.
169  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
170
171  // Analize return values of ISD::RET
172  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
173
174  // If this is the first return lowered for this function, add the regs to the
175  // liveout set for the function.
176  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
177    for (unsigned i = 0; i != RVLocs.size(); ++i)
178      if (RVLocs[i].isRegLoc())
179        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
180  }
181
182  // The chain is always operand #0
183  SDValue Chain = Op.getOperand(0);
184  SDValue Flag;
185
186  // Copy the result values into the output registers.
187  for (unsigned i = 0; i != RVLocs.size(); ++i) {
188    CCValAssign &VA = RVLocs[i];
189    assert(VA.isRegLoc() && "Can only return in registers!");
190
191    // ISD::RET => ret chain, (regnum1,val1), ...
192    // So i*2+1 index only the regnums
193    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
194                             Op.getOperand(i*2+1), Flag);
195
196    // Guarantee that all emitted copies are stuck together,
197    // avoiding something bad.
198    Flag = Chain.getValue(1);
199  }
200
201  if (Flag.getNode())
202    return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
203
204  // Return Void
205  return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
206}
207
208const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
209  switch (Opcode) {
210  default: return NULL;
211  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
212  }
213}
214
215