PPCInstrInfo.cpp revision 4406604047423576e36657c7ede266ca42e79642 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33/// getPointerRegClass - Return the register class to use to hold pointers.
34/// This is used for addressing modes.
35const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
36  if (TM.getSubtargetImpl()->isPPC64())
37    return &PPC::G8RCRegClass;
38  else
39    return &PPC::GPRCRegClass;
40}
41
42
43bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
44                               unsigned& sourceReg,
45                               unsigned& destReg) const {
46  unsigned oc = MI.getOpcode();
47  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
49    assert(MI.getNumOperands() >= 3 &&
50           MI.getOperand(0).isRegister() &&
51           MI.getOperand(1).isRegister() &&
52           MI.getOperand(2).isRegister() &&
53           "invalid PPC OR instruction!");
54    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55      sourceReg = MI.getOperand(1).getReg();
56      destReg = MI.getOperand(0).getReg();
57      return true;
58    }
59  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
60    assert(MI.getNumOperands() >= 3 &&
61           MI.getOperand(0).isRegister() &&
62           MI.getOperand(2).isImmediate() &&
63           "invalid PPC ADDI instruction!");
64    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
65      sourceReg = MI.getOperand(1).getReg();
66      destReg = MI.getOperand(0).getReg();
67      return true;
68    }
69  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
70    assert(MI.getNumOperands() >= 3 &&
71           MI.getOperand(0).isRegister() &&
72           MI.getOperand(1).isRegister() &&
73           MI.getOperand(2).isImmediate() &&
74           "invalid PPC ORI instruction!");
75    if (MI.getOperand(2).getImm() == 0) {
76      sourceReg = MI.getOperand(1).getReg();
77      destReg = MI.getOperand(0).getReg();
78      return true;
79    }
80  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
81             oc == PPC::FMRSD) {      // fmr r1, r2
82    assert(MI.getNumOperands() >= 2 &&
83           MI.getOperand(0).isRegister() &&
84           MI.getOperand(1).isRegister() &&
85           "invalid PPC FMR instruction");
86    sourceReg = MI.getOperand(1).getReg();
87    destReg = MI.getOperand(0).getReg();
88    return true;
89  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
90    assert(MI.getNumOperands() >= 2 &&
91           MI.getOperand(0).isRegister() &&
92           MI.getOperand(1).isRegister() &&
93           "invalid PPC MCRF instruction");
94    sourceReg = MI.getOperand(1).getReg();
95    destReg = MI.getOperand(0).getReg();
96    return true;
97  }
98  return false;
99}
100
101unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
102                                           int &FrameIndex) const {
103  switch (MI->getOpcode()) {
104  default: break;
105  case PPC::LD:
106  case PPC::LWZ:
107  case PPC::LFS:
108  case PPC::LFD:
109    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
110        MI->getOperand(2).isFI()) {
111      FrameIndex = MI->getOperand(2).getIndex();
112      return MI->getOperand(0).getReg();
113    }
114    break;
115  }
116  return 0;
117}
118
119unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
120                                          int &FrameIndex) const {
121  switch (MI->getOpcode()) {
122  default: break;
123  case PPC::STD:
124  case PPC::STW:
125  case PPC::STFS:
126  case PPC::STFD:
127    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
128        MI->getOperand(2).isFI()) {
129      FrameIndex = MI->getOperand(2).getIndex();
130      return MI->getOperand(0).getReg();
131    }
132    break;
133  }
134  return 0;
135}
136
137// commuteInstruction - We can commute rlwimi instructions, but only if the
138// rotate amt is zero.  We also have to munge the immediates a bit.
139MachineInstr *
140PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
141  // Normal instructions can be commuted the obvious way.
142  if (MI->getOpcode() != PPC::RLWIMI)
143    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
144
145  // Cannot commute if it has a non-zero rotate count.
146  if (MI->getOperand(3).getImm() != 0)
147    return 0;
148
149  // If we have a zero rotate count, we have:
150  //   M = mask(MB,ME)
151  //   Op0 = (Op1 & ~M) | (Op2 & M)
152  // Change this to:
153  //   M = mask((ME+1)&31, (MB-1)&31)
154  //   Op0 = (Op2 & ~M) | (Op1 & M)
155
156  // Swap op1/op2
157  unsigned Reg0 = MI->getOperand(0).getReg();
158  unsigned Reg1 = MI->getOperand(1).getReg();
159  unsigned Reg2 = MI->getOperand(2).getReg();
160  bool Reg1IsKill = MI->getOperand(1).isKill();
161  bool Reg2IsKill = MI->getOperand(2).isKill();
162  bool ChangeReg0 = false;
163  // If machine instrs are no longer in two-address forms, update
164  // destination register as well.
165  if (Reg0 == Reg1) {
166    // Must be two address instruction!
167    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
168           "Expecting a two-address instruction!");
169    Reg2IsKill = false;
170    ChangeReg0 = true;
171  }
172
173  // Masks.
174  unsigned MB = MI->getOperand(4).getImm();
175  unsigned ME = MI->getOperand(5).getImm();
176
177  if (NewMI) {
178    // Create a new instruction.
179    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
180    bool Reg0IsDead = MI->getOperand(0).isDead();
181    return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
182      .addReg(Reg2, false, false, Reg2IsKill)
183      .addReg(Reg1, false, false, Reg1IsKill)
184      .addImm((ME+1) & 31)
185      .addImm((MB-1) & 31);
186  }
187
188  if (ChangeReg0)
189    MI->getOperand(0).setReg(Reg2);
190  MI->getOperand(2).setReg(Reg1);
191  MI->getOperand(1).setReg(Reg2);
192  MI->getOperand(2).setIsKill(Reg1IsKill);
193  MI->getOperand(1).setIsKill(Reg2IsKill);
194
195  // Swap the mask around.
196  MI->getOperand(4).setImm((ME+1) & 31);
197  MI->getOperand(5).setImm((MB-1) & 31);
198  return MI;
199}
200
201void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
202                              MachineBasicBlock::iterator MI) const {
203  BuildMI(MBB, MI, get(PPC::NOP));
204}
205
206
207// Branch analysis.
208bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209                                 MachineBasicBlock *&FBB,
210                                 std::vector<MachineOperand> &Cond) const {
211  // If the block has no terminators, it just falls into the block after it.
212  MachineBasicBlock::iterator I = MBB.end();
213  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
214    return false;
215
216  // Get the last instruction in the block.
217  MachineInstr *LastInst = I;
218
219  // If there is only one terminator instruction, process it.
220  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
221    if (LastInst->getOpcode() == PPC::B) {
222      TBB = LastInst->getOperand(0).getMBB();
223      return false;
224    } else if (LastInst->getOpcode() == PPC::BCC) {
225      // Block ends with fall-through condbranch.
226      TBB = LastInst->getOperand(2).getMBB();
227      Cond.push_back(LastInst->getOperand(0));
228      Cond.push_back(LastInst->getOperand(1));
229      return false;
230    }
231    // Otherwise, don't know what this is.
232    return true;
233  }
234
235  // Get the instruction before it if it's a terminator.
236  MachineInstr *SecondLastInst = I;
237
238  // If there are three terminators, we don't know what sort of block this is.
239  if (SecondLastInst && I != MBB.begin() &&
240      isUnpredicatedTerminator(--I))
241    return true;
242
243  // If the block ends with PPC::B and PPC:BCC, handle it.
244  if (SecondLastInst->getOpcode() == PPC::BCC &&
245      LastInst->getOpcode() == PPC::B) {
246    TBB =  SecondLastInst->getOperand(2).getMBB();
247    Cond.push_back(SecondLastInst->getOperand(0));
248    Cond.push_back(SecondLastInst->getOperand(1));
249    FBB = LastInst->getOperand(0).getMBB();
250    return false;
251  }
252
253  // If the block ends with two PPC:Bs, handle it.  The second one is not
254  // executed, so remove it.
255  if (SecondLastInst->getOpcode() == PPC::B &&
256      LastInst->getOpcode() == PPC::B) {
257    TBB = SecondLastInst->getOperand(0).getMBB();
258    I = LastInst;
259    I->eraseFromParent();
260    return false;
261  }
262
263  // Otherwise, can't handle this.
264  return true;
265}
266
267unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
268  MachineBasicBlock::iterator I = MBB.end();
269  if (I == MBB.begin()) return 0;
270  --I;
271  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
272    return 0;
273
274  // Remove the branch.
275  I->eraseFromParent();
276
277  I = MBB.end();
278
279  if (I == MBB.begin()) return 1;
280  --I;
281  if (I->getOpcode() != PPC::BCC)
282    return 1;
283
284  // Remove the branch.
285  I->eraseFromParent();
286  return 2;
287}
288
289unsigned
290PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
291                           MachineBasicBlock *FBB,
292                           const std::vector<MachineOperand> &Cond) const {
293  // Shouldn't be a fall through.
294  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
295  assert((Cond.size() == 2 || Cond.size() == 0) &&
296         "PPC branch conditions have two components!");
297
298  // One-way branch.
299  if (FBB == 0) {
300    if (Cond.empty())   // Unconditional branch
301      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
302    else                // Conditional branch
303      BuildMI(&MBB, get(PPC::BCC))
304        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
305    return 1;
306  }
307
308  // Two-way Conditional Branch.
309  BuildMI(&MBB, get(PPC::BCC))
310    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
311  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
312  return 2;
313}
314
315void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
316                                   MachineBasicBlock::iterator MI,
317                                   unsigned DestReg, unsigned SrcReg,
318                                   const TargetRegisterClass *DestRC,
319                                   const TargetRegisterClass *SrcRC) const {
320  if (DestRC != SrcRC) {
321    cerr << "Not yet supported!";
322    abort();
323  }
324
325  if (DestRC == PPC::GPRCRegisterClass) {
326    BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
327  } else if (DestRC == PPC::G8RCRegisterClass) {
328    BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
329  } else if (DestRC == PPC::F4RCRegisterClass) {
330    BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
331  } else if (DestRC == PPC::F8RCRegisterClass) {
332    BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
333  } else if (DestRC == PPC::CRRCRegisterClass) {
334    BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
335  } else if (DestRC == PPC::VRRCRegisterClass) {
336    BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
337  } else if (DestRC == PPC::CRBITRCRegisterClass) {
338    BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
339  } else {
340    cerr << "Attempt to copy register that is not GPR or FPR";
341    abort();
342  }
343}
344
345bool
346PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill,
347                                  int FrameIdx,
348                                  const TargetRegisterClass *RC,
349                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
350  if (RC == PPC::GPRCRegisterClass) {
351    if (SrcReg != PPC::LR) {
352      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
353                                         .addReg(SrcReg, false, false, isKill),
354                                         FrameIdx));
355    } else {
356      // FIXME: this spills LR immediately to memory in one step.  To do this,
357      // we use R11, which we know cannot be used in the prolog/epilog.  This is
358      // a hack.
359      NewMIs.push_back(BuildMI(get(PPC::MFLR), PPC::R11));
360      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
361                                         .addReg(PPC::R11, false, false, isKill),
362                                         FrameIdx));
363    }
364  } else if (RC == PPC::G8RCRegisterClass) {
365    if (SrcReg != PPC::LR8) {
366      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
367                              .addReg(SrcReg, false, false, isKill), FrameIdx));
368    } else {
369      // FIXME: this spills LR immediately to memory in one step.  To do this,
370      // we use R11, which we know cannot be used in the prolog/epilog.  This is
371      // a hack.
372      NewMIs.push_back(BuildMI(get(PPC::MFLR8), PPC::X11));
373      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
374                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
375    }
376  } else if (RC == PPC::F8RCRegisterClass) {
377    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFD))
378                              .addReg(SrcReg, false, false, isKill), FrameIdx));
379  } else if (RC == PPC::F4RCRegisterClass) {
380    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFS))
381                              .addReg(SrcReg, false, false, isKill), FrameIdx));
382  } else if (RC == PPC::CRRCRegisterClass) {
383    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
384        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
385      // FIXME (64-bit): Enable
386      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR))
387                                         .addReg(SrcReg, false, false, isKill),
388                                         FrameIdx));
389      return true;
390    } else {
391      // FIXME: We use R0 here, because it isn't available for RA.  We need to
392      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
393      // to save all of the CRBits.
394      NewMIs.push_back(BuildMI(get(PPC::MFCR), PPC::R0));
395
396      // If the saved register wasn't CR0, shift the bits left so that they are
397      // in CR0's slot.
398      if (SrcReg != PPC::CR0) {
399        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
400        // rlwinm r0, r0, ShiftBits, 0, 31.
401        NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
402                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
403      }
404
405      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
406                                         .addReg(PPC::R0, false, false, isKill),
407                                         FrameIdx));
408    }
409  } else if (RC == PPC::CRBITRCRegisterClass) {
410    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
411    // backend currently only uses CR1EQ as an individual bit, this should
412    // not cause any bug. If we need other uses of CR bits, the following
413    // code may be invalid.
414    unsigned Reg = 0;
415    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
416      Reg = PPC::CR0;
417    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
418      Reg = PPC::CR1;
419    else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
420      Reg = PPC::CR2;
421    else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
422      Reg = PPC::CR3;
423    else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
424      Reg = PPC::CR4;
425    else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
426      Reg = PPC::CR5;
427    else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
428      Reg = PPC::CR6;
429    else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
430      Reg = PPC::CR7;
431
432    return StoreRegToStackSlot(Reg, isKill, FrameIdx,
433                               PPC::CRRCRegisterClass, NewMIs);
434
435  } else if (RC == PPC::VRRCRegisterClass) {
436    // We don't have indexed addressing for vector loads.  Emit:
437    // R0 = ADDI FI#
438    // STVX VAL, 0, R0
439    //
440    // FIXME: We use R0 here, because it isn't available for RA.
441    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
442                                       FrameIdx, 0, 0));
443    NewMIs.push_back(BuildMI(get(PPC::STVX))
444         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
445  } else {
446    assert(0 && "Unknown regclass!");
447    abort();
448  }
449
450  return false;
451}
452
453void
454PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
455                                  MachineBasicBlock::iterator MI,
456                                  unsigned SrcReg, bool isKill, int FrameIdx,
457                                  const TargetRegisterClass *RC) const {
458  SmallVector<MachineInstr*, 4> NewMIs;
459
460  if (StoreRegToStackSlot(SrcReg, isKill, FrameIdx, RC, NewMIs)) {
461    PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
462    FuncInfo->setSpillsCR();
463  }
464
465  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
466    MBB.insert(MI, NewMIs[i]);
467}
468
469void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
470                                  bool isKill,
471                                  SmallVectorImpl<MachineOperand> &Addr,
472                                  const TargetRegisterClass *RC,
473                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
474  if (Addr[0].isFrameIndex()) {
475    if (StoreRegToStackSlot(SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs)) {
476      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
477      FuncInfo->setSpillsCR();
478    }
479
480    return;
481  }
482
483  unsigned Opc = 0;
484  if (RC == PPC::GPRCRegisterClass) {
485    Opc = PPC::STW;
486  } else if (RC == PPC::G8RCRegisterClass) {
487    Opc = PPC::STD;
488  } else if (RC == PPC::F8RCRegisterClass) {
489    Opc = PPC::STFD;
490  } else if (RC == PPC::F4RCRegisterClass) {
491    Opc = PPC::STFS;
492  } else if (RC == PPC::VRRCRegisterClass) {
493    Opc = PPC::STVX;
494  } else {
495    assert(0 && "Unknown regclass!");
496    abort();
497  }
498  MachineInstrBuilder MIB = BuildMI(get(Opc))
499    .addReg(SrcReg, false, false, isKill);
500  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
501    MachineOperand &MO = Addr[i];
502    if (MO.isRegister())
503      MIB.addReg(MO.getReg());
504    else if (MO.isImmediate())
505      MIB.addImm(MO.getImm());
506    else
507      MIB.addFrameIndex(MO.getIndex());
508  }
509  NewMIs.push_back(MIB);
510  return;
511}
512
513void
514PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
515                                   const TargetRegisterClass *RC,
516                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
517  if (RC == PPC::GPRCRegisterClass) {
518    if (DestReg != PPC::LR) {
519      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), DestReg),
520                                         FrameIdx));
521    } else {
522      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R11),
523                                         FrameIdx));
524      NewMIs.push_back(BuildMI(get(PPC::MTLR)).addReg(PPC::R11));
525    }
526  } else if (RC == PPC::G8RCRegisterClass) {
527    if (DestReg != PPC::LR8) {
528      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), DestReg),
529                                         FrameIdx));
530    } else {
531      NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), PPC::R11),
532                                         FrameIdx));
533      NewMIs.push_back(BuildMI(get(PPC::MTLR8)).addReg(PPC::R11));
534    }
535  } else if (RC == PPC::F8RCRegisterClass) {
536    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFD), DestReg),
537                                       FrameIdx));
538  } else if (RC == PPC::F4RCRegisterClass) {
539    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFS), DestReg),
540                                       FrameIdx));
541  } else if (RC == PPC::CRRCRegisterClass) {
542    // FIXME: We use R0 here, because it isn't available for RA.
543    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R0),
544                                       FrameIdx));
545
546    // If the reloaded register isn't CR0, shift the bits right so that they are
547    // in the right CR's slot.
548    if (DestReg != PPC::CR0) {
549      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
550      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
551      NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
552                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
553    }
554
555    NewMIs.push_back(BuildMI(get(PPC::MTCRF), DestReg).addReg(PPC::R0));
556  } else if (RC == PPC::CRBITRCRegisterClass) {
557
558    unsigned Reg = 0;
559    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
560      Reg = PPC::CR0;
561    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
562      Reg = PPC::CR1;
563    else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
564      Reg = PPC::CR2;
565    else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
566      Reg = PPC::CR3;
567    else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
568      Reg = PPC::CR4;
569    else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
570      Reg = PPC::CR5;
571    else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
572      Reg = PPC::CR6;
573    else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
574      Reg = PPC::CR7;
575
576    return LoadRegFromStackSlot(Reg, FrameIdx,
577                                PPC::CRRCRegisterClass, NewMIs);
578
579  } else if (RC == PPC::VRRCRegisterClass) {
580    // We don't have indexed addressing for vector loads.  Emit:
581    // R0 = ADDI FI#
582    // Dest = LVX 0, R0
583    //
584    // FIXME: We use R0 here, because it isn't available for RA.
585    NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
586                                       FrameIdx, 0, 0));
587    NewMIs.push_back(BuildMI(get(PPC::LVX),DestReg).addReg(PPC::R0)
588                     .addReg(PPC::R0));
589  } else {
590    assert(0 && "Unknown regclass!");
591    abort();
592  }
593}
594
595void
596PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
597                                   MachineBasicBlock::iterator MI,
598                                   unsigned DestReg, int FrameIdx,
599                                   const TargetRegisterClass *RC) const {
600  SmallVector<MachineInstr*, 4> NewMIs;
601  LoadRegFromStackSlot(DestReg, FrameIdx, RC, NewMIs);
602  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
603    MBB.insert(MI, NewMIs[i]);
604}
605
606void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
607                                   SmallVectorImpl<MachineOperand> &Addr,
608                                   const TargetRegisterClass *RC,
609                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
610  if (Addr[0].isFrameIndex()) {
611    LoadRegFromStackSlot(DestReg, Addr[0].getIndex(), RC, NewMIs);
612    return;
613  }
614
615  unsigned Opc = 0;
616  if (RC == PPC::GPRCRegisterClass) {
617    assert(DestReg != PPC::LR && "Can't handle this yet!");
618    Opc = PPC::LWZ;
619  } else if (RC == PPC::G8RCRegisterClass) {
620    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
621    Opc = PPC::LD;
622  } else if (RC == PPC::F8RCRegisterClass) {
623    Opc = PPC::LFD;
624  } else if (RC == PPC::F4RCRegisterClass) {
625    Opc = PPC::LFS;
626  } else if (RC == PPC::VRRCRegisterClass) {
627    Opc = PPC::LVX;
628  } else {
629    assert(0 && "Unknown regclass!");
630    abort();
631  }
632  MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
633  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
634    MachineOperand &MO = Addr[i];
635    if (MO.isRegister())
636      MIB.addReg(MO.getReg());
637    else if (MO.isImmediate())
638      MIB.addImm(MO.getImm());
639    else
640      MIB.addFrameIndex(MO.getIndex());
641  }
642  NewMIs.push_back(MIB);
643  return;
644}
645
646/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
647/// copy instructions, turning them into load/store instructions.
648MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
649                                              MachineInstr *MI,
650                                              SmallVectorImpl<unsigned> &Ops,
651                                              int FrameIndex) const {
652  if (Ops.size() != 1) return NULL;
653
654  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
655  // it takes more than one instruction to store it.
656  unsigned Opc = MI->getOpcode();
657  unsigned OpNum = Ops[0];
658
659  MachineInstr *NewMI = NULL;
660  if ((Opc == PPC::OR &&
661       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
662    if (OpNum == 0) {  // move -> store
663      unsigned InReg = MI->getOperand(1).getReg();
664      NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
665                                FrameIndex);
666    } else {           // move -> load
667      unsigned OutReg = MI->getOperand(0).getReg();
668      NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
669                                FrameIndex);
670    }
671  } else if ((Opc == PPC::OR8 &&
672              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
673    if (OpNum == 0) {  // move -> store
674      unsigned InReg = MI->getOperand(1).getReg();
675      NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
676                                FrameIndex);
677    } else {           // move -> load
678      unsigned OutReg = MI->getOperand(0).getReg();
679      NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
680    }
681  } else if (Opc == PPC::FMRD) {
682    if (OpNum == 0) {  // move -> store
683      unsigned InReg = MI->getOperand(1).getReg();
684      NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
685                                FrameIndex);
686    } else {           // move -> load
687      unsigned OutReg = MI->getOperand(0).getReg();
688      NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
689    }
690  } else if (Opc == PPC::FMRS) {
691    if (OpNum == 0) {  // move -> store
692      unsigned InReg = MI->getOperand(1).getReg();
693      NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
694                                FrameIndex);
695    } else {           // move -> load
696      unsigned OutReg = MI->getOperand(0).getReg();
697      NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
698    }
699  }
700
701  if (NewMI)
702    NewMI->copyKillDeadInfo(MI);
703  return NewMI;
704}
705
706bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
707                                        SmallVectorImpl<unsigned> &Ops) const {
708  if (Ops.size() != 1) return false;
709
710  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
711  // it takes more than one instruction to store it.
712  unsigned Opc = MI->getOpcode();
713
714  if ((Opc == PPC::OR &&
715       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
716    return true;
717  else if ((Opc == PPC::OR8 &&
718              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
719    return true;
720  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
721    return true;
722
723  return false;
724}
725
726
727bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
728  if (MBB.empty()) return false;
729
730  switch (MBB.back().getOpcode()) {
731  case PPC::BLR:   // Return.
732  case PPC::B:     // Uncond branch.
733  case PPC::BCTR:  // Indirect branch.
734    return true;
735  default: return false;
736  }
737}
738
739bool PPCInstrInfo::
740ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
741  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
742  // Leave the CR# the same, but invert the condition.
743  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
744  return false;
745}
746
747/// GetInstSize - Return the number of bytes of code the specified
748/// instruction may be.  This returns the maximum number of bytes.
749///
750unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
751  switch (MI->getOpcode()) {
752  case PPC::INLINEASM: {       // Inline Asm: Variable size.
753    const MachineFunction *MF = MI->getParent()->getParent();
754    const char *AsmStr = MI->getOperand(0).getSymbolName();
755    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
756  }
757  case PPC::DBG_LABEL:
758  case PPC::EH_LABEL:
759  case PPC::GC_LABEL:
760    return 0;
761  default:
762    return 4; // PowerPC instructions are all 4 bytes
763  }
764}
765