PPCInstrInfo.cpp revision bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCInstrInfo.h" 15#include "PPCPredicates.h" 16#include "PPCGenInstrInfo.inc" 17#include "PPCTargetMachine.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19using namespace llvm; 20 21PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 22 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm), 23 RI(*TM.getSubtargetImpl(), *this) {} 24 25/// getPointerRegClass - Return the register class to use to hold pointers. 26/// This is used for addressing modes. 27const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const { 28 if (TM.getSubtargetImpl()->isPPC64()) 29 return &PPC::G8RCRegClass; 30 else 31 return &PPC::GPRCRegClass; 32} 33 34 35bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 36 unsigned& sourceReg, 37 unsigned& destReg) const { 38 MachineOpCode oc = MI.getOpcode(); 39 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 40 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 41 assert(MI.getNumOperands() >= 3 && 42 MI.getOperand(0).isRegister() && 43 MI.getOperand(1).isRegister() && 44 MI.getOperand(2).isRegister() && 45 "invalid PPC OR instruction!"); 46 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 47 sourceReg = MI.getOperand(1).getReg(); 48 destReg = MI.getOperand(0).getReg(); 49 return true; 50 } 51 } else if (oc == PPC::ADDI) { // addi r1, r2, 0 52 assert(MI.getNumOperands() >= 3 && 53 MI.getOperand(0).isRegister() && 54 MI.getOperand(2).isImmediate() && 55 "invalid PPC ADDI instruction!"); 56 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { 57 sourceReg = MI.getOperand(1).getReg(); 58 destReg = MI.getOperand(0).getReg(); 59 return true; 60 } 61 } else if (oc == PPC::ORI) { // ori r1, r2, 0 62 assert(MI.getNumOperands() >= 3 && 63 MI.getOperand(0).isRegister() && 64 MI.getOperand(1).isRegister() && 65 MI.getOperand(2).isImmediate() && 66 "invalid PPC ORI instruction!"); 67 if (MI.getOperand(2).getImmedValue()==0) { 68 sourceReg = MI.getOperand(1).getReg(); 69 destReg = MI.getOperand(0).getReg(); 70 return true; 71 } 72 } else if (oc == PPC::FMRS || oc == PPC::FMRD || 73 oc == PPC::FMRSD) { // fmr r1, r2 74 assert(MI.getNumOperands() >= 2 && 75 MI.getOperand(0).isRegister() && 76 MI.getOperand(1).isRegister() && 77 "invalid PPC FMR instruction"); 78 sourceReg = MI.getOperand(1).getReg(); 79 destReg = MI.getOperand(0).getReg(); 80 return true; 81 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 82 assert(MI.getNumOperands() >= 2 && 83 MI.getOperand(0).isRegister() && 84 MI.getOperand(1).isRegister() && 85 "invalid PPC MCRF instruction"); 86 sourceReg = MI.getOperand(1).getReg(); 87 destReg = MI.getOperand(0).getReg(); 88 return true; 89 } 90 return false; 91} 92 93unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 94 int &FrameIndex) const { 95 switch (MI->getOpcode()) { 96 default: break; 97 case PPC::LD: 98 case PPC::LWZ: 99 case PPC::LFS: 100 case PPC::LFD: 101 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 102 MI->getOperand(2).isFrameIndex()) { 103 FrameIndex = MI->getOperand(2).getFrameIndex(); 104 return MI->getOperand(0).getReg(); 105 } 106 break; 107 } 108 return 0; 109} 110 111unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 112 int &FrameIndex) const { 113 switch (MI->getOpcode()) { 114 default: break; 115 case PPC::STD: 116 case PPC::STW: 117 case PPC::STFS: 118 case PPC::STFD: 119 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 120 MI->getOperand(2).isFrameIndex()) { 121 FrameIndex = MI->getOperand(2).getFrameIndex(); 122 return MI->getOperand(0).getReg(); 123 } 124 break; 125 } 126 return 0; 127} 128 129// commuteInstruction - We can commute rlwimi instructions, but only if the 130// rotate amt is zero. We also have to munge the immediates a bit. 131MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { 132 // Normal instructions can be commuted the obvious way. 133 if (MI->getOpcode() != PPC::RLWIMI) 134 return TargetInstrInfo::commuteInstruction(MI); 135 136 // Cannot commute if it has a non-zero rotate count. 137 if (MI->getOperand(3).getImmedValue() != 0) 138 return 0; 139 140 // If we have a zero rotate count, we have: 141 // M = mask(MB,ME) 142 // Op0 = (Op1 & ~M) | (Op2 & M) 143 // Change this to: 144 // M = mask((ME+1)&31, (MB-1)&31) 145 // Op0 = (Op2 & ~M) | (Op1 & M) 146 147 // Swap op1/op2 148 unsigned Reg1 = MI->getOperand(1).getReg(); 149 unsigned Reg2 = MI->getOperand(2).getReg(); 150 bool Reg1IsKill = MI->getOperand(1).isKill(); 151 bool Reg2IsKill = MI->getOperand(2).isKill(); 152 MI->getOperand(2).setReg(Reg1); 153 MI->getOperand(1).setReg(Reg2); 154 if (Reg1IsKill) 155 MI->getOperand(2).setIsKill(); 156 else 157 MI->getOperand(2).unsetIsKill(); 158 if (Reg2IsKill) 159 MI->getOperand(1).setIsKill(); 160 else 161 MI->getOperand(1).unsetIsKill(); 162 163 // Swap the mask around. 164 unsigned MB = MI->getOperand(4).getImmedValue(); 165 unsigned ME = MI->getOperand(5).getImmedValue(); 166 MI->getOperand(4).setImmedValue((ME+1) & 31); 167 MI->getOperand(5).setImmedValue((MB-1) & 31); 168 return MI; 169} 170 171void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 172 MachineBasicBlock::iterator MI) const { 173 BuildMI(MBB, MI, get(PPC::NOP)); 174} 175 176 177// Branch analysis. 178bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 179 MachineBasicBlock *&FBB, 180 std::vector<MachineOperand> &Cond) const { 181 // If the block has no terminators, it just falls into the block after it. 182 MachineBasicBlock::iterator I = MBB.end(); 183 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 184 return false; 185 186 // Get the last instruction in the block. 187 MachineInstr *LastInst = I; 188 189 // If there is only one terminator instruction, process it. 190 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 191 if (LastInst->getOpcode() == PPC::B) { 192 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 193 return false; 194 } else if (LastInst->getOpcode() == PPC::BCC) { 195 // Block ends with fall-through condbranch. 196 TBB = LastInst->getOperand(2).getMachineBasicBlock(); 197 Cond.push_back(LastInst->getOperand(0)); 198 Cond.push_back(LastInst->getOperand(1)); 199 return false; 200 } 201 // Otherwise, don't know what this is. 202 return true; 203 } 204 205 // Get the instruction before it if it's a terminator. 206 MachineInstr *SecondLastInst = I; 207 208 // If there are three terminators, we don't know what sort of block this is. 209 if (SecondLastInst && I != MBB.begin() && 210 isUnpredicatedTerminator(--I)) 211 return true; 212 213 // If the block ends with PPC::B and PPC:BCC, handle it. 214 if (SecondLastInst->getOpcode() == PPC::BCC && 215 LastInst->getOpcode() == PPC::B) { 216 TBB = SecondLastInst->getOperand(2).getMachineBasicBlock(); 217 Cond.push_back(SecondLastInst->getOperand(0)); 218 Cond.push_back(SecondLastInst->getOperand(1)); 219 FBB = LastInst->getOperand(0).getMachineBasicBlock(); 220 return false; 221 } 222 223 // Otherwise, can't handle this. 224 return true; 225} 226 227unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 228 MachineBasicBlock::iterator I = MBB.end(); 229 if (I == MBB.begin()) return 0; 230 --I; 231 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 232 return 0; 233 234 // Remove the branch. 235 I->eraseFromParent(); 236 237 I = MBB.end(); 238 239 if (I == MBB.begin()) return 1; 240 --I; 241 if (I->getOpcode() != PPC::BCC) 242 return 1; 243 244 // Remove the branch. 245 I->eraseFromParent(); 246 return 2; 247} 248 249unsigned 250PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 251 MachineBasicBlock *FBB, 252 const std::vector<MachineOperand> &Cond) const { 253 // Shouldn't be a fall through. 254 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 255 assert((Cond.size() == 2 || Cond.size() == 0) && 256 "PPC branch conditions have two components!"); 257 258 // One-way branch. 259 if (FBB == 0) { 260 if (Cond.empty()) // Unconditional branch 261 BuildMI(&MBB, get(PPC::B)).addMBB(TBB); 262 else // Conditional branch 263 BuildMI(&MBB, get(PPC::BCC)) 264 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 265 return 1; 266 } 267 268 // Two-way Conditional Branch. 269 BuildMI(&MBB, get(PPC::BCC)) 270 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 271 BuildMI(&MBB, get(PPC::B)).addMBB(FBB); 272 return 2; 273} 274 275bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 276 if (MBB.empty()) return false; 277 278 switch (MBB.back().getOpcode()) { 279 case PPC::BLR: // Return. 280 case PPC::B: // Uncond branch. 281 case PPC::BCTR: // Indirect branch. 282 return true; 283 default: return false; 284 } 285} 286 287bool PPCInstrInfo:: 288ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 289 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 290 // Leave the CR# the same, but invert the condition. 291 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 292 return false; 293} 294