PPCTargetMachine.cpp revision b1e1180ca0b32f37aa74d7ad703eeaf91e66c8fa
1//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Top-level implementation for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PowerPC.h" 15#include "PowerPCTargetMachine.h" 16#include "PowerPCFrameInfo.h" 17#include "PPC32TargetMachine.h" 18#include "PPC32JITInfo.h" 19#include "llvm/Module.h" 20#include "llvm/PassManager.h" 21#include "llvm/Analysis/Verifier.h" 22#include "llvm/CodeGen/IntrinsicLowering.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/Passes.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/Target/TargetMachineRegistry.h" 27#include "llvm/Transforms/Scalar.h" 28#include "llvm/Support/CommandLine.h" 29#include <iostream> 30using namespace llvm; 31 32namespace { 33 const char *PPC32ID = "PowerPC/32bit"; 34 35 static cl::opt<bool> EnablePPCDAGDAG("enable-ppc-dag-isel", cl::Hidden, 36 cl::desc("Enable DAG-to-DAG isel for PPC (beta)")); 37 38 // Register the targets 39 RegisterTarget<PPC32TargetMachine> 40 X("ppc32", " PowerPC 32-bit"); 41} 42 43PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name, 44 IntrinsicLowering *IL, 45 const Module &M, 46 const std::string &FS, 47 const TargetData &TD, 48 const PowerPCFrameInfo &TFI) 49: TargetMachine(name, IL, TD), FrameInfo(TFI), Subtarget(M, FS) { 50 if (TargetDefault == PPCTarget) { 51 if (Subtarget.isAIX()) PPCTarget = TargetAIX; 52 if (Subtarget.isDarwin()) PPCTarget = TargetDarwin; 53 } 54} 55 56unsigned PPC32TargetMachine::getJITMatchQuality() { 57#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) 58 return 10; 59#else 60 return 0; 61#endif 62} 63 64/// addPassesToEmitFile - Add passes to the specified pass manager to implement 65/// a static compiler for this target. 66/// 67bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM, 68 std::ostream &Out, 69 CodeGenFileType FileType) { 70 if (FileType != TargetMachine::AssemblyFile) return true; 71 72 // Run loop strength reduction before anything else. 73 PM.add(createLoopStrengthReducePass()); 74 PM.add(createCFGSimplificationPass()); 75 76 // FIXME: Implement efficient support for garbage collection intrinsics. 77 PM.add(createLowerGCPass()); 78 79 // FIXME: Implement the invoke/unwind instructions! 80 PM.add(createLowerInvokePass()); 81 82 // FIXME: Implement the switch instruction in the instruction selector! 83 PM.add(createLowerSwitchPass()); 84 85 // Make sure that no unreachable blocks are instruction selected. 86 PM.add(createUnreachableBlockEliminationPass()); 87 88 // Install an instruction selector. 89 if (EnablePPCDAGDAG) 90 PM.add(createPPC32ISelDag(*this)); 91 else 92 PM.add(createPPC32ISelPattern(*this)); 93 94 if (PrintMachineCode) 95 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 96 97 PM.add(createRegisterAllocator()); 98 99 if (PrintMachineCode) 100 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 101 102 PM.add(createPrologEpilogCodeInserter()); 103 104 // Must run branch selection immediately preceding the asm printer 105 PM.add(createPPCBranchSelectionPass()); 106 107 // Decide which asm printer to use. If the user has not specified one on 108 // the command line, choose whichever one matches the default (current host). 109 switch (PPCTarget) { 110 case TargetAIX: 111 PM.add(createAIXAsmPrinter(Out, *this)); 112 break; 113 case TargetDefault: 114 case TargetDarwin: 115 PM.add(createDarwinAsmPrinter(Out, *this)); 116 break; 117 } 118 119 PM.add(createMachineCodeDeleter()); 120 return false; 121} 122 123void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) { 124 // The JIT does not support or need PIC. 125 PICEnabled = false; 126 127 // Run loop strength reduction before anything else. 128 PM.add(createLoopStrengthReducePass()); 129 PM.add(createCFGSimplificationPass()); 130 131 // FIXME: Implement efficient support for garbage collection intrinsics. 132 PM.add(createLowerGCPass()); 133 134 // FIXME: Implement the invoke/unwind instructions! 135 PM.add(createLowerInvokePass()); 136 137 // FIXME: Implement the switch instruction in the instruction selector! 138 PM.add(createLowerSwitchPass()); 139 140 // Make sure that no unreachable blocks are instruction selected. 141 PM.add(createUnreachableBlockEliminationPass()); 142 143 // Install an instruction selector. 144 PM.add(createPPC32ISelPattern(TM)); 145 146 PM.add(createRegisterAllocator()); 147 PM.add(createPrologEpilogCodeInserter()); 148 149 // Must run branch selection immediately preceding the asm printer 150 PM.add(createPPCBranchSelectionPass()); 151 152 if (PrintMachineCode) 153 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 154} 155 156/// PowerPCTargetMachine ctor - Create an ILP32 architecture model 157/// 158PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL, 159 const std::string &FS) 160 : PowerPCTargetMachine(PPC32ID, IL, M, FS, 161 TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1), 162 PowerPCFrameInfo(*this, false)), JITInfo(*this) {} 163 164unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) { 165 // We strongly match "powerpc-*". 166 std::string TT = M.getTargetTriple(); 167 if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-") 168 return 20; 169 170 if (M.getEndianness() == Module::BigEndian && 171 M.getPointerSize() == Module::Pointer32) 172 return 10; // Weak match 173 else if (M.getEndianness() != Module::AnyEndianness || 174 M.getPointerSize() != Module::AnyPointerSize) 175 return 0; // Match for some other target 176 177 return getJITMatchQuality()/2; 178} 179