AMDGPUInstrInfo.cpp revision a2b4eb6d15a13de257319ac6231b5ab622cd02b1
1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief Implementation of the TargetInstrInfo class that is common to all 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// AMD GPUs. 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUInstrInfo.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPURegisterInfo.h" 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUTargetMachine.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineFrameInfo.h" 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_INSTRINFO_CTOR 245e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0Tom Stellard#define GET_INSTRINFO_NAMED_OPS 25f767018b1048f228b0c2a71d7e4008750aff0ef5Christian Konig#define GET_INSTRMAP_INFO 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenInstrInfo.inc" 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 28f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardusing namespace llvm; 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 30f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) 315b00e833fabbf5bdf2973c63c39d4a0d0143853aVincent Lejeune : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { } 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return RI; 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 36f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 37f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SrcReg, unsigned &DstReg, 39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SubIdx) const { 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 47f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 48f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 49f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 50f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 51f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 52f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 53f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 54f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 55f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 56f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 57f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 58f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 59f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 60f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 61f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 62f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, 63f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 64f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 65f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 66f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 67f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, 68f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 69f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 70f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 71f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 72f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, 73f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 74f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 75f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 76f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 77f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 78f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 79f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 80f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 81f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator &MBBI, 82f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard LiveVariables *LV) const { 83f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 84f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return NULL; 85f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 86f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter, 87f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock &MBB) const { 88f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard while (iter != MBB.end()) { 89f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (iter->getOpcode()) { 90f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: 91f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 92f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_i32: 93f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_f32: 94f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH: 95f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 96f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard }; 97f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard ++iter; 98f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 99f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 100f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 101f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 102f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 103f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 104f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 105f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned SrcReg, bool isKill, 106f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex, 107f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 108f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 109f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"Not Implemented"); 110f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 111f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 112f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 113f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 114f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 115f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned DestReg, int FrameIndex, 116f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 117f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 118f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"Not Implemented"); 119f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 120f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 12104c559569f87d755c3f2828a765f5eb7308e6753Tom Stellardbool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const { 12204c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard MachineBasicBlock *MBB = MI->getParent(); 123a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int OffsetOpIdx = 124a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::addr); 125a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard // addr is a custom operand with multiple MI operands, and only the 126a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard // first MI operand is given a name. 127a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int RegOpIdx = OffsetOpIdx + 1; 128a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int ChanOpIdx = 129a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::chan); 13004c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 1315203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman if (isRegisterLoad(*MI)) { 132a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int DstOpIdx = 133a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 134a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); 135a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned Channel = MI->getOperand(ChanOpIdx).getImm(); 1365203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman unsigned Address = calculateIndirectAddress(RegIndex, Channel); 137a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); 1385203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { 139a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(), 1405203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman getIndirectAddrRegClass()->getRegister(Address)); 14104c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard } else { 142a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(), 1435203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman Address, OffsetReg); 14404c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard } 1455203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } else if (isRegisterStore(*MI)) { 146a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int ValOpIdx = 147a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::val); 148a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 149a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); 150a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned Channel = MI->getOperand(ChanOpIdx).getImm(); 1515203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman unsigned Address = calculateIndirectAddress(RegIndex, Channel); 152a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); 1535203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { 1545203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address), 155a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard MI->getOperand(ValOpIdx).getReg()); 1565203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } else { 157a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(), 158a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard calculateIndirectAddress(RegIndex, Channel), 159a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard OffsetReg); 1605203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } 1615203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } else { 1625203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman return false; 16304c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard } 16404c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 16504c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard MBB->erase(MI); 16604c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard return true; 16704c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard} 16804c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 16904c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 170f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 171f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 172f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 173f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 174f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex) const { 175f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 176f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 177f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 178f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr* 179f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 180f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 181f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 182f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *LoadMI) const { 183f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 184f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 185f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 186f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 187f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 188f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops) const { 189f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 190f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 191f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 192f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 193f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 194f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Reg, bool UnfoldLoad, 195f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldStore, 196f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<MachineInstr*> &NewMIs) const { 197f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 198f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 199f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 200f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 201f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 202f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 203f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<SDNode*> &NewNodes) const { 204f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 205f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 206f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 207f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 208f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned 209f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 210f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldLoad, bool UnfoldStore, 211f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned *LoadRegIndex) const { 212f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 213f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 214f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 215f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 216f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 217f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int64_t Offset1, int64_t Offset2, 218f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned NumLoads) const { 219f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(Offset2 > Offset1 220f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard && "Second offset should be larger than first offset!"); 221f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // If we have less than 16 loads in a row, and the offsets are within 16, 222f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // then schedule together. 223f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Make the loads schedule near if it fits in a cacheline 224f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return (NumLoads < 16 && (Offset2 - Offset1) < 16); 225f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 226f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 227f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 228f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 229f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 230f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 231f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 232f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 233f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB, 234f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI) const { 235f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 236f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 237f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 238f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { 239f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 240f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 241f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 242f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 243f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 244f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<MachineOperand> &Pred2) 245f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 246f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 247f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 248f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 249f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 250f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI, 251f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard std::vector<MachineOperand> &Pred) const { 252f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 253f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 254f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 255f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 256f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { 257f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 258f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return MI->getDesc().isPredicable(); 259f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 260f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 261f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 262f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 263f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 264f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 265f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 266c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 267c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellardbool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const { 268c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE; 269c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard} 270c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 271c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellardbool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const { 272c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD; 273c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard} 274c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 275a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellardint AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { 276a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineRegisterInfo &MRI = MF.getRegInfo(); 277a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineFrameInfo *MFI = MF.getFrameInfo(); 278a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int Offset = -1; 279a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 280a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (MFI->getNumObjects() == 0) { 281a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return -1; 282a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 283a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 284a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (MRI.livein_empty()) { 285a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return 0; 286a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 287a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 288a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass(); 289a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 290a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard LE = MRI.livein_end(); 291a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard LI != LE; ++LI) { 292a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned Reg = LI->first; 293a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (TargetRegisterInfo::isVirtualRegister(Reg) || 294a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard !IndirectRC->contains(Reg)) 295a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard continue; 296a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 297a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegIndex; 298a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegEnd; 299a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; 300a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard ++RegIndex) { 301a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (IndirectRC->getRegister(RegIndex) == Reg) 302a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard break; 303a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 304a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard Offset = std::max(Offset, (int)RegIndex); 305a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 306a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 307a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return Offset + 1; 308a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard} 309a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 310a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellardint AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { 311a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int Offset = 0; 312a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineFrameInfo *MFI = MF.getFrameInfo(); 313a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 314a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard // Variable sized objects are not supported 315a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard assert(!MFI->hasVarSizedObjects()); 316a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 317a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (MFI->getNumObjects() == 0) { 318a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return -1; 319a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 320a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 321a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1); 322a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 323a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return getIndirectIndexBegin(MF) + Offset; 324a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard} 325a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 326c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 327f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, 328f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard DebugLoc DL) const { 329f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineRegisterInfo &MRI = MF.getRegInfo(); 330f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const AMDGPURegisterInfo & RI = getRegisterInfo(); 331f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 332f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard for (unsigned i = 0; i < MI.getNumOperands(); i++) { 333f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineOperand &MO = MI.getOperand(i); 334f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // Convert dst regclass to one that is supported by the ISA 335f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (MO.isReg() && MO.isDef()) { 336f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 337f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 338f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass); 339f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 340f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(newRegClass); 341f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 342f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MRI.setRegClass(MO.getReg(), newRegClass); 343f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 344f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 345f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 346f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 3470f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard 3480f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellardint AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { 3490f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard switch (Channels) { 3500f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard default: return Opcode; 3510f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1); 3520f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2); 3530f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3); 3540f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard } 3550f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard} 356