AMDGPUInstrInfo.cpp revision f98f2ce29e6e2996fa58f38979143eceaa818335
1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief Implementation of the TargetInstrInfo class that is common to all 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// AMD GPUs. 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUInstrInfo.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPURegisterInfo.h" 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUTargetMachine.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDIL.h" 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineFrameInfo.h" 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_INSTRINFO_CTOR 25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenInstrInfo.inc" 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardusing namespace llvm; 28f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) 30f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { } 31f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return RI; 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 36f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 37f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SrcReg, unsigned &DstReg, 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SubIdx) const { 39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 47f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 48f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 49f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 50f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 51f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 52f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 53f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 54f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 55f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 56f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 57f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 58f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 59f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 60f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 61f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, 62f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 63f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 64f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 65f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 66f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, 67f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 68f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 69f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 70f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 71f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, 72f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 73f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 74f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 75f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 76f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 77f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 78f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 79f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 80f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator &MBBI, 81f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard LiveVariables *LV) const { 82f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 83f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return NULL; 84f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 85f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter, 86f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock &MBB) const { 87f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard while (iter != MBB.end()) { 88f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (iter->getOpcode()) { 89f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: 90f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 91f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_i32: 92f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_f32: 93f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH: 94f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 95f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard }; 96f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard ++iter; 97f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 98f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 99f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 100f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 101f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineBasicBlock::iterator skipFlowControl(MachineBasicBlock *MBB) { 102f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator tmp = MBB->end(); 103f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (!MBB->size()) { 104f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return MBB->end(); 105f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 106f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard while (--tmp) { 107f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (tmp->getOpcode() == AMDGPU::ENDLOOP 108f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard || tmp->getOpcode() == AMDGPU::ENDIF 109f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard || tmp->getOpcode() == AMDGPU::ELSE) { 110f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (tmp == MBB->begin()) { 111f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return tmp; 112f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } else { 113f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard continue; 114f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 115f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } else { 116f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return ++tmp; 117f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 118f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 119f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return MBB->end(); 120f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 121f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 122f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 123f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 124f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 125f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned SrcReg, bool isKill, 126f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex, 127f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 128f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 129f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"Not Implemented"); 130f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 131f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 132f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 133f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 134f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 135f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned DestReg, int FrameIndex, 136f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 137f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 138f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"Not Implemented"); 139f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 140f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 141f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 142f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 143f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 144f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 145f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex) const { 146f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 147f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 148f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 149f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr* 150f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 151f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 152f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 153f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *LoadMI) const { 154f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 155f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 156f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 157f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 158f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 159f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops) const { 160f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 161f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 162f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 163f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 164f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 165f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Reg, bool UnfoldLoad, 166f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldStore, 167f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<MachineInstr*> &NewMIs) const { 168f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 169f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 170f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 171f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 172f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 173f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 174f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<SDNode*> &NewNodes) const { 175f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 176f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 177f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 178f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 179f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned 180f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 181f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldLoad, bool UnfoldStore, 182f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned *LoadRegIndex) const { 183f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 184f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 185f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 186f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 187f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 188f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int64_t Offset1, int64_t Offset2, 189f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned NumLoads) const { 190f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(Offset2 > Offset1 191f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard && "Second offset should be larger than first offset!"); 192f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // If we have less than 16 loads in a row, and the offsets are within 16, 193f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // then schedule together. 194f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Make the loads schedule near if it fits in a cacheline 195f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return (NumLoads < 16 && (Offset2 - Offset1) < 16); 196f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 197f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 198f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 199f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 200f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 201f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 202f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 203f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 204f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB, 205f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI) const { 206f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 207f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 208f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 209f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { 210f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 211f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 212f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 213f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 214f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 215f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<MachineOperand> &Pred2) 216f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 217f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 218f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 219f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 220f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 221f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI, 222f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard std::vector<MachineOperand> &Pred) const { 223f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 224f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 225f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 226f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 227f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { 228f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 229f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return MI->getDesc().isPredicable(); 230f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 231f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 232f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 233f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 234f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 235f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 236f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 237f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 238f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, 239f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard DebugLoc DL) const { 240f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineRegisterInfo &MRI = MF.getRegInfo(); 241f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const AMDGPURegisterInfo & RI = getRegisterInfo(); 242f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 243f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard for (unsigned i = 0; i < MI.getNumOperands(); i++) { 244f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineOperand &MO = MI.getOperand(i); 245f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // Convert dst regclass to one that is supported by the ISA 246f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (MO.isReg() && MO.isDef()) { 247f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 248f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 249f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass); 250f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 251f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(newRegClass); 252f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 253f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MRI.setRegClass(MO.getReg(), newRegClass); 254f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 255f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 256f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 257f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 258