X86AsmParser.cpp revision 5ea1ea8db810aaf51f68e32119006629a2f06f30 
1//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/X86BaseInfo.h"
11#include "llvm/ADT/APFloat.h"
12#include "llvm/ADT/SmallString.h"
13#include "llvm/ADT/SmallVector.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Twine.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCParser/MCAsmLexer.h"
20#include "llvm/MC/MCParser/MCAsmParser.h"
21#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCStreamer.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/MCSymbol.h"
26#include "llvm/MC/MCTargetAsmParser.h"
27#include "llvm/Support/SourceMgr.h"
28#include "llvm/Support/TargetRegistry.h"
29#include "llvm/Support/raw_ostream.h"
30
31using namespace llvm;
32
33namespace {
34struct X86Operand;
35
36class X86AsmParser : public MCTargetAsmParser {
37  MCSubtargetInfo &STI;
38  MCAsmParser &Parser;
39  ParseInstructionInfo *InstInfo;
40private:
41  MCAsmParser &getParser() const { return Parser; }
42
43  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
44
45  bool Error(SMLoc L, const Twine &Msg,
46             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(),
47             bool MatchingInlineAsm = false) {
48    if (MatchingInlineAsm) return true;
49    return Parser.Error(L, Msg, Ranges);
50  }
51
52  X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
53    Error(Loc, Msg);
54    return 0;
55  }
56
57  X86Operand *ParseOperand();
58  X86Operand *ParseATTOperand();
59  X86Operand *ParseIntelOperand();
60  X86Operand *ParseIntelOffsetOfOperator();
61  X86Operand *ParseIntelOperator(unsigned OpKind);
62  X86Operand *ParseIntelMemOperand(unsigned SegReg, uint64_t ImmDisp,
63                                   SMLoc StartLoc);
64  X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc SizeDirLoc,
65                                       uint64_t ImmDisp, unsigned Size);
66  X86Operand *ParseIntelVarWithQualifier(const MCExpr *&Disp,
67                                         StringRef &Identifier);
68  X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
69
70  X86Operand *CreateMemForInlineAsm(const MCExpr *Disp, SMLoc Start, SMLoc End,
71                                    SMLoc SizeDirLoc, unsigned Size,
72                                    StringRef SymName);
73
74  bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr **NewDisp,
75                             SmallString<64> &Err);
76
77  bool ParseDirectiveWord(unsigned Size, SMLoc L);
78  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
79
80  bool processInstruction(MCInst &Inst,
81                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
82
83  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
84                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
85                               MCStreamer &Out, unsigned &ErrorInfo,
86                               bool MatchingInlineAsm);
87
88  /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
89  /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
90  bool isSrcOp(X86Operand &Op);
91
92  /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
93  /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
94  bool isDstOp(X86Operand &Op);
95
96  bool is64BitMode() const {
97    // FIXME: Can tablegen auto-generate this?
98    return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
99  }
100  void SwitchMode() {
101    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
102    setAvailableFeatures(FB);
103  }
104
105  /// @name Auto-generated Matcher Functions
106  /// {
107
108#define GET_ASSEMBLER_HEADER
109#include "X86GenAsmMatcher.inc"
110
111  /// }
112
113public:
114  X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
115    : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
116
117    // Initialize the set of available features.
118    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
119  }
120  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
121
122  virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
123                                SMLoc NameLoc,
124                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
125
126  virtual bool ParseDirective(AsmToken DirectiveID);
127
128  bool isParsingIntelSyntax() {
129    return getParser().getAssemblerDialect();
130  }
131};
132} // end anonymous namespace
133
134/// @name Auto-generated Match Functions
135/// {
136
137static unsigned MatchRegisterName(StringRef Name);
138
139/// }
140
141static bool isImmSExti16i8Value(uint64_t Value) {
142  return ((                                  Value <= 0x000000000000007FULL)||
143          (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
144          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
145}
146
147static bool isImmSExti32i8Value(uint64_t Value) {
148  return ((                                  Value <= 0x000000000000007FULL)||
149          (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
150          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
151}
152
153static bool isImmZExtu32u8Value(uint64_t Value) {
154    return (Value <= 0x00000000000000FFULL);
155}
156
157static bool isImmSExti64i8Value(uint64_t Value) {
158  return ((                                  Value <= 0x000000000000007FULL)||
159          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
160}
161
162static bool isImmSExti64i32Value(uint64_t Value) {
163  return ((                                  Value <= 0x000000007FFFFFFFULL)||
164          (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
165}
166namespace {
167
168/// X86Operand - Instances of this class represent a parsed X86 machine
169/// instruction.
170struct X86Operand : public MCParsedAsmOperand {
171  enum KindTy {
172    Token,
173    Register,
174    Immediate,
175    Memory
176  } Kind;
177
178  SMLoc StartLoc, EndLoc;
179  SMLoc OffsetOfLoc;
180  StringRef SymName;
181  bool AddressOf;
182
183  struct TokOp {
184    const char *Data;
185    unsigned Length;
186  };
187
188  struct RegOp {
189    unsigned RegNo;
190  };
191
192  struct ImmOp {
193    const MCExpr *Val;
194  };
195
196  struct MemOp {
197    unsigned SegReg;
198    const MCExpr *Disp;
199    unsigned BaseReg;
200    unsigned IndexReg;
201    unsigned Scale;
202    unsigned Size;
203  };
204
205  union {
206    struct TokOp Tok;
207    struct RegOp Reg;
208    struct ImmOp Imm;
209    struct MemOp Mem;
210  };
211
212  X86Operand(KindTy K, SMLoc Start, SMLoc End)
213    : Kind(K), StartLoc(Start), EndLoc(End) {}
214
215  StringRef getSymName() { return SymName; }
216
217  /// getStartLoc - Get the location of the first token of this operand.
218  SMLoc getStartLoc() const { return StartLoc; }
219  /// getEndLoc - Get the location of the last token of this operand.
220  SMLoc getEndLoc() const { return EndLoc; }
221  /// getLocRange - Get the range between the first and last token of this
222  /// operand.
223  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
224  /// getOffsetOfLoc - Get the location of the offset operator.
225  SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
226
227  virtual void print(raw_ostream &OS) const {}
228
229  StringRef getToken() const {
230    assert(Kind == Token && "Invalid access!");
231    return StringRef(Tok.Data, Tok.Length);
232  }
233  void setTokenValue(StringRef Value) {
234    assert(Kind == Token && "Invalid access!");
235    Tok.Data = Value.data();
236    Tok.Length = Value.size();
237  }
238
239  unsigned getReg() const {
240    assert(Kind == Register && "Invalid access!");
241    return Reg.RegNo;
242  }
243
244  const MCExpr *getImm() const {
245    assert(Kind == Immediate && "Invalid access!");
246    return Imm.Val;
247  }
248
249  const MCExpr *getMemDisp() const {
250    assert(Kind == Memory && "Invalid access!");
251    return Mem.Disp;
252  }
253  unsigned getMemSegReg() const {
254    assert(Kind == Memory && "Invalid access!");
255    return Mem.SegReg;
256  }
257  unsigned getMemBaseReg() const {
258    assert(Kind == Memory && "Invalid access!");
259    return Mem.BaseReg;
260  }
261  unsigned getMemIndexReg() const {
262    assert(Kind == Memory && "Invalid access!");
263    return Mem.IndexReg;
264  }
265  unsigned getMemScale() const {
266    assert(Kind == Memory && "Invalid access!");
267    return Mem.Scale;
268  }
269
270  bool isToken() const {return Kind == Token; }
271
272  bool isImm() const { return Kind == Immediate; }
273
274  bool isImmSExti16i8() const {
275    if (!isImm())
276      return false;
277
278    // If this isn't a constant expr, just assume it fits and let relaxation
279    // handle it.
280    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
281    if (!CE)
282      return true;
283
284    // Otherwise, check the value is in a range that makes sense for this
285    // extension.
286    return isImmSExti16i8Value(CE->getValue());
287  }
288  bool isImmSExti32i8() const {
289    if (!isImm())
290      return false;
291
292    // If this isn't a constant expr, just assume it fits and let relaxation
293    // handle it.
294    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
295    if (!CE)
296      return true;
297
298    // Otherwise, check the value is in a range that makes sense for this
299    // extension.
300    return isImmSExti32i8Value(CE->getValue());
301  }
302  bool isImmZExtu32u8() const {
303    if (!isImm())
304      return false;
305
306    // If this isn't a constant expr, just assume it fits and let relaxation
307    // handle it.
308    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
309    if (!CE)
310      return true;
311
312    // Otherwise, check the value is in a range that makes sense for this
313    // extension.
314    return isImmZExtu32u8Value(CE->getValue());
315  }
316  bool isImmSExti64i8() const {
317    if (!isImm())
318      return false;
319
320    // If this isn't a constant expr, just assume it fits and let relaxation
321    // handle it.
322    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
323    if (!CE)
324      return true;
325
326    // Otherwise, check the value is in a range that makes sense for this
327    // extension.
328    return isImmSExti64i8Value(CE->getValue());
329  }
330  bool isImmSExti64i32() const {
331    if (!isImm())
332      return false;
333
334    // If this isn't a constant expr, just assume it fits and let relaxation
335    // handle it.
336    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
337    if (!CE)
338      return true;
339
340    // Otherwise, check the value is in a range that makes sense for this
341    // extension.
342    return isImmSExti64i32Value(CE->getValue());
343  }
344
345  bool isOffsetOf() const {
346    return OffsetOfLoc.getPointer();
347  }
348
349  bool needAddressOf() const {
350    return AddressOf;
351  }
352
353  bool isMem() const { return Kind == Memory; }
354  bool isMem8() const {
355    return Kind == Memory && (!Mem.Size || Mem.Size == 8);
356  }
357  bool isMem16() const {
358    return Kind == Memory && (!Mem.Size || Mem.Size == 16);
359  }
360  bool isMem32() const {
361    return Kind == Memory && (!Mem.Size || Mem.Size == 32);
362  }
363  bool isMem64() const {
364    return Kind == Memory && (!Mem.Size || Mem.Size == 64);
365  }
366  bool isMem80() const {
367    return Kind == Memory && (!Mem.Size || Mem.Size == 80);
368  }
369  bool isMem128() const {
370    return Kind == Memory && (!Mem.Size || Mem.Size == 128);
371  }
372  bool isMem256() const {
373    return Kind == Memory && (!Mem.Size || Mem.Size == 256);
374  }
375
376  bool isMemVX32() const {
377    return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
378      getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
379  }
380  bool isMemVY32() const {
381    return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
382      getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
383  }
384  bool isMemVX64() const {
385    return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
386      getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
387  }
388  bool isMemVY64() const {
389    return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
390      getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
391  }
392
393  bool isAbsMem() const {
394    return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
395      !getMemIndexReg() && getMemScale() == 1;
396  }
397
398  bool isReg() const { return Kind == Register; }
399
400  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
401    // Add as immediates when possible.
402    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
403      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
404    else
405      Inst.addOperand(MCOperand::CreateExpr(Expr));
406  }
407
408  void addRegOperands(MCInst &Inst, unsigned N) const {
409    assert(N == 1 && "Invalid number of operands!");
410    Inst.addOperand(MCOperand::CreateReg(getReg()));
411  }
412
413  void addImmOperands(MCInst &Inst, unsigned N) const {
414    assert(N == 1 && "Invalid number of operands!");
415    addExpr(Inst, getImm());
416  }
417
418  void addMem8Operands(MCInst &Inst, unsigned N) const {
419    addMemOperands(Inst, N);
420  }
421  void addMem16Operands(MCInst &Inst, unsigned N) const {
422    addMemOperands(Inst, N);
423  }
424  void addMem32Operands(MCInst &Inst, unsigned N) const {
425    addMemOperands(Inst, N);
426  }
427  void addMem64Operands(MCInst &Inst, unsigned N) const {
428    addMemOperands(Inst, N);
429  }
430  void addMem80Operands(MCInst &Inst, unsigned N) const {
431    addMemOperands(Inst, N);
432  }
433  void addMem128Operands(MCInst &Inst, unsigned N) const {
434    addMemOperands(Inst, N);
435  }
436  void addMem256Operands(MCInst &Inst, unsigned N) const {
437    addMemOperands(Inst, N);
438  }
439  void addMemVX32Operands(MCInst &Inst, unsigned N) const {
440    addMemOperands(Inst, N);
441  }
442  void addMemVY32Operands(MCInst &Inst, unsigned N) const {
443    addMemOperands(Inst, N);
444  }
445  void addMemVX64Operands(MCInst &Inst, unsigned N) const {
446    addMemOperands(Inst, N);
447  }
448  void addMemVY64Operands(MCInst &Inst, unsigned N) const {
449    addMemOperands(Inst, N);
450  }
451
452  void addMemOperands(MCInst &Inst, unsigned N) const {
453    assert((N == 5) && "Invalid number of operands!");
454    Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
455    Inst.addOperand(MCOperand::CreateImm(getMemScale()));
456    Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
457    addExpr(Inst, getMemDisp());
458    Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
459  }
460
461  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
462    assert((N == 1) && "Invalid number of operands!");
463    // Add as immediates when possible.
464    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
465      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
466    else
467      Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
468  }
469
470  static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
471    SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
472    X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
473    Res->Tok.Data = Str.data();
474    Res->Tok.Length = Str.size();
475    return Res;
476  }
477
478  static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
479                               bool AddressOf = false,
480                               SMLoc OffsetOfLoc = SMLoc(),
481                               StringRef SymName = StringRef()) {
482    X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
483    Res->Reg.RegNo = RegNo;
484    Res->AddressOf = AddressOf;
485    Res->OffsetOfLoc = OffsetOfLoc;
486    Res->SymName = SymName;
487    return Res;
488  }
489
490  static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
491    X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
492    Res->Imm.Val = Val;
493    return Res;
494  }
495
496  /// Create an absolute memory operand.
497  static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
498                               unsigned Size = 0,
499                               StringRef SymName = StringRef()) {
500    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
501    Res->Mem.SegReg   = 0;
502    Res->Mem.Disp     = Disp;
503    Res->Mem.BaseReg  = 0;
504    Res->Mem.IndexReg = 0;
505    Res->Mem.Scale    = 1;
506    Res->Mem.Size     = Size;
507    Res->SymName = SymName;
508    Res->AddressOf = false;
509    return Res;
510  }
511
512  /// Create a generalized memory operand.
513  static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
514                               unsigned BaseReg, unsigned IndexReg,
515                               unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
516                               unsigned Size = 0,
517                               StringRef SymName = StringRef()) {
518    // We should never just have a displacement, that should be parsed as an
519    // absolute memory operand.
520    assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
521
522    // The scale should always be one of {1,2,4,8}.
523    assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
524           "Invalid scale!");
525    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
526    Res->Mem.SegReg   = SegReg;
527    Res->Mem.Disp     = Disp;
528    Res->Mem.BaseReg  = BaseReg;
529    Res->Mem.IndexReg = IndexReg;
530    Res->Mem.Scale    = Scale;
531    Res->Mem.Size     = Size;
532    Res->SymName = SymName;
533    Res->AddressOf = false;
534    return Res;
535  }
536};
537
538} // end anonymous namespace.
539
540bool X86AsmParser::isSrcOp(X86Operand &Op) {
541  unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
542
543  return (Op.isMem() &&
544    (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
545    isa<MCConstantExpr>(Op.Mem.Disp) &&
546    cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
547    Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
548}
549
550bool X86AsmParser::isDstOp(X86Operand &Op) {
551  unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
552
553  return Op.isMem() &&
554    (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
555    isa<MCConstantExpr>(Op.Mem.Disp) &&
556    cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
557    Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
558}
559
560bool X86AsmParser::ParseRegister(unsigned &RegNo,
561                                 SMLoc &StartLoc, SMLoc &EndLoc) {
562  RegNo = 0;
563  const AsmToken &PercentTok = Parser.getTok();
564  StartLoc = PercentTok.getLoc();
565
566  // If we encounter a %, ignore it. This code handles registers with and
567  // without the prefix, unprefixed registers can occur in cfi directives.
568  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
569    Parser.Lex(); // Eat percent token.
570
571  const AsmToken &Tok = Parser.getTok();
572  EndLoc = Tok.getEndLoc();
573
574  if (Tok.isNot(AsmToken::Identifier)) {
575    if (isParsingIntelSyntax()) return true;
576    return Error(StartLoc, "invalid register name",
577                 SMRange(StartLoc, EndLoc));
578  }
579
580  RegNo = MatchRegisterName(Tok.getString());
581
582  // If the match failed, try the register name as lowercase.
583  if (RegNo == 0)
584    RegNo = MatchRegisterName(Tok.getString().lower());
585
586  if (!is64BitMode()) {
587    // FIXME: This should be done using Requires<In32BitMode> and
588    // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
589    // checked.
590    // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
591    // REX prefix.
592    if (RegNo == X86::RIZ ||
593        X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
594        X86II::isX86_64NonExtLowByteReg(RegNo) ||
595        X86II::isX86_64ExtendedReg(RegNo))
596      return Error(StartLoc, "register %"
597                   + Tok.getString() + " is only available in 64-bit mode",
598                   SMRange(StartLoc, EndLoc));
599  }
600
601  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
602  if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
603    RegNo = X86::ST0;
604    Parser.Lex(); // Eat 'st'
605
606    // Check to see if we have '(4)' after %st.
607    if (getLexer().isNot(AsmToken::LParen))
608      return false;
609    // Lex the paren.
610    getParser().Lex();
611
612    const AsmToken &IntTok = Parser.getTok();
613    if (IntTok.isNot(AsmToken::Integer))
614      return Error(IntTok.getLoc(), "expected stack index");
615    switch (IntTok.getIntVal()) {
616    case 0: RegNo = X86::ST0; break;
617    case 1: RegNo = X86::ST1; break;
618    case 2: RegNo = X86::ST2; break;
619    case 3: RegNo = X86::ST3; break;
620    case 4: RegNo = X86::ST4; break;
621    case 5: RegNo = X86::ST5; break;
622    case 6: RegNo = X86::ST6; break;
623    case 7: RegNo = X86::ST7; break;
624    default: return Error(IntTok.getLoc(), "invalid stack index");
625    }
626
627    if (getParser().Lex().isNot(AsmToken::RParen))
628      return Error(Parser.getTok().getLoc(), "expected ')'");
629
630    EndLoc = Parser.getTok().getEndLoc();
631    Parser.Lex(); // Eat ')'
632    return false;
633  }
634
635  EndLoc = Parser.getTok().getEndLoc();
636
637  // If this is "db[0-7]", match it as an alias
638  // for dr[0-7].
639  if (RegNo == 0 && Tok.getString().size() == 3 &&
640      Tok.getString().startswith("db")) {
641    switch (Tok.getString()[2]) {
642    case '0': RegNo = X86::DR0; break;
643    case '1': RegNo = X86::DR1; break;
644    case '2': RegNo = X86::DR2; break;
645    case '3': RegNo = X86::DR3; break;
646    case '4': RegNo = X86::DR4; break;
647    case '5': RegNo = X86::DR5; break;
648    case '6': RegNo = X86::DR6; break;
649    case '7': RegNo = X86::DR7; break;
650    }
651
652    if (RegNo != 0) {
653      EndLoc = Parser.getTok().getEndLoc();
654      Parser.Lex(); // Eat it.
655      return false;
656    }
657  }
658
659  if (RegNo == 0) {
660    if (isParsingIntelSyntax()) return true;
661    return Error(StartLoc, "invalid register name",
662                 SMRange(StartLoc, EndLoc));
663  }
664
665  Parser.Lex(); // Eat identifier token.
666  return false;
667}
668
669X86Operand *X86AsmParser::ParseOperand() {
670  if (isParsingIntelSyntax())
671    return ParseIntelOperand();
672  return ParseATTOperand();
673}
674
675/// getIntelMemOperandSize - Return intel memory operand size.
676static unsigned getIntelMemOperandSize(StringRef OpStr) {
677  unsigned Size = StringSwitch<unsigned>(OpStr)
678    .Cases("BYTE", "byte", 8)
679    .Cases("WORD", "word", 16)
680    .Cases("DWORD", "dword", 32)
681    .Cases("QWORD", "qword", 64)
682    .Cases("XWORD", "xword", 80)
683    .Cases("XMMWORD", "xmmword", 128)
684    .Cases("YMMWORD", "ymmword", 256)
685    .Default(0);
686  return Size;
687}
688
689enum InfixCalculatorTok {
690  IC_PLUS = 0,
691  IC_MINUS,
692  IC_MULTIPLY,
693  IC_DIVIDE,
694  IC_RPAREN,
695  IC_LPAREN,
696  IC_IMM,
697  IC_REGISTER
698};
699static const char OpPrecedence[] = {
700  0, // IC_PLUS
701  0, // IC_MINUS
702  1, // IC_MULTIPLY
703  1, // IC_DIVIDE
704  2, // IC_RPAREN
705  3, // IC_LPAREN
706  0, // IC_IMM
707  0  // IC_REGISTER
708};
709
710class InfixCalculator {
711  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
712  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
713  SmallVector<ICToken, 4> PostfixStack;
714
715public:
716  int64_t popOperand() {
717    assert (!PostfixStack.empty() && "Poped an empty stack!");
718    ICToken Op = PostfixStack.pop_back_val();
719    assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
720            && "Expected and immediate or register!");
721    return Op.second;
722  }
723  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
724    assert ((Op == IC_IMM || Op == IC_REGISTER) &&
725            "Unexpected operand!");
726    PostfixStack.push_back(std::make_pair(Op, Val));
727  }
728
729  void popOperator() { InfixOperatorStack.pop_back_val(); }
730  void pushOperator(InfixCalculatorTok Op) {
731    // Push the new operator if the stack is empty.
732    if (InfixOperatorStack.empty()) {
733      InfixOperatorStack.push_back(Op);
734      return;
735    }
736
737    // Push the new operator if it has a higher precedence than the operator on
738    // the top of the stack or the operator on the top of the stack is a left
739    // parentheses.
740    unsigned Idx = InfixOperatorStack.size() - 1;
741    InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
742    if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
743      InfixOperatorStack.push_back(Op);
744      return;
745    }
746
747    // The operator on the top of the stack has higher precedence than the
748    // new operator.
749    unsigned ParenCount = 0;
750    while (1) {
751      // Nothing to process.
752      if (InfixOperatorStack.empty())
753        break;
754
755      Idx = InfixOperatorStack.size() - 1;
756      StackOp = InfixOperatorStack[Idx];
757      if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
758        break;
759
760      // If we have an even parentheses count and we see a left parentheses,
761      // then stop processing.
762      if (!ParenCount && StackOp == IC_LPAREN)
763        break;
764
765      if (StackOp == IC_RPAREN) {
766        ++ParenCount;
767        InfixOperatorStack.pop_back_val();
768      } else if (StackOp == IC_LPAREN) {
769        --ParenCount;
770        InfixOperatorStack.pop_back_val();
771      } else {
772        InfixOperatorStack.pop_back_val();
773        PostfixStack.push_back(std::make_pair(StackOp, 0));
774      }
775    }
776    // Push the new operator.
777    InfixOperatorStack.push_back(Op);
778  }
779  int64_t execute() {
780    // Push any remaining operators onto the postfix stack.
781    while (!InfixOperatorStack.empty()) {
782      InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
783      if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
784        PostfixStack.push_back(std::make_pair(StackOp, 0));
785    }
786
787    if (PostfixStack.empty())
788      return 0;
789
790    SmallVector<ICToken, 16> OperandStack;
791    for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
792      ICToken Op = PostfixStack[i];
793      if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
794        OperandStack.push_back(Op);
795      } else {
796        assert (OperandStack.size() > 1 && "Too few operands.");
797        int64_t Val;
798        ICToken Op2 = OperandStack.pop_back_val();
799        ICToken Op1 = OperandStack.pop_back_val();
800        switch (Op.first) {
801        default:
802          report_fatal_error("Unexpected operator!");
803          break;
804        case IC_PLUS:
805          Val = Op1.second + Op2.second;
806          OperandStack.push_back(std::make_pair(IC_IMM, Val));
807          break;
808        case IC_MINUS:
809          Val = Op1.second - Op2.second;
810          OperandStack.push_back(std::make_pair(IC_IMM, Val));
811          break;
812        case IC_MULTIPLY:
813          assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
814                  "Multiply operation with an immediate and a register!");
815          Val = Op1.second * Op2.second;
816          OperandStack.push_back(std::make_pair(IC_IMM, Val));
817          break;
818        case IC_DIVIDE:
819          assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
820                  "Divide operation with an immediate and a register!");
821          assert (Op2.second != 0 && "Division by zero!");
822          Val = Op1.second / Op2.second;
823          OperandStack.push_back(std::make_pair(IC_IMM, Val));
824          break;
825        }
826      }
827    }
828    assert (OperandStack.size() == 1 && "Expected a single result.");
829    return OperandStack.pop_back_val().second;
830  }
831};
832
833enum IntelBracExprState {
834  IBES_PLUS,
835  IBES_MINUS,
836  IBES_MULTIPLY,
837  IBES_DIVIDE,
838  IBES_LBRAC,
839  IBES_RBRAC,
840  IBES_LPAREN,
841  IBES_RPAREN,
842  IBES_REGISTER,
843  IBES_REGISTER_STAR,
844  IBES_INTEGER,
845  IBES_INTEGER_STAR,
846  IBES_IDENTIFIER,
847  IBES_ERROR
848};
849
850class IntelBracExprStateMachine {
851  IntelBracExprState State;
852  unsigned BaseReg, IndexReg, TmpReg, Scale;
853  int64_t Disp;
854  InfixCalculator IC;
855public:
856  IntelBracExprStateMachine(MCAsmParser &parser, int64_t disp) :
857    State(IBES_PLUS), BaseReg(0), IndexReg(0), TmpReg(0), Scale(1), Disp(disp){}
858
859  unsigned getBaseReg() { return BaseReg; }
860  unsigned getIndexReg() { return IndexReg; }
861  unsigned getScale() { return Scale; }
862  int64_t getDisp() { return Disp + IC.execute(); }
863  bool isValidEndState() { return State == IBES_RBRAC; }
864
865  void onPlus() {
866    switch (State) {
867    default:
868      State = IBES_ERROR;
869      break;
870    case IBES_INTEGER:
871    case IBES_RPAREN:
872      State = IBES_PLUS;
873      IC.pushOperator(IC_PLUS);
874      break;
875    case IBES_REGISTER:
876      State = IBES_PLUS;
877      // If we already have a BaseReg, then assume this is the IndexReg with a
878      // scale of 1.
879      if (!BaseReg) {
880        BaseReg = TmpReg;
881      } else {
882        assert (!IndexReg && "BaseReg/IndexReg already set!");
883        IndexReg = TmpReg;
884        Scale = 1;
885      }
886      IC.pushOperator(IC_PLUS);
887      break;
888    }
889  }
890  void onMinus() {
891    switch (State) {
892    default:
893      State = IBES_ERROR;
894      break;
895    case IBES_PLUS:
896    case IBES_LPAREN:
897      IC.pushOperand(IC_IMM);
898    case IBES_INTEGER:
899    case IBES_RPAREN:
900      State = IBES_MINUS;
901      IC.pushOperator(IC_MINUS);
902      break;
903    case IBES_REGISTER:
904      State = IBES_MINUS;
905      // If we already have a BaseReg, then assume this is the IndexReg with a
906      // scale of 1.
907      if (!BaseReg) {
908        BaseReg = TmpReg;
909      } else {
910        assert (!IndexReg && "BaseReg/IndexReg already set!");
911        IndexReg = TmpReg;
912        Scale = 1;
913      }
914      IC.pushOperator(IC_MINUS);
915      break;
916    }
917  }
918  void onRegister(unsigned Reg) {
919    switch (State) {
920    default:
921      State = IBES_ERROR;
922      break;
923    case IBES_PLUS:
924    case IBES_LPAREN:
925      State = IBES_REGISTER;
926      TmpReg = Reg;
927      IC.pushOperand(IC_REGISTER);
928      break;
929    case IBES_INTEGER_STAR:
930      assert (!IndexReg && "IndexReg already set!");
931      State = IBES_INTEGER;
932      IndexReg = Reg;
933      Scale = IC.popOperand();
934      IC.pushOperand(IC_IMM);
935      IC.popOperator();
936      break;
937    }
938  }
939  void onDispExpr() {
940    switch (State) {
941    default:
942      State = IBES_ERROR;
943      break;
944    case IBES_PLUS:
945    case IBES_MINUS:
946      State = IBES_INTEGER;
947      IC.pushOperand(IC_IMM);
948      break;
949    }
950  }
951  void onInteger(int64_t TmpInt) {
952    switch (State) {
953    default:
954      State = IBES_ERROR;
955      break;
956    case IBES_PLUS:
957    case IBES_MINUS:
958    case IBES_MULTIPLY:
959    case IBES_DIVIDE:
960    case IBES_LPAREN:
961    case IBES_INTEGER_STAR:
962      State = IBES_INTEGER;
963      IC.pushOperand(IC_IMM, TmpInt);
964      break;
965    case IBES_REGISTER_STAR:
966      assert (!IndexReg && "IndexReg already set!");
967      State = IBES_INTEGER;
968      IndexReg = TmpReg;
969      Scale = TmpInt;
970      IC.popOperator();
971      break;
972    }
973  }
974  void onStar() {
975    switch (State) {
976    default:
977      State = IBES_ERROR;
978      break;
979    case IBES_INTEGER:
980      State = IBES_INTEGER_STAR;
981      IC.pushOperator(IC_MULTIPLY);
982      break;
983    case IBES_REGISTER:
984      State = IBES_REGISTER_STAR;
985      IC.pushOperator(IC_MULTIPLY);
986      break;
987    case IBES_RPAREN:
988      State = IBES_MULTIPLY;
989      IC.pushOperator(IC_MULTIPLY);
990      break;
991    }
992  }
993  void onDivide() {
994    switch (State) {
995    default:
996      State = IBES_ERROR;
997      break;
998    case IBES_INTEGER:
999      State = IBES_DIVIDE;
1000      IC.pushOperator(IC_DIVIDE);
1001      break;
1002    }
1003  }
1004  void onLBrac() {
1005    switch (State) {
1006    default:
1007      State = IBES_ERROR;
1008      break;
1009    case IBES_RBRAC:
1010      State = IBES_PLUS;
1011      IC.pushOperator(IC_PLUS);
1012      break;
1013    }
1014  }
1015  void onRBrac() {
1016    switch (State) {
1017    default:
1018      State = IBES_ERROR;
1019      break;
1020    case IBES_RPAREN:
1021    case IBES_INTEGER:
1022      State = IBES_RBRAC;
1023      break;
1024    case IBES_REGISTER:
1025      State = IBES_RBRAC;
1026      // If we already have a BaseReg, then assume this is the IndexReg with a
1027      // scale of 1.
1028      if (!BaseReg) {
1029        BaseReg = TmpReg;
1030      } else {
1031        assert (!IndexReg && "BaseReg/IndexReg already set!");
1032        IndexReg = TmpReg;
1033        Scale = 1;
1034      }
1035      break;
1036    }
1037  }
1038  void onLParen() {
1039    switch (State) {
1040    default:
1041      State = IBES_ERROR;
1042      break;
1043    case IBES_PLUS:
1044    case IBES_MINUS:
1045    case IBES_MULTIPLY:
1046    case IBES_DIVIDE:
1047    case IBES_INTEGER_STAR:
1048    case IBES_LPAREN:
1049      State = IBES_LPAREN;
1050      IC.pushOperator(IC_LPAREN);
1051      break;
1052    }
1053  }
1054  void onRParen() {
1055    switch (State) {
1056    default:
1057      State = IBES_ERROR;
1058      break;
1059    case IBES_REGISTER:
1060    case IBES_INTEGER:
1061    case IBES_PLUS:
1062    case IBES_MINUS:
1063    case IBES_MULTIPLY:
1064    case IBES_DIVIDE:
1065    case IBES_RPAREN:
1066      State = IBES_RPAREN;
1067      IC.pushOperator(IC_RPAREN);
1068      break;
1069    }
1070  }
1071};
1072
1073X86Operand *X86AsmParser::CreateMemForInlineAsm(const MCExpr *Disp, SMLoc Start,
1074                                                SMLoc End, SMLoc SizeDirLoc,
1075                                                unsigned Size, StringRef SymName) {
1076  bool NeedSizeDir = false;
1077  bool IsVarDecl = false;
1078
1079  if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Disp)) {
1080    const MCSymbol &Sym = SymRef->getSymbol();
1081    // FIXME: The SemaLookup will fail if the name is anything other then an
1082    // identifier.
1083    // FIXME: Pass a valid SMLoc.
1084    unsigned tLength, tSize, tType;
1085    SemaCallback->LookupInlineAsmIdentifier(Sym.getName(), NULL, tLength, tSize,
1086                                            tType, IsVarDecl);
1087    if (!Size) {
1088      Size = tType * 8; // Size is in terms of bits in this context.
1089      NeedSizeDir = Size > 0;
1090    }
1091  }
1092
1093  // If this is not a VarDecl then assume it is a FuncDecl or some other label
1094  // reference.  We need an 'r' constraint here, so we need to create register
1095  // operand to ensure proper matching.  Just pick a GPR based on the size of
1096  // a pointer.
1097  if (!IsVarDecl) {
1098    unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1099    return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true, SMLoc(),
1100      SymName);
1101  }
1102
1103  if (NeedSizeDir)
1104    InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, SizeDirLoc,
1105                                                /*Len*/0, Size));
1106
1107  // When parsing inline assembly we set the base register to a non-zero value
1108  // as we don't know the actual value at this time.  This is necessary to
1109  // get the matching correct in some cases.
1110  return X86Operand::CreateMem(/*SegReg*/0, Disp, /*BaseReg*/1, /*IndexReg*/0,
1111                               /*Scale*/1, Start, End, Size, SymName);
1112}
1113
1114X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
1115                                                   SMLoc SizeDirLoc,
1116                                                   uint64_t ImmDisp,
1117                                                   unsigned Size) {
1118  const AsmToken &Tok = Parser.getTok();
1119  SMLoc Start = Tok.getLoc(), End = Tok.getEndLoc();
1120
1121  // Eat '['
1122  if (getLexer().isNot(AsmToken::LBrac))
1123    return ErrorOperand(Start, "Expected '[' token!");
1124  Parser.Lex();
1125
1126  unsigned TmpReg = 0;
1127
1128  // Try to handle '[' 'Symbol' ']'
1129  if (getLexer().is(AsmToken::Identifier)) {
1130    SMLoc Loc = Tok.getLoc();
1131    if (ParseRegister(TmpReg, Loc, End)) {
1132      const MCExpr *Disp;
1133      StringRef Identifier = Tok.getString();
1134      if (getParser().parseExpression(Disp, End))
1135        return 0;
1136
1137      if (X86Operand *Err = ParseIntelVarWithQualifier(Disp, Identifier))
1138        return Err;
1139
1140      if (getLexer().isNot(AsmToken::RBrac))
1141        return ErrorOperand(Tok.getLoc(), "Expected ']' token!");
1142
1143      if (isParsingInlineAsm()) {
1144        // Remove the '[' and ']' from the IR string.
1145        InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, Start, 1));
1146        InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, Tok.getLoc(), 1));
1147      }
1148      Parser.Lex(); // Eat ']'
1149      if (!isParsingInlineAsm())
1150        return X86Operand::CreateMem(Disp, Start, End, Size);
1151      return CreateMemForInlineAsm(Disp, Start, End, SizeDirLoc, Size,
1152                                   Identifier);
1153    }
1154  }
1155
1156  // Parse [ BaseReg + Scale*IndexReg + Disp ].  We may have already parsed an
1157  // immediate displacement before the bracketed expression.
1158  bool Done = false;
1159  IntelBracExprStateMachine SM(Parser, ImmDisp);
1160
1161  // If we parsed a register, then the end loc has already been set and
1162  // the identifier has already been lexed.  We also need to update the
1163  // state.
1164  if (TmpReg)
1165    SM.onRegister(TmpReg);
1166
1167  const MCExpr *Disp = 0;
1168  while (!Done) {
1169    bool UpdateLocLex = true;
1170
1171    // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1172    // identifier.  Don't try an parse it as a register.
1173    if (Tok.getString().startswith("."))
1174      break;
1175
1176    switch (getLexer().getKind()) {
1177    default: {
1178      if (SM.isValidEndState()) {
1179        Done = true;
1180        break;
1181      }
1182      return ErrorOperand(Tok.getLoc(), "Unexpected token!");
1183    }
1184    case AsmToken::Identifier: {
1185      // This could be a register or a displacement expression.
1186      SMLoc Loc = Tok.getLoc();
1187      if(!ParseRegister(TmpReg, Loc, End)) {
1188        SM.onRegister(TmpReg);
1189        UpdateLocLex = false;
1190        break;
1191      } else if (!getParser().parsePrimaryExpr(Disp, End)) {
1192        SM.onDispExpr();
1193        UpdateLocLex = false;
1194        break;
1195      }
1196      return ErrorOperand(Tok.getLoc(), "Unexpected identifier!");
1197    }
1198    case AsmToken::Integer:
1199      if (isParsingInlineAsm())
1200        InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1201                                                    Tok.getLoc()));
1202      SM.onInteger(Tok.getIntVal());
1203      break;
1204    case AsmToken::Plus:    SM.onPlus(); break;
1205    case AsmToken::Minus:   SM.onMinus(); break;
1206    case AsmToken::Star:    SM.onStar(); break;
1207    case AsmToken::Slash:   SM.onDivide(); break;
1208    case AsmToken::LBrac:   SM.onLBrac(); break;
1209    case AsmToken::RBrac:   SM.onRBrac(); break;
1210    case AsmToken::LParen:  SM.onLParen(); break;
1211    case AsmToken::RParen:  SM.onRParen(); break;
1212    }
1213    if (!Done && UpdateLocLex) {
1214      End = Tok.getLoc();
1215      Parser.Lex(); // Consume the token.
1216    }
1217  }
1218  if (isParsingInlineAsm() && Disp && isa<MCSymbolRefExpr>(Disp)) {
1219    // Remove the '[' and ']' from the IR string.
1220    InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, Start, 1));
1221    InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
1222  }
1223
1224  if (!Disp)
1225    Disp = MCConstantExpr::Create(SM.getDisp(), getContext());
1226
1227  // Parse the dot operator (e.g., [ebx].foo.bar).
1228  if (Tok.getString().startswith(".")) {
1229    SmallString<64> Err;
1230    const MCExpr *NewDisp;
1231    if (ParseIntelDotOperator(Disp, &NewDisp, Err))
1232      return ErrorOperand(Tok.getLoc(), Err);
1233
1234    End = Tok.getEndLoc();
1235    Parser.Lex();  // Eat the field.
1236    Disp = NewDisp;
1237  }
1238
1239  int BaseReg = SM.getBaseReg();
1240  int IndexReg = SM.getIndexReg();
1241
1242  // handle [-42]
1243  if (!BaseReg && !IndexReg) {
1244    if (!SegReg)
1245      return X86Operand::CreateMem(Disp, Start, End, Size);
1246    else
1247      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1248  }
1249
1250  int Scale = SM.getScale();
1251  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1252                               End, Size);
1253}
1254
1255// Inline assembly may use variable names with namespace alias qualifiers.
1256X86Operand *X86AsmParser::ParseIntelVarWithQualifier(const MCExpr *&Disp,
1257                                                     StringRef &Identifier) {
1258  // We should only see Foo::Bar if we're parsing inline assembly.
1259  if (!isParsingInlineAsm())
1260    return 0;
1261
1262  // If we don't see a ':' then there can't be a qualifier.
1263  if (getLexer().isNot(AsmToken::Colon))
1264    return 0;
1265
1266  bool Done = false;
1267  const AsmToken &Tok = Parser.getTok();
1268  AsmToken IdentEnd = Tok;
1269  while (!Done) {
1270    switch (getLexer().getKind()) {
1271    default:
1272      Done = true;
1273      break;
1274    case AsmToken::Colon:
1275      getLexer().Lex(); // Consume ':'.
1276      if (getLexer().isNot(AsmToken::Colon))
1277        return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1278      getLexer().Lex(); // Consume second ':'.
1279      if (getLexer().isNot(AsmToken::Identifier))
1280        return ErrorOperand(Tok.getLoc(), "Expected an identifier token!");
1281      break;
1282    case AsmToken::Identifier:
1283      IdentEnd = Tok;
1284      getLexer().Lex(); // Consume the identifier.
1285      break;
1286    }
1287  }
1288
1289  unsigned Len = IdentEnd.getLoc().getPointer() - Identifier.data();
1290  Identifier = StringRef(Identifier.data(), Len + IdentEnd.getString().size());
1291  MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1292  MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1293  Disp = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1294  return 0;
1295}
1296
1297/// ParseIntelMemOperand - Parse intel style memory operand.
1298X86Operand *X86AsmParser::ParseIntelMemOperand(unsigned SegReg,
1299                                               uint64_t ImmDisp,
1300                                               SMLoc Start) {
1301  const AsmToken &Tok = Parser.getTok();
1302  SMLoc End;
1303
1304  unsigned Size = getIntelMemOperandSize(Tok.getString());
1305  if (Size) {
1306    Parser.Lex();
1307    assert ((Tok.getString() == "PTR" || Tok.getString() == "ptr") &&
1308            "Unexpected token!");
1309    Parser.Lex();
1310  }
1311
1312  // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1313  if (getLexer().is(AsmToken::Integer)) {
1314    if (isParsingInlineAsm())
1315      InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1316                                                  Tok.getLoc()));
1317    uint64_t ImmDisp = Tok.getIntVal();
1318    Parser.Lex(); // Eat the integer.
1319    if (getLexer().isNot(AsmToken::LBrac))
1320      return ErrorOperand(Start, "Expected '[' token!");
1321    return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1322  }
1323
1324  if (getLexer().is(AsmToken::LBrac))
1325    return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1326
1327  if (!ParseRegister(SegReg, Start, End)) {
1328    // Handel SegReg : [ ... ]
1329    if (getLexer().isNot(AsmToken::Colon))
1330      return ErrorOperand(Start, "Expected ':' token!");
1331    Parser.Lex(); // Eat :
1332    if (getLexer().isNot(AsmToken::LBrac))
1333      return ErrorOperand(Start, "Expected '[' token!");
1334    return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1335  }
1336
1337  const MCExpr *Disp = 0;
1338  StringRef Identifier = Tok.getString();
1339  if (getParser().parseExpression(Disp, End))
1340    return 0;
1341
1342  if (!isParsingInlineAsm())
1343    return X86Operand::CreateMem(Disp, Start, End, Size);
1344
1345  if (X86Operand *Err = ParseIntelVarWithQualifier(Disp, Identifier))
1346    return Err;
1347
1348  return CreateMemForInlineAsm(Disp, Start, End, Start, Size, Identifier);
1349}
1350
1351/// Parse the '.' operator.
1352bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1353                                         const MCExpr **NewDisp,
1354                                         SmallString<64> &Err) {
1355  const AsmToken &Tok = Parser.getTok();
1356  uint64_t OrigDispVal, DotDispVal;
1357
1358  // FIXME: Handle non-constant expressions.
1359  if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp)) {
1360    OrigDispVal = OrigDisp->getValue();
1361  } else {
1362    Err = "Non-constant offsets are not supported!";
1363    return true;
1364  }
1365
1366  // Drop the '.'.
1367  StringRef DotDispStr = Tok.getString().drop_front(1);
1368
1369  // .Imm gets lexed as a real.
1370  if (Tok.is(AsmToken::Real)) {
1371    APInt DotDisp;
1372    DotDispStr.getAsInteger(10, DotDisp);
1373    DotDispVal = DotDisp.getZExtValue();
1374  } else if (Tok.is(AsmToken::Identifier)) {
1375    // We should only see an identifier when parsing the original inline asm.
1376    // The front-end should rewrite this in terms of immediates.
1377    assert (isParsingInlineAsm() && "Unexpected field name!");
1378
1379    unsigned DotDisp;
1380    std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1381    if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1382                                           DotDisp)) {
1383      Err = "Unable to lookup field reference!";
1384      return true;
1385    }
1386    DotDispVal = DotDisp;
1387  } else {
1388    Err = "Unexpected token type!";
1389    return true;
1390  }
1391
1392  if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1393    SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1394    unsigned Len = DotDispStr.size();
1395    unsigned Val = OrigDispVal + DotDispVal;
1396    InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1397                                                Val));
1398  }
1399
1400  *NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1401  return false;
1402}
1403
1404/// Parse the 'offset' operator.  This operator is used to specify the
1405/// location rather then the content of a variable.
1406X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1407  const AsmToken &Tok = Parser.getTok();
1408  SMLoc OffsetOfLoc = Tok.getLoc();
1409  Parser.Lex(); // Eat offset.
1410  assert (Tok.is(AsmToken::Identifier) && "Expected an identifier");
1411
1412  const MCExpr *Val;
1413  SMLoc Start = Tok.getLoc(), End;
1414  StringRef Identifier = Tok.getString();
1415  if (getParser().parsePrimaryExpr(Val, End))
1416    return ErrorOperand(Start, "Unable to parse expression!");
1417
1418  const MCExpr *Disp = 0;
1419  if (X86Operand *Err = ParseIntelVarWithQualifier(Disp, Identifier))
1420    return Err;
1421
1422  // Don't emit the offset operator.
1423  InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1424
1425  // The offset operator will have an 'r' constraint, thus we need to create
1426  // register operand to ensure proper matching.  Just pick a GPR based on
1427  // the size of a pointer.
1428  unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1429  return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1430                               OffsetOfLoc, Identifier);
1431}
1432
1433enum IntelOperatorKind {
1434  IOK_LENGTH,
1435  IOK_SIZE,
1436  IOK_TYPE
1437};
1438
1439/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators.  The LENGTH operator
1440/// returns the number of elements in an array.  It returns the value 1 for
1441/// non-array variables.  The SIZE operator returns the size of a C or C++
1442/// variable.  A variable's size is the product of its LENGTH and TYPE.  The
1443/// TYPE operator returns the size of a C or C++ type or variable. If the
1444/// variable is an array, TYPE returns the size of a single element.
1445X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1446  const AsmToken &Tok = Parser.getTok();
1447  SMLoc TypeLoc = Tok.getLoc();
1448  Parser.Lex(); // Eat operator.
1449  assert (Tok.is(AsmToken::Identifier) && "Expected an identifier");
1450
1451  const MCExpr *Val;
1452  SMLoc Start = Tok.getLoc(), End;
1453  if (getParser().parsePrimaryExpr(Val, End))
1454    return 0;
1455
1456  unsigned Length = 0, Size = 0, Type = 0;
1457  if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Val)) {
1458    const MCSymbol &Sym = SymRef->getSymbol();
1459    // FIXME: The SemaLookup will fail if the name is anything other then an
1460    // identifier.
1461    // FIXME: Pass a valid SMLoc.
1462    bool IsVarDecl;
1463    if (!SemaCallback->LookupInlineAsmIdentifier(Sym.getName(), NULL, Length,
1464                                                 Size, Type, IsVarDecl))
1465      return ErrorOperand(Start, "Unable to lookup expr!");
1466  }
1467  unsigned CVal;
1468  switch(OpKind) {
1469  default: llvm_unreachable("Unexpected operand kind!");
1470  case IOK_LENGTH: CVal = Length; break;
1471  case IOK_SIZE: CVal = Size; break;
1472  case IOK_TYPE: CVal = Type; break;
1473  }
1474
1475  // Rewrite the type operator and the C or C++ type or variable in terms of an
1476  // immediate.  E.g. TYPE foo -> $$4
1477  unsigned Len = End.getPointer() - TypeLoc.getPointer();
1478  InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1479
1480  const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1481  return X86Operand::CreateImm(Imm, Start, End);
1482}
1483
1484X86Operand *X86AsmParser::ParseIntelOperand() {
1485  const AsmToken &Tok = Parser.getTok();
1486  SMLoc Start = Tok.getLoc(), End;
1487  StringRef AsmTokStr = Tok.getString();
1488
1489  // Offset, length, type and size operators.
1490  if (isParsingInlineAsm()) {
1491    if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1492      return ParseIntelOffsetOfOperator();
1493    if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1494      return ParseIntelOperator(IOK_LENGTH);
1495    if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1496      return ParseIntelOperator(IOK_SIZE);
1497    if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1498      return ParseIntelOperator(IOK_TYPE);
1499  }
1500
1501  // Immediate.
1502  if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
1503      getLexer().is(AsmToken::Minus)) {
1504    const MCExpr *Val;
1505    bool isInteger = getLexer().is(AsmToken::Integer);
1506    if (!getParser().parseExpression(Val, End)) {
1507      if (isParsingInlineAsm())
1508        InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1509      // Immediate.
1510      if (getLexer().isNot(AsmToken::LBrac))
1511        return X86Operand::CreateImm(Val, Start, End);
1512
1513      // Only positive immediates are valid.
1514      if (!isInteger) {
1515        Error(Tok.getLoc(), "expected a positive immediate "
1516              "displacement before bracketed expr.");
1517        return 0;
1518      }
1519
1520      // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1521      if (uint64_t ImmDisp = dyn_cast<MCConstantExpr>(Val)->getValue())
1522        return ParseIntelMemOperand(/*SegReg=*/0, ImmDisp, Start);
1523    }
1524  }
1525
1526  // Register.
1527  unsigned RegNo = 0;
1528  if (!ParseRegister(RegNo, Start, End)) {
1529    // If this is a segment register followed by a ':', then this is the start
1530    // of a memory reference, otherwise this is a normal register reference.
1531    if (getLexer().isNot(AsmToken::Colon))
1532      return X86Operand::CreateReg(RegNo, Start, End);
1533
1534    getParser().Lex(); // Eat the colon.
1535    return ParseIntelMemOperand(/*SegReg=*/RegNo, /*Disp=*/0, Start);
1536  }
1537
1538  // Memory operand.
1539  return ParseIntelMemOperand(/*SegReg=*/0, /*Disp=*/0, Start);
1540}
1541
1542X86Operand *X86AsmParser::ParseATTOperand() {
1543  switch (getLexer().getKind()) {
1544  default:
1545    // Parse a memory operand with no segment register.
1546    return ParseMemOperand(0, Parser.getTok().getLoc());
1547  case AsmToken::Percent: {
1548    // Read the register.
1549    unsigned RegNo;
1550    SMLoc Start, End;
1551    if (ParseRegister(RegNo, Start, End)) return 0;
1552    if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1553      Error(Start, "%eiz and %riz can only be used as index registers",
1554            SMRange(Start, End));
1555      return 0;
1556    }
1557
1558    // If this is a segment register followed by a ':', then this is the start
1559    // of a memory reference, otherwise this is a normal register reference.
1560    if (getLexer().isNot(AsmToken::Colon))
1561      return X86Operand::CreateReg(RegNo, Start, End);
1562
1563    getParser().Lex(); // Eat the colon.
1564    return ParseMemOperand(RegNo, Start);
1565  }
1566  case AsmToken::Dollar: {
1567    // $42 -> immediate.
1568    SMLoc Start = Parser.getTok().getLoc(), End;
1569    Parser.Lex();
1570    const MCExpr *Val;
1571    if (getParser().parseExpression(Val, End))
1572      return 0;
1573    return X86Operand::CreateImm(Val, Start, End);
1574  }
1575  }
1576}
1577
1578/// ParseMemOperand: segment: disp(basereg, indexreg, scale).  The '%ds:' prefix
1579/// has already been parsed if present.
1580X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1581
1582  // We have to disambiguate a parenthesized expression "(4+5)" from the start
1583  // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)".  The
1584  // only way to do this without lookahead is to eat the '(' and see what is
1585  // after it.
1586  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1587  if (getLexer().isNot(AsmToken::LParen)) {
1588    SMLoc ExprEnd;
1589    if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1590
1591    // After parsing the base expression we could either have a parenthesized
1592    // memory address or not.  If not, return now.  If so, eat the (.
1593    if (getLexer().isNot(AsmToken::LParen)) {
1594      // Unless we have a segment register, treat this as an immediate.
1595      if (SegReg == 0)
1596        return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1597      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1598    }
1599
1600    // Eat the '('.
1601    Parser.Lex();
1602  } else {
1603    // Okay, we have a '('.  We don't know if this is an expression or not, but
1604    // so we have to eat the ( to see beyond it.
1605    SMLoc LParenLoc = Parser.getTok().getLoc();
1606    Parser.Lex(); // Eat the '('.
1607
1608    if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1609      // Nothing to do here, fall into the code below with the '(' part of the
1610      // memory operand consumed.
1611    } else {
1612      SMLoc ExprEnd;
1613
1614      // It must be an parenthesized expression, parse it now.
1615      if (getParser().parseParenExpression(Disp, ExprEnd))
1616        return 0;
1617
1618      // After parsing the base expression we could either have a parenthesized
1619      // memory address or not.  If not, return now.  If so, eat the (.
1620      if (getLexer().isNot(AsmToken::LParen)) {
1621        // Unless we have a segment register, treat this as an immediate.
1622        if (SegReg == 0)
1623          return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1624        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1625      }
1626
1627      // Eat the '('.
1628      Parser.Lex();
1629    }
1630  }
1631
1632  // If we reached here, then we just ate the ( of the memory operand.  Process
1633  // the rest of the memory operand.
1634  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1635  SMLoc IndexLoc;
1636
1637  if (getLexer().is(AsmToken::Percent)) {
1638    SMLoc StartLoc, EndLoc;
1639    if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1640    if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1641      Error(StartLoc, "eiz and riz can only be used as index registers",
1642            SMRange(StartLoc, EndLoc));
1643      return 0;
1644    }
1645  }
1646
1647  if (getLexer().is(AsmToken::Comma)) {
1648    Parser.Lex(); // Eat the comma.
1649    IndexLoc = Parser.getTok().getLoc();
1650
1651    // Following the comma we should have either an index register, or a scale
1652    // value. We don't support the later form, but we want to parse it
1653    // correctly.
1654    //
1655    // Not that even though it would be completely consistent to support syntax
1656    // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
1657    if (getLexer().is(AsmToken::Percent)) {
1658      SMLoc L;
1659      if (ParseRegister(IndexReg, L, L)) return 0;
1660
1661      if (getLexer().isNot(AsmToken::RParen)) {
1662        // Parse the scale amount:
1663        //  ::= ',' [scale-expression]
1664        if (getLexer().isNot(AsmToken::Comma)) {
1665          Error(Parser.getTok().getLoc(),
1666                "expected comma in scale expression");
1667          return 0;
1668        }
1669        Parser.Lex(); // Eat the comma.
1670
1671        if (getLexer().isNot(AsmToken::RParen)) {
1672          SMLoc Loc = Parser.getTok().getLoc();
1673
1674          int64_t ScaleVal;
1675          if (getParser().parseAbsoluteExpression(ScaleVal)){
1676            Error(Loc, "expected scale expression");
1677            return 0;
1678          }
1679
1680          // Validate the scale amount.
1681          if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
1682            Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
1683            return 0;
1684          }
1685          Scale = (unsigned)ScaleVal;
1686        }
1687      }
1688    } else if (getLexer().isNot(AsmToken::RParen)) {
1689      // A scale amount without an index is ignored.
1690      // index.
1691      SMLoc Loc = Parser.getTok().getLoc();
1692
1693      int64_t Value;
1694      if (getParser().parseAbsoluteExpression(Value))
1695        return 0;
1696
1697      if (Value != 1)
1698        Warning(Loc, "scale factor without index register is ignored");
1699      Scale = 1;
1700    }
1701  }
1702
1703  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
1704  if (getLexer().isNot(AsmToken::RParen)) {
1705    Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
1706    return 0;
1707  }
1708  SMLoc MemEnd = Parser.getTok().getEndLoc();
1709  Parser.Lex(); // Eat the ')'.
1710
1711  // If we have both a base register and an index register make sure they are
1712  // both 64-bit or 32-bit registers.
1713  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1714  if (BaseReg != 0 && IndexReg != 0) {
1715    if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1716        (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1717         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
1718        IndexReg != X86::RIZ) {
1719      Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
1720      return 0;
1721    }
1722    if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1723        (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1724         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
1725        IndexReg != X86::EIZ){
1726      Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
1727      return 0;
1728    }
1729  }
1730
1731  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1732                               MemStart, MemEnd);
1733}
1734
1735bool X86AsmParser::
1736ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1737                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1738  InstInfo = &Info;
1739  StringRef PatchedName = Name;
1740
1741  // FIXME: Hack to recognize setneb as setne.
1742  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
1743      PatchedName != "setb" && PatchedName != "setnb")
1744    PatchedName = PatchedName.substr(0, Name.size()-1);
1745
1746  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
1747  const MCExpr *ExtraImmOp = 0;
1748  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
1749      (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
1750       PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
1751    bool IsVCMP = PatchedName[0] == 'v';
1752    unsigned SSECCIdx = IsVCMP ? 4 : 3;
1753    unsigned SSEComparisonCode = StringSwitch<unsigned>(
1754      PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1755      .Case("eq",       0x00)
1756      .Case("lt",       0x01)
1757      .Case("le",       0x02)
1758      .Case("unord",    0x03)
1759      .Case("neq",      0x04)
1760      .Case("nlt",      0x05)
1761      .Case("nle",      0x06)
1762      .Case("ord",      0x07)
1763      /* AVX only from here */
1764      .Case("eq_uq",    0x08)
1765      .Case("nge",      0x09)
1766      .Case("ngt",      0x0A)
1767      .Case("false",    0x0B)
1768      .Case("neq_oq",   0x0C)
1769      .Case("ge",       0x0D)
1770      .Case("gt",       0x0E)
1771      .Case("true",     0x0F)
1772      .Case("eq_os",    0x10)
1773      .Case("lt_oq",    0x11)
1774      .Case("le_oq",    0x12)
1775      .Case("unord_s",  0x13)
1776      .Case("neq_us",   0x14)
1777      .Case("nlt_uq",   0x15)
1778      .Case("nle_uq",   0x16)
1779      .Case("ord_s",    0x17)
1780      .Case("eq_us",    0x18)
1781      .Case("nge_uq",   0x19)
1782      .Case("ngt_uq",   0x1A)
1783      .Case("false_os", 0x1B)
1784      .Case("neq_os",   0x1C)
1785      .Case("ge_oq",    0x1D)
1786      .Case("gt_oq",    0x1E)
1787      .Case("true_us",  0x1F)
1788      .Default(~0U);
1789    if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1790      ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1791                                          getParser().getContext());
1792      if (PatchedName.endswith("ss")) {
1793        PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1794      } else if (PatchedName.endswith("sd")) {
1795        PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1796      } else if (PatchedName.endswith("ps")) {
1797        PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1798      } else {
1799        assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1800        PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1801      }
1802    }
1803  }
1804
1805  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1806
1807  if (ExtraImmOp && !isParsingIntelSyntax())
1808    Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1809
1810  // Determine whether this is an instruction prefix.
1811  bool isPrefix =
1812    Name == "lock" || Name == "rep" ||
1813    Name == "repe" || Name == "repz" ||
1814    Name == "repne" || Name == "repnz" ||
1815    Name == "rex64" || Name == "data16";
1816
1817
1818  // This does the actual operand parsing.  Don't parse any more if we have a
1819  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1820  // just want to parse the "lock" as the first instruction and the "incl" as
1821  // the next one.
1822  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1823
1824    // Parse '*' modifier.
1825    if (getLexer().is(AsmToken::Star)) {
1826      SMLoc Loc = Parser.getTok().getLoc();
1827      Operands.push_back(X86Operand::CreateToken("*", Loc));
1828      Parser.Lex(); // Eat the star.
1829    }
1830
1831    // Read the first operand.
1832    if (X86Operand *Op = ParseOperand())
1833      Operands.push_back(Op);
1834    else {
1835      Parser.eatToEndOfStatement();
1836      return true;
1837    }
1838
1839    while (getLexer().is(AsmToken::Comma)) {
1840      Parser.Lex();  // Eat the comma.
1841
1842      // Parse and remember the operand.
1843      if (X86Operand *Op = ParseOperand())
1844        Operands.push_back(Op);
1845      else {
1846        Parser.eatToEndOfStatement();
1847        return true;
1848      }
1849    }
1850
1851    if (getLexer().isNot(AsmToken::EndOfStatement)) {
1852      SMLoc Loc = getLexer().getLoc();
1853      Parser.eatToEndOfStatement();
1854      return Error(Loc, "unexpected token in argument list");
1855    }
1856  }
1857
1858  if (getLexer().is(AsmToken::EndOfStatement))
1859    Parser.Lex(); // Consume the EndOfStatement
1860  else if (isPrefix && getLexer().is(AsmToken::Slash))
1861    Parser.Lex(); // Consume the prefix separator Slash
1862
1863  if (ExtraImmOp && isParsingIntelSyntax())
1864    Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1865
1866  // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1867  // "outb %al, %dx".  Out doesn't take a memory form, but this is a widely
1868  // documented form in various unofficial manuals, so a lot of code uses it.
1869  if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1870      Operands.size() == 3) {
1871    X86Operand &Op = *(X86Operand*)Operands.back();
1872    if (Op.isMem() && Op.Mem.SegReg == 0 &&
1873        isa<MCConstantExpr>(Op.Mem.Disp) &&
1874        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1875        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1876      SMLoc Loc = Op.getEndLoc();
1877      Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1878      delete &Op;
1879    }
1880  }
1881  // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1882  if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1883      Operands.size() == 3) {
1884    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1885    if (Op.isMem() && Op.Mem.SegReg == 0 &&
1886        isa<MCConstantExpr>(Op.Mem.Disp) &&
1887        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1888        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1889      SMLoc Loc = Op.getEndLoc();
1890      Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1891      delete &Op;
1892    }
1893  }
1894  // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1895  if (Name.startswith("ins") && Operands.size() == 3 &&
1896      (Name == "insb" || Name == "insw" || Name == "insl")) {
1897    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1898    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1899    if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1900      Operands.pop_back();
1901      Operands.pop_back();
1902      delete &Op;
1903      delete &Op2;
1904    }
1905  }
1906
1907  // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1908  if (Name.startswith("outs") && Operands.size() == 3 &&
1909      (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1910    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1911    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1912    if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1913      Operands.pop_back();
1914      Operands.pop_back();
1915      delete &Op;
1916      delete &Op2;
1917    }
1918  }
1919
1920  // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1921  if (Name.startswith("movs") && Operands.size() == 3 &&
1922      (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1923       (is64BitMode() && Name == "movsq"))) {
1924    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1925    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1926    if (isSrcOp(Op) && isDstOp(Op2)) {
1927      Operands.pop_back();
1928      Operands.pop_back();
1929      delete &Op;
1930      delete &Op2;
1931    }
1932  }
1933  // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1934  if (Name.startswith("lods") && Operands.size() == 3 &&
1935      (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1936       Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1937    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1938    X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1939    if (isSrcOp(*Op1) && Op2->isReg()) {
1940      const char *ins;
1941      unsigned reg = Op2->getReg();
1942      bool isLods = Name == "lods";
1943      if (reg == X86::AL && (isLods || Name == "lodsb"))
1944        ins = "lodsb";
1945      else if (reg == X86::AX && (isLods || Name == "lodsw"))
1946        ins = "lodsw";
1947      else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1948        ins = "lodsl";
1949      else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1950        ins = "lodsq";
1951      else
1952        ins = NULL;
1953      if (ins != NULL) {
1954        Operands.pop_back();
1955        Operands.pop_back();
1956        delete Op1;
1957        delete Op2;
1958        if (Name != ins)
1959          static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1960      }
1961    }
1962  }
1963  // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1964  if (Name.startswith("stos") && Operands.size() == 3 &&
1965      (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1966       Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1967    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1968    X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1969    if (isDstOp(*Op2) && Op1->isReg()) {
1970      const char *ins;
1971      unsigned reg = Op1->getReg();
1972      bool isStos = Name == "stos";
1973      if (reg == X86::AL && (isStos || Name == "stosb"))
1974        ins = "stosb";
1975      else if (reg == X86::AX && (isStos || Name == "stosw"))
1976        ins = "stosw";
1977      else if (reg == X86::EAX && (isStos || Name == "stosl"))
1978        ins = "stosl";
1979      else if (reg == X86::RAX && (isStos || Name == "stosq"))
1980        ins = "stosq";
1981      else
1982        ins = NULL;
1983      if (ins != NULL) {
1984        Operands.pop_back();
1985        Operands.pop_back();
1986        delete Op1;
1987        delete Op2;
1988        if (Name != ins)
1989          static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1990      }
1991    }
1992  }
1993
1994  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>.  Canonicalize to
1995  // "shift <op>".
1996  if ((Name.startswith("shr") || Name.startswith("sar") ||
1997       Name.startswith("shl") || Name.startswith("sal") ||
1998       Name.startswith("rcl") || Name.startswith("rcr") ||
1999       Name.startswith("rol") || Name.startswith("ror")) &&
2000      Operands.size() == 3) {
2001    if (isParsingIntelSyntax()) {
2002      // Intel syntax
2003      X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2004      if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2005          cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2006        delete Operands[2];
2007        Operands.pop_back();
2008      }
2009    } else {
2010      X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2011      if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2012          cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2013        delete Operands[1];
2014        Operands.erase(Operands.begin() + 1);
2015      }
2016    }
2017  }
2018
2019  // Transforms "int $3" into "int3" as a size optimization.  We can't write an
2020  // instalias with an immediate operand yet.
2021  if (Name == "int" && Operands.size() == 2) {
2022    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2023    if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2024        cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2025      delete Operands[1];
2026      Operands.erase(Operands.begin() + 1);
2027      static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2028    }
2029  }
2030
2031  return false;
2032}
2033
2034static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2035                            bool isCmp) {
2036  MCInst TmpInst;
2037  TmpInst.setOpcode(Opcode);
2038  if (!isCmp)
2039    TmpInst.addOperand(MCOperand::CreateReg(Reg));
2040  TmpInst.addOperand(MCOperand::CreateReg(Reg));
2041  TmpInst.addOperand(Inst.getOperand(0));
2042  Inst = TmpInst;
2043  return true;
2044}
2045
2046static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2047                                bool isCmp = false) {
2048  if (!Inst.getOperand(0).isImm() ||
2049      !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2050    return false;
2051
2052  return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2053}
2054
2055static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2056                                bool isCmp = false) {
2057  if (!Inst.getOperand(0).isImm() ||
2058      !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2059    return false;
2060
2061  return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2062}
2063
2064static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2065                                bool isCmp = false) {
2066  if (!Inst.getOperand(0).isImm() ||
2067      !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2068    return false;
2069
2070  return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2071}
2072
2073bool X86AsmParser::
2074processInstruction(MCInst &Inst,
2075                   const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2076  switch (Inst.getOpcode()) {
2077  default: return false;
2078  case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2079  case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2080  case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2081  case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2082  case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2083  case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2084  case X86::OR16i16:  return convert16i16to16ri8(Inst, X86::OR16ri8);
2085  case X86::OR32i32:  return convert32i32to32ri8(Inst, X86::OR32ri8);
2086  case X86::OR64i32:  return convert64i32to64ri8(Inst, X86::OR64ri8);
2087  case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2088  case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2089  case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2090  case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2091  case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2092  case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2093  case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2094  case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2095  case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2096  case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2097  case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2098  case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2099  case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2100  case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2101  case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2102  }
2103}
2104
2105static const char *getSubtargetFeatureName(unsigned Val);
2106bool X86AsmParser::
2107MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2108                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2109                        MCStreamer &Out, unsigned &ErrorInfo,
2110                        bool MatchingInlineAsm) {
2111  assert(!Operands.empty() && "Unexpect empty operand list!");
2112  X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2113  assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2114  ArrayRef<SMRange> EmptyRanges = ArrayRef<SMRange>();
2115
2116  // First, handle aliases that expand to multiple instructions.
2117  // FIXME: This should be replaced with a real .td file alias mechanism.
2118  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2119  // call.
2120  if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2121      Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2122      Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2123      Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2124    MCInst Inst;
2125    Inst.setOpcode(X86::WAIT);
2126    Inst.setLoc(IDLoc);
2127    if (!MatchingInlineAsm)
2128      Out.EmitInstruction(Inst);
2129
2130    const char *Repl =
2131      StringSwitch<const char*>(Op->getToken())
2132        .Case("finit",  "fninit")
2133        .Case("fsave",  "fnsave")
2134        .Case("fstcw",  "fnstcw")
2135        .Case("fstcww",  "fnstcw")
2136        .Case("fstenv", "fnstenv")
2137        .Case("fstsw",  "fnstsw")
2138        .Case("fstsww", "fnstsw")
2139        .Case("fclex",  "fnclex")
2140        .Default(0);
2141    assert(Repl && "Unknown wait-prefixed instruction");
2142    delete Operands[0];
2143    Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2144  }
2145
2146  bool WasOriginallyInvalidOperand = false;
2147  MCInst Inst;
2148
2149  // First, try a direct match.
2150  switch (MatchInstructionImpl(Operands, Inst,
2151                               ErrorInfo, MatchingInlineAsm,
2152                               isParsingIntelSyntax())) {
2153  default: break;
2154  case Match_Success:
2155    // Some instructions need post-processing to, for example, tweak which
2156    // encoding is selected. Loop on it while changes happen so the
2157    // individual transformations can chain off each other.
2158    if (!MatchingInlineAsm)
2159      while (processInstruction(Inst, Operands))
2160        ;
2161
2162    Inst.setLoc(IDLoc);
2163    if (!MatchingInlineAsm)
2164      Out.EmitInstruction(Inst);
2165    Opcode = Inst.getOpcode();
2166    return false;
2167  case Match_MissingFeature: {
2168    assert(ErrorInfo && "Unknown missing feature!");
2169    // Special case the error message for the very common case where only
2170    // a single subtarget feature is missing.
2171    std::string Msg = "instruction requires:";
2172    unsigned Mask = 1;
2173    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2174      if (ErrorInfo & Mask) {
2175        Msg += " ";
2176        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2177      }
2178      Mask <<= 1;
2179    }
2180    return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2181  }
2182  case Match_InvalidOperand:
2183    WasOriginallyInvalidOperand = true;
2184    break;
2185  case Match_MnemonicFail:
2186    break;
2187  }
2188
2189  // FIXME: Ideally, we would only attempt suffix matches for things which are
2190  // valid prefixes, and we could just infer the right unambiguous
2191  // type. However, that requires substantially more matcher support than the
2192  // following hack.
2193
2194  // Change the operand to point to a temporary token.
2195  StringRef Base = Op->getToken();
2196  SmallString<16> Tmp;
2197  Tmp += Base;
2198  Tmp += ' ';
2199  Op->setTokenValue(Tmp.str());
2200
2201  // If this instruction starts with an 'f', then it is a floating point stack
2202  // instruction.  These come in up to three forms for 32-bit, 64-bit, and
2203  // 80-bit floating point, which use the suffixes s,l,t respectively.
2204  //
2205  // Otherwise, we assume that this may be an integer instruction, which comes
2206  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2207  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2208
2209  // Check for the various suffix matches.
2210  Tmp[Base.size()] = Suffixes[0];
2211  unsigned ErrorInfoIgnore;
2212  unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2213  unsigned Match1, Match2, Match3, Match4;
2214
2215  Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2216                                isParsingIntelSyntax());
2217  // If this returned as a missing feature failure, remember that.
2218  if (Match1 == Match_MissingFeature)
2219    ErrorInfoMissingFeature = ErrorInfoIgnore;
2220  Tmp[Base.size()] = Suffixes[1];
2221  Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2222                                isParsingIntelSyntax());
2223  // If this returned as a missing feature failure, remember that.
2224  if (Match2 == Match_MissingFeature)
2225    ErrorInfoMissingFeature = ErrorInfoIgnore;
2226  Tmp[Base.size()] = Suffixes[2];
2227  Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2228                                isParsingIntelSyntax());
2229  // If this returned as a missing feature failure, remember that.
2230  if (Match3 == Match_MissingFeature)
2231    ErrorInfoMissingFeature = ErrorInfoIgnore;
2232  Tmp[Base.size()] = Suffixes[3];
2233  Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2234                                isParsingIntelSyntax());
2235  // If this returned as a missing feature failure, remember that.
2236  if (Match4 == Match_MissingFeature)
2237    ErrorInfoMissingFeature = ErrorInfoIgnore;
2238
2239  // Restore the old token.
2240  Op->setTokenValue(Base);
2241
2242  // If exactly one matched, then we treat that as a successful match (and the
2243  // instruction will already have been filled in correctly, since the failing
2244  // matches won't have modified it).
2245  unsigned NumSuccessfulMatches =
2246    (Match1 == Match_Success) + (Match2 == Match_Success) +
2247    (Match3 == Match_Success) + (Match4 == Match_Success);
2248  if (NumSuccessfulMatches == 1) {
2249    Inst.setLoc(IDLoc);
2250    if (!MatchingInlineAsm)
2251      Out.EmitInstruction(Inst);
2252    Opcode = Inst.getOpcode();
2253    return false;
2254  }
2255
2256  // Otherwise, the match failed, try to produce a decent error message.
2257
2258  // If we had multiple suffix matches, then identify this as an ambiguous
2259  // match.
2260  if (NumSuccessfulMatches > 1) {
2261    char MatchChars[4];
2262    unsigned NumMatches = 0;
2263    if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2264    if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2265    if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2266    if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2267
2268    SmallString<126> Msg;
2269    raw_svector_ostream OS(Msg);
2270    OS << "ambiguous instructions require an explicit suffix (could be ";
2271    for (unsigned i = 0; i != NumMatches; ++i) {
2272      if (i != 0)
2273        OS << ", ";
2274      if (i + 1 == NumMatches)
2275        OS << "or ";
2276      OS << "'" << Base << MatchChars[i] << "'";
2277    }
2278    OS << ")";
2279    Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2280    return true;
2281  }
2282
2283  // Okay, we know that none of the variants matched successfully.
2284
2285  // If all of the instructions reported an invalid mnemonic, then the original
2286  // mnemonic was invalid.
2287  if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2288      (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2289    if (!WasOriginallyInvalidOperand) {
2290      ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2291        Op->getLocRange();
2292      return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2293                   Ranges, MatchingInlineAsm);
2294    }
2295
2296    // Recover location info for the operand if we know which was the problem.
2297    if (ErrorInfo != ~0U) {
2298      if (ErrorInfo >= Operands.size())
2299        return Error(IDLoc, "too few operands for instruction",
2300                     EmptyRanges, MatchingInlineAsm);
2301
2302      X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2303      if (Operand->getStartLoc().isValid()) {
2304        SMRange OperandRange = Operand->getLocRange();
2305        return Error(Operand->getStartLoc(), "invalid operand for instruction",
2306                     OperandRange, MatchingInlineAsm);
2307      }
2308    }
2309
2310    return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2311                 MatchingInlineAsm);
2312  }
2313
2314  // If one instruction matched with a missing feature, report this as a
2315  // missing feature.
2316  if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2317      (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2318    std::string Msg = "instruction requires:";
2319    unsigned Mask = 1;
2320    for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2321      if (ErrorInfoMissingFeature & Mask) {
2322        Msg += " ";
2323        Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2324      }
2325      Mask <<= 1;
2326    }
2327    return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2328  }
2329
2330  // If one instruction matched with an invalid operand, report this as an
2331  // operand failure.
2332  if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2333      (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2334    Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2335          MatchingInlineAsm);
2336    return true;
2337  }
2338
2339  // If all of these were an outright failure, report it in a useless way.
2340  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2341        EmptyRanges, MatchingInlineAsm);
2342  return true;
2343}
2344
2345
2346bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2347  StringRef IDVal = DirectiveID.getIdentifier();
2348  if (IDVal == ".word")
2349    return ParseDirectiveWord(2, DirectiveID.getLoc());
2350  else if (IDVal.startswith(".code"))
2351    return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2352  else if (IDVal.startswith(".att_syntax")) {
2353    getParser().setAssemblerDialect(0);
2354    return false;
2355  } else if (IDVal.startswith(".intel_syntax")) {
2356    getParser().setAssemblerDialect(1);
2357    if (getLexer().isNot(AsmToken::EndOfStatement)) {
2358      if(Parser.getTok().getString() == "noprefix") {
2359        // FIXME : Handle noprefix
2360        Parser.Lex();
2361      } else
2362        return true;
2363    }
2364    return false;
2365  }
2366  return true;
2367}
2368
2369/// ParseDirectiveWord
2370///  ::= .word [ expression (, expression)* ]
2371bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2372  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2373    for (;;) {
2374      const MCExpr *Value;
2375      if (getParser().parseExpression(Value))
2376        return true;
2377
2378      getParser().getStreamer().EmitValue(Value, Size);
2379
2380      if (getLexer().is(AsmToken::EndOfStatement))
2381        break;
2382
2383      // FIXME: Improve diagnostic.
2384      if (getLexer().isNot(AsmToken::Comma))
2385        return Error(L, "unexpected token in directive");
2386      Parser.Lex();
2387    }
2388  }
2389
2390  Parser.Lex();
2391  return false;
2392}
2393
2394/// ParseDirectiveCode
2395///  ::= .code32 | .code64
2396bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2397  if (IDVal == ".code32") {
2398    Parser.Lex();
2399    if (is64BitMode()) {
2400      SwitchMode();
2401      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2402    }
2403  } else if (IDVal == ".code64") {
2404    Parser.Lex();
2405    if (!is64BitMode()) {
2406      SwitchMode();
2407      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2408    }
2409  } else {
2410    return Error(L, "unexpected directive " + IDVal);
2411  }
2412
2413  return false;
2414}
2415
2416// Force static initialization.
2417extern "C" void LLVMInitializeX86AsmParser() {
2418  RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2419  RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2420}
2421
2422#define GET_REGISTER_MATCHER
2423#define GET_MATCHER_IMPLEMENTATION
2424#define GET_SUBTARGET_FEATURE_NAME
2425#include "X86GenAsmMatcher.inc"
2426