X86AsmParser.cpp revision f9e008bf673a8eeb04766bfc99f51068608809d2 
1//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/X86BaseInfo.h"
11#include "llvm/MC/MCTargetAsmParser.h"
12#include "llvm/MC/MCStreamer.h"
13#include "llvm/MC/MCExpr.h"
14#include "llvm/MC/MCInst.h"
15#include "llvm/MC/MCRegisterInfo.h"
16#include "llvm/MC/MCSubtargetInfo.h"
17#include "llvm/MC/MCParser/MCAsmLexer.h"
18#include "llvm/MC/MCParser/MCAsmParser.h"
19#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20#include "llvm/ADT/SmallString.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/ADT/Twine.h"
24#include "llvm/Support/SourceMgr.h"
25#include "llvm/Support/TargetRegistry.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30namespace {
31struct X86Operand;
32
33class X86AsmParser : public MCTargetAsmParser {
34  MCSubtargetInfo &STI;
35  MCAsmParser &Parser;
36private:
37  MCAsmParser &getParser() const { return Parser; }
38
39  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
40
41  bool Error(SMLoc L, const Twine &Msg,
42             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(),
43             bool matchingInlineAsm = false) {
44    if (matchingInlineAsm) return true;
45    return Parser.Error(L, Msg, Ranges);
46  }
47
48  X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
49    Error(Loc, Msg);
50    return 0;
51  }
52
53  X86Operand *ParseOperand();
54  X86Operand *ParseATTOperand();
55  X86Operand *ParseIntelOperand();
56  X86Operand *ParseIntelMemOperand();
57  X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
58  X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
59
60  bool ParseDirectiveWord(unsigned Size, SMLoc L);
61  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
62
63  bool processInstruction(MCInst &Inst,
64                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
65
66  bool MatchAndEmitInstruction(SMLoc IDLoc,
67                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
68                               MCStreamer &Out);
69  bool MatchInstruction(SMLoc IDLoc,
70                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71                        MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
72  SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,
73                       unsigned &OrigErrorInfo, bool matchingInlineAsm = false);
74
75  /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
76  /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
77  bool isSrcOp(X86Operand &Op);
78
79  /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
80  /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
81  bool isDstOp(X86Operand &Op);
82
83  bool is64BitMode() const {
84    // FIXME: Can tablegen auto-generate this?
85    return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
86  }
87  void SwitchMode() {
88    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
89    setAvailableFeatures(FB);
90  }
91
92  /// @name Auto-generated Matcher Functions
93  /// {
94
95#define GET_ASSEMBLER_HEADER
96#include "X86GenAsmMatcher.inc"
97
98  /// }
99
100public:
101  X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
102    : MCTargetAsmParser(), STI(sti), Parser(parser) {
103
104    // Initialize the set of available features.
105    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
106  }
107  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
108
109  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
110                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
111
112  virtual bool ParseDirective(AsmToken DirectiveID);
113
114  bool isParsingIntelSyntax() {
115    return getParser().getAssemblerDialect();
116  }
117};
118} // end anonymous namespace
119
120/// @name Auto-generated Match Functions
121/// {
122
123static unsigned MatchRegisterName(StringRef Name);
124
125/// }
126
127static bool isImmSExti16i8Value(uint64_t Value) {
128  return ((                                  Value <= 0x000000000000007FULL)||
129          (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
130          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
131}
132
133static bool isImmSExti32i8Value(uint64_t Value) {
134  return ((                                  Value <= 0x000000000000007FULL)||
135          (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
136          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
137}
138
139static bool isImmZExtu32u8Value(uint64_t Value) {
140    return (Value <= 0x00000000000000FFULL);
141}
142
143static bool isImmSExti64i8Value(uint64_t Value) {
144  return ((                                  Value <= 0x000000000000007FULL)||
145          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
146}
147
148static bool isImmSExti64i32Value(uint64_t Value) {
149  return ((                                  Value <= 0x000000007FFFFFFFULL)||
150          (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
151}
152namespace {
153
154/// X86Operand - Instances of this class represent a parsed X86 machine
155/// instruction.
156struct X86Operand : public MCParsedAsmOperand {
157  enum KindTy {
158    Token,
159    Register,
160    Immediate,
161    Memory
162  } Kind;
163
164  SMLoc StartLoc, EndLoc;
165
166  union {
167    struct {
168      const char *Data;
169      unsigned Length;
170    } Tok;
171
172    struct {
173      unsigned RegNo;
174    } Reg;
175
176    struct {
177      const MCExpr *Val;
178    } Imm;
179
180    struct {
181      unsigned SegReg;
182      const MCExpr *Disp;
183      unsigned BaseReg;
184      unsigned IndexReg;
185      unsigned Scale;
186      unsigned Size;
187    } Mem;
188  };
189
190  X86Operand(KindTy K, SMLoc Start, SMLoc End)
191    : Kind(K), StartLoc(Start), EndLoc(End) {}
192
193  /// getStartLoc - Get the location of the first token of this operand.
194  SMLoc getStartLoc() const { return StartLoc; }
195  /// getEndLoc - Get the location of the last token of this operand.
196  SMLoc getEndLoc() const { return EndLoc; }
197  /// getLocRange - Get the range between the first and last token of this
198  /// operand.
199  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
200
201  virtual void print(raw_ostream &OS) const {}
202
203  StringRef getToken() const {
204    assert(Kind == Token && "Invalid access!");
205    return StringRef(Tok.Data, Tok.Length);
206  }
207  void setTokenValue(StringRef Value) {
208    assert(Kind == Token && "Invalid access!");
209    Tok.Data = Value.data();
210    Tok.Length = Value.size();
211  }
212
213  unsigned getReg() const {
214    assert(Kind == Register && "Invalid access!");
215    return Reg.RegNo;
216  }
217
218  const MCExpr *getImm() const {
219    assert(Kind == Immediate && "Invalid access!");
220    return Imm.Val;
221  }
222
223  const MCExpr *getMemDisp() const {
224    assert(Kind == Memory && "Invalid access!");
225    return Mem.Disp;
226  }
227  unsigned getMemSegReg() const {
228    assert(Kind == Memory && "Invalid access!");
229    return Mem.SegReg;
230  }
231  unsigned getMemBaseReg() const {
232    assert(Kind == Memory && "Invalid access!");
233    return Mem.BaseReg;
234  }
235  unsigned getMemIndexReg() const {
236    assert(Kind == Memory && "Invalid access!");
237    return Mem.IndexReg;
238  }
239  unsigned getMemScale() const {
240    assert(Kind == Memory && "Invalid access!");
241    return Mem.Scale;
242  }
243
244  bool isToken() const {return Kind == Token; }
245
246  bool isImm() const { return Kind == Immediate; }
247
248  bool isImmSExti16i8() const {
249    if (!isImm())
250      return false;
251
252    // If this isn't a constant expr, just assume it fits and let relaxation
253    // handle it.
254    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
255    if (!CE)
256      return true;
257
258    // Otherwise, check the value is in a range that makes sense for this
259    // extension.
260    return isImmSExti16i8Value(CE->getValue());
261  }
262  bool isImmSExti32i8() const {
263    if (!isImm())
264      return false;
265
266    // If this isn't a constant expr, just assume it fits and let relaxation
267    // handle it.
268    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
269    if (!CE)
270      return true;
271
272    // Otherwise, check the value is in a range that makes sense for this
273    // extension.
274    return isImmSExti32i8Value(CE->getValue());
275  }
276  bool isImmZExtu32u8() const {
277    if (!isImm())
278      return false;
279
280    // If this isn't a constant expr, just assume it fits and let relaxation
281    // handle it.
282    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
283    if (!CE)
284      return true;
285
286    // Otherwise, check the value is in a range that makes sense for this
287    // extension.
288    return isImmZExtu32u8Value(CE->getValue());
289  }
290  bool isImmSExti64i8() const {
291    if (!isImm())
292      return false;
293
294    // If this isn't a constant expr, just assume it fits and let relaxation
295    // handle it.
296    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
297    if (!CE)
298      return true;
299
300    // Otherwise, check the value is in a range that makes sense for this
301    // extension.
302    return isImmSExti64i8Value(CE->getValue());
303  }
304  bool isImmSExti64i32() const {
305    if (!isImm())
306      return false;
307
308    // If this isn't a constant expr, just assume it fits and let relaxation
309    // handle it.
310    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
311    if (!CE)
312      return true;
313
314    // Otherwise, check the value is in a range that makes sense for this
315    // extension.
316    return isImmSExti64i32Value(CE->getValue());
317  }
318
319  bool isMem() const { return Kind == Memory; }
320  bool isMem8() const {
321    return Kind == Memory && (!Mem.Size || Mem.Size == 8);
322  }
323  bool isMem16() const {
324    return Kind == Memory && (!Mem.Size || Mem.Size == 16);
325  }
326  bool isMem32() const {
327    return Kind == Memory && (!Mem.Size || Mem.Size == 32);
328  }
329  bool isMem64() const {
330    return Kind == Memory && (!Mem.Size || Mem.Size == 64);
331  }
332  bool isMem80() const {
333    return Kind == Memory && (!Mem.Size || Mem.Size == 80);
334  }
335  bool isMem128() const {
336    return Kind == Memory && (!Mem.Size || Mem.Size == 128);
337  }
338  bool isMem256() const {
339    return Kind == Memory && (!Mem.Size || Mem.Size == 256);
340  }
341
342  bool isMemVX32() const {
343    return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
344      getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
345  }
346  bool isMemVY32() const {
347    return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
348      getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
349  }
350  bool isMemVX64() const {
351    return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
352      getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
353  }
354  bool isMemVY64() const {
355    return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
356      getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
357  }
358
359  bool isAbsMem() const {
360    return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
361      !getMemIndexReg() && getMemScale() == 1;
362  }
363
364  bool isReg() const { return Kind == Register; }
365
366  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
367    // Add as immediates when possible.
368    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
369      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
370    else
371      Inst.addOperand(MCOperand::CreateExpr(Expr));
372  }
373
374  void addRegOperands(MCInst &Inst, unsigned N) const {
375    assert(N == 1 && "Invalid number of operands!");
376    Inst.addOperand(MCOperand::CreateReg(getReg()));
377  }
378
379  void addImmOperands(MCInst &Inst, unsigned N) const {
380    assert(N == 1 && "Invalid number of operands!");
381    addExpr(Inst, getImm());
382  }
383
384  void addMem8Operands(MCInst &Inst, unsigned N) const {
385    addMemOperands(Inst, N);
386  }
387  void addMem16Operands(MCInst &Inst, unsigned N) const {
388    addMemOperands(Inst, N);
389  }
390  void addMem32Operands(MCInst &Inst, unsigned N) const {
391    addMemOperands(Inst, N);
392  }
393  void addMem64Operands(MCInst &Inst, unsigned N) const {
394    addMemOperands(Inst, N);
395  }
396  void addMem80Operands(MCInst &Inst, unsigned N) const {
397    addMemOperands(Inst, N);
398  }
399  void addMem128Operands(MCInst &Inst, unsigned N) const {
400    addMemOperands(Inst, N);
401  }
402  void addMem256Operands(MCInst &Inst, unsigned N) const {
403    addMemOperands(Inst, N);
404  }
405  void addMemVX32Operands(MCInst &Inst, unsigned N) const {
406    addMemOperands(Inst, N);
407  }
408  void addMemVY32Operands(MCInst &Inst, unsigned N) const {
409    addMemOperands(Inst, N);
410  }
411  void addMemVX64Operands(MCInst &Inst, unsigned N) const {
412    addMemOperands(Inst, N);
413  }
414  void addMemVY64Operands(MCInst &Inst, unsigned N) const {
415    addMemOperands(Inst, N);
416  }
417
418  void addMemOperands(MCInst &Inst, unsigned N) const {
419    assert((N == 5) && "Invalid number of operands!");
420    Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
421    Inst.addOperand(MCOperand::CreateImm(getMemScale()));
422    Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
423    addExpr(Inst, getMemDisp());
424    Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
425  }
426
427  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
428    assert((N == 1) && "Invalid number of operands!");
429    // Add as immediates when possible.
430    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
431      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
432    else
433      Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
434  }
435
436  static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
437    SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size() - 1);
438    X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
439    Res->Tok.Data = Str.data();
440    Res->Tok.Length = Str.size();
441    return Res;
442  }
443
444  static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
445    X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
446    Res->Reg.RegNo = RegNo;
447    return Res;
448  }
449
450  static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
451    X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
452    Res->Imm.Val = Val;
453    return Res;
454  }
455
456  /// Create an absolute memory operand.
457  static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
458                               SMLoc EndLoc, unsigned Size = 0) {
459    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
460    Res->Mem.SegReg   = 0;
461    Res->Mem.Disp     = Disp;
462    Res->Mem.BaseReg  = 0;
463    Res->Mem.IndexReg = 0;
464    Res->Mem.Scale    = 1;
465    Res->Mem.Size     = Size;
466    return Res;
467  }
468
469  /// Create a generalized memory operand.
470  static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
471                               unsigned BaseReg, unsigned IndexReg,
472                               unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
473                               unsigned Size = 0) {
474    // We should never just have a displacement, that should be parsed as an
475    // absolute memory operand.
476    assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
477
478    // The scale should always be one of {1,2,4,8}.
479    assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
480           "Invalid scale!");
481    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
482    Res->Mem.SegReg   = SegReg;
483    Res->Mem.Disp     = Disp;
484    Res->Mem.BaseReg  = BaseReg;
485    Res->Mem.IndexReg = IndexReg;
486    Res->Mem.Scale    = Scale;
487    Res->Mem.Size     = Size;
488    return Res;
489  }
490};
491
492} // end anonymous namespace.
493
494bool X86AsmParser::isSrcOp(X86Operand &Op) {
495  unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
496
497  return (Op.isMem() &&
498    (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
499    isa<MCConstantExpr>(Op.Mem.Disp) &&
500    cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
501    Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
502}
503
504bool X86AsmParser::isDstOp(X86Operand &Op) {
505  unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
506
507  return Op.isMem() &&
508    (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
509    isa<MCConstantExpr>(Op.Mem.Disp) &&
510    cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
511    Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
512}
513
514bool X86AsmParser::ParseRegister(unsigned &RegNo,
515                                 SMLoc &StartLoc, SMLoc &EndLoc) {
516  RegNo = 0;
517  const AsmToken &PercentTok = Parser.getTok();
518  StartLoc = PercentTok.getLoc();
519
520  // If we encounter a %, ignore it. This code handles registers with and
521  // without the prefix, unprefixed registers can occur in cfi directives.
522  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
523    Parser.Lex(); // Eat percent token.
524
525  const AsmToken &Tok = Parser.getTok();
526  if (Tok.isNot(AsmToken::Identifier)) {
527    if (isParsingIntelSyntax()) return true;
528    return Error(StartLoc, "invalid register name",
529                 SMRange(StartLoc, Tok.getEndLoc()));
530  }
531
532  RegNo = MatchRegisterName(Tok.getString());
533
534  // If the match failed, try the register name as lowercase.
535  if (RegNo == 0)
536    RegNo = MatchRegisterName(Tok.getString().lower());
537
538  if (!is64BitMode()) {
539    // FIXME: This should be done using Requires<In32BitMode> and
540    // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
541    // checked.
542    // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
543    // REX prefix.
544    if (RegNo == X86::RIZ ||
545        X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
546        X86II::isX86_64NonExtLowByteReg(RegNo) ||
547        X86II::isX86_64ExtendedReg(RegNo))
548      return Error(StartLoc, "register %"
549                   + Tok.getString() + " is only available in 64-bit mode",
550                   SMRange(StartLoc, Tok.getEndLoc()));
551  }
552
553  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
554  if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
555    RegNo = X86::ST0;
556    EndLoc = Tok.getLoc();
557    Parser.Lex(); // Eat 'st'
558
559    // Check to see if we have '(4)' after %st.
560    if (getLexer().isNot(AsmToken::LParen))
561      return false;
562    // Lex the paren.
563    getParser().Lex();
564
565    const AsmToken &IntTok = Parser.getTok();
566    if (IntTok.isNot(AsmToken::Integer))
567      return Error(IntTok.getLoc(), "expected stack index");
568    switch (IntTok.getIntVal()) {
569    case 0: RegNo = X86::ST0; break;
570    case 1: RegNo = X86::ST1; break;
571    case 2: RegNo = X86::ST2; break;
572    case 3: RegNo = X86::ST3; break;
573    case 4: RegNo = X86::ST4; break;
574    case 5: RegNo = X86::ST5; break;
575    case 6: RegNo = X86::ST6; break;
576    case 7: RegNo = X86::ST7; break;
577    default: return Error(IntTok.getLoc(), "invalid stack index");
578    }
579
580    if (getParser().Lex().isNot(AsmToken::RParen))
581      return Error(Parser.getTok().getLoc(), "expected ')'");
582
583    EndLoc = Tok.getLoc();
584    Parser.Lex(); // Eat ')'
585    return false;
586  }
587
588  // If this is "db[0-7]", match it as an alias
589  // for dr[0-7].
590  if (RegNo == 0 && Tok.getString().size() == 3 &&
591      Tok.getString().startswith("db")) {
592    switch (Tok.getString()[2]) {
593    case '0': RegNo = X86::DR0; break;
594    case '1': RegNo = X86::DR1; break;
595    case '2': RegNo = X86::DR2; break;
596    case '3': RegNo = X86::DR3; break;
597    case '4': RegNo = X86::DR4; break;
598    case '5': RegNo = X86::DR5; break;
599    case '6': RegNo = X86::DR6; break;
600    case '7': RegNo = X86::DR7; break;
601    }
602
603    if (RegNo != 0) {
604      EndLoc = Tok.getLoc();
605      Parser.Lex(); // Eat it.
606      return false;
607    }
608  }
609
610  if (RegNo == 0) {
611    if (isParsingIntelSyntax()) return true;
612    return Error(StartLoc, "invalid register name",
613                 SMRange(StartLoc, Tok.getEndLoc()));
614  }
615
616  EndLoc = Tok.getEndLoc();
617  Parser.Lex(); // Eat identifier token.
618  return false;
619}
620
621X86Operand *X86AsmParser::ParseOperand() {
622  if (isParsingIntelSyntax())
623    return ParseIntelOperand();
624  return ParseATTOperand();
625}
626
627/// getIntelMemOperandSize - Return intel memory operand size.
628static unsigned getIntelMemOperandSize(StringRef OpStr) {
629  unsigned Size = StringSwitch<unsigned>(OpStr)
630    .Cases("BYTE", "byte", 8)
631    .Cases("WORD", "word", 16)
632    .Cases("DWORD", "dword", 32)
633    .Cases("QWORD", "qword", 64)
634    .Cases("XWORD", "xword", 80)
635    .Cases("XMMWORD", "xmmword", 128)
636    .Cases("YMMWORD", "ymmword", 256)
637    .Default(0);
638  return Size;
639}
640
641X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
642                                                   unsigned Size) {
643  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
644  SMLoc Start = Parser.getTok().getLoc(), End;
645
646  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
647  // Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
648
649  // Eat '['
650  if (getLexer().isNot(AsmToken::LBrac))
651    return ErrorOperand(Start, "Expected '[' token!");
652  Parser.Lex();
653
654  if (getLexer().is(AsmToken::Identifier)) {
655    // Parse BaseReg
656    if (ParseRegister(BaseReg, Start, End)) {
657      // Handle '[' 'symbol' ']'
658      if (getParser().ParseExpression(Disp, End)) return 0;
659      if (getLexer().isNot(AsmToken::RBrac))
660        return ErrorOperand(Start, "Expected ']' token!");
661      Parser.Lex();
662      return X86Operand::CreateMem(Disp, Start, End, Size);
663    }
664  } else if (getLexer().is(AsmToken::Integer)) {
665      int64_t Val = Parser.getTok().getIntVal();
666      Parser.Lex();
667      SMLoc Loc = Parser.getTok().getLoc();
668      if (getLexer().is(AsmToken::RBrac)) {
669        // Handle '[' number ']'
670        Parser.Lex();
671        const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
672        if (SegReg)
673          return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
674                                       Start, End, Size);
675        return X86Operand::CreateMem(Disp, Start, End, Size);
676      } else if (getLexer().is(AsmToken::Star)) {
677        // Handle '[' Scale*IndexReg ']'
678        Parser.Lex();
679        SMLoc IdxRegLoc = Parser.getTok().getLoc();
680        if (ParseRegister(IndexReg, IdxRegLoc, End))
681          return ErrorOperand(IdxRegLoc, "Expected register");
682        Scale = Val;
683      } else
684        return ErrorOperand(Loc, "Unexpected token");
685  }
686
687  if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus)) {
688    bool isPlus = getLexer().is(AsmToken::Plus);
689    Parser.Lex();
690    SMLoc PlusLoc = Parser.getTok().getLoc();
691    if (getLexer().is(AsmToken::Integer)) {
692      int64_t Val = Parser.getTok().getIntVal();
693      Parser.Lex();
694      if (getLexer().is(AsmToken::Star)) {
695        Parser.Lex();
696        SMLoc IdxRegLoc = Parser.getTok().getLoc();
697        if (ParseRegister(IndexReg, IdxRegLoc, End))
698          return ErrorOperand(IdxRegLoc, "Expected register");
699        Scale = Val;
700      } else if (getLexer().is(AsmToken::RBrac)) {
701        const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
702        Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
703      } else
704        return ErrorOperand(PlusLoc, "unexpected token after +");
705    } else if (getLexer().is(AsmToken::Identifier)) {
706      // This could be an index register or a displacement expression.
707      End = Parser.getTok().getLoc();
708      if (!IndexReg)
709        ParseRegister(IndexReg, Start, End);
710      else if (getParser().ParseExpression(Disp, End)) return 0;
711    }
712  }
713
714  if (getLexer().isNot(AsmToken::RBrac))
715    if (getParser().ParseExpression(Disp, End)) return 0;
716
717  End = Parser.getTok().getLoc();
718  if (getLexer().isNot(AsmToken::RBrac))
719    return ErrorOperand(End, "expected ']' token!");
720  Parser.Lex();
721  End = Parser.getTok().getLoc();
722
723  // handle [-42]
724  if (!BaseReg && !IndexReg)
725    return X86Operand::CreateMem(Disp, Start, End, Size);
726
727  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
728                               Start, End, Size);
729}
730
731/// ParseIntelMemOperand - Parse intel style memory operand.
732X86Operand *X86AsmParser::ParseIntelMemOperand() {
733  const AsmToken &Tok = Parser.getTok();
734  SMLoc Start = Parser.getTok().getLoc(), End;
735  unsigned SegReg = 0;
736
737  unsigned Size = getIntelMemOperandSize(Tok.getString());
738  if (Size) {
739    Parser.Lex();
740    assert ((Tok.getString() == "PTR" || Tok.getString() == "ptr") &&
741            "Unexpected token!");
742    Parser.Lex();
743  }
744
745  if (getLexer().is(AsmToken::LBrac))
746    return ParseIntelBracExpression(SegReg, Size);
747
748  if (!ParseRegister(SegReg, Start, End)) {
749    // Handel SegReg : [ ... ]
750    if (getLexer().isNot(AsmToken::Colon))
751      return ErrorOperand(Start, "Expected ':' token!");
752    Parser.Lex(); // Eat :
753    if (getLexer().isNot(AsmToken::LBrac))
754      return ErrorOperand(Start, "Expected '[' token!");
755    return ParseIntelBracExpression(SegReg, Size);
756  }
757
758  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
759  if (getParser().ParseExpression(Disp, End)) return 0;
760  return X86Operand::CreateMem(Disp, Start, End, Size);
761}
762
763X86Operand *X86AsmParser::ParseIntelOperand() {
764  SMLoc Start = Parser.getTok().getLoc(), End;
765
766  // immediate.
767  if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
768      getLexer().is(AsmToken::Minus)) {
769    const MCExpr *Val;
770    if (!getParser().ParseExpression(Val, End)) {
771      End = Parser.getTok().getLoc();
772      return X86Operand::CreateImm(Val, Start, End);
773    }
774  }
775
776  // register
777  unsigned RegNo = 0;
778  if (!ParseRegister(RegNo, Start, End)) {
779    End = Parser.getTok().getLoc();
780    return X86Operand::CreateReg(RegNo, Start, End);
781  }
782
783  // mem operand
784  return ParseIntelMemOperand();
785}
786
787X86Operand *X86AsmParser::ParseATTOperand() {
788  switch (getLexer().getKind()) {
789  default:
790    // Parse a memory operand with no segment register.
791    return ParseMemOperand(0, Parser.getTok().getLoc());
792  case AsmToken::Percent: {
793    // Read the register.
794    unsigned RegNo;
795    SMLoc Start, End;
796    if (ParseRegister(RegNo, Start, End)) return 0;
797    if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
798      Error(Start, "%eiz and %riz can only be used as index registers",
799            SMRange(Start, End));
800      return 0;
801    }
802
803    // If this is a segment register followed by a ':', then this is the start
804    // of a memory reference, otherwise this is a normal register reference.
805    if (getLexer().isNot(AsmToken::Colon))
806      return X86Operand::CreateReg(RegNo, Start, End);
807
808
809    getParser().Lex(); // Eat the colon.
810    return ParseMemOperand(RegNo, Start);
811  }
812  case AsmToken::Dollar: {
813    // $42 -> immediate.
814    SMLoc Start = Parser.getTok().getLoc(), End;
815    Parser.Lex();
816    const MCExpr *Val;
817    if (getParser().ParseExpression(Val, End))
818      return 0;
819    return X86Operand::CreateImm(Val, Start, End);
820  }
821  }
822}
823
824/// ParseMemOperand: segment: disp(basereg, indexreg, scale).  The '%ds:' prefix
825/// has already been parsed if present.
826X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
827
828  // We have to disambiguate a parenthesized expression "(4+5)" from the start
829  // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)".  The
830  // only way to do this without lookahead is to eat the '(' and see what is
831  // after it.
832  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
833  if (getLexer().isNot(AsmToken::LParen)) {
834    SMLoc ExprEnd;
835    if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
836
837    // After parsing the base expression we could either have a parenthesized
838    // memory address or not.  If not, return now.  If so, eat the (.
839    if (getLexer().isNot(AsmToken::LParen)) {
840      // Unless we have a segment register, treat this as an immediate.
841      if (SegReg == 0)
842        return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
843      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
844    }
845
846    // Eat the '('.
847    Parser.Lex();
848  } else {
849    // Okay, we have a '('.  We don't know if this is an expression or not, but
850    // so we have to eat the ( to see beyond it.
851    SMLoc LParenLoc = Parser.getTok().getLoc();
852    Parser.Lex(); // Eat the '('.
853
854    if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
855      // Nothing to do here, fall into the code below with the '(' part of the
856      // memory operand consumed.
857    } else {
858      SMLoc ExprEnd;
859
860      // It must be an parenthesized expression, parse it now.
861      if (getParser().ParseParenExpression(Disp, ExprEnd))
862        return 0;
863
864      // After parsing the base expression we could either have a parenthesized
865      // memory address or not.  If not, return now.  If so, eat the (.
866      if (getLexer().isNot(AsmToken::LParen)) {
867        // Unless we have a segment register, treat this as an immediate.
868        if (SegReg == 0)
869          return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
870        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
871      }
872
873      // Eat the '('.
874      Parser.Lex();
875    }
876  }
877
878  // If we reached here, then we just ate the ( of the memory operand.  Process
879  // the rest of the memory operand.
880  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
881  SMLoc IndexLoc;
882
883  if (getLexer().is(AsmToken::Percent)) {
884    SMLoc StartLoc, EndLoc;
885    if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
886    if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
887      Error(StartLoc, "eiz and riz can only be used as index registers",
888            SMRange(StartLoc, EndLoc));
889      return 0;
890    }
891  }
892
893  if (getLexer().is(AsmToken::Comma)) {
894    Parser.Lex(); // Eat the comma.
895    IndexLoc = Parser.getTok().getLoc();
896
897    // Following the comma we should have either an index register, or a scale
898    // value. We don't support the later form, but we want to parse it
899    // correctly.
900    //
901    // Not that even though it would be completely consistent to support syntax
902    // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
903    if (getLexer().is(AsmToken::Percent)) {
904      SMLoc L;
905      if (ParseRegister(IndexReg, L, L)) return 0;
906
907      if (getLexer().isNot(AsmToken::RParen)) {
908        // Parse the scale amount:
909        //  ::= ',' [scale-expression]
910        if (getLexer().isNot(AsmToken::Comma)) {
911          Error(Parser.getTok().getLoc(),
912                "expected comma in scale expression");
913          return 0;
914        }
915        Parser.Lex(); // Eat the comma.
916
917        if (getLexer().isNot(AsmToken::RParen)) {
918          SMLoc Loc = Parser.getTok().getLoc();
919
920          int64_t ScaleVal;
921          if (getParser().ParseAbsoluteExpression(ScaleVal)){
922            Error(Loc, "expected scale expression");
923            return 0;
924          }
925
926          // Validate the scale amount.
927          if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
928            Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
929            return 0;
930          }
931          Scale = (unsigned)ScaleVal;
932        }
933      }
934    } else if (getLexer().isNot(AsmToken::RParen)) {
935      // A scale amount without an index is ignored.
936      // index.
937      SMLoc Loc = Parser.getTok().getLoc();
938
939      int64_t Value;
940      if (getParser().ParseAbsoluteExpression(Value))
941        return 0;
942
943      if (Value != 1)
944        Warning(Loc, "scale factor without index register is ignored");
945      Scale = 1;
946    }
947  }
948
949  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
950  if (getLexer().isNot(AsmToken::RParen)) {
951    Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
952    return 0;
953  }
954  SMLoc MemEnd = Parser.getTok().getLoc();
955  Parser.Lex(); // Eat the ')'.
956
957  // If we have both a base register and an index register make sure they are
958  // both 64-bit or 32-bit registers.
959  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
960  if (BaseReg != 0 && IndexReg != 0) {
961    if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
962        (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
963         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
964        IndexReg != X86::RIZ) {
965      Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
966      return 0;
967    }
968    if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
969        (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
970         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
971        IndexReg != X86::EIZ){
972      Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
973      return 0;
974    }
975  }
976
977  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
978                               MemStart, MemEnd);
979}
980
981bool X86AsmParser::
982ParseInstruction(StringRef Name, SMLoc NameLoc,
983                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
984  StringRef PatchedName = Name;
985
986  // FIXME: Hack to recognize setneb as setne.
987  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
988      PatchedName != "setb" && PatchedName != "setnb")
989    PatchedName = PatchedName.substr(0, Name.size()-1);
990
991  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
992  const MCExpr *ExtraImmOp = 0;
993  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
994      (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
995       PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
996    bool IsVCMP = PatchedName[0] == 'v';
997    unsigned SSECCIdx = IsVCMP ? 4 : 3;
998    unsigned SSEComparisonCode = StringSwitch<unsigned>(
999      PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1000      .Case("eq",       0x00)
1001      .Case("lt",       0x01)
1002      .Case("le",       0x02)
1003      .Case("unord",    0x03)
1004      .Case("neq",      0x04)
1005      .Case("nlt",      0x05)
1006      .Case("nle",      0x06)
1007      .Case("ord",      0x07)
1008      /* AVX only from here */
1009      .Case("eq_uq",    0x08)
1010      .Case("nge",      0x09)
1011      .Case("ngt",      0x0A)
1012      .Case("false",    0x0B)
1013      .Case("neq_oq",   0x0C)
1014      .Case("ge",       0x0D)
1015      .Case("gt",       0x0E)
1016      .Case("true",     0x0F)
1017      .Case("eq_os",    0x10)
1018      .Case("lt_oq",    0x11)
1019      .Case("le_oq",    0x12)
1020      .Case("unord_s",  0x13)
1021      .Case("neq_us",   0x14)
1022      .Case("nlt_uq",   0x15)
1023      .Case("nle_uq",   0x16)
1024      .Case("ord_s",    0x17)
1025      .Case("eq_us",    0x18)
1026      .Case("nge_uq",   0x19)
1027      .Case("ngt_uq",   0x1A)
1028      .Case("false_os", 0x1B)
1029      .Case("neq_os",   0x1C)
1030      .Case("ge_oq",    0x1D)
1031      .Case("gt_oq",    0x1E)
1032      .Case("true_us",  0x1F)
1033      .Default(~0U);
1034    if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1035      ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1036                                          getParser().getContext());
1037      if (PatchedName.endswith("ss")) {
1038        PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1039      } else if (PatchedName.endswith("sd")) {
1040        PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1041      } else if (PatchedName.endswith("ps")) {
1042        PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1043      } else {
1044        assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1045        PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1046      }
1047    }
1048  }
1049
1050  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1051
1052  if (ExtraImmOp && !isParsingIntelSyntax())
1053    Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1054
1055  // Determine whether this is an instruction prefix.
1056  bool isPrefix =
1057    Name == "lock" || Name == "rep" ||
1058    Name == "repe" || Name == "repz" ||
1059    Name == "repne" || Name == "repnz" ||
1060    Name == "rex64" || Name == "data16";
1061
1062
1063  // This does the actual operand parsing.  Don't parse any more if we have a
1064  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1065  // just want to parse the "lock" as the first instruction and the "incl" as
1066  // the next one.
1067  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1068
1069    // Parse '*' modifier.
1070    if (getLexer().is(AsmToken::Star)) {
1071      SMLoc Loc = Parser.getTok().getLoc();
1072      Operands.push_back(X86Operand::CreateToken("*", Loc));
1073      Parser.Lex(); // Eat the star.
1074    }
1075
1076    // Read the first operand.
1077    if (X86Operand *Op = ParseOperand())
1078      Operands.push_back(Op);
1079    else {
1080      Parser.EatToEndOfStatement();
1081      return true;
1082    }
1083
1084    while (getLexer().is(AsmToken::Comma)) {
1085      Parser.Lex();  // Eat the comma.
1086
1087      // Parse and remember the operand.
1088      if (X86Operand *Op = ParseOperand())
1089        Operands.push_back(Op);
1090      else {
1091        Parser.EatToEndOfStatement();
1092        return true;
1093      }
1094    }
1095
1096    if (getLexer().isNot(AsmToken::EndOfStatement)) {
1097      SMLoc Loc = getLexer().getLoc();
1098      Parser.EatToEndOfStatement();
1099      return Error(Loc, "unexpected token in argument list");
1100    }
1101  }
1102
1103  if (getLexer().is(AsmToken::EndOfStatement))
1104    Parser.Lex(); // Consume the EndOfStatement
1105  else if (isPrefix && getLexer().is(AsmToken::Slash))
1106    Parser.Lex(); // Consume the prefix separator Slash
1107
1108  if (ExtraImmOp && isParsingIntelSyntax())
1109    Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1110
1111  // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1112  // "outb %al, %dx".  Out doesn't take a memory form, but this is a widely
1113  // documented form in various unofficial manuals, so a lot of code uses it.
1114  if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1115      Operands.size() == 3) {
1116    X86Operand &Op = *(X86Operand*)Operands.back();
1117    if (Op.isMem() && Op.Mem.SegReg == 0 &&
1118        isa<MCConstantExpr>(Op.Mem.Disp) &&
1119        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1120        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1121      SMLoc Loc = Op.getEndLoc();
1122      Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1123      delete &Op;
1124    }
1125  }
1126  // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1127  if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1128      Operands.size() == 3) {
1129    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1130    if (Op.isMem() && Op.Mem.SegReg == 0 &&
1131        isa<MCConstantExpr>(Op.Mem.Disp) &&
1132        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1133        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1134      SMLoc Loc = Op.getEndLoc();
1135      Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1136      delete &Op;
1137    }
1138  }
1139  // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1140  if (Name.startswith("ins") && Operands.size() == 3 &&
1141      (Name == "insb" || Name == "insw" || Name == "insl")) {
1142    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1143    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1144    if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1145      Operands.pop_back();
1146      Operands.pop_back();
1147      delete &Op;
1148      delete &Op2;
1149    }
1150  }
1151
1152  // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1153  if (Name.startswith("outs") && Operands.size() == 3 &&
1154      (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1155    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1156    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1157    if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1158      Operands.pop_back();
1159      Operands.pop_back();
1160      delete &Op;
1161      delete &Op2;
1162    }
1163  }
1164
1165  // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1166  if (Name.startswith("movs") && Operands.size() == 3 &&
1167      (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1168       (is64BitMode() && Name == "movsq"))) {
1169    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1170    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1171    if (isSrcOp(Op) && isDstOp(Op2)) {
1172      Operands.pop_back();
1173      Operands.pop_back();
1174      delete &Op;
1175      delete &Op2;
1176    }
1177  }
1178  // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1179  if (Name.startswith("lods") && Operands.size() == 3 &&
1180      (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1181       Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1182    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1183    X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1184    if (isSrcOp(*Op1) && Op2->isReg()) {
1185      const char *ins;
1186      unsigned reg = Op2->getReg();
1187      bool isLods = Name == "lods";
1188      if (reg == X86::AL && (isLods || Name == "lodsb"))
1189        ins = "lodsb";
1190      else if (reg == X86::AX && (isLods || Name == "lodsw"))
1191        ins = "lodsw";
1192      else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1193        ins = "lodsl";
1194      else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1195        ins = "lodsq";
1196      else
1197        ins = NULL;
1198      if (ins != NULL) {
1199        Operands.pop_back();
1200        Operands.pop_back();
1201        delete Op1;
1202        delete Op2;
1203        if (Name != ins)
1204          static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1205      }
1206    }
1207  }
1208  // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1209  if (Name.startswith("stos") && Operands.size() == 3 &&
1210      (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1211       Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1212    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1213    X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1214    if (isDstOp(*Op2) && Op1->isReg()) {
1215      const char *ins;
1216      unsigned reg = Op1->getReg();
1217      bool isStos = Name == "stos";
1218      if (reg == X86::AL && (isStos || Name == "stosb"))
1219        ins = "stosb";
1220      else if (reg == X86::AX && (isStos || Name == "stosw"))
1221        ins = "stosw";
1222      else if (reg == X86::EAX && (isStos || Name == "stosl"))
1223        ins = "stosl";
1224      else if (reg == X86::RAX && (isStos || Name == "stosq"))
1225        ins = "stosq";
1226      else
1227        ins = NULL;
1228      if (ins != NULL) {
1229        Operands.pop_back();
1230        Operands.pop_back();
1231        delete Op1;
1232        delete Op2;
1233        if (Name != ins)
1234          static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1235      }
1236    }
1237  }
1238
1239  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>.  Canonicalize to
1240  // "shift <op>".
1241  if ((Name.startswith("shr") || Name.startswith("sar") ||
1242       Name.startswith("shl") || Name.startswith("sal") ||
1243       Name.startswith("rcl") || Name.startswith("rcr") ||
1244       Name.startswith("rol") || Name.startswith("ror")) &&
1245      Operands.size() == 3) {
1246    if (isParsingIntelSyntax()) {
1247      // Intel syntax
1248      X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
1249      if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1250          cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1251        delete Operands[2];
1252        Operands.pop_back();
1253      }
1254    } else {
1255      X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1256      if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1257          cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1258        delete Operands[1];
1259        Operands.erase(Operands.begin() + 1);
1260      }
1261    }
1262  }
1263
1264  // Transforms "int $3" into "int3" as a size optimization.  We can't write an
1265  // instalias with an immediate operand yet.
1266  if (Name == "int" && Operands.size() == 2) {
1267    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1268    if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1269        cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
1270      delete Operands[1];
1271      Operands.erase(Operands.begin() + 1);
1272      static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
1273    }
1274  }
1275
1276  return false;
1277}
1278
1279bool X86AsmParser::
1280processInstruction(MCInst &Inst,
1281                   const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1282  switch (Inst.getOpcode()) {
1283  default: return false;
1284  case X86::AND16i16: {
1285    if (!Inst.getOperand(0).isImm() ||
1286        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1287      return false;
1288
1289    MCInst TmpInst;
1290    TmpInst.setOpcode(X86::AND16ri8);
1291    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1292    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1293    TmpInst.addOperand(Inst.getOperand(0));
1294    Inst = TmpInst;
1295    return true;
1296  }
1297  case X86::AND32i32: {
1298    if (!Inst.getOperand(0).isImm() ||
1299        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1300      return false;
1301
1302    MCInst TmpInst;
1303    TmpInst.setOpcode(X86::AND32ri8);
1304    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1305    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1306    TmpInst.addOperand(Inst.getOperand(0));
1307    Inst = TmpInst;
1308    return true;
1309  }
1310  case X86::AND64i32: {
1311    if (!Inst.getOperand(0).isImm() ||
1312        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1313      return false;
1314
1315    MCInst TmpInst;
1316    TmpInst.setOpcode(X86::AND64ri8);
1317    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1318    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1319    TmpInst.addOperand(Inst.getOperand(0));
1320    Inst = TmpInst;
1321    return true;
1322  }
1323  case X86::XOR16i16: {
1324    if (!Inst.getOperand(0).isImm() ||
1325        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1326      return false;
1327
1328    MCInst TmpInst;
1329    TmpInst.setOpcode(X86::XOR16ri8);
1330    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1331    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1332    TmpInst.addOperand(Inst.getOperand(0));
1333    Inst = TmpInst;
1334    return true;
1335  }
1336  case X86::XOR32i32: {
1337    if (!Inst.getOperand(0).isImm() ||
1338        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1339      return false;
1340
1341    MCInst TmpInst;
1342    TmpInst.setOpcode(X86::XOR32ri8);
1343    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1344    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1345    TmpInst.addOperand(Inst.getOperand(0));
1346    Inst = TmpInst;
1347    return true;
1348  }
1349  case X86::XOR64i32: {
1350    if (!Inst.getOperand(0).isImm() ||
1351        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1352      return false;
1353
1354    MCInst TmpInst;
1355    TmpInst.setOpcode(X86::XOR64ri8);
1356    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1357    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1358    TmpInst.addOperand(Inst.getOperand(0));
1359    Inst = TmpInst;
1360    return true;
1361  }
1362  case X86::OR16i16: {
1363    if (!Inst.getOperand(0).isImm() ||
1364        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1365      return false;
1366
1367    MCInst TmpInst;
1368    TmpInst.setOpcode(X86::OR16ri8);
1369    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1370    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1371    TmpInst.addOperand(Inst.getOperand(0));
1372    Inst = TmpInst;
1373    return true;
1374  }
1375  case X86::OR32i32: {
1376    if (!Inst.getOperand(0).isImm() ||
1377        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1378      return false;
1379
1380    MCInst TmpInst;
1381    TmpInst.setOpcode(X86::OR32ri8);
1382    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1383    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1384    TmpInst.addOperand(Inst.getOperand(0));
1385    Inst = TmpInst;
1386    return true;
1387  }
1388  case X86::OR64i32: {
1389    if (!Inst.getOperand(0).isImm() ||
1390        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1391      return false;
1392
1393    MCInst TmpInst;
1394    TmpInst.setOpcode(X86::OR64ri8);
1395    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1396    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1397    TmpInst.addOperand(Inst.getOperand(0));
1398    Inst = TmpInst;
1399    return true;
1400  }
1401  case X86::CMP16i16: {
1402    if (!Inst.getOperand(0).isImm() ||
1403        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1404      return false;
1405
1406    MCInst TmpInst;
1407    TmpInst.setOpcode(X86::CMP16ri8);
1408    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1409    TmpInst.addOperand(Inst.getOperand(0));
1410    Inst = TmpInst;
1411    return true;
1412  }
1413  case X86::CMP32i32: {
1414    if (!Inst.getOperand(0).isImm() ||
1415        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1416      return false;
1417
1418    MCInst TmpInst;
1419    TmpInst.setOpcode(X86::CMP32ri8);
1420    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1421    TmpInst.addOperand(Inst.getOperand(0));
1422    Inst = TmpInst;
1423    return true;
1424  }
1425  case X86::CMP64i32: {
1426    if (!Inst.getOperand(0).isImm() ||
1427        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1428      return false;
1429
1430    MCInst TmpInst;
1431    TmpInst.setOpcode(X86::CMP64ri8);
1432    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1433    TmpInst.addOperand(Inst.getOperand(0));
1434    Inst = TmpInst;
1435    return true;
1436  }
1437  case X86::ADD16i16: {
1438    if (!Inst.getOperand(0).isImm() ||
1439        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1440      return false;
1441
1442    MCInst TmpInst;
1443    TmpInst.setOpcode(X86::ADD16ri8);
1444    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1445    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1446    TmpInst.addOperand(Inst.getOperand(0));
1447    Inst = TmpInst;
1448    return true;
1449  }
1450  case X86::ADD32i32: {
1451    if (!Inst.getOperand(0).isImm() ||
1452        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1453      return false;
1454
1455    MCInst TmpInst;
1456    TmpInst.setOpcode(X86::ADD32ri8);
1457    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1458    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1459    TmpInst.addOperand(Inst.getOperand(0));
1460    Inst = TmpInst;
1461    return true;
1462  }
1463  case X86::ADD64i32: {
1464    if (!Inst.getOperand(0).isImm() ||
1465        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1466      return false;
1467
1468    MCInst TmpInst;
1469    TmpInst.setOpcode(X86::ADD64ri8);
1470    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1471    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1472    TmpInst.addOperand(Inst.getOperand(0));
1473    Inst = TmpInst;
1474    return true;
1475  }
1476  case X86::SUB16i16: {
1477    if (!Inst.getOperand(0).isImm() ||
1478        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1479      return false;
1480
1481    MCInst TmpInst;
1482    TmpInst.setOpcode(X86::SUB16ri8);
1483    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1484    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1485    TmpInst.addOperand(Inst.getOperand(0));
1486    Inst = TmpInst;
1487    return true;
1488  }
1489  case X86::SUB32i32: {
1490    if (!Inst.getOperand(0).isImm() ||
1491        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1492      return false;
1493
1494    MCInst TmpInst;
1495    TmpInst.setOpcode(X86::SUB32ri8);
1496    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1497    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1498    TmpInst.addOperand(Inst.getOperand(0));
1499    Inst = TmpInst;
1500    return true;
1501  }
1502  case X86::SUB64i32: {
1503    if (!Inst.getOperand(0).isImm() ||
1504        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1505      return false;
1506
1507    MCInst TmpInst;
1508    TmpInst.setOpcode(X86::SUB64ri8);
1509    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1510    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1511    TmpInst.addOperand(Inst.getOperand(0));
1512    Inst = TmpInst;
1513    return true;
1514  }
1515  }
1516}
1517
1518bool X86AsmParser::
1519MatchAndEmitInstruction(SMLoc IDLoc,
1520                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1521                        MCStreamer &Out) {
1522  unsigned Kind;
1523  unsigned Opcode;
1524  unsigned ErrorInfo;
1525  SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints;
1526  bool Error = MatchInstruction(IDLoc, Operands, Out, Kind, Opcode,
1527                                MapAndConstraints, ErrorInfo);
1528  return Error;
1529}
1530
1531bool X86AsmParser::
1532MatchInstruction(SMLoc IDLoc,
1533                 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1534                 MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
1535  SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,
1536                 unsigned &OrigErrorInfo, bool matchingInlineAsm) {
1537  assert(!Operands.empty() && "Unexpect empty operand list!");
1538  X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1539  assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1540  ArrayRef<SMRange> EmptyRanges = ArrayRef<SMRange>();
1541
1542  // First, handle aliases that expand to multiple instructions.
1543  // FIXME: This should be replaced with a real .td file alias mechanism.
1544  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
1545  // call.
1546  if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
1547      Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
1548      Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1549      Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1550    MCInst Inst;
1551    Inst.setOpcode(X86::WAIT);
1552    Inst.setLoc(IDLoc);
1553    if (!matchingInlineAsm)
1554      Out.EmitInstruction(Inst);
1555
1556    const char *Repl =
1557      StringSwitch<const char*>(Op->getToken())
1558        .Case("finit",  "fninit")
1559        .Case("fsave",  "fnsave")
1560        .Case("fstcw",  "fnstcw")
1561        .Case("fstcww",  "fnstcw")
1562        .Case("fstenv", "fnstenv")
1563        .Case("fstsw",  "fnstsw")
1564        .Case("fstsww", "fnstsw")
1565        .Case("fclex",  "fnclex")
1566        .Default(0);
1567    assert(Repl && "Unknown wait-prefixed instruction");
1568    delete Operands[0];
1569    Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1570  }
1571
1572  bool WasOriginallyInvalidOperand = false;
1573  MCInst Inst;
1574
1575  // First, try a direct match.
1576  switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints,
1577                               OrigErrorInfo, matchingInlineAsm,
1578                               isParsingIntelSyntax())) {
1579  default: break;
1580  case Match_Success:
1581    // Some instructions need post-processing to, for example, tweak which
1582    // encoding is selected. Loop on it while changes happen so the
1583    // individual transformations can chain off each other.
1584    if (!matchingInlineAsm)
1585      while (processInstruction(Inst, Operands))
1586        ;
1587
1588    Inst.setLoc(IDLoc);
1589    if (!matchingInlineAsm)
1590      Out.EmitInstruction(Inst);
1591    Opcode = Inst.getOpcode();
1592    return false;
1593  case Match_MissingFeature:
1594    Error(IDLoc, "instruction requires a CPU feature not currently enabled",
1595          EmptyRanges, matchingInlineAsm);
1596    return true;
1597  case Match_InvalidOperand:
1598    WasOriginallyInvalidOperand = true;
1599    break;
1600  case Match_MnemonicFail:
1601    break;
1602  }
1603
1604  // FIXME: Ideally, we would only attempt suffix matches for things which are
1605  // valid prefixes, and we could just infer the right unambiguous
1606  // type. However, that requires substantially more matcher support than the
1607  // following hack.
1608
1609  // Change the operand to point to a temporary token.
1610  StringRef Base = Op->getToken();
1611  SmallString<16> Tmp;
1612  Tmp += Base;
1613  Tmp += ' ';
1614  Op->setTokenValue(Tmp.str());
1615
1616  // If this instruction starts with an 'f', then it is a floating point stack
1617  // instruction.  These come in up to three forms for 32-bit, 64-bit, and
1618  // 80-bit floating point, which use the suffixes s,l,t respectively.
1619  //
1620  // Otherwise, we assume that this may be an integer instruction, which comes
1621  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
1622  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
1623
1624  // Check for the various suffix matches.
1625  Tmp[Base.size()] = Suffixes[0];
1626  unsigned ErrorInfoIgnore;
1627  unsigned Match1, Match2, Match3, Match4;
1628  unsigned tKind;
1629
1630  SmallVector<std::pair< unsigned, std::string >, 4> tMapAndConstraints[4];
1631  Match1 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[0],
1632                                ErrorInfoIgnore, isParsingIntelSyntax());
1633  if (Match1 == Match_Success) Kind = tKind;
1634  Tmp[Base.size()] = Suffixes[1];
1635  Match2 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[1],
1636                                ErrorInfoIgnore, isParsingIntelSyntax());
1637  if (Match2 == Match_Success) Kind = tKind;
1638  Tmp[Base.size()] = Suffixes[2];
1639  Match3 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[2],
1640                                ErrorInfoIgnore, isParsingIntelSyntax());
1641  if (Match3 == Match_Success) Kind = tKind;
1642  Tmp[Base.size()] = Suffixes[3];
1643  Match4 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[3],
1644                                ErrorInfoIgnore, isParsingIntelSyntax());
1645  if (Match4 == Match_Success) Kind = tKind;
1646
1647  // Restore the old token.
1648  Op->setTokenValue(Base);
1649
1650  // If exactly one matched, then we treat that as a successful match (and the
1651  // instruction will already have been filled in correctly, since the failing
1652  // matches won't have modified it).
1653  unsigned NumSuccessfulMatches =
1654    (Match1 == Match_Success) + (Match2 == Match_Success) +
1655    (Match3 == Match_Success) + (Match4 == Match_Success);
1656  if (NumSuccessfulMatches == 1) {
1657    Inst.setLoc(IDLoc);
1658    if (!matchingInlineAsm)
1659      Out.EmitInstruction(Inst);
1660    Opcode = Inst.getOpcode();
1661    // FIXME: Handle the map and constraints.
1662    return false;
1663  }
1664
1665  // Otherwise, the match failed, try to produce a decent error message.
1666
1667  // If we had multiple suffix matches, then identify this as an ambiguous
1668  // match.
1669  if (NumSuccessfulMatches > 1) {
1670    char MatchChars[4];
1671    unsigned NumMatches = 0;
1672    if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
1673    if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
1674    if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
1675    if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
1676
1677    SmallString<126> Msg;
1678    raw_svector_ostream OS(Msg);
1679    OS << "ambiguous instructions require an explicit suffix (could be ";
1680    for (unsigned i = 0; i != NumMatches; ++i) {
1681      if (i != 0)
1682        OS << ", ";
1683      if (i + 1 == NumMatches)
1684        OS << "or ";
1685      OS << "'" << Base << MatchChars[i] << "'";
1686    }
1687    OS << ")";
1688    Error(IDLoc, OS.str(), EmptyRanges, matchingInlineAsm);
1689    return true;
1690  }
1691
1692  // Okay, we know that none of the variants matched successfully.
1693
1694  // If all of the instructions reported an invalid mnemonic, then the original
1695  // mnemonic was invalid.
1696  if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
1697      (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
1698    if (!WasOriginallyInvalidOperand) {
1699      ArrayRef<SMRange> Ranges = matchingInlineAsm ? EmptyRanges :
1700        Op->getLocRange();
1701      return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
1702                   Ranges, matchingInlineAsm);
1703    }
1704
1705    // Recover location info for the operand if we know which was the problem.
1706    if (OrigErrorInfo != ~0U) {
1707      if (OrigErrorInfo >= Operands.size())
1708        return Error(IDLoc, "too few operands for instruction",
1709                     EmptyRanges, matchingInlineAsm);
1710
1711      X86Operand *Operand = (X86Operand*)Operands[OrigErrorInfo];
1712      if (Operand->getStartLoc().isValid()) {
1713        SMRange OperandRange = Operand->getLocRange();
1714        return Error(Operand->getStartLoc(), "invalid operand for instruction",
1715                     OperandRange, matchingInlineAsm);
1716      }
1717    }
1718
1719    return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
1720                 matchingInlineAsm);
1721  }
1722
1723  // If one instruction matched with a missing feature, report this as a
1724  // missing feature.
1725  if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
1726      (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
1727    Error(IDLoc, "instruction requires a CPU feature not currently enabled",
1728          EmptyRanges, matchingInlineAsm);
1729    return true;
1730  }
1731
1732  // If one instruction matched with an invalid operand, report this as an
1733  // operand failure.
1734  if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
1735      (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
1736    Error(IDLoc, "invalid operand for instruction", EmptyRanges,
1737          matchingInlineAsm);
1738    return true;
1739  }
1740
1741  // If all of these were an outright failure, report it in a useless way.
1742  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
1743        EmptyRanges, matchingInlineAsm);
1744  return true;
1745}
1746
1747
1748bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
1749  StringRef IDVal = DirectiveID.getIdentifier();
1750  if (IDVal == ".word")
1751    return ParseDirectiveWord(2, DirectiveID.getLoc());
1752  else if (IDVal.startswith(".code"))
1753    return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
1754  else if (IDVal.startswith(".att_syntax")) {
1755    getParser().setAssemblerDialect(0);
1756    return false;
1757  } else if (IDVal.startswith(".intel_syntax")) {
1758    getParser().setAssemblerDialect(1);
1759    if (getLexer().isNot(AsmToken::EndOfStatement)) {
1760      if(Parser.getTok().getString() == "noprefix") {
1761        // FIXME : Handle noprefix
1762        Parser.Lex();
1763      } else
1764        return true;
1765    }
1766    return false;
1767  }
1768  return true;
1769}
1770
1771/// ParseDirectiveWord
1772///  ::= .word [ expression (, expression)* ]
1773bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1774  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1775    for (;;) {
1776      const MCExpr *Value;
1777      if (getParser().ParseExpression(Value))
1778        return true;
1779
1780      getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1781
1782      if (getLexer().is(AsmToken::EndOfStatement))
1783        break;
1784
1785      // FIXME: Improve diagnostic.
1786      if (getLexer().isNot(AsmToken::Comma))
1787        return Error(L, "unexpected token in directive");
1788      Parser.Lex();
1789    }
1790  }
1791
1792  Parser.Lex();
1793  return false;
1794}
1795
1796/// ParseDirectiveCode
1797///  ::= .code32 | .code64
1798bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
1799  if (IDVal == ".code32") {
1800    Parser.Lex();
1801    if (is64BitMode()) {
1802      SwitchMode();
1803      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1804    }
1805  } else if (IDVal == ".code64") {
1806    Parser.Lex();
1807    if (!is64BitMode()) {
1808      SwitchMode();
1809      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
1810    }
1811  } else {
1812    return Error(L, "unexpected directive " + IDVal);
1813  }
1814
1815  return false;
1816}
1817
1818
1819extern "C" void LLVMInitializeX86AsmLexer();
1820
1821// Force static initialization.
1822extern "C" void LLVMInitializeX86AsmParser() {
1823  RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
1824  RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
1825  LLVMInitializeX86AsmLexer();
1826}
1827
1828#define GET_REGISTER_MATCHER
1829#define GET_MATCHER_IMPLEMENTATION
1830#include "X86GenAsmMatcher.inc"
1831