InstrInfoEmitter.cpp revision 214884ba03bb3ba791a14db51a61aaa694ddcff8
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15#include "InstrInfoEmitter.h" 16#include "CodeGenTarget.h" 17#include "Record.h" 18#include <algorithm> 19#include <iostream> 20using namespace llvm; 21 22static void PrintDefList(const std::vector<Record*> &Uses, 23 unsigned Num, std::ostream &OS) { 24 OS << "static const unsigned ImplicitList" << Num << "[] = { "; 25 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 26 OS << getQualifiedName(Uses[i]) << ", "; 27 OS << "0 };\n"; 28} 29 30//===----------------------------------------------------------------------===// 31// Instruction Itinerary Information. 32//===----------------------------------------------------------------------===// 33 34struct RecordNameComparator { 35 bool operator()(const Record *Rec1, const Record *Rec2) const { 36 return Rec1->getName() < Rec2->getName(); 37 } 38}; 39 40void InstrInfoEmitter::GatherItinClasses() { 41 std::vector<Record*> DefList = 42 Records.getAllDerivedDefinitions("InstrItinClass"); 43 std::sort(DefList.begin(), DefList.end(), RecordNameComparator()); 44 45 for (unsigned i = 0, N = DefList.size(); i < N; i++) 46 ItinClassMap[DefList[i]->getName()] = i; 47} 48 49unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) { 50 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()]; 51} 52 53//===----------------------------------------------------------------------===// 54// Operand Info Emission. 55//===----------------------------------------------------------------------===// 56 57std::vector<std::string> 58InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 59 std::vector<std::string> Result; 60 61 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { 62 // Handle aggregate operands and normal operands the same way by expanding 63 // either case into a list of operands for this op. 64 std::vector<CodeGenInstruction::OperandInfo> OperandList; 65 66 // This might be a multiple operand thing. Targets like X86 have 67 // registers in their multi-operand operands. It may also be an anonymous 68 // operand, which has a single operand, but no declared class for the 69 // operand. 70 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; 71 72 if (!MIOI || MIOI->getNumArgs() == 0) { 73 // Single, anonymous, operand. 74 OperandList.push_back(Inst.OperandList[i]); 75 } else { 76 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { 77 OperandList.push_back(Inst.OperandList[i]); 78 79 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef(); 80 OperandList.back().Rec = OpR; 81 } 82 } 83 84 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 85 Record *OpR = OperandList[j].Rec; 86 std::string Res; 87 88 if (OpR->isSubClassOf("RegisterClass")) 89 Res += getQualifiedName(OpR) + "RegClassID, "; 90 else 91 Res += "0, "; 92 // Fill in applicable flags. 93 Res += "0"; 94 95 // Ptr value whose register class is resolved via callback. 96 if (OpR->getName() == "ptr_rc") 97 Res += "|(1<<TOI::LookupPtrRegClass)"; 98 99 // Predicate operands. Check to see if the original unexpanded operand 100 // was of type PredicateOperand. 101 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand")) 102 Res += "|(1<<TOI::Predicate)"; 103 104 // Optional def operands. Check to see if the original unexpanded operand 105 // was of type OptionalDefOperand. 106 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand")) 107 Res += "|(1<<TOI::OptionalDef)"; 108 109 // Fill in constraint info. 110 Res += ", " + Inst.OperandList[i].Constraints[j]; 111 Result.push_back(Res); 112 } 113 } 114 115 return Result; 116} 117 118void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS, 119 OperandInfoMapTy &OperandInfoIDs) { 120 // ID #0 is for no operand info. 121 unsigned OperandListNum = 0; 122 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 123 124 OS << "\n"; 125 const CodeGenTarget &Target = CDP.getTargetInfo(); 126 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 127 E = Target.inst_end(); II != E; ++II) { 128 std::vector<std::string> OperandInfo = GetOperandInfo(II->second); 129 unsigned &N = OperandInfoIDs[OperandInfo]; 130 if (N != 0) continue; 131 132 N = ++OperandListNum; 133 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; 134 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 135 OS << "{ " << OperandInfo[i] << " }, "; 136 OS << "};\n"; 137 } 138} 139 140//===----------------------------------------------------------------------===// 141// Instruction Analysis 142//===----------------------------------------------------------------------===// 143 144class InstAnalyzer { 145 const CodeGenDAGPatterns &CDP; 146 bool &mayStore; 147 bool &mayLoad; 148 bool &HasSideEffects; 149public: 150 InstAnalyzer(const CodeGenDAGPatterns &cdp, 151 bool &maystore, bool &mayload, bool &hse) 152 : CDP(cdp), mayStore(maystore), mayLoad(mayload), HasSideEffects(hse){ 153 } 154 155 void Analyze(Record *InstRecord) { 156 const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern(); 157 if (Pattern == 0) { 158 HasSideEffects = 1; 159 return; // No pattern. 160 } 161 162 // FIXME: Assume only the first tree is the pattern. The others are clobber 163 // nodes. 164 AnalyzeNode(Pattern->getTree(0)); 165 } 166 167private: 168 void AnalyzeNode(const TreePatternNode *N) { 169 if (N->isLeaf()) 170 return; 171 172 // Analyze children. 173 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) 174 AnalyzeNode(N->getChild(i)); 175 176 // Ignore set nodes, which are not SDNodes. 177 if (N->getOperator()->getName() == "set") 178 return; 179 180 // Get information about the SDNode for the operator. 181 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); 182 183 // If node writes to memory, it obviously stores to memory. 184 if (OpInfo.hasProperty(SDNPMayStore)) 185 mayStore = true; 186 187 // If it reads memory, remember this. 188 if (OpInfo.hasProperty(SDNPMayLoad)) 189 mayLoad = true; 190 191 // If it reads memory, remember this. 192 if (OpInfo.hasProperty(SDNPSideEffect)) 193 HasSideEffects = true; 194 195 if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) { 196 // If this is an intrinsic, analyze it. 197 if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem) 198 mayLoad = true;// These may load memory. 199 200 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem) 201 mayStore = true;// Intrinsics that can write to memory are 'mayStore'. 202 203 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteMem) 204 // WriteMem intrinsics can have other strange effects. 205 HasSideEffects = true; 206 } 207 } 208 209}; 210 211void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, 212 bool &MayStore, bool &MayLoad, 213 bool &HasSideEffects) { 214 MayStore = MayLoad = HasSideEffects = false; 215 216 InstAnalyzer(CDP, MayStore, MayLoad, HasSideEffects).Analyze(Inst.TheDef); 217 218 // InstAnalyzer only correctly analyzes mayStore/mayLoad so far. 219 if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it. 220 // If we decided that this is a store from the pattern, then the .td file 221 // entry is redundant. 222 if (MayStore) 223 fprintf(stderr, 224 "Warning: mayStore flag explicitly set on instruction '%s'" 225 " but flag already inferred from pattern.\n", 226 Inst.TheDef->getName().c_str()); 227 MayStore = true; 228 } 229 230 if (Inst.mayLoad) { // If the .td file explicitly sets mayLoad, use it. 231 // If we decided that this is a load from the pattern, then the .td file 232 // entry is redundant. 233 if (MayLoad) 234 fprintf(stderr, 235 "Warning: mayLoad flag explicitly set on instruction '%s'" 236 " but flag already inferred from pattern.\n", 237 Inst.TheDef->getName().c_str()); 238 MayLoad = true; 239 } 240 241 if (Inst.neverHasSideEffects) { 242 // If we already decided that this instruction has no side effects, then the 243 // .td file entry is redundant. 244 if (!HasSideEffects) 245 fprintf(stderr, 246 "Warning: neverHasSideEffects flag explicitly set on instruction" 247 " '%s' but flag already inferred from pattern.\n", 248 Inst.TheDef->getName().c_str()); 249 HasSideEffects = false; 250 } 251} 252 253 254//===----------------------------------------------------------------------===// 255// Main Output. 256//===----------------------------------------------------------------------===// 257 258// run - Emit the main instruction description records for the target... 259void InstrInfoEmitter::run(std::ostream &OS) { 260 GatherItinClasses(); 261 262 EmitSourceFileHeader("Target Instruction Descriptors", OS); 263 OS << "namespace llvm {\n\n"; 264 265 CodeGenTarget Target; 266 const std::string &TargetName = Target.getName(); 267 Record *InstrInfo = Target.getInstructionSet(); 268 269 // Keep track of all of the def lists we have emitted already. 270 std::map<std::vector<Record*>, unsigned> EmittedLists; 271 unsigned ListNumber = 0; 272 273 // Emit all of the instruction's implicit uses and defs. 274 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 275 E = Target.inst_end(); II != E; ++II) { 276 Record *Inst = II->second.TheDef; 277 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 278 if (!Uses.empty()) { 279 unsigned &IL = EmittedLists[Uses]; 280 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 281 } 282 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 283 if (!Defs.empty()) { 284 unsigned &IL = EmittedLists[Defs]; 285 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 286 } 287 } 288 289 OperandInfoMapTy OperandInfoIDs; 290 291 // Emit all of the operand info records. 292 EmitOperandInfo(OS, OperandInfoIDs); 293 294 // Emit all of the TargetInstrDesc records in their ENUM ordering. 295 // 296 OS << "\nstatic const TargetInstrDesc " << TargetName 297 << "Insts[] = {\n"; 298 std::vector<const CodeGenInstruction*> NumberedInstructions; 299 Target.getInstructionsByEnumValue(NumberedInstructions); 300 301 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 302 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 303 OperandInfoIDs, OS); 304 OS << "};\n"; 305 OS << "} // End llvm namespace \n"; 306} 307 308void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 309 Record *InstrInfo, 310 std::map<std::vector<Record*>, unsigned> &EmittedLists, 311 const OperandInfoMapTy &OpInfo, 312 std::ostream &OS) { 313 // Determine properties of the instruction from its pattern. 314 bool mayStore, mayLoad, HasSideEffects; 315 InferFromPattern(Inst, mayStore, mayLoad, HasSideEffects); 316 317 int MinOperands = 0; 318 if (!Inst.OperandList.empty()) 319 // Each logical operand can be multiple MI operands. 320 MinOperands = Inst.OperandList.back().MIOperandNo + 321 Inst.OperandList.back().MINumOperands; 322 323 OS << " { "; 324 OS << Num << ",\t" << MinOperands << ",\t" 325 << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) 326 << ",\t\"" << Inst.TheDef->getName() << "\", 0"; 327 328 // Emit all of the target indepedent flags... 329 if (Inst.isReturn) OS << "|(1<<TID::Return)"; 330 if (Inst.isBranch) OS << "|(1<<TID::Branch)"; 331 if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; 332 if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; 333 if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; 334 if (Inst.isCall) OS << "|(1<<TID::Call)"; 335 if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)"; 336 if (mayLoad) OS << "|(1<<TID::MayLoad)"; 337 if (mayStore) OS << "|(1<<TID::MayStore)"; 338 if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)"; 339 if (Inst.isPredicable) OS << "|(1<<TID::Predicable)"; 340 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)"; 341 if (Inst.isCommutable) OS << "|(1<<TID::Commutable)"; 342 if (Inst.isTerminator) OS << "|(1<<TID::Terminator)"; 343 if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)"; 344 if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)"; 345 if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)"; 346 if (Inst.usesCustomDAGSchedInserter) 347 OS << "|(1<<TID::UsesCustomDAGSchedInserter)"; 348 if (Inst.isVariadic) OS << "|(1<<TID::Variadic)"; 349 if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)"; 350 if (!HasSideEffects) OS << "|(1<<TID::NeverHasSideEffects)"; 351 OS << ", 0"; 352 353 // Emit all of the target-specific flags... 354 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields"); 355 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts"); 356 if (LI->getSize() != Shift->getSize()) 357 throw "Lengths of " + InstrInfo->getName() + 358 ":(TargetInfoFields, TargetInfoPositions) must be equal!"; 359 360 for (unsigned i = 0, e = LI->getSize(); i != e; ++i) 361 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)), 362 dynamic_cast<IntInit*>(Shift->getElement(i)), OS); 363 364 OS << ", "; 365 366 // Emit the implicit uses and defs lists... 367 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 368 if (UseList.empty()) 369 OS << "NULL, "; 370 else 371 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 372 373 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 374 if (DefList.empty()) 375 OS << "NULL, "; 376 else 377 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 378 379 // Emit the operand info. 380 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 381 if (OperandInfo.empty()) 382 OS << "0"; 383 else 384 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 385 386 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 387} 388 389 390void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, 391 IntInit *ShiftInt, std::ostream &OS) { 392 if (Val == 0 || ShiftInt == 0) 393 throw std::string("Illegal value or shift amount in TargetInfo*!"); 394 RecordVal *RV = R->getValue(Val->getValue()); 395 int Shift = ShiftInt->getValue(); 396 397 if (RV == 0 || RV->getValue() == 0) { 398 // This isn't an error if this is a builtin instruction. 399 if (R->getName() != "PHI" && 400 R->getName() != "INLINEASM" && 401 R->getName() != "LABEL" && 402 R->getName() != "EXTRACT_SUBREG" && 403 R->getName() != "INSERT_SUBREG") 404 throw R->getName() + " doesn't have a field named '" + 405 Val->getValue() + "'!"; 406 return; 407 } 408 409 Init *Value = RV->getValue(); 410 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) { 411 if (BI->getValue()) OS << "|(1<<" << Shift << ")"; 412 return; 413 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) { 414 // Convert the Bits to an integer to print... 415 Init *I = BI->convertInitializerTo(new IntRecTy()); 416 if (I) 417 if (IntInit *II = dynamic_cast<IntInit*>(I)) { 418 if (II->getValue()) { 419 if (Shift) 420 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 421 else 422 OS << "|" << II->getValue(); 423 } 424 return; 425 } 426 427 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) { 428 if (II->getValue()) { 429 if (Shift) 430 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 431 else 432 OS << II->getValue(); 433 } 434 return; 435 } 436 437 std::cerr << "Unhandled initializer: " << *Val << "\n"; 438 throw "In record '" + R->getName() + "' for TSFlag emission."; 439} 440 441