InstrInfoEmitter.cpp revision a938ac6223c5fd315ab745086d843df5e0604e09
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15#include "InstrInfoEmitter.h" 16#include "CodeGenTarget.h" 17#include "Record.h" 18#include <algorithm> 19using namespace llvm; 20 21static void PrintDefList(const std::vector<Record*> &Uses, 22 unsigned Num, raw_ostream &OS) { 23 OS << "static const unsigned ImplicitList" << Num << "[] = { "; 24 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 25 OS << getQualifiedName(Uses[i]) << ", "; 26 OS << "0 };\n"; 27} 28 29static void PrintBarriers(std::vector<Record*> &Barriers, 30 unsigned Num, raw_ostream &OS) { 31 OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; 32 for (unsigned i = 0, e = Barriers.size(); i != e; ++i) 33 OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; 34 OS << "NULL };\n"; 35} 36 37//===----------------------------------------------------------------------===// 38// Instruction Itinerary Information. 39//===----------------------------------------------------------------------===// 40 41struct RecordNameComparator { 42 bool operator()(const Record *Rec1, const Record *Rec2) const { 43 return Rec1->getName() < Rec2->getName(); 44 } 45}; 46 47void InstrInfoEmitter::GatherItinClasses() { 48 std::vector<Record*> DefList = 49 Records.getAllDerivedDefinitions("InstrItinClass"); 50 std::sort(DefList.begin(), DefList.end(), RecordNameComparator()); 51 52 for (unsigned i = 0, N = DefList.size(); i < N; i++) 53 ItinClassMap[DefList[i]->getName()] = i; 54} 55 56unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) { 57 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()]; 58} 59 60//===----------------------------------------------------------------------===// 61// Operand Info Emission. 62//===----------------------------------------------------------------------===// 63 64std::vector<std::string> 65InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 66 std::vector<std::string> Result; 67 68 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { 69 // Handle aggregate operands and normal operands the same way by expanding 70 // either case into a list of operands for this op. 71 std::vector<CodeGenInstruction::OperandInfo> OperandList; 72 73 // This might be a multiple operand thing. Targets like X86 have 74 // registers in their multi-operand operands. It may also be an anonymous 75 // operand, which has a single operand, but no declared class for the 76 // operand. 77 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; 78 79 if (!MIOI || MIOI->getNumArgs() == 0) { 80 // Single, anonymous, operand. 81 OperandList.push_back(Inst.OperandList[i]); 82 } else { 83 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { 84 OperandList.push_back(Inst.OperandList[i]); 85 86 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef(); 87 OperandList.back().Rec = OpR; 88 } 89 } 90 91 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 92 Record *OpR = OperandList[j].Rec; 93 std::string Res; 94 95 if (OpR->isSubClassOf("RegisterClass")) 96 Res += getQualifiedName(OpR) + "RegClassID, "; 97 else 98 Res += "0, "; 99 // Fill in applicable flags. 100 Res += "0"; 101 102 // Ptr value whose register class is resolved via callback. 103 if (OpR->isSubClassOf("PointerLikeRegClass")) 104 Res += "|(1<<TOI::LookupPtrRegClass)"; 105 106 // Predicate operands. Check to see if the original unexpanded operand 107 // was of type PredicateOperand. 108 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand")) 109 Res += "|(1<<TOI::Predicate)"; 110 111 // Optional def operands. Check to see if the original unexpanded operand 112 // was of type OptionalDefOperand. 113 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand")) 114 Res += "|(1<<TOI::OptionalDef)"; 115 116 // Fill in constraint info. 117 Res += ", " + Inst.OperandList[i].Constraints[j]; 118 Result.push_back(Res); 119 } 120 } 121 122 return Result; 123} 124 125void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 126 OperandInfoMapTy &OperandInfoIDs) { 127 // ID #0 is for no operand info. 128 unsigned OperandListNum = 0; 129 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 130 131 OS << "\n"; 132 const CodeGenTarget &Target = CDP.getTargetInfo(); 133 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 134 E = Target.inst_end(); II != E; ++II) { 135 std::vector<std::string> OperandInfo = GetOperandInfo(II->second); 136 unsigned &N = OperandInfoIDs[OperandInfo]; 137 if (N != 0) continue; 138 139 N = ++OperandListNum; 140 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; 141 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 142 OS << "{ " << OperandInfo[i] << " }, "; 143 OS << "};\n"; 144 } 145} 146 147void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs, 148 const std::vector<CodeGenRegisterClass> &RCs, 149 std::vector<Record*> &Barriers) { 150 std::set<Record*> DefSet; 151 unsigned NumDefs = Defs.size(); 152 for (unsigned i = 0; i < NumDefs; ++i) 153 DefSet.insert(Defs[i]); 154 155 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 156 const CodeGenRegisterClass &RC = RCs[i]; 157 unsigned NumRegs = RC.Elements.size(); 158 if (NumRegs > NumDefs) 159 continue; // Can't possibly clobber this RC. 160 161 bool Clobber = true; 162 for (unsigned j = 0; j < NumRegs; ++j) { 163 Record *Reg = RC.Elements[j]; 164 if (!DefSet.count(Reg)) { 165 Clobber = false; 166 break; 167 } 168 } 169 if (Clobber) 170 Barriers.push_back(RC.TheDef); 171 } 172} 173 174//===----------------------------------------------------------------------===// 175// Main Output. 176//===----------------------------------------------------------------------===// 177 178// run - Emit the main instruction description records for the target... 179void InstrInfoEmitter::run(raw_ostream &OS) { 180 GatherItinClasses(); 181 182 EmitSourceFileHeader("Target Instruction Descriptors", OS); 183 OS << "namespace llvm {\n\n"; 184 185 CodeGenTarget &Target = CDP.getTargetInfo(); 186 const std::string &TargetName = Target.getName(); 187 Record *InstrInfo = Target.getInstructionSet(); 188 const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses(); 189 190 // Keep track of all of the def lists we have emitted already. 191 std::map<std::vector<Record*>, unsigned> EmittedLists; 192 unsigned ListNumber = 0; 193 std::map<std::vector<Record*>, unsigned> EmittedBarriers; 194 unsigned BarrierNumber = 0; 195 std::map<Record*, unsigned> BarriersMap; 196 197 // Emit all of the instruction's implicit uses and defs. 198 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 199 E = Target.inst_end(); II != E; ++II) { 200 Record *Inst = II->second.TheDef; 201 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 202 if (!Uses.empty()) { 203 unsigned &IL = EmittedLists[Uses]; 204 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 205 } 206 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 207 if (!Defs.empty()) { 208 std::vector<Record*> RCBarriers; 209 DetectRegisterClassBarriers(Defs, RCs, RCBarriers); 210 if (!RCBarriers.empty()) { 211 unsigned &IB = EmittedBarriers[RCBarriers]; 212 if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); 213 BarriersMap.insert(std::make_pair(Inst, IB)); 214 } 215 216 unsigned &IL = EmittedLists[Defs]; 217 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 218 } 219 } 220 221 OperandInfoMapTy OperandInfoIDs; 222 223 // Emit all of the operand info records. 224 EmitOperandInfo(OS, OperandInfoIDs); 225 226 // Emit all of the TargetInstrDesc records in their ENUM ordering. 227 // 228 OS << "\nstatic const TargetInstrDesc " << TargetName 229 << "Insts[] = {\n"; 230 std::vector<const CodeGenInstruction*> NumberedInstructions; 231 Target.getInstructionsByEnumValue(NumberedInstructions); 232 233 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 234 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 235 BarriersMap, OperandInfoIDs, OS); 236 OS << "};\n"; 237 OS << "} // End llvm namespace \n"; 238} 239 240void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 241 Record *InstrInfo, 242 std::map<std::vector<Record*>, unsigned> &EmittedLists, 243 std::map<Record*, unsigned> &BarriersMap, 244 const OperandInfoMapTy &OpInfo, 245 raw_ostream &OS) { 246 int MinOperands = 0; 247 if (!Inst.OperandList.empty()) 248 // Each logical operand can be multiple MI operands. 249 MinOperands = Inst.OperandList.back().MIOperandNo + 250 Inst.OperandList.back().MINumOperands; 251 252 OS << " { "; 253 OS << Num << ",\t" << MinOperands << ",\t" 254 << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) 255 << ",\t\"" << Inst.TheDef->getName() << "\", 0"; 256 257 // Emit all of the target indepedent flags... 258 if (Inst.isReturn) OS << "|(1<<TID::Return)"; 259 if (Inst.isBranch) OS << "|(1<<TID::Branch)"; 260 if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; 261 if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; 262 if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; 263 if (Inst.isCall) OS << "|(1<<TID::Call)"; 264 if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)"; 265 if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)"; 266 if (Inst.mayStore) OS << "|(1<<TID::MayStore)"; 267 if (Inst.isPredicable) OS << "|(1<<TID::Predicable)"; 268 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)"; 269 if (Inst.isCommutable) OS << "|(1<<TID::Commutable)"; 270 if (Inst.isTerminator) OS << "|(1<<TID::Terminator)"; 271 if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)"; 272 if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)"; 273 if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)"; 274 if (Inst.usesCustomDAGSchedInserter) 275 OS << "|(1<<TID::UsesCustomDAGSchedInserter)"; 276 if (Inst.isVariadic) OS << "|(1<<TID::Variadic)"; 277 if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)"; 278 if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)"; 279 OS << ", 0"; 280 281 // Emit all of the target-specific flags... 282 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields"); 283 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts"); 284 if (LI->getSize() != Shift->getSize()) 285 throw "Lengths of " + InstrInfo->getName() + 286 ":(TargetInfoFields, TargetInfoPositions) must be equal!"; 287 288 for (unsigned i = 0, e = LI->getSize(); i != e; ++i) 289 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)), 290 dynamic_cast<IntInit*>(Shift->getElement(i)), OS); 291 292 OS << ", "; 293 294 // Emit the implicit uses and defs lists... 295 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 296 if (UseList.empty()) 297 OS << "NULL, "; 298 else 299 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 300 301 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 302 if (DefList.empty()) 303 OS << "NULL, "; 304 else 305 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 306 307 std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef); 308 if (BI == BarriersMap.end()) 309 OS << "NULL, "; 310 else 311 OS << "Barriers" << BI->second << ", "; 312 313 // Emit the operand info. 314 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 315 if (OperandInfo.empty()) 316 OS << "0"; 317 else 318 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 319 320 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 321} 322 323 324void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, 325 IntInit *ShiftInt, raw_ostream &OS) { 326 if (Val == 0 || ShiftInt == 0) 327 throw std::string("Illegal value or shift amount in TargetInfo*!"); 328 RecordVal *RV = R->getValue(Val->getValue()); 329 int Shift = ShiftInt->getValue(); 330 331 if (RV == 0 || RV->getValue() == 0) { 332 // This isn't an error if this is a builtin instruction. 333 if (R->getName() != "PHI" && 334 R->getName() != "INLINEASM" && 335 R->getName() != "DBG_LABEL" && 336 R->getName() != "EH_LABEL" && 337 R->getName() != "GC_LABEL" && 338 R->getName() != "DECLARE" && 339 R->getName() != "EXTRACT_SUBREG" && 340 R->getName() != "INSERT_SUBREG" && 341 R->getName() != "IMPLICIT_DEF" && 342 R->getName() != "SUBREG_TO_REG" && 343 R->getName() != "COPY_TO_REGCLASS") 344 throw R->getName() + " doesn't have a field named '" + 345 Val->getValue() + "'!"; 346 return; 347 } 348 349 Init *Value = RV->getValue(); 350 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) { 351 if (BI->getValue()) OS << "|(1<<" << Shift << ")"; 352 return; 353 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) { 354 // Convert the Bits to an integer to print... 355 Init *I = BI->convertInitializerTo(new IntRecTy()); 356 if (I) 357 if (IntInit *II = dynamic_cast<IntInit*>(I)) { 358 if (II->getValue()) { 359 if (Shift) 360 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 361 else 362 OS << "|" << II->getValue(); 363 } 364 return; 365 } 366 367 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) { 368 if (II->getValue()) { 369 if (Shift) 370 OS << "|(" << II->getValue() << "<<" << Shift << ")"; 371 else 372 OS << II->getValue(); 373 } 374 return; 375 } 376 377 errs() << "Unhandled initializer: " << *Val << "\n"; 378 throw "In record '" + R->getName() + "' for TSFlag emission."; 379} 380 381