InstrInfoEmitter.cpp revision b923d2f5f5958719214472906e9810de262ab447
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15 16#include "CodeGenDAGPatterns.h" 17#include "CodeGenSchedule.h" 18#include "CodeGenTarget.h" 19#include "SequenceToOffsetTable.h" 20#include "TableGenBackends.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/TableGen/Error.h" 23#include "llvm/TableGen/Record.h" 24#include "llvm/TableGen/TableGenBackend.h" 25#include <algorithm> 26#include <cstdio> 27#include <map> 28#include <vector> 29using namespace llvm; 30 31namespace { 32class InstrInfoEmitter { 33 RecordKeeper &Records; 34 CodeGenDAGPatterns CDP; 35 const CodeGenSchedModels &SchedModels; 36 37public: 38 InstrInfoEmitter(RecordKeeper &R): 39 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {} 40 41 // run - Output the instruction set description. 42 void run(raw_ostream &OS); 43 44private: 45 void emitEnums(raw_ostream &OS); 46 47 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy; 48 49 /// The keys of this map are maps which have OpName enum values as their keys 50 /// and instruction operand indices as their values. The values of this map 51 /// are lists of instruction names. 52 typedef std::map<std::map<unsigned, unsigned>, 53 std::vector<std::string> > OpNameMapTy; 54 typedef std::map<std::string, unsigned>::iterator StrUintMapIter; 55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 56 Record *InstrInfo, 57 std::map<std::vector<Record*>, unsigned> &EL, 58 const OperandInfoMapTy &OpInfo, 59 raw_ostream &OS); 60 void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target); 61 void initOperandMapData( 62 const std::vector<const CodeGenInstruction *> NumberedInstructions, 63 const std::string &Namespace, 64 std::map<std::string, unsigned> &Operands, 65 OpNameMapTy &OperandMap); 66 void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target, 67 const std::vector<const CodeGenInstruction*> &NumberedInstructions); 68 69 // Operand information. 70 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); 71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 72}; 73} // End anonymous namespace 74 75static void PrintDefList(const std::vector<Record*> &Uses, 76 unsigned Num, raw_ostream &OS) { 77 OS << "static const uint16_t ImplicitList" << Num << "[] = { "; 78 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 79 OS << getQualifiedName(Uses[i]) << ", "; 80 OS << "0 };\n"; 81} 82 83//===----------------------------------------------------------------------===// 84// Operand Info Emission. 85//===----------------------------------------------------------------------===// 86 87std::vector<std::string> 88InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 89 std::vector<std::string> Result; 90 91 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 92 // Handle aggregate operands and normal operands the same way by expanding 93 // either case into a list of operands for this op. 94 std::vector<CGIOperandList::OperandInfo> OperandList; 95 96 // This might be a multiple operand thing. Targets like X86 have 97 // registers in their multi-operand operands. It may also be an anonymous 98 // operand, which has a single operand, but no declared class for the 99 // operand. 100 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 101 102 if (!MIOI || MIOI->getNumArgs() == 0) { 103 // Single, anonymous, operand. 104 OperandList.push_back(Inst.Operands[i]); 105 } else { 106 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 107 OperandList.push_back(Inst.Operands[i]); 108 109 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); 110 OperandList.back().Rec = OpR; 111 } 112 } 113 114 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 115 Record *OpR = OperandList[j].Rec; 116 std::string Res; 117 118 if (OpR->isSubClassOf("RegisterOperand")) 119 OpR = OpR->getValueAsDef("RegClass"); 120 if (OpR->isSubClassOf("RegisterClass")) 121 Res += getQualifiedName(OpR) + "RegClassID, "; 122 else if (OpR->isSubClassOf("PointerLikeRegClass")) 123 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; 124 else 125 // -1 means the operand does not have a fixed register class. 126 Res += "-1, "; 127 128 // Fill in applicable flags. 129 Res += "0"; 130 131 // Ptr value whose register class is resolved via callback. 132 if (OpR->isSubClassOf("PointerLikeRegClass")) 133 Res += "|(1<<MCOI::LookupPtrRegClass)"; 134 135 // Predicate operands. Check to see if the original unexpanded operand 136 // was of type PredicateOp. 137 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOp")) 138 Res += "|(1<<MCOI::Predicate)"; 139 140 // Optional def operands. Check to see if the original unexpanded operand 141 // was of type OptionalDefOperand. 142 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) 143 Res += "|(1<<MCOI::OptionalDef)"; 144 145 // Fill in operand type. 146 Res += ", MCOI::"; 147 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type."); 148 Res += Inst.Operands[i].OperandType; 149 150 // Fill in constraint info. 151 Res += ", "; 152 153 const CGIOperandList::ConstraintInfo &Constraint = 154 Inst.Operands[i].Constraints[j]; 155 if (Constraint.isNone()) 156 Res += "0"; 157 else if (Constraint.isEarlyClobber()) 158 Res += "(1 << MCOI::EARLY_CLOBBER)"; 159 else { 160 assert(Constraint.isTied()); 161 Res += "((" + utostr(Constraint.getTiedOperand()) + 162 " << 16) | (1 << MCOI::TIED_TO))"; 163 } 164 165 Result.push_back(Res); 166 } 167 } 168 169 return Result; 170} 171 172void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 173 OperandInfoMapTy &OperandInfoIDs) { 174 // ID #0 is for no operand info. 175 unsigned OperandListNum = 0; 176 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 177 178 OS << "\n"; 179 const CodeGenTarget &Target = CDP.getTargetInfo(); 180 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 181 E = Target.inst_end(); II != E; ++II) { 182 std::vector<std::string> OperandInfo = GetOperandInfo(**II); 183 unsigned &N = OperandInfoIDs[OperandInfo]; 184 if (N != 0) continue; 185 186 N = ++OperandListNum; 187 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { "; 188 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 189 OS << "{ " << OperandInfo[i] << " }, "; 190 OS << "};\n"; 191 } 192} 193 194 195/// Initialize data structures for generating operand name mappings. 196/// 197/// \param Operands [out] A map used to generate the OpName enum with operand 198/// names as its keys and operand enum values as its values. 199/// \param OperandMap [out] A map for representing the operand name mappings for 200/// each instructions. This is used to generate the OperandMap table as 201/// well as the getNamedOperandIdx() function. 202void InstrInfoEmitter::initOperandMapData( 203 const std::vector<const CodeGenInstruction *> NumberedInstructions, 204 const std::string &Namespace, 205 std::map<std::string, unsigned> &Operands, 206 OpNameMapTy &OperandMap) { 207 208 unsigned NumOperands = 0; 209 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 210 const CodeGenInstruction *Inst = NumberedInstructions[i]; 211 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) { 212 continue; 213 } 214 std::map<unsigned, unsigned> OpList; 215 for (unsigned j = 0, je = Inst->Operands.size(); j != je; ++j) { 216 const CGIOperandList::OperandInfo &Info = Inst->Operands[j]; 217 StrUintMapIter I = Operands.find(Info.Name); 218 219 if (I == Operands.end()) { 220 I = Operands.insert(Operands.begin(), 221 std::pair<std::string, unsigned>(Info.Name, NumOperands++)); 222 } 223 OpList[I->second] = Info.MIOperandNo; 224 } 225 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); 226 } 227} 228 229/// Generate a table and function for looking up the indices of operands by 230/// name. 231/// 232/// This code generates: 233/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry 234/// for each operand name. 235/// - A 2-dimensional table called OperandMap for mapping OpName enum values to 236/// operand indices. 237/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) 238/// for looking up the operand index for an instruction, given a value from 239/// OpName enum 240void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, 241 const CodeGenTarget &Target, 242 const std::vector<const CodeGenInstruction*> &NumberedInstructions) { 243 244 const std::string &Namespace = Target.getInstNamespace(); 245 std::string OpNameNS = "OpName"; 246 // Map of operand names to their enumeration value. This will be used to 247 // generate the OpName enum. 248 std::map<std::string, unsigned> Operands; 249 OpNameMapTy OperandMap; 250 251 initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap); 252 253 OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n"; 254 OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n"; 255 OS << "namespace llvm {"; 256 OS << "namespace " << Namespace << " {\n"; 257 OS << "namespace " << OpNameNS << " { \n"; 258 OS << "enum {\n"; 259 for (StrUintMapIter i = Operands.begin(), e = Operands.end(); i != e; ++i) 260 OS << " " << i->first << " = " << i->second << ",\n"; 261 262 OS << "OPERAND_LAST"; 263 OS << "\n};\n"; 264 OS << "} // End namespace OpName\n"; 265 OS << "} // End namespace " << Namespace << "\n"; 266 OS << "} // End namespace llvm\n"; 267 OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n"; 268 269 OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n"; 270 OS << "#undef GET_INSTRINFO_NAMED_OPS\n"; 271 OS << "namespace llvm {"; 272 OS << "namespace " << Namespace << " {\n"; 273 OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n"; 274 if (!Operands.empty()) { 275 OS << " static const int16_t OperandMap [][" << Operands.size() 276 << "] = {\n"; 277 for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end(); 278 i != e; ++i) { 279 const std::map<unsigned, unsigned> &OpList = i->first; 280 OS << "{"; 281 282 // Emit a row of the OperandMap table 283 for (unsigned ii = 0, ie = Operands.size(); ii != ie; ++ii) 284 OS << (OpList.count(ii) == 0 ? -1 : (int)OpList.find(ii)->second) 285 << ", "; 286 287 OS << "},\n"; 288 } 289 OS << "};\n"; 290 291 OS << " switch(Opcode) {\n"; 292 unsigned TableIndex = 0; 293 for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end(); 294 i != e; ++i) { 295 std::vector<std::string> &OpcodeList = i->second; 296 297 for (unsigned ii = 0, ie = OpcodeList.size(); ii != ie; ++ii) 298 OS << " case " << OpcodeList[ii] << ":\n"; 299 300 OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n"; 301 } 302 OS << " default: return -1;\n"; 303 OS << " }\n"; 304 } else { 305 // There are no operands, so no need to emit anything 306 OS << " return -1;\n"; 307 } 308 OS << "}\n"; 309 OS << "} // End namespace " << Namespace << "\n"; 310 OS << "} // End namespace llvm\n"; 311 OS << "#endif //GET_INSTRINFO_NAMED_OPS\n"; 312 313} 314 315/// Generate an enum for all the operand types for this target, under the 316/// llvm::TargetNamespace::OpTypes namespace. 317/// Operand types are all definitions derived of the Operand Target.td class. 318void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS, 319 const CodeGenTarget &Target) { 320 321 const std::string &Namespace = Target.getInstNamespace(); 322 std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand"); 323 324 OS << "\n#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 325 OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 326 OS << "namespace llvm {"; 327 OS << "namespace " << Namespace << " {\n"; 328 OS << "namespace OpTypes { \n"; 329 OS << "enum OperandType {\n"; 330 331 for (unsigned oi = 0, oe = Operands.size(); oi != oe; ++oi) { 332 if (!Operands[oi]->isAnonymous()) 333 OS << " " << Operands[oi]->getName() << " = " << oi << ",\n"; 334 } 335 336 OS << " OPERAND_TYPE_LIST_END" << "\n};\n"; 337 OS << "} // End namespace OpTypes\n"; 338 OS << "} // End namespace " << Namespace << "\n"; 339 OS << "} // End namespace llvm\n"; 340 OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 341} 342 343//===----------------------------------------------------------------------===// 344// Main Output. 345//===----------------------------------------------------------------------===// 346 347// run - Emit the main instruction description records for the target... 348void InstrInfoEmitter::run(raw_ostream &OS) { 349 emitSourceFileHeader("Target Instruction Enum Values", OS); 350 emitEnums(OS); 351 352 emitSourceFileHeader("Target Instruction Descriptors", OS); 353 354 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n"; 355 OS << "#undef GET_INSTRINFO_MC_DESC\n"; 356 357 OS << "namespace llvm {\n\n"; 358 359 CodeGenTarget &Target = CDP.getTargetInfo(); 360 const std::string &TargetName = Target.getName(); 361 Record *InstrInfo = Target.getInstructionSet(); 362 363 // Keep track of all of the def lists we have emitted already. 364 std::map<std::vector<Record*>, unsigned> EmittedLists; 365 unsigned ListNumber = 0; 366 367 // Emit all of the instruction's implicit uses and defs. 368 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 369 E = Target.inst_end(); II != E; ++II) { 370 Record *Inst = (*II)->TheDef; 371 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 372 if (!Uses.empty()) { 373 unsigned &IL = EmittedLists[Uses]; 374 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 375 } 376 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 377 if (!Defs.empty()) { 378 unsigned &IL = EmittedLists[Defs]; 379 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 380 } 381 } 382 383 OperandInfoMapTy OperandInfoIDs; 384 385 // Emit all of the operand info records. 386 EmitOperandInfo(OS, OperandInfoIDs); 387 388 // Emit all of the MCInstrDesc records in their ENUM ordering. 389 // 390 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n"; 391 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 392 Target.getInstructionsByEnumValue(); 393 394 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 395 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 396 OperandInfoIDs, OS); 397 OS << "};\n\n"; 398 399 // Build an array of instruction names 400 SequenceToOffsetTable<std::string> InstrNames; 401 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 402 const CodeGenInstruction *Instr = NumberedInstructions[i]; 403 InstrNames.add(Instr->TheDef->getName()); 404 } 405 406 InstrNames.layout(); 407 OS << "extern const char " << TargetName << "InstrNameData[] = {\n"; 408 InstrNames.emit(OS, printChar); 409 OS << "};\n\n"; 410 411 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {"; 412 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 413 if (i % 8 == 0) 414 OS << "\n "; 415 const CodeGenInstruction *Instr = NumberedInstructions[i]; 416 OS << InstrNames.get(Instr->TheDef->getName()) << "U, "; 417 } 418 419 OS << "\n};\n\n"; 420 421 // MCInstrInfo initialization routine. 422 OS << "static inline void Init" << TargetName 423 << "MCInstrInfo(MCInstrInfo *II) {\n"; 424 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, " 425 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 426 << NumberedInstructions.size() << ");\n}\n\n"; 427 428 OS << "} // End llvm namespace \n"; 429 430 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; 431 432 // Create a TargetInstrInfo subclass to hide the MC layer initialization. 433 OS << "\n#ifdef GET_INSTRINFO_HEADER\n"; 434 OS << "#undef GET_INSTRINFO_HEADER\n"; 435 436 std::string ClassName = TargetName + "GenInstrInfo"; 437 OS << "namespace llvm {\n"; 438 OS << "struct " << ClassName << " : public TargetInstrInfo {\n" 439 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n" 440 << " virtual ~" << ClassName << "();\n" 441 << "};\n"; 442 OS << "} // End llvm namespace \n"; 443 444 OS << "#endif // GET_INSTRINFO_HEADER\n\n"; 445 446 OS << "\n#ifdef GET_INSTRINFO_CTOR_DTOR\n"; 447 OS << "#undef GET_INSTRINFO_CTOR_DTOR\n"; 448 449 OS << "namespace llvm {\n"; 450 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; 451 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n"; 452 OS << "extern const char " << TargetName << "InstrNameData[];\n"; 453 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n" 454 << " : TargetInstrInfo(SO, DO) {\n" 455 << " InitMCInstrInfo(" << TargetName << "Insts, " 456 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 457 << NumberedInstructions.size() << ");\n}\n" 458 << ClassName << "::~" << ClassName << "() {}\n"; 459 OS << "} // End llvm namespace \n"; 460 461 OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n"; 462 463 emitOperandNameMappings(OS, Target, NumberedInstructions); 464 465 emitOperandTypesEnum(OS, Target); 466} 467 468void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 469 Record *InstrInfo, 470 std::map<std::vector<Record*>, unsigned> &EmittedLists, 471 const OperandInfoMapTy &OpInfo, 472 raw_ostream &OS) { 473 int MinOperands = 0; 474 if (!Inst.Operands.empty()) 475 // Each logical operand can be multiple MI operands. 476 MinOperands = Inst.Operands.back().MIOperandNo + 477 Inst.Operands.back().MINumOperands; 478 479 OS << " { "; 480 OS << Num << ",\t" << MinOperands << ",\t" 481 << Inst.Operands.NumDefs << ",\t" 482 << SchedModels.getSchedClassIdx(Inst) << ",\t" 483 << Inst.TheDef->getValueAsInt("Size") << ",\t0"; 484 485 // Emit all of the target indepedent flags... 486 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)"; 487 if (Inst.isReturn) OS << "|(1<<MCID::Return)"; 488 if (Inst.isBranch) OS << "|(1<<MCID::Branch)"; 489 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)"; 490 if (Inst.isCompare) OS << "|(1<<MCID::Compare)"; 491 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)"; 492 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)"; 493 if (Inst.isSelect) OS << "|(1<<MCID::Select)"; 494 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)"; 495 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)"; 496 if (Inst.isCall) OS << "|(1<<MCID::Call)"; 497 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)"; 498 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)"; 499 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)"; 500 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)"; 501 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)"; 502 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)"; 503 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)"; 504 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)"; 505 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)"; 506 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)"; 507 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)"; 508 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)"; 509 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)"; 510 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)"; 511 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)"; 512 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; 513 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; 514 515 // Emit all of the target-specific flags... 516 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); 517 if (!TSF) 518 PrintFatalError("no TSFlags?"); 519 uint64_t Value = 0; 520 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { 521 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) 522 Value |= uint64_t(Bit->getValue()) << i; 523 else 524 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); 525 } 526 OS << ", 0x"; 527 OS.write_hex(Value); 528 OS << "ULL, "; 529 530 // Emit the implicit uses and defs lists... 531 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 532 if (UseList.empty()) 533 OS << "NULL, "; 534 else 535 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 536 537 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 538 if (DefList.empty()) 539 OS << "NULL, "; 540 else 541 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 542 543 // Emit the operand info. 544 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 545 if (OperandInfo.empty()) 546 OS << "0"; 547 else 548 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 549 550 CodeGenTarget &Target = CDP.getTargetInfo(); 551 if (Inst.HasComplexDeprecationPredicate) 552 // Emit a function pointer to the complex predicate method. 553 OS << ",0" 554 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo"; 555 else if (!Inst.DeprecatedReason.empty()) 556 // Emit the Subtarget feature. 557 OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason 558 << ",0"; 559 else 560 // Instruction isn't deprecated. 561 OS << ",0,0"; 562 563 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 564} 565 566// emitEnums - Print out enum values for all of the instructions. 567void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 568 569 OS << "\n#ifdef GET_INSTRINFO_ENUM\n"; 570 OS << "#undef GET_INSTRINFO_ENUM\n"; 571 572 OS << "namespace llvm {\n\n"; 573 574 CodeGenTarget Target(Records); 575 576 // We must emit the PHI opcode first... 577 std::string Namespace = Target.getInstNamespace(); 578 579 if (Namespace.empty()) { 580 fprintf(stderr, "No instructions defined!\n"); 581 exit(1); 582 } 583 584 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 585 Target.getInstructionsByEnumValue(); 586 587 OS << "namespace " << Namespace << " {\n"; 588 OS << " enum {\n"; 589 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 590 OS << " " << NumberedInstructions[i]->TheDef->getName() 591 << "\t= " << i << ",\n"; 592 } 593 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; 594 OS << " };\n"; 595 OS << "namespace Sched {\n"; 596 OS << " enum {\n"; 597 for (unsigned i = 0, e = SchedModels.numInstrSchedClasses(); i != e; ++i) { 598 OS << " " << SchedModels.getSchedClass(i).Name 599 << "\t= " << i << ",\n"; 600 } 601 OS << " SCHED_LIST_END = " << SchedModels.numInstrSchedClasses() << "\n"; 602 OS << " };\n}\n}\n"; 603 OS << "} // End llvm namespace \n"; 604 605 OS << "#endif // GET_INSTRINFO_ENUM\n\n"; 606} 607 608namespace llvm { 609 610void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 611 InstrInfoEmitter(RK).run(OS); 612 EmitMapTable(RK, OS); 613} 614 615} // End llvm namespace 616