InstrInfoEmitter.cpp revision dcc8b4f5d3f62ae84aae100638085dedeee91588 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "Record.h"
18#include <algorithm>
19#include <iostream>
20using namespace llvm;
21
22static void PrintDefList(const std::vector<Record*> &Uses,
23                         unsigned Num, std::ostream &OS) {
24  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26    OS << getQualifiedName(Uses[i]) << ", ";
27  OS << "0 };\n";
28}
29
30//===----------------------------------------------------------------------===//
31// Instruction Itinerary Information.
32//===----------------------------------------------------------------------===//
33
34struct RecordNameComparator {
35  bool operator()(const Record *Rec1, const Record *Rec2) const {
36    return Rec1->getName() < Rec2->getName();
37  }
38};
39
40void InstrInfoEmitter::GatherItinClasses() {
41  std::vector<Record*> DefList =
42  Records.getAllDerivedDefinitions("InstrItinClass");
43  std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
44
45  for (unsigned i = 0, N = DefList.size(); i < N; i++)
46    ItinClassMap[DefList[i]->getName()] = i;
47}
48
49unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
50  return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
51}
52
53//===----------------------------------------------------------------------===//
54// Operand Info Emission.
55//===----------------------------------------------------------------------===//
56
57std::vector<std::string>
58InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
59  std::vector<std::string> Result;
60
61  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
62    // Handle aggregate operands and normal operands the same way by expanding
63    // either case into a list of operands for this op.
64    std::vector<CodeGenInstruction::OperandInfo> OperandList;
65
66    // This might be a multiple operand thing.  Targets like X86 have
67    // registers in their multi-operand operands.  It may also be an anonymous
68    // operand, which has a single operand, but no declared class for the
69    // operand.
70    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
71
72    if (!MIOI || MIOI->getNumArgs() == 0) {
73      // Single, anonymous, operand.
74      OperandList.push_back(Inst.OperandList[i]);
75    } else {
76      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
77        OperandList.push_back(Inst.OperandList[i]);
78
79        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
80        OperandList.back().Rec = OpR;
81      }
82    }
83
84    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
85      Record *OpR = OperandList[j].Rec;
86      std::string Res;
87
88      if (OpR->isSubClassOf("RegisterClass"))
89        Res += getQualifiedName(OpR) + "RegClassID, ";
90      else
91        Res += "0, ";
92      // Fill in applicable flags.
93      Res += "0";
94
95      // Ptr value whose register class is resolved via callback.
96      if (OpR->getName() == "ptr_rc")
97        Res += "|(1<<TOI::LookupPtrRegClass)";
98
99      // Predicate operands.  Check to see if the original unexpanded operand
100      // was of type PredicateOperand.
101      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
102        Res += "|(1<<TOI::Predicate)";
103
104      // Optional def operands.  Check to see if the original unexpanded operand
105      // was of type OptionalDefOperand.
106      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
107        Res += "|(1<<TOI::OptionalDef)";
108
109      // Fill in constraint info.
110      Res += ", " + Inst.OperandList[i].Constraints[j];
111      Result.push_back(Res);
112    }
113  }
114
115  return Result;
116}
117
118void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
119                                       OperandInfoMapTy &OperandInfoIDs) {
120  // ID #0 is for no operand info.
121  unsigned OperandListNum = 0;
122  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
123
124  OS << "\n";
125  const CodeGenTarget &Target = CDP.getTargetInfo();
126  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
127       E = Target.inst_end(); II != E; ++II) {
128    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
129    unsigned &N = OperandInfoIDs[OperandInfo];
130    if (N != 0) continue;
131
132    N = ++OperandListNum;
133    OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
134    for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
135      OS << "{ " << OperandInfo[i] << " }, ";
136    OS << "};\n";
137  }
138}
139
140//===----------------------------------------------------------------------===//
141// Instruction Analysis
142//===----------------------------------------------------------------------===//
143
144class InstAnalyzer {
145  const CodeGenDAGPatterns &CDP;
146  bool &mayStore;
147  bool &mayLoad;
148  bool &NeverHasSideEffects;
149public:
150  InstAnalyzer(const CodeGenDAGPatterns &cdp,
151               bool &maystore, bool &mayload, bool &nhse)
152    : CDP(cdp), mayStore(maystore), mayLoad(mayload), NeverHasSideEffects(nhse){
153  }
154
155  void Analyze(Record *InstRecord) {
156    const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern();
157    if (Pattern == 0) return;  // No pattern.
158
159    // Assume there is no side-effect unless we see one.
160    NeverHasSideEffects = true;
161
162    // FIXME: Assume only the first tree is the pattern. The others are clobber
163    // nodes.
164    AnalyzeNode(Pattern->getTree(0));
165  }
166
167private:
168  void AnalyzeNode(const TreePatternNode *N) {
169    if (N->isLeaf())
170      return;
171
172    if (N->getOperator()->getName() != "set") {
173      // Get information about the SDNode for the operator.
174      const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
175
176      // If node writes to memory, it obviously stores to memory.
177      if (OpInfo.hasProperty(SDNPMayStore)) {
178        mayStore = true;
179      } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
180        // If this is an intrinsic, analyze it.
181        if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
182          mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
183      }
184    }
185
186    for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
187      AnalyzeNode(N->getChild(i));
188  }
189
190};
191
192void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
193                                        bool &mayStore, bool &mayLoad,
194                                        bool &NeverHasSideEffects) {
195  mayStore = mayLoad = NeverHasSideEffects = false;
196
197  InstAnalyzer(CDP, mayStore, mayLoad,NeverHasSideEffects).Analyze(Inst.TheDef);
198
199  // InstAnalyzer only correctly analyzes mayStore so far.
200  if (Inst.mayStore) {  // If the .td file explicitly sets mayStore, use it.
201    // If we decided that this is a store from the pattern, then the .td file
202    // entry is redundant.
203    if (mayStore)
204      fprintf(stderr,
205              "Warning: mayStore flag explicitly set on instruction '%s'"
206              " but flag already inferred from pattern.\n",
207              Inst.TheDef->getName().c_str());
208    mayStore = true;
209  }
210
211  // These two override everything.
212  mayLoad             = Inst.mayLoad;
213  NeverHasSideEffects = Inst.neverHasSideEffects;
214
215#if 0
216  // If the .td file explicitly says there is no side effect, believe it.
217  if (Inst.neverHasSideEffects)
218    NeverHasSideEffects = true;
219#endif
220}
221
222
223//===----------------------------------------------------------------------===//
224// Main Output.
225//===----------------------------------------------------------------------===//
226
227// run - Emit the main instruction description records for the target...
228void InstrInfoEmitter::run(std::ostream &OS) {
229  GatherItinClasses();
230
231  EmitSourceFileHeader("Target Instruction Descriptors", OS);
232  OS << "namespace llvm {\n\n";
233
234  CodeGenTarget Target;
235  const std::string &TargetName = Target.getName();
236  Record *InstrInfo = Target.getInstructionSet();
237
238  // Keep track of all of the def lists we have emitted already.
239  std::map<std::vector<Record*>, unsigned> EmittedLists;
240  unsigned ListNumber = 0;
241
242  // Emit all of the instruction's implicit uses and defs.
243  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
244         E = Target.inst_end(); II != E; ++II) {
245    Record *Inst = II->second.TheDef;
246    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
247    if (!Uses.empty()) {
248      unsigned &IL = EmittedLists[Uses];
249      if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
250    }
251    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
252    if (!Defs.empty()) {
253      unsigned &IL = EmittedLists[Defs];
254      if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
255    }
256  }
257
258  OperandInfoMapTy OperandInfoIDs;
259
260  // Emit all of the operand info records.
261  EmitOperandInfo(OS, OperandInfoIDs);
262
263  // Emit all of the TargetInstrDesc records in their ENUM ordering.
264  //
265  OS << "\nstatic const TargetInstrDesc " << TargetName
266     << "Insts[] = {\n";
267  std::vector<const CodeGenInstruction*> NumberedInstructions;
268  Target.getInstructionsByEnumValue(NumberedInstructions);
269
270  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
271    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
272               OperandInfoIDs, OS);
273  OS << "};\n";
274  OS << "} // End llvm namespace \n";
275}
276
277void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
278                                  Record *InstrInfo,
279                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
280                                  const OperandInfoMapTy &OpInfo,
281                                  std::ostream &OS) {
282  // Determine properties of the instruction from its pattern.
283  bool mayStore, mayLoad, NeverHasSideEffects;
284  InferFromPattern(Inst, mayStore, mayLoad, NeverHasSideEffects);
285
286  if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
287    std::cerr << "error: Instruction '" << Inst.TheDef->getName()
288      << "' is marked with 'mayHaveSideEffects', but it can never have them!\n";
289    exit(1);
290  }
291
292  int MinOperands = 0;
293  if (!Inst.OperandList.empty())
294    // Each logical operand can be multiple MI operands.
295    MinOperands = Inst.OperandList.back().MIOperandNo +
296                  Inst.OperandList.back().MINumOperands;
297
298  OS << "  { ";
299  OS << Num << ",\t" << MinOperands << ",\t"
300     << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
301     << ",\t\"" << Inst.TheDef->getName() << "\", 0";
302
303  // Emit all of the target indepedent flags...
304  if (Inst.isReturn)     OS << "|(1<<TID::Return)";
305  if (Inst.isBranch)     OS << "|(1<<TID::Branch)";
306  if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
307  if (Inst.isBarrier)    OS << "|(1<<TID::Barrier)";
308  if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
309  if (Inst.isCall)       OS << "|(1<<TID::Call)";
310  if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
311  if (mayLoad)           OS << "|(1<<TID::MayLoad)";
312  if (mayStore)          OS << "|(1<<TID::MayStore)";
313  if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
314  if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
315  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
316  if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
317  if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
318  if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
319  if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
320  if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
321  if (Inst.usesCustomDAGSchedInserter)
322    OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
323  if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
324  if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)";
325  if (NeverHasSideEffects)     OS << "|(1<<TID::NeverHasSideEffects)";
326  OS << ", 0";
327
328  // Emit all of the target-specific flags...
329  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
330  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
331  if (LI->getSize() != Shift->getSize())
332    throw "Lengths of " + InstrInfo->getName() +
333          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
334
335  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
336    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
337                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
338
339  OS << ", ";
340
341  // Emit the implicit uses and defs lists...
342  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
343  if (UseList.empty())
344    OS << "NULL, ";
345  else
346    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
347
348  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
349  if (DefList.empty())
350    OS << "NULL, ";
351  else
352    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
353
354  // Emit the operand info.
355  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
356  if (OperandInfo.empty())
357    OS << "0";
358  else
359    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
360
361  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
362}
363
364
365void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
366                                        IntInit *ShiftInt, std::ostream &OS) {
367  if (Val == 0 || ShiftInt == 0)
368    throw std::string("Illegal value or shift amount in TargetInfo*!");
369  RecordVal *RV = R->getValue(Val->getValue());
370  int Shift = ShiftInt->getValue();
371
372  if (RV == 0 || RV->getValue() == 0) {
373    // This isn't an error if this is a builtin instruction.
374    if (R->getName() != "PHI" &&
375        R->getName() != "INLINEASM" &&
376        R->getName() != "LABEL" &&
377        R->getName() != "EXTRACT_SUBREG" &&
378        R->getName() != "INSERT_SUBREG")
379      throw R->getName() + " doesn't have a field named '" +
380            Val->getValue() + "'!";
381    return;
382  }
383
384  Init *Value = RV->getValue();
385  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
386    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
387    return;
388  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
389    // Convert the Bits to an integer to print...
390    Init *I = BI->convertInitializerTo(new IntRecTy());
391    if (I)
392      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
393        if (II->getValue()) {
394          if (Shift)
395            OS << "|(" << II->getValue() << "<<" << Shift << ")";
396          else
397            OS << "|" << II->getValue();
398        }
399        return;
400      }
401
402  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
403    if (II->getValue()) {
404      if (Shift)
405        OS << "|(" << II->getValue() << "<<" << Shift << ")";
406      else
407        OS << II->getValue();
408    }
409    return;
410  }
411
412  std::cerr << "Unhandled initializer: " << *Val << "\n";
413  throw "In record '" + R->getName() + "' for TSFlag emission.";
414}
415
416