InstrInfoEmitter.cpp revision eff5c3623848152b60457318af8e23df25496449 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "Record.h"
18#include <algorithm>
19using namespace llvm;
20
21// runEnums - Print out enum values for all of the instructions.
22void InstrInfoEmitter::runEnums(std::ostream &OS) {
23  EmitSourceFileHeader("Target Instruction Enum Values", OS);
24  OS << "namespace llvm {\n\n";
25
26  CodeGenTarget Target;
27
28  // We must emit the PHI opcode first...
29  Record *InstrInfo = Target.getInstructionSet();
30
31  std::string Namespace;
32  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
33       E = Target.inst_end(); II != E; ++II) {
34    if (II->second.Namespace != "TargetInstrInfo") {
35      Namespace = II->second.Namespace;
36      break;
37    }
38  }
39
40  if (Namespace.empty()) {
41    std::cerr << "No instructions defined!\n";
42    exit(1);
43  }
44
45  std::vector<const CodeGenInstruction*> NumberedInstructions;
46  Target.getInstructionsByEnumValue(NumberedInstructions);
47
48  OS << "namespace " << Namespace << " {\n";
49  OS << "  enum {\n";
50  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
51    OS << "    " << NumberedInstructions[i]->TheDef->getName()
52       << "\t= " << i << ",\n";
53  }
54  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
55  OS << "  };\n}\n";
56  OS << "} // End llvm namespace \n";
57}
58
59void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
60                                    unsigned Num, std::ostream &OS) const {
61  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
62  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
63    OS << getQualifiedName(Uses[i]) << ", ";
64  OS << "0 };\n";
65}
66
67static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
68  std::vector<Record*> Result;
69  if (Inst.hasVariableNumberOfOperands)
70    return Result;  // No info for variable operand instrs.
71
72  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
73    if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
74      Result.push_back(Inst.OperandList[i].Rec);
75    } else {
76      // This might be a multiple operand thing.
77      // Targets like X86 have registers in their multi-operand operands.
78      DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
79      unsigned NumDefs = MIOI->getNumArgs();
80      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
81        if (NumDefs <= j) {
82          Result.push_back(0);
83        } else {
84          DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
85          Result.push_back(Def ? Def->getDef() : 0);
86        }
87      }
88    }
89  }
90  return Result;
91}
92
93
94// run - Emit the main instruction description records for the target...
95void InstrInfoEmitter::run(std::ostream &OS) {
96  GatherItinClasses();
97
98  EmitSourceFileHeader("Target Instruction Descriptors", OS);
99  OS << "namespace llvm {\n\n";
100
101  CodeGenTarget Target;
102  const std::string &TargetName = Target.getName();
103  Record *InstrInfo = Target.getInstructionSet();
104
105  // Emit empty implicit uses and defs lists
106  OS << "static const unsigned EmptyImpList[] = { 0 };\n";
107
108  // Keep track of all of the def lists we have emitted already.
109  std::map<std::vector<Record*>, unsigned> EmittedLists;
110  unsigned ListNumber = 0;
111
112  // Emit all of the instruction's implicit uses and defs.
113  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
114         E = Target.inst_end(); II != E; ++II) {
115    Record *Inst = II->second.TheDef;
116    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
117    if (!Uses.empty()) {
118      unsigned &IL = EmittedLists[Uses];
119      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
120    }
121    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
122    if (!Defs.empty()) {
123      unsigned &IL = EmittedLists[Defs];
124      if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
125    }
126  }
127
128  std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
129  unsigned OperandListNum = 0;
130  OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
131
132  // Emit all of the operand info records.
133  OS << "\n";
134  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
135       E = Target.inst_end(); II != E; ++II) {
136    std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
137    unsigned &N = OperandInfosEmitted[OperandInfo];
138    if (N == 0) {
139      N = ++OperandListNum;
140      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
141      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
142        Record *RC = OperandInfo[i];
143        // FIXME: We only care about register operands for now.
144        if (RC && RC->isSubClassOf("RegisterClass")) {
145          OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
146        } else {
147          OS << "{ 0 }, ";
148        }
149      }
150      OS << "};\n";
151    }
152  }
153
154  // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
155  //
156  OS << "\nstatic const TargetInstrDescriptor " << TargetName
157     << "Insts[] = {\n";
158  std::vector<const CodeGenInstruction*> NumberedInstructions;
159  Target.getInstructionsByEnumValue(NumberedInstructions);
160
161  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
162    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
163               OperandInfosEmitted, OS);
164  OS << "};\n";
165  OS << "} // End llvm namespace \n";
166}
167
168void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
169                                  Record *InstrInfo,
170                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
171                               std::map<std::vector<Record*>, unsigned> &OpInfo,
172                                  std::ostream &OS) {
173  int NumOperands;
174  if (Inst.hasVariableNumberOfOperands)
175    NumOperands = -1;
176  else if (!Inst.OperandList.empty())
177    // Each logical operand can be multiple MI operands.
178    NumOperands = Inst.OperandList.back().MIOperandNo +
179                  Inst.OperandList.back().MINumOperands;
180  else
181    NumOperands = 0;
182
183  OS << "  { \"";
184  if (Inst.Name.empty())
185    OS << Inst.TheDef->getName();
186  else
187    OS << Inst.Name;
188
189  unsigned ItinClass = !IsItineraries ? 0 :
190            ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
191
192  OS << "\",\t" << NumOperands << ", " << ItinClass
193     << ", 0";
194
195  // Try to determine (from the pattern), if the instruction is a store.
196  bool isStore = false;
197  if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
198    ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
199    if (LI && LI->getSize() > 0) {
200      DagInit *Dag = (DagInit *)LI->getElement(0);
201      DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
202      if (OpDef) {
203        Record *Operator = OpDef->getDef();
204        if (Operator->isSubClassOf("SDNode") &&
205            Operator->getValueAsString("Opcode") == "ISD::STORE")
206          isStore = true;
207      }
208    }
209  }
210
211  // Emit all of the target indepedent flags...
212  if (Inst.isReturn)     OS << "|M_RET_FLAG";
213  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
214  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
215  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
216  if (Inst.isCall)       OS << "|M_CALL_FLAG";
217  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
218  if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
219  if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
220  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
221  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
222  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
223  if (Inst.usesCustomDAGSchedInserter)
224    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
225  OS << ", 0";
226
227  // Emit all of the target-specific flags...
228  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
229  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
230  if (LI->getSize() != Shift->getSize())
231    throw "Lengths of " + InstrInfo->getName() +
232          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
233
234  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
235    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
236                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
237
238  OS << ", ";
239
240  // Emit the implicit uses and defs lists...
241  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
242  if (UseList.empty())
243    OS << "EmptyImpList, ";
244  else
245    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
246
247  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
248  if (DefList.empty())
249    OS << "EmptyImpList, ";
250  else
251    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
252
253  // Emit the operand info.
254  std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
255  if (OperandInfo.empty())
256    OS << "0";
257  else
258    OS << "OperandInfo" << OpInfo[OperandInfo];
259
260  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
261}
262
263struct LessRecord {
264  bool operator()(const Record *Rec1, const Record *Rec2) const {
265    return Rec1->getName() < Rec2->getName();
266  }
267};
268void InstrInfoEmitter::GatherItinClasses() {
269  std::vector<Record*> DefList =
270                          Records.getAllDerivedDefinitions("InstrItinClass");
271  IsItineraries = !DefList.empty();
272
273  if (!IsItineraries) return;
274
275  std::sort(DefList.begin(), DefList.end(), LessRecord());
276
277  for (unsigned i = 0, N = DefList.size(); i < N; i++) {
278    Record *Def = DefList[i];
279    ItinClassMap[Def->getName()] = i;
280  }
281}
282
283unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
284  return ItinClassMap[ItinName];
285}
286
287void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
288                                        IntInit *ShiftInt, std::ostream &OS) {
289  if (Val == 0 || ShiftInt == 0)
290    throw std::string("Illegal value or shift amount in TargetInfo*!");
291  RecordVal *RV = R->getValue(Val->getValue());
292  int Shift = ShiftInt->getValue();
293
294  if (RV == 0 || RV->getValue() == 0) {
295    // This isn't an error if this is a builtin instruction.
296    if (R->getName() != "PHI" && R->getName() != "INLINEASM")
297      throw R->getName() + " doesn't have a field named '" +
298            Val->getValue() + "'!";
299    return;
300  }
301
302  Init *Value = RV->getValue();
303  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
304    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
305    return;
306  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
307    // Convert the Bits to an integer to print...
308    Init *I = BI->convertInitializerTo(new IntRecTy());
309    if (I)
310      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
311        if (II->getValue()) {
312          if (Shift)
313            OS << "|(" << II->getValue() << "<<" << Shift << ")";
314          else
315            OS << "|" << II->getValue();
316        }
317        return;
318      }
319
320  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
321    if (II->getValue()) {
322      if (Shift)
323        OS << "|(" << II->getValue() << "<<" << Shift << ")";
324      else
325        OS << II->getValue();
326    }
327    return;
328  }
329
330  std::cerr << "Unhandled initializer: " << *Val << "\n";
331  throw "In record '" + R->getName() + "' for TSFlag emission.";
332}
333
334