r600_state_common.c revision a19e6a8f2840be9a59e46c8d408658715ae47bf0
1/* 2 * Copyright 2010 Red Hat Inc. 3 * 2010 Jerome Glisse 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie <airlied@redhat.com> 25 * Jerome Glisse <jglisse@redhat.com> 26 */ 27#include "util/u_blitter.h" 28#include "util/u_memory.h" 29#include "util/u_format.h" 30#include "pipebuffer/pb_buffer.h" 31#include "pipe/p_shader_tokens.h" 32#include "tgsi/tgsi_parse.h" 33#include "r600_formats.h" 34#include "r600_pipe.h" 35#include "r600d.h" 36 37static void r600_spi_update(struct r600_pipe_context *rctx); 38 39static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim) 40{ 41 static const int prim_conv[] = { 42 V_008958_DI_PT_POINTLIST, 43 V_008958_DI_PT_LINELIST, 44 V_008958_DI_PT_LINELOOP, 45 V_008958_DI_PT_LINESTRIP, 46 V_008958_DI_PT_TRILIST, 47 V_008958_DI_PT_TRISTRIP, 48 V_008958_DI_PT_TRIFAN, 49 V_008958_DI_PT_QUADLIST, 50 V_008958_DI_PT_QUADSTRIP, 51 V_008958_DI_PT_POLYGON, 52 -1, 53 -1, 54 -1, 55 -1 56 }; 57 58 *prim = prim_conv[pprim]; 59 if (*prim == -1) { 60 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim); 61 return false; 62 } 63 return true; 64} 65 66/* common state between evergreen and r600 */ 67void r600_bind_blend_state(struct pipe_context *ctx, void *state) 68{ 69 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 70 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state; 71 struct r600_pipe_state *rstate; 72 73 if (state == NULL) 74 return; 75 rstate = &blend->rstate; 76 rctx->states[rstate->id] = rstate; 77 rctx->cb_target_mask = blend->cb_target_mask; 78 r600_context_pipe_state_set(&rctx->ctx, rstate); 79} 80 81void r600_bind_dsa_state(struct pipe_context *ctx, void *state) 82{ 83 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 84 struct r600_pipe_dsa *dsa = state; 85 struct r600_pipe_state *rstate; 86 87 if (state == NULL) 88 return; 89 rstate = &dsa->rstate; 90 rctx->states[rstate->id] = rstate; 91 rctx->alpha_ref = dsa->alpha_ref; 92 rctx->alpha_ref_dirty = true; 93 r600_context_pipe_state_set(&rctx->ctx, rstate); 94} 95 96void r600_bind_rs_state(struct pipe_context *ctx, void *state) 97{ 98 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 99 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 100 101 if (state == NULL) 102 return; 103 104 rctx->clamp_vertex_color = rs->clamp_vertex_color; 105 rctx->clamp_fragment_color = rs->clamp_fragment_color; 106 rctx->flatshade = rs->flatshade; 107 rctx->sprite_coord_enable = rs->sprite_coord_enable; 108 rctx->rasterizer = rs; 109 110 rctx->states[rs->rstate.id] = &rs->rstate; 111 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate); 112 113 if (rctx->chip_class >= EVERGREEN) { 114 evergreen_polygon_offset_update(rctx); 115 } else { 116 r600_polygon_offset_update(rctx); 117 } 118 if (rctx->ps_shader && rctx->vs_shader) 119 rctx->spi_dirty = true; 120} 121 122void r600_delete_rs_state(struct pipe_context *ctx, void *state) 123{ 124 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 125 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 126 127 if (rctx->rasterizer == rs) { 128 rctx->rasterizer = NULL; 129 } 130 if (rctx->states[rs->rstate.id] == &rs->rstate) { 131 rctx->states[rs->rstate.id] = NULL; 132 } 133 free(rs); 134} 135 136void r600_sampler_view_destroy(struct pipe_context *ctx, 137 struct pipe_sampler_view *state) 138{ 139 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 140 141 pipe_resource_reference(&state->texture, NULL); 142 FREE(resource); 143} 144 145void r600_delete_state(struct pipe_context *ctx, void *state) 146{ 147 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 148 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state; 149 150 if (rctx->states[rstate->id] == rstate) { 151 rctx->states[rstate->id] = NULL; 152 } 153 for (int i = 0; i < rstate->nregs; i++) { 154 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 155 } 156 free(rstate); 157} 158 159void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) 160{ 161 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 162 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 163 164 rctx->vertex_elements = v; 165 if (v) { 166 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state, 167 v->vmgr_elements); 168 169 rctx->states[v->rstate.id] = &v->rstate; 170 r600_context_pipe_state_set(&rctx->ctx, &v->rstate); 171 } 172} 173 174void r600_delete_vertex_element(struct pipe_context *ctx, void *state) 175{ 176 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 177 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 178 179 if (rctx->states[v->rstate.id] == &v->rstate) { 180 rctx->states[v->rstate.id] = NULL; 181 } 182 if (rctx->vertex_elements == state) 183 rctx->vertex_elements = NULL; 184 185 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL); 186 u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements); 187 FREE(state); 188} 189 190 191void r600_set_index_buffer(struct pipe_context *ctx, 192 const struct pipe_index_buffer *ib) 193{ 194 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 195 196 if (ib) { 197 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 198 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer)); 199 } else { 200 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 201 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer)); 202 } 203 204 /* TODO make this more like a state */ 205} 206 207void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 208 const struct pipe_vertex_buffer *buffers) 209{ 210 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 211 int i; 212 213 /* Zero states. */ 214 for (i = 0; i < count; i++) { 215 if (!buffers[i].buffer) { 216 if (rctx->chip_class >= EVERGREEN) { 217 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i); 218 } else { 219 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i); 220 } 221 } 222 } 223 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) { 224 if (rctx->chip_class >= EVERGREEN) { 225 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i); 226 } else { 227 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i); 228 } 229 } 230 231 u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers); 232} 233 234void *r600_create_vertex_elements(struct pipe_context *ctx, 235 unsigned count, 236 const struct pipe_vertex_element *elements) 237{ 238 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 239 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); 240 241 assert(count < 32); 242 if (!v) 243 return NULL; 244 245 v->count = count; 246 v->vmgr_elements = 247 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count, 248 elements, v->elements); 249 250 if (r600_vertex_elements_build_fetch_shader(rctx, v)) { 251 FREE(v); 252 return NULL; 253 } 254 255 return v; 256} 257 258void *r600_create_shader_state(struct pipe_context *ctx, 259 const struct pipe_shader_state *state) 260{ 261 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader); 262 int r; 263 264 shader->tokens = tgsi_dup_tokens(state->tokens); 265 266 r = r600_pipe_shader_create(ctx, shader); 267 if (r) { 268 return NULL; 269 } 270 return shader; 271} 272 273void r600_bind_ps_shader(struct pipe_context *ctx, void *state) 274{ 275 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 276 277 /* TODO delete old shader */ 278 rctx->ps_shader = (struct r600_pipe_shader *)state; 279 if (state) { 280 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate); 281 } 282 if (rctx->ps_shader && rctx->vs_shader) { 283 rctx->spi_dirty = true; 284 r600_adjust_gprs(rctx); 285 } 286} 287 288void r600_bind_vs_shader(struct pipe_context *ctx, void *state) 289{ 290 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 291 292 /* TODO delete old shader */ 293 rctx->vs_shader = (struct r600_pipe_shader *)state; 294 if (state) { 295 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate); 296 } 297 if (rctx->ps_shader && rctx->vs_shader) { 298 rctx->spi_dirty = true; 299 r600_adjust_gprs(rctx); 300 } 301} 302 303void r600_delete_ps_shader(struct pipe_context *ctx, void *state) 304{ 305 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 306 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state; 307 308 if (rctx->ps_shader == shader) { 309 rctx->ps_shader = NULL; 310 } 311 312 free(shader->tokens); 313 r600_pipe_shader_destroy(ctx, shader); 314 free(shader); 315} 316 317void r600_delete_vs_shader(struct pipe_context *ctx, void *state) 318{ 319 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 320 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state; 321 322 if (rctx->vs_shader == shader) { 323 rctx->vs_shader = NULL; 324 } 325 326 free(shader->tokens); 327 r600_pipe_shader_destroy(ctx, shader); 328 free(shader); 329} 330 331static void r600_update_alpha_ref(struct r600_pipe_context *rctx) 332{ 333 unsigned alpha_ref; 334 struct r600_pipe_state rstate; 335 336 alpha_ref = rctx->alpha_ref; 337 rstate.nregs = 0; 338 if (rctx->export_16bpc) 339 alpha_ref &= ~0x1FFF; 340 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0); 341 342 r600_context_pipe_state_set(&rctx->ctx, &rstate); 343 rctx->alpha_ref_dirty = false; 344} 345 346/* FIXME optimize away spi update when it's not needed */ 347static void r600_spi_block_init(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate) 348{ 349 int i; 350 rstate->nregs = 0; 351 rstate->id = R600_PIPE_STATE_SPI; 352 for (i = 0; i < 32; i++) { 353 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 0, 0xFFFFFFFF, NULL, 0); 354 } 355} 356 357static void r600_spi_update(struct r600_pipe_context *rctx) 358{ 359 struct r600_pipe_shader *shader = rctx->ps_shader; 360 struct r600_pipe_state *rstate = &rctx->spi; 361 struct r600_shader *rshader = &shader->shader; 362 unsigned i, tmp, sid; 363 364 if (rctx->spi.id == 0) 365 r600_spi_block_init(rctx, &rctx->spi); 366 367 rstate->nregs = 0; 368 for (i = 0; i < rshader->ninput; i++) { 369 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 370 rshader->input[i].name == TGSI_SEMANTIC_FACE) 371 if (rctx->chip_class >= EVERGREEN) 372 continue; 373 else 374 sid=0; 375 else 376 sid=r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i); 377 378 tmp = S_028644_SEMANTIC(sid); 379 380 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR || 381 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || 382 rshader->input[i].name == TGSI_SEMANTIC_POSITION) { 383 tmp |= S_028644_FLAT_SHADE(rctx->flatshade); 384 } 385 386 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 387 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 388 tmp |= S_028644_PT_SPRITE_TEX(1); 389 } 390 391 if (rctx->chip_class < EVERGREEN) { 392 if (rshader->input[i].centroid) 393 tmp |= S_028644_SEL_CENTROID(1); 394 395 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) 396 tmp |= S_028644_SEL_LINEAR(1); 397 } 398 399 r600_pipe_state_mod_reg(rstate, tmp); 400 } 401 402 rctx->spi_dirty = false; 403 r600_context_pipe_state_set(&rctx->ctx, rstate); 404} 405 406void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 407 struct pipe_resource *buffer) 408{ 409 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 410 struct r600_resource *rbuffer = r600_resource(buffer); 411 struct r600_pipe_resource_state *rstate; 412 uint32_t offset; 413 414 /* Note that the state tracker can unbind constant buffers by 415 * passing NULL here. 416 */ 417 if (buffer == NULL) { 418 return; 419 } 420 421 r600_upload_const_buffer(rctx, &rbuffer, &offset); 422 423 switch (shader) { 424 case PIPE_SHADER_VERTEX: 425 rctx->vs_const_buffer.nregs = 0; 426 r600_pipe_state_add_reg(&rctx->vs_const_buffer, 427 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 428 ALIGN_DIVUP(buffer->width0 >> 4, 16), 429 0xFFFFFFFF, NULL, 0); 430 r600_pipe_state_add_reg(&rctx->vs_const_buffer, 431 R_028980_ALU_CONST_CACHE_VS_0, 432 offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ); 433 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer); 434 435 rstate = &rctx->vs_const_buffer_resource[index]; 436 if (!rstate->id) { 437 if (rctx->chip_class >= EVERGREEN) { 438 evergreen_pipe_init_buffer_resource(rctx, rstate); 439 } else { 440 r600_pipe_init_buffer_resource(rctx, rstate); 441 } 442 } 443 444 if (rctx->chip_class >= EVERGREEN) { 445 evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ); 446 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index); 447 } else { 448 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ); 449 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index); 450 } 451 break; 452 case PIPE_SHADER_FRAGMENT: 453 rctx->ps_const_buffer.nregs = 0; 454 r600_pipe_state_add_reg(&rctx->ps_const_buffer, 455 R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 456 ALIGN_DIVUP(buffer->width0 >> 4, 16), 457 0xFFFFFFFF, NULL, 0); 458 r600_pipe_state_add_reg(&rctx->ps_const_buffer, 459 R_028940_ALU_CONST_CACHE_PS_0, 460 offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ); 461 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer); 462 463 rstate = &rctx->ps_const_buffer_resource[index]; 464 if (!rstate->id) { 465 if (rctx->chip_class >= EVERGREEN) { 466 evergreen_pipe_init_buffer_resource(rctx, rstate); 467 } else { 468 r600_pipe_init_buffer_resource(rctx, rstate); 469 } 470 } 471 if (rctx->chip_class >= EVERGREEN) { 472 evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ); 473 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index); 474 } else { 475 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ); 476 r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index); 477 } 478 break; 479 default: 480 R600_ERR("unsupported %d\n", shader); 481 return; 482 } 483 484 if (buffer != &rbuffer->b.b.b) 485 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL); 486} 487 488static void r600_vertex_buffer_update(struct r600_pipe_context *rctx) 489{ 490 struct r600_pipe_resource_state *rstate; 491 struct r600_resource *rbuffer; 492 struct pipe_vertex_buffer *vertex_buffer; 493 unsigned i, count, offset; 494 495 if (rctx->vertex_elements->vbuffer_need_offset) { 496 /* one resource per vertex elements */ 497 count = rctx->vertex_elements->count; 498 } else { 499 /* bind vertex buffer once */ 500 count = rctx->vbuf_mgr->nr_real_vertex_buffers; 501 } 502 503 for (i = 0 ; i < count; i++) { 504 rstate = &rctx->fs_resource[i]; 505 506 if (rctx->vertex_elements->vbuffer_need_offset) { 507 /* one resource per vertex elements */ 508 unsigned vbuffer_index; 509 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index; 510 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index]; 511 rbuffer = (struct r600_resource*)vertex_buffer->buffer; 512 offset = rctx->vertex_elements->vbuffer_offset[i]; 513 } else { 514 /* bind vertex buffer once */ 515 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i]; 516 rbuffer = (struct r600_resource*)vertex_buffer->buffer; 517 offset = 0; 518 } 519 if (vertex_buffer == NULL || rbuffer == NULL) 520 continue; 521 offset += vertex_buffer->buffer_offset; 522 523 if (!rstate->id) { 524 if (rctx->chip_class >= EVERGREEN) { 525 evergreen_pipe_init_buffer_resource(rctx, rstate); 526 } else { 527 r600_pipe_init_buffer_resource(rctx, rstate); 528 } 529 } 530 531 if (rctx->chip_class >= EVERGREEN) { 532 evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ); 533 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i); 534 } else { 535 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ); 536 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i); 537 } 538 } 539} 540 541static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader) 542{ 543 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 544 int r; 545 546 r600_pipe_shader_destroy(ctx, shader); 547 r = r600_pipe_shader_create(ctx, shader); 548 if (r) { 549 return r; 550 } 551 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate); 552 553 return 0; 554} 555 556static void r600_update_derived_state(struct r600_pipe_context *rctx) 557{ 558 if (!rctx->blitter->running) { 559 if (rctx->have_depth_fb || rctx->have_depth_texture) 560 r600_flush_depth_textures(rctx); 561 } 562 563 if (rctx->chip_class < EVERGREEN) { 564 r600_update_sampler_states(rctx); 565 } 566 567 if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) { 568 r600_shader_rebuild(&rctx->context, rctx->vs_shader); 569 } 570 571 if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) || 572 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all && 573 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) { 574 r600_shader_rebuild(&rctx->context, rctx->ps_shader); 575 } 576 577 if (rctx->spi_dirty) { 578 r600_spi_update(rctx); 579 } 580 581 if (rctx->alpha_ref_dirty) { 582 r600_update_alpha_ref(rctx); 583 } 584} 585 586void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) 587{ 588 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 589 struct pipe_draw_info info = *dinfo; 590 struct r600_draw rdraw = {}; 591 struct pipe_index_buffer ib = {}; 592 unsigned prim, mask; 593 594 if (!info.count || 595 (info.indexed && !rctx->index_buffer.buffer) || 596 !r600_conv_pipe_prim(info.mode, &prim)) { 597 return; 598 } 599 600 r600_update_derived_state(rctx); 601 602 u_vbuf_draw_begin(rctx->vbuf_mgr, dinfo); 603 r600_vertex_buffer_update(rctx); 604 605 rdraw.vgt_num_indices = info.count; 606 rdraw.vgt_num_instances = info.instance_count; 607 608 if (info.indexed) { 609 /* Adjust min/max_index by the index bias. */ 610 if (info.max_index != ~0) { 611 info.min_index += info.index_bias; 612 info.max_index += info.index_bias; 613 } 614 615 /* Initialize the index buffer struct. */ 616 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); 617 ib.index_size = rctx->index_buffer.index_size; 618 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size; 619 620 /* Translate or upload, if needed. */ 621 r600_translate_index_buffer(rctx, &ib, info.count); 622 623 if (u_vbuf_resource(ib.buffer)->user_ptr) { 624 r600_upload_index_buffer(rctx, &ib, info.count); 625 } 626 627 /* Initialize the r600_draw struct with index buffer info. */ 628 if (ib.index_size == 4) { 629 rdraw.vgt_index_type = VGT_INDEX_32 | 630 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0); 631 } else { 632 rdraw.vgt_index_type = VGT_INDEX_16 | 633 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0); 634 } 635 rdraw.indices = (struct r600_resource*)ib.buffer; 636 rdraw.indices_bo_offset = ib.offset; 637 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA; 638 } else { 639 info.index_bias = info.start; 640 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX; 641 } 642 643 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; 644 645 if (rctx->vgt.id != R600_PIPE_STATE_VGT) { 646 rctx->vgt.id = R600_PIPE_STATE_VGT; 647 rctx->vgt.nregs = 0; 648 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0); 649 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0); 650 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, info.max_index, 0xFFFFFFFF, NULL, 0); 651 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, info.min_index, 0xFFFFFFFF, NULL, 0); 652 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0); 653 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0); 654 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0); 655 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0); 656 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0); 657 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 658 0, 659 S_028814_PROVOKING_VTX_LAST(1), NULL, 0); 660 } 661 662 rctx->vgt.nregs = 0; 663 r600_pipe_state_mod_reg(&rctx->vgt, prim); 664 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask); 665 r600_pipe_state_mod_reg(&rctx->vgt, info.max_index); 666 r600_pipe_state_mod_reg(&rctx->vgt, info.min_index); 667 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); 668 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); 669 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); 670 r600_pipe_state_mod_reg(&rctx->vgt, 0); 671 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance); 672 if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) { 673 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1)); 674 } 675 676 r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt); 677 678 if (rctx->chip_class >= EVERGREEN) { 679 evergreen_context_draw(&rctx->ctx, &rdraw); 680 } else { 681 r600_context_draw(&rctx->ctx, &rdraw); 682 } 683 684 if (rctx->framebuffer.zsbuf) 685 { 686 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture; 687 ((struct r600_resource_texture *)tex)->dirty_db = TRUE; 688 } 689 690 pipe_resource_reference(&ib.buffer, NULL); 691 u_vbuf_draw_end(rctx->vbuf_mgr); 692} 693 694void _r600_pipe_state_add_reg(struct r600_context *ctx, 695 struct r600_pipe_state *state, 696 u32 offset, u32 value, u32 mask, 697 u32 range_id, u32 block_id, 698 struct r600_resource *bo, 699 enum radeon_bo_usage usage) 700{ 701 struct r600_range *range; 702 struct r600_block *block; 703 704 if (bo) assert(usage); 705 706 range = &ctx->range[range_id]; 707 block = range->blocks[block_id]; 708 state->regs[state->nregs].block = block; 709 state->regs[state->nregs].id = (offset - block->start_offset) >> 2; 710 711 state->regs[state->nregs].value = value; 712 state->regs[state->nregs].mask = mask; 713 state->regs[state->nregs].bo = bo; 714 state->regs[state->nregs].bo_usage = usage; 715 716 state->nregs++; 717 assert(state->nregs < R600_BLOCK_MAX_REG); 718} 719 720void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 721 u32 offset, u32 value, u32 mask, 722 struct r600_resource *bo, 723 enum radeon_bo_usage usage) 724{ 725 if (bo) assert(usage); 726 727 state->regs[state->nregs].id = offset; 728 state->regs[state->nregs].block = NULL; 729 state->regs[state->nregs].value = value; 730 state->regs[state->nregs].mask = mask; 731 state->regs[state->nregs].bo = bo; 732 state->regs[state->nregs].bo_usage = usage; 733 734 state->nregs++; 735 assert(state->nregs < R600_BLOCK_MAX_REG); 736} 737