r600_state_common.c revision f237fd431b512f1d67c88a8d29581b5bef143bbf
1/* 2 * Copyright 2010 Red Hat Inc. 3 * 2010 Jerome Glisse 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie <airlied@redhat.com> 25 * Jerome Glisse <jglisse@redhat.com> 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include "util/u_blitter.h" 31#include "util/u_upload_mgr.h" 32#include "tgsi/tgsi_parse.h" 33#include <byteswap.h> 34 35static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom) 36{ 37 struct radeon_winsys_cs *cs = rctx->cs; 38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom; 39 40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS); 41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw); 42 cs->cdw += cb->atom.num_dw; 43} 44 45void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags) 46{ 47 cb->atom.emit = r600_emit_command_buffer; 48 cb->atom.num_dw = 0; 49 cb->atom.flags = flags; 50 cb->buf = CALLOC(1, 4 * num_dw); 51 cb->max_num_dw = num_dw; 52} 53 54void r600_release_command_buffer(struct r600_command_buffer *cb) 55{ 56 FREE(cb->buf); 57} 58 59static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom) 60{ 61 struct radeon_winsys_cs *cs = rctx->cs; 62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom; 63 64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */ 66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */ 67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */ 68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */ 69 70 a->flush_flags = 0; 71} 72 73static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom) 74{ 75 struct radeon_winsys_cs *cs = rctx->cs; 76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); 78} 79 80void r600_init_atom(struct r600_atom *atom, 81 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 82 unsigned num_dw, enum r600_atom_flags flags) 83{ 84 atom->emit = emit; 85 atom->num_dw = num_dw; 86 atom->flags = flags; 87} 88 89static void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom) 90{ 91 struct radeon_winsys_cs *cs = rctx->cs; 92 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom; 93 unsigned alpha_ref = a->sx_alpha_ref; 94 95 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) { 96 alpha_ref &= ~0x1FFF; 97 } 98 99 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL, 100 a->sx_alpha_test_control | 101 S_028410_ALPHA_TEST_BYPASS(a->bypass)); 102 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref); 103} 104 105void r600_init_common_atoms(struct r600_context *rctx) 106{ 107 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY); 108 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY); 109 r600_init_atom(&rctx->alphatest_state.atom, r600_emit_alphatest_state, 3, 0); 110 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 111} 112 113unsigned r600_get_cb_flush_flags(struct r600_context *rctx) 114{ 115 unsigned flags = 0; 116 117 if (rctx->framebuffer.nr_cbufs) { 118 flags |= S_0085F0_CB_ACTION_ENA(1) | 119 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT); 120 } 121 122 /* Workaround for broken flushing on some R6xx chipsets. */ 123 if (rctx->family == CHIP_RV670 || 124 rctx->family == CHIP_RS780 || 125 rctx->family == CHIP_RS880) { 126 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) | 127 S_0085F0_DEST_BASE_0_ENA(1); 128 } 129 return flags; 130} 131 132void r600_texture_barrier(struct pipe_context *ctx) 133{ 134 struct r600_context *rctx = (struct r600_context *)ctx; 135 136 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx); 137 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom); 138} 139 140static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim) 141{ 142 static const int prim_conv[] = { 143 V_008958_DI_PT_POINTLIST, 144 V_008958_DI_PT_LINELIST, 145 V_008958_DI_PT_LINELOOP, 146 V_008958_DI_PT_LINESTRIP, 147 V_008958_DI_PT_TRILIST, 148 V_008958_DI_PT_TRISTRIP, 149 V_008958_DI_PT_TRIFAN, 150 V_008958_DI_PT_QUADLIST, 151 V_008958_DI_PT_QUADSTRIP, 152 V_008958_DI_PT_POLYGON, 153 -1, 154 -1, 155 -1, 156 -1 157 }; 158 159 *prim = prim_conv[pprim]; 160 if (*prim == -1) { 161 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim); 162 return false; 163 } 164 return true; 165} 166 167/* common state between evergreen and r600 */ 168void r600_bind_blend_state(struct pipe_context *ctx, void *state) 169{ 170 struct r600_context *rctx = (struct r600_context *)ctx; 171 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state; 172 struct r600_pipe_state *rstate; 173 bool update_cb = false; 174 175 if (state == NULL) 176 return; 177 rstate = &blend->rstate; 178 rctx->states[rstate->id] = rstate; 179 rctx->dual_src_blend = blend->dual_src_blend; 180 r600_context_pipe_state_set(rctx, rstate); 181 182 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) { 183 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask; 184 update_cb = true; 185 } 186 if (rctx->chip_class <= R700 && 187 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) { 188 rctx->cb_misc_state.cb_color_control = blend->cb_color_control; 189 update_cb = true; 190 } 191 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) { 192 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend; 193 update_cb = true; 194 } 195 if (update_cb) { 196 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 197 } 198} 199 200void r600_set_blend_color(struct pipe_context *ctx, 201 const struct pipe_blend_color *state) 202{ 203 struct r600_context *rctx = (struct r600_context *)ctx; 204 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 205 206 if (rstate == NULL) 207 return; 208 209 rstate->id = R600_PIPE_STATE_BLEND_COLOR; 210 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0])); 211 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 212 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 213 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 214 215 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); 216 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; 217 r600_context_pipe_state_set(rctx, rstate); 218} 219 220static void r600_set_stencil_ref(struct pipe_context *ctx, 221 const struct r600_stencil_ref *state) 222{ 223 struct r600_context *rctx = (struct r600_context *)ctx; 224 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 225 226 if (rstate == NULL) 227 return; 228 229 rstate->id = R600_PIPE_STATE_STENCIL_REF; 230 r600_pipe_state_add_reg(rstate, 231 R_028430_DB_STENCILREFMASK, 232 S_028430_STENCILREF(state->ref_value[0]) | 233 S_028430_STENCILMASK(state->valuemask[0]) | 234 S_028430_STENCILWRITEMASK(state->writemask[0])); 235 r600_pipe_state_add_reg(rstate, 236 R_028434_DB_STENCILREFMASK_BF, 237 S_028434_STENCILREF_BF(state->ref_value[1]) | 238 S_028434_STENCILMASK_BF(state->valuemask[1]) | 239 S_028434_STENCILWRITEMASK_BF(state->writemask[1])); 240 241 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); 242 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; 243 r600_context_pipe_state_set(rctx, rstate); 244} 245 246void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 247 const struct pipe_stencil_ref *state) 248{ 249 struct r600_context *rctx = (struct r600_context *)ctx; 250 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; 251 struct r600_stencil_ref ref; 252 253 rctx->stencil_ref = *state; 254 255 if (!dsa) 256 return; 257 258 ref.ref_value[0] = state->ref_value[0]; 259 ref.ref_value[1] = state->ref_value[1]; 260 ref.valuemask[0] = dsa->valuemask[0]; 261 ref.valuemask[1] = dsa->valuemask[1]; 262 ref.writemask[0] = dsa->writemask[0]; 263 ref.writemask[1] = dsa->writemask[1]; 264 265 r600_set_stencil_ref(ctx, &ref); 266} 267 268void r600_bind_dsa_state(struct pipe_context *ctx, void *state) 269{ 270 struct r600_context *rctx = (struct r600_context *)ctx; 271 struct r600_pipe_dsa *dsa = state; 272 struct r600_pipe_state *rstate; 273 struct r600_stencil_ref ref; 274 275 if (state == NULL) 276 return; 277 rstate = &dsa->rstate; 278 rctx->states[rstate->id] = rstate; 279 r600_context_pipe_state_set(rctx, rstate); 280 281 ref.ref_value[0] = rctx->stencil_ref.ref_value[0]; 282 ref.ref_value[1] = rctx->stencil_ref.ref_value[1]; 283 ref.valuemask[0] = dsa->valuemask[0]; 284 ref.valuemask[1] = dsa->valuemask[1]; 285 ref.writemask[0] = dsa->writemask[0]; 286 ref.writemask[1] = dsa->writemask[1]; 287 288 r600_set_stencil_ref(ctx, &ref); 289 290 /* Update alphatest state. */ 291 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control || 292 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) { 293 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control; 294 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref; 295 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 296 } 297} 298 299void r600_set_max_scissor(struct r600_context *rctx) 300{ 301 /* Set a scissor state such that it doesn't do anything. */ 302 struct pipe_scissor_state scissor; 303 scissor.minx = 0; 304 scissor.miny = 0; 305 scissor.maxx = 8192; 306 scissor.maxy = 8192; 307 308 r600_set_scissor_state(rctx, &scissor); 309} 310 311void r600_bind_rs_state(struct pipe_context *ctx, void *state) 312{ 313 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 314 struct r600_context *rctx = (struct r600_context *)ctx; 315 316 if (state == NULL) 317 return; 318 319 rctx->sprite_coord_enable = rs->sprite_coord_enable; 320 rctx->two_side = rs->two_side; 321 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 322 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; 323 324 rctx->rasterizer = rs; 325 326 rctx->states[rs->rstate.id] = &rs->rstate; 327 r600_context_pipe_state_set(rctx, &rs->rstate); 328 329 if (rctx->chip_class >= EVERGREEN) { 330 evergreen_polygon_offset_update(rctx); 331 } else { 332 r600_polygon_offset_update(rctx); 333 } 334 335 /* Workaround for a missing scissor enable on r600. */ 336 if (rctx->chip_class == R600) { 337 if (rs->scissor_enable != rctx->scissor_enable) { 338 rctx->scissor_enable = rs->scissor_enable; 339 340 if (rs->scissor_enable) { 341 r600_set_scissor_state(rctx, &rctx->scissor_state); 342 } else { 343 r600_set_max_scissor(rctx); 344 } 345 } 346 } 347} 348 349void r600_delete_rs_state(struct pipe_context *ctx, void *state) 350{ 351 struct r600_context *rctx = (struct r600_context *)ctx; 352 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 353 354 if (rctx->rasterizer == rs) { 355 rctx->rasterizer = NULL; 356 } 357 if (rctx->states[rs->rstate.id] == &rs->rstate) { 358 rctx->states[rs->rstate.id] = NULL; 359 } 360 free(rs); 361} 362 363void r600_sampler_view_destroy(struct pipe_context *ctx, 364 struct pipe_sampler_view *state) 365{ 366 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 367 368 pipe_resource_reference(&state->texture, NULL); 369 FREE(resource); 370} 371 372void r600_delete_state(struct pipe_context *ctx, void *state) 373{ 374 struct r600_context *rctx = (struct r600_context *)ctx; 375 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state; 376 377 if (rctx->states[rstate->id] == rstate) { 378 rctx->states[rstate->id] = NULL; 379 } 380 for (int i = 0; i < rstate->nregs; i++) { 381 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 382 } 383 free(rstate); 384} 385 386void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) 387{ 388 struct r600_context *rctx = (struct r600_context *)ctx; 389 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 390 391 rctx->vertex_elements = v; 392 if (v) { 393 r600_inval_shader_cache(rctx); 394 395 rctx->states[v->rstate.id] = &v->rstate; 396 r600_context_pipe_state_set(rctx, &v->rstate); 397 } 398} 399 400void r600_delete_vertex_element(struct pipe_context *ctx, void *state) 401{ 402 struct r600_context *rctx = (struct r600_context *)ctx; 403 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 404 405 if (rctx->states[v->rstate.id] == &v->rstate) { 406 rctx->states[v->rstate.id] = NULL; 407 } 408 if (rctx->vertex_elements == state) 409 rctx->vertex_elements = NULL; 410 411 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL); 412 FREE(state); 413} 414 415void r600_set_index_buffer(struct pipe_context *ctx, 416 const struct pipe_index_buffer *ib) 417{ 418 struct r600_context *rctx = (struct r600_context *)ctx; 419 420 if (ib) { 421 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 422 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 423 } else { 424 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 425 } 426} 427 428void r600_vertex_buffers_dirty(struct r600_context *rctx) 429{ 430 if (rctx->vertex_buffer_state.dirty_mask) { 431 r600_inval_vertex_cache(rctx); 432 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) * 433 util_bitcount(rctx->vertex_buffer_state.dirty_mask); 434 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom); 435 } 436} 437 438void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 439 const struct pipe_vertex_buffer *input) 440{ 441 struct r600_context *rctx = (struct r600_context *)ctx; 442 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state; 443 struct pipe_vertex_buffer *vb = state->vb; 444 unsigned i; 445 /* This sets 1-bit for buffers with index >= count. */ 446 uint32_t disable_mask = ~((1ull << count) - 1); 447 /* These are the new buffers set by this function. */ 448 uint32_t new_buffer_mask = 0; 449 450 /* Set buffers with index >= count to NULL. */ 451 uint32_t remaining_buffers_mask = 452 rctx->vertex_buffer_state.enabled_mask & disable_mask; 453 454 while (remaining_buffers_mask) { 455 i = u_bit_scan(&remaining_buffers_mask); 456 pipe_resource_reference(&vb[i].buffer, NULL); 457 } 458 459 /* Set vertex buffers. */ 460 for (i = 0; i < count; i++) { 461 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) { 462 if (input[i].buffer) { 463 vb[i].stride = input[i].stride; 464 vb[i].buffer_offset = input[i].buffer_offset; 465 pipe_resource_reference(&vb[i].buffer, input[i].buffer); 466 new_buffer_mask |= 1 << i; 467 } else { 468 pipe_resource_reference(&vb[i].buffer, NULL); 469 disable_mask |= 1 << i; 470 } 471 } 472 } 473 474 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask; 475 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask; 476 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask; 477 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask; 478 479 r600_vertex_buffers_dirty(rctx); 480} 481 482void r600_sampler_views_dirty(struct r600_context *rctx, 483 struct r600_samplerview_state *state) 484{ 485 if (state->dirty_mask) { 486 r600_inval_texture_cache(rctx); 487 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) * 488 util_bitcount(state->dirty_mask); 489 r600_atom_dirty(rctx, &state->atom); 490 } 491} 492 493void r600_set_sampler_views(struct r600_context *rctx, 494 struct r600_textures_info *dst, 495 unsigned count, 496 struct pipe_sampler_view **views) 497{ 498 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views; 499 unsigned i; 500 /* This sets 1-bit for textures with index >= count. */ 501 uint32_t disable_mask = ~((1ull << count) - 1); 502 /* These are the new textures set by this function. */ 503 uint32_t new_mask = 0; 504 505 /* Set textures with index >= count to NULL. */ 506 uint32_t remaining_mask = dst->views.enabled_mask & disable_mask; 507 508 while (remaining_mask) { 509 i = u_bit_scan(&remaining_mask); 510 assert(dst->views.views[i]); 511 512 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL); 513 } 514 515 for (i = 0; i < count; i++) { 516 if (rviews[i] == dst->views.views[i]) { 517 continue; 518 } 519 520 if (rviews[i]) { 521 struct r600_resource_texture *rtex = 522 (struct r600_resource_texture*)rviews[i]->base.texture; 523 524 if (rtex->is_depth && !rtex->is_flushing_texture) { 525 dst->views.depth_texture_mask |= 1 << i; 526 } else { 527 dst->views.depth_texture_mask &= ~(1 << i); 528 } 529 530 /* Changing from array to non-arrays textures and vice 531 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */ 532 if (rctx->chip_class <= R700 && 533 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 534 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) { 535 dst->samplers_dirty = true; 536 } 537 538 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]); 539 new_mask |= 1 << i; 540 } else { 541 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL); 542 disable_mask |= 1 << i; 543 } 544 } 545 546 dst->views.enabled_mask &= ~disable_mask; 547 dst->views.dirty_mask &= dst->views.enabled_mask; 548 dst->views.enabled_mask |= new_mask; 549 dst->views.dirty_mask |= new_mask; 550 dst->views.depth_texture_mask &= dst->views.enabled_mask; 551 552 r600_sampler_views_dirty(rctx, &dst->views); 553} 554 555void *r600_create_vertex_elements(struct pipe_context *ctx, 556 unsigned count, 557 const struct pipe_vertex_element *elements) 558{ 559 struct r600_context *rctx = (struct r600_context *)ctx; 560 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); 561 562 assert(count < 32); 563 if (!v) 564 return NULL; 565 566 v->count = count; 567 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 568 569 if (r600_vertex_elements_build_fetch_shader(rctx, v)) { 570 FREE(v); 571 return NULL; 572 } 573 574 return v; 575} 576 577/* Compute the key for the hw shader variant */ 578static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx, 579 struct r600_pipe_shader_selector * sel) 580{ 581 struct r600_context *rctx = (struct r600_context *)ctx; 582 unsigned key; 583 584 if (sel->type == PIPE_SHADER_FRAGMENT) { 585 key = rctx->two_side | 586 MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1; 587 } else 588 key = 0; 589 590 return key; 591} 592 593/* Select the hw shader variant depending on the current state. 594 * (*dirty) is set to 1 if current variant was changed */ 595static int r600_shader_select(struct pipe_context *ctx, 596 struct r600_pipe_shader_selector* sel, 597 unsigned *dirty) 598{ 599 unsigned key; 600 struct r600_context *rctx = (struct r600_context *)ctx; 601 struct r600_pipe_shader * shader = NULL; 602 int r; 603 604 key = r600_shader_selector_key(ctx, sel); 605 606 /* Check if we don't need to change anything. 607 * This path is also used for most shaders that don't need multiple 608 * variants, it will cost just a computation of the key and this 609 * test. */ 610 if (likely(sel->current && sel->current->key == key)) { 611 return 0; 612 } 613 614 /* lookup if we have other variants in the list */ 615 if (sel->num_shaders > 1) { 616 struct r600_pipe_shader *p = sel->current, *c = p->next_variant; 617 618 while (c && c->key != key) { 619 p = c; 620 c = c->next_variant; 621 } 622 623 if (c) { 624 p->next_variant = c->next_variant; 625 shader = c; 626 } 627 } 628 629 if (unlikely(!shader)) { 630 shader = CALLOC(1, sizeof(struct r600_pipe_shader)); 631 shader->selector = sel; 632 633 r = r600_pipe_shader_create(ctx, shader); 634 if (unlikely(r)) { 635 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n", 636 sel->type, key, r); 637 sel->current = NULL; 638 return r; 639 } 640 641 /* We don't know the value of nr_ps_max_color_exports until we built 642 * at least one variant, so we may need to recompute the key after 643 * building first variant. */ 644 if (sel->type == PIPE_SHADER_FRAGMENT && 645 sel->num_shaders == 0) { 646 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports; 647 key = r600_shader_selector_key(ctx, sel); 648 } 649 650 shader->key = key; 651 sel->num_shaders++; 652 } 653 654 if (dirty) 655 *dirty = 1; 656 657 shader->next_variant = sel->current; 658 sel->current = shader; 659 660 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) { 661 r600_adjust_gprs(rctx); 662 } 663 664 if (rctx->ps_shader && 665 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) { 666 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs; 667 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 668 } 669 return 0; 670} 671 672static void *r600_create_shader_state(struct pipe_context *ctx, 673 const struct pipe_shader_state *state, 674 unsigned pipe_shader_type) 675{ 676 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector); 677 int r; 678 679 sel->type = pipe_shader_type; 680 sel->tokens = tgsi_dup_tokens(state->tokens); 681 sel->so = state->stream_output; 682 683 r = r600_shader_select(ctx, sel, NULL); 684 if (r) 685 return NULL; 686 687 return sel; 688} 689 690void *r600_create_shader_state_ps(struct pipe_context *ctx, 691 const struct pipe_shader_state *state) 692{ 693 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 694} 695 696void *r600_create_shader_state_vs(struct pipe_context *ctx, 697 const struct pipe_shader_state *state) 698{ 699 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 700} 701 702void r600_bind_ps_shader(struct pipe_context *ctx, void *state) 703{ 704 struct r600_context *rctx = (struct r600_context *)ctx; 705 706 if (!state) 707 state = rctx->dummy_pixel_shader; 708 709 rctx->ps_shader = (struct r600_pipe_shader_selector *)state; 710 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate); 711 712 if (rctx->chip_class <= R700) { 713 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all; 714 715 if (rctx->cb_misc_state.multiwrite != multiwrite) { 716 rctx->cb_misc_state.multiwrite = multiwrite; 717 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 718 } 719 720 if (rctx->vs_shader) 721 r600_adjust_gprs(rctx); 722 } 723 724 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) { 725 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs; 726 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 727 } 728} 729 730void r600_bind_vs_shader(struct pipe_context *ctx, void *state) 731{ 732 struct r600_context *rctx = (struct r600_context *)ctx; 733 734 rctx->vs_shader = (struct r600_pipe_shader_selector *)state; 735 if (state) { 736 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate); 737 738 if (rctx->chip_class < EVERGREEN && rctx->ps_shader) 739 r600_adjust_gprs(rctx); 740 } 741} 742 743static void r600_delete_shader_selector(struct pipe_context *ctx, 744 struct r600_pipe_shader_selector *sel) 745{ 746 struct r600_pipe_shader *p = sel->current, *c; 747 while (p) { 748 c = p->next_variant; 749 r600_pipe_shader_destroy(ctx, p); 750 free(p); 751 p = c; 752 } 753 754 free(sel->tokens); 755 free(sel); 756} 757 758 759void r600_delete_ps_shader(struct pipe_context *ctx, void *state) 760{ 761 struct r600_context *rctx = (struct r600_context *)ctx; 762 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state; 763 764 if (rctx->ps_shader == sel) { 765 rctx->ps_shader = NULL; 766 } 767 768 r600_delete_shader_selector(ctx, sel); 769} 770 771void r600_delete_vs_shader(struct pipe_context *ctx, void *state) 772{ 773 struct r600_context *rctx = (struct r600_context *)ctx; 774 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state; 775 776 if (rctx->vs_shader == sel) { 777 rctx->vs_shader = NULL; 778 } 779 780 r600_delete_shader_selector(ctx, sel); 781} 782 783void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state) 784{ 785 if (state->dirty_mask) { 786 r600_inval_shader_cache(rctx); 787 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 788 : util_bitcount(state->dirty_mask)*19; 789 r600_atom_dirty(rctx, &state->atom); 790 } 791} 792 793void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 794 struct pipe_constant_buffer *input) 795{ 796 struct r600_context *rctx = (struct r600_context *)ctx; 797 struct r600_constbuf_state *state; 798 struct pipe_constant_buffer *cb; 799 const uint8_t *ptr; 800 801 switch (shader) { 802 case PIPE_SHADER_VERTEX: 803 state = &rctx->vs_constbuf_state; 804 break; 805 case PIPE_SHADER_FRAGMENT: 806 state = &rctx->ps_constbuf_state; 807 break; 808 default: 809 return; 810 } 811 812 /* Note that the state tracker can unbind constant buffers by 813 * passing NULL here. 814 */ 815 if (unlikely(!input)) { 816 state->enabled_mask &= ~(1 << index); 817 state->dirty_mask &= ~(1 << index); 818 pipe_resource_reference(&state->cb[index].buffer, NULL); 819 return; 820 } 821 822 cb = &state->cb[index]; 823 cb->buffer_size = input->buffer_size; 824 825 ptr = input->user_buffer; 826 827 if (ptr) { 828 /* Upload the user buffer. */ 829 if (R600_BIG_ENDIAN) { 830 uint32_t *tmpPtr; 831 unsigned i, size = input->buffer_size; 832 833 if (!(tmpPtr = malloc(size))) { 834 R600_ERR("Failed to allocate BE swap buffer.\n"); 835 return; 836 } 837 838 for (i = 0; i < size / 4; ++i) { 839 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]); 840 } 841 842 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer); 843 free(tmpPtr); 844 } else { 845 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer); 846 } 847 } else { 848 /* Setup the hw buffer. */ 849 cb->buffer_offset = input->buffer_offset; 850 pipe_resource_reference(&cb->buffer, input->buffer); 851 } 852 853 state->enabled_mask |= 1 << index; 854 state->dirty_mask |= 1 << index; 855 r600_constant_buffers_dirty(rctx, state); 856} 857 858struct pipe_stream_output_target * 859r600_create_so_target(struct pipe_context *ctx, 860 struct pipe_resource *buffer, 861 unsigned buffer_offset, 862 unsigned buffer_size) 863{ 864 struct r600_context *rctx = (struct r600_context *)ctx; 865 struct r600_so_target *t; 866 void *ptr; 867 868 t = CALLOC_STRUCT(r600_so_target); 869 if (!t) { 870 return NULL; 871 } 872 873 t->b.reference.count = 1; 874 t->b.context = ctx; 875 pipe_resource_reference(&t->b.buffer, buffer); 876 t->b.buffer_offset = buffer_offset; 877 t->b.buffer_size = buffer_size; 878 879 t->filled_size = (struct r600_resource*) 880 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4); 881 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); 882 memset(ptr, 0, t->filled_size->buf->size); 883 rctx->ws->buffer_unmap(t->filled_size->cs_buf); 884 885 return &t->b; 886} 887 888void r600_so_target_destroy(struct pipe_context *ctx, 889 struct pipe_stream_output_target *target) 890{ 891 struct r600_so_target *t = (struct r600_so_target*)target; 892 pipe_resource_reference(&t->b.buffer, NULL); 893 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL); 894 FREE(t); 895} 896 897void r600_set_so_targets(struct pipe_context *ctx, 898 unsigned num_targets, 899 struct pipe_stream_output_target **targets, 900 unsigned append_bitmask) 901{ 902 struct r600_context *rctx = (struct r600_context *)ctx; 903 unsigned i; 904 905 /* Stop streamout. */ 906 if (rctx->num_so_targets && !rctx->streamout_start) { 907 r600_context_streamout_end(rctx); 908 } 909 910 /* Set the new targets. */ 911 for (i = 0; i < num_targets; i++) { 912 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]); 913 } 914 for (; i < rctx->num_so_targets; i++) { 915 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL); 916 } 917 918 rctx->num_so_targets = num_targets; 919 rctx->streamout_start = num_targets != 0; 920 rctx->streamout_append_bitmask = append_bitmask; 921} 922 923static void r600_update_derived_state(struct r600_context *rctx) 924{ 925 struct pipe_context * ctx = (struct pipe_context*)rctx; 926 unsigned ps_dirty = 0; 927 928 if (!rctx->blitter->running) { 929 /* Flush depth textures which need to be flushed. */ 930 if (rctx->vs_samplers.views.depth_texture_mask) { 931 r600_flush_depth_textures(rctx, &rctx->vs_samplers.views); 932 } 933 if (rctx->ps_samplers.views.depth_texture_mask) { 934 r600_flush_depth_textures(rctx, &rctx->ps_samplers.views); 935 } 936 } 937 938 if (rctx->chip_class < EVERGREEN) { 939 r600_update_sampler_states(rctx); 940 } 941 942 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty); 943 944 if (rctx->ps_shader && ((rctx->sprite_coord_enable && 945 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) || 946 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) { 947 948 if (rctx->chip_class >= EVERGREEN) 949 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current); 950 else 951 r600_pipe_shader_ps(ctx, rctx->ps_shader->current); 952 953 ps_dirty = 1; 954 } 955 956 if (ps_dirty) 957 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate); 958 959 if (rctx->chip_class >= EVERGREEN) { 960 evergreen_update_dual_export_state(rctx); 961 } else { 962 r600_update_dual_export_state(rctx); 963 } 964} 965 966static unsigned r600_conv_prim_to_gs_out(unsigned mode) 967{ 968 static const int prim_conv[] = { 969 V_028A6C_OUTPRIM_TYPE_POINTLIST, 970 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 971 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 972 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 973 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 974 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 975 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 976 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 977 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 978 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 979 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 980 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 981 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 982 V_028A6C_OUTPRIM_TYPE_TRISTRIP 983 }; 984 assert(mode < Elements(prim_conv)); 985 986 return prim_conv[mode]; 987} 988 989void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) 990{ 991 struct r600_context *rctx = (struct r600_context *)ctx; 992 struct pipe_draw_info info = *dinfo; 993 struct pipe_index_buffer ib = {}; 994 unsigned prim, ls_mask = 0; 995 struct r600_block *dirty_block = NULL, *next_block = NULL; 996 struct r600_atom *state = NULL, *next_state = NULL; 997 struct radeon_winsys_cs *cs = rctx->cs; 998 uint64_t va; 999 uint8_t *ptr; 1000 1001 if ((!info.count && (info.indexed || !info.count_from_stream_output)) || 1002 !r600_conv_pipe_prim(info.mode, &prim)) { 1003 assert(0); 1004 return; 1005 } 1006 1007 if (!rctx->vs_shader) { 1008 assert(0); 1009 return; 1010 } 1011 1012 r600_update_derived_state(rctx); 1013 1014 if (info.indexed) { 1015 /* Initialize the index buffer struct. */ 1016 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); 1017 ib.user_buffer = rctx->index_buffer.user_buffer; 1018 ib.index_size = rctx->index_buffer.index_size; 1019 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size; 1020 1021 /* Translate or upload, if needed. */ 1022 r600_translate_index_buffer(rctx, &ib, info.count); 1023 1024 ptr = (uint8_t*)ib.user_buffer; 1025 if (!ib.buffer && ptr) { 1026 u_upload_data(rctx->uploader, 0, info.count * ib.index_size, 1027 ptr, &ib.offset, &ib.buffer); 1028 } 1029 } else { 1030 info.index_bias = info.start; 1031 } 1032 1033 if (rctx->vgt.id != R600_PIPE_STATE_VGT) { 1034 rctx->vgt.id = R600_PIPE_STATE_VGT; 1035 rctx->vgt.nregs = 0; 1036 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim); 1037 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0); 1038 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias); 1039 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index); 1040 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart); 1041 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance); 1042 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0); 1043 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0); 1044 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0); 1045 } 1046 1047 rctx->vgt.nregs = 0; 1048 r600_pipe_state_mod_reg(&rctx->vgt, prim); 1049 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode)); 1050 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); 1051 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); 1052 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); 1053 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance); 1054 1055 if (prim == V_008958_DI_PT_LINELIST) 1056 ls_mask = 1; 1057 else if (prim == V_008958_DI_PT_LINESTRIP || 1058 prim == V_008958_DI_PT_LINELOOP) 1059 ls_mask = 2; 1060 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple); 1061 r600_pipe_state_mod_reg(&rctx->vgt, 1062 rctx->vs_shader->current->pa_cl_vs_out_cntl | 1063 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write)); 1064 r600_pipe_state_mod_reg(&rctx->vgt, 1065 rctx->pa_cl_clip_cntl | 1066 (rctx->vs_shader->current->shader.clip_dist_write || 1067 rctx->vs_shader->current->shader.vs_prohibit_ucps ? 1068 0 : rctx->rasterizer->clip_plane_enable & 0x3F)); 1069 1070 r600_context_pipe_state_set(rctx, &rctx->vgt); 1071 1072 /* Emit states (the function expects that we emit at most 17 dwords here). */ 1073 r600_need_cs_space(rctx, 0, TRUE); 1074 1075 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) { 1076 r600_emit_atom(rctx, state); 1077 } 1078 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) { 1079 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */); 1080 } 1081 rctx->pm4_dirty_cdwords = 0; 1082 1083 /* Enable stream out if needed. */ 1084 if (rctx->streamout_start) { 1085 r600_context_streamout_begin(rctx); 1086 rctx->streamout_start = FALSE; 1087 } 1088 1089 /* draw packet */ 1090 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing); 1091 cs->buf[cs->cdw++] = info.instance_count; 1092 if (info.indexed) { 1093 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing); 1094 cs->buf[cs->cdw++] = ib.index_size == 4 ? 1095 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) : 1096 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)); 1097 1098 va = r600_resource_va(ctx->screen, ib.buffer); 1099 va += ib.offset; 1100 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing); 1101 cs->buf[cs->cdw++] = va; 1102 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; 1103 cs->buf[cs->cdw++] = info.count; 1104 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA; 1105 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing); 1106 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ); 1107 } else { 1108 if (info.count_from_stream_output) { 1109 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output; 1110 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size); 1111 1112 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw); 1113 1114 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); 1115 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; 1116 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1117 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1118 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ 1119 cs->buf[cs->cdw++] = 0; /* unused */ 1120 1121 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1122 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ); 1123 } 1124 1125 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing); 1126 cs->buf[cs->cdw++] = info.count; 1127 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX | 1128 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0); 1129 } 1130 1131 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING; 1132 1133 /* Set the depth buffer as dirty. */ 1134 if (rctx->framebuffer.zsbuf) { 1135 struct pipe_surface *surf = rctx->framebuffer.zsbuf; 1136 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture; 1137 1138 rtex->dirty_db_mask |= 1 << surf->u.tex.level; 1139 } 1140 1141 pipe_resource_reference(&ib.buffer, NULL); 1142} 1143 1144void _r600_pipe_state_add_reg_bo(struct r600_context *ctx, 1145 struct r600_pipe_state *state, 1146 uint32_t offset, uint32_t value, 1147 uint32_t range_id, uint32_t block_id, 1148 struct r600_resource *bo, 1149 enum radeon_bo_usage usage) 1150 1151{ 1152 struct r600_range *range; 1153 struct r600_block *block; 1154 1155 if (bo) assert(usage); 1156 1157 range = &ctx->range[range_id]; 1158 block = range->blocks[block_id]; 1159 state->regs[state->nregs].block = block; 1160 state->regs[state->nregs].id = (offset - block->start_offset) >> 2; 1161 1162 state->regs[state->nregs].value = value; 1163 state->regs[state->nregs].bo = bo; 1164 state->regs[state->nregs].bo_usage = usage; 1165 1166 state->nregs++; 1167 assert(state->nregs < R600_BLOCK_MAX_REG); 1168} 1169 1170void _r600_pipe_state_add_reg(struct r600_context *ctx, 1171 struct r600_pipe_state *state, 1172 uint32_t offset, uint32_t value, 1173 uint32_t range_id, uint32_t block_id) 1174{ 1175 _r600_pipe_state_add_reg_bo(ctx, state, offset, value, 1176 range_id, block_id, NULL, 0); 1177} 1178 1179void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 1180 uint32_t offset, uint32_t value, 1181 struct r600_resource *bo, 1182 enum radeon_bo_usage usage) 1183{ 1184 if (bo) assert(usage); 1185 1186 state->regs[state->nregs].id = offset; 1187 state->regs[state->nregs].block = NULL; 1188 state->regs[state->nregs].value = value; 1189 state->regs[state->nregs].bo = bo; 1190 state->regs[state->nregs].bo_usage = usage; 1191 1192 state->nregs++; 1193 assert(state->nregs < R600_BLOCK_MAX_REG); 1194} 1195 1196uint32_t r600_translate_stencil_op(int s_op) 1197{ 1198 switch (s_op) { 1199 case PIPE_STENCIL_OP_KEEP: 1200 return V_028800_STENCIL_KEEP; 1201 case PIPE_STENCIL_OP_ZERO: 1202 return V_028800_STENCIL_ZERO; 1203 case PIPE_STENCIL_OP_REPLACE: 1204 return V_028800_STENCIL_REPLACE; 1205 case PIPE_STENCIL_OP_INCR: 1206 return V_028800_STENCIL_INCR; 1207 case PIPE_STENCIL_OP_DECR: 1208 return V_028800_STENCIL_DECR; 1209 case PIPE_STENCIL_OP_INCR_WRAP: 1210 return V_028800_STENCIL_INCR_WRAP; 1211 case PIPE_STENCIL_OP_DECR_WRAP: 1212 return V_028800_STENCIL_DECR_WRAP; 1213 case PIPE_STENCIL_OP_INVERT: 1214 return V_028800_STENCIL_INVERT; 1215 default: 1216 R600_ERR("Unknown stencil op %d", s_op); 1217 assert(0); 1218 break; 1219 } 1220 return 0; 1221} 1222 1223uint32_t r600_translate_fill(uint32_t func) 1224{ 1225 switch(func) { 1226 case PIPE_POLYGON_MODE_FILL: 1227 return 2; 1228 case PIPE_POLYGON_MODE_LINE: 1229 return 1; 1230 case PIPE_POLYGON_MODE_POINT: 1231 return 0; 1232 default: 1233 assert(0); 1234 return 0; 1235 } 1236} 1237 1238unsigned r600_tex_wrap(unsigned wrap) 1239{ 1240 switch (wrap) { 1241 default: 1242 case PIPE_TEX_WRAP_REPEAT: 1243 return V_03C000_SQ_TEX_WRAP; 1244 case PIPE_TEX_WRAP_CLAMP: 1245 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; 1246 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1247 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; 1248 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1249 return V_03C000_SQ_TEX_CLAMP_BORDER; 1250 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1251 return V_03C000_SQ_TEX_MIRROR; 1252 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1253 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1254 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1255 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1256 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1257 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; 1258 } 1259} 1260 1261unsigned r600_tex_filter(unsigned filter) 1262{ 1263 switch (filter) { 1264 default: 1265 case PIPE_TEX_FILTER_NEAREST: 1266 return V_03C000_SQ_TEX_XY_FILTER_POINT; 1267 case PIPE_TEX_FILTER_LINEAR: 1268 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; 1269 } 1270} 1271 1272unsigned r600_tex_mipfilter(unsigned filter) 1273{ 1274 switch (filter) { 1275 case PIPE_TEX_MIPFILTER_NEAREST: 1276 return V_03C000_SQ_TEX_Z_FILTER_POINT; 1277 case PIPE_TEX_MIPFILTER_LINEAR: 1278 return V_03C000_SQ_TEX_Z_FILTER_LINEAR; 1279 default: 1280 case PIPE_TEX_MIPFILTER_NONE: 1281 return V_03C000_SQ_TEX_Z_FILTER_NONE; 1282 } 1283} 1284 1285unsigned r600_tex_compare(unsigned compare) 1286{ 1287 switch (compare) { 1288 default: 1289 case PIPE_FUNC_NEVER: 1290 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; 1291 case PIPE_FUNC_LESS: 1292 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; 1293 case PIPE_FUNC_EQUAL: 1294 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; 1295 case PIPE_FUNC_LEQUAL: 1296 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1297 case PIPE_FUNC_GREATER: 1298 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; 1299 case PIPE_FUNC_NOTEQUAL: 1300 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1301 case PIPE_FUNC_GEQUAL: 1302 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1303 case PIPE_FUNC_ALWAYS: 1304 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1305 } 1306} 1307