AMDGPUISelLowering.cpp revision ef8e66bc165ea2ef9987ab6406268ce195f74eb0
1f903da7335433ae243cf7ff59662be1a03ee9a14Tom Stellard//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 2a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 3a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// The LLVM Compiler Infrastructure 4a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 5a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file is distributed under the University of Illinois Open Source 6a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// License. See LICENSE.TXT for details. 7a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 8a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 9a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 10f903da7335433ae243cf7ff59662be1a03ee9a14Tom Stellard// This is the parent TargetLowering class for hardware code gen targets. 11a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 12a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 13a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 14a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPUISelLowering.h" 15431bb79a41bd5e7402954385daea1594c3e750abTom Stellard#include "AMDILIntrinsicInfo.h" 16a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPUUtil.h" 17a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 18a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 19a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardusing namespace llvm; 20a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 21a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardAMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : 22a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard AMDILTargetLowering(TM) 23a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 24431bb79a41bd5e7402954385daea1594c3e750abTom Stellard // We need to custom lower some of the intrinsics 25431bb79a41bd5e7402954385daea1594c3e750abTom Stellard setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 26431bb79a41bd5e7402954385daea1594c3e750abTom Stellard} 27431bb79a41bd5e7402954385daea1594c3e750abTom Stellard 28431bb79a41bd5e7402954385daea1594c3e750abTom StellardSDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 29431bb79a41bd5e7402954385daea1594c3e750abTom Stellard const 30431bb79a41bd5e7402954385daea1594c3e750abTom Stellard{ 31431bb79a41bd5e7402954385daea1594c3e750abTom Stellard switch (Op.getOpcode()) { 32431bb79a41bd5e7402954385daea1594c3e750abTom Stellard default: return AMDILTargetLowering::LowerOperation(Op, DAG); 33431bb79a41bd5e7402954385daea1594c3e750abTom Stellard case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 34431bb79a41bd5e7402954385daea1594c3e750abTom Stellard } 35431bb79a41bd5e7402954385daea1594c3e750abTom Stellard} 36431bb79a41bd5e7402954385daea1594c3e750abTom Stellard 37431bb79a41bd5e7402954385daea1594c3e750abTom StellardSDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 38431bb79a41bd5e7402954385daea1594c3e750abTom Stellard SelectionDAG &DAG) const 39431bb79a41bd5e7402954385daea1594c3e750abTom Stellard{ 40431bb79a41bd5e7402954385daea1594c3e750abTom Stellard unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 41431bb79a41bd5e7402954385daea1594c3e750abTom Stellard DebugLoc DL = Op.getDebugLoc(); 42431bb79a41bd5e7402954385daea1594c3e750abTom Stellard EVT VT = Op.getValueType(); 43431bb79a41bd5e7402954385daea1594c3e750abTom Stellard 44431bb79a41bd5e7402954385daea1594c3e750abTom Stellard switch (IntrinsicID) { 45431bb79a41bd5e7402954385daea1594c3e750abTom Stellard default: return Op; 469a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard case AMDGPUIntrinsic::AMDIL_abs: 479a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard return LowerIntrinsicIABS(Op, DAG); 48ef8e66bc165ea2ef9987ab6406268ce195f74eb0Tom Stellard case AMDGPUIntrinsic::AMDIL_mad: 49ef8e66bc165ea2ef9987ab6406268ce195f74eb0Tom Stellard return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1), 50ef8e66bc165ea2ef9987ab6406268ce195f74eb0Tom Stellard Op.getOperand(2), Op.getOperand(3)); 51431bb79a41bd5e7402954385daea1594c3e750abTom Stellard case AMDGPUIntrinsic::AMDIL_max: 52431bb79a41bd5e7402954385daea1594c3e750abTom Stellard return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), 53431bb79a41bd5e7402954385daea1594c3e750abTom Stellard Op.getOperand(2)); 54431bb79a41bd5e7402954385daea1594c3e750abTom Stellard case AMDGPUIntrinsic::AMDGPU_imax: 55431bb79a41bd5e7402954385daea1594c3e750abTom Stellard return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), 56431bb79a41bd5e7402954385daea1594c3e750abTom Stellard Op.getOperand(2)); 57431bb79a41bd5e7402954385daea1594c3e750abTom Stellard case AMDGPUIntrinsic::AMDGPU_umax: 58431bb79a41bd5e7402954385daea1594c3e750abTom Stellard return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), 59431bb79a41bd5e7402954385daea1594c3e750abTom Stellard Op.getOperand(2)); 60431bb79a41bd5e7402954385daea1594c3e750abTom Stellard } 61a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 62a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 639a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard///IABS(a) = SMAX(sub(0, a), a) 649a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom StellardSDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, 659a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard SelectionDAG &DAG) const 669a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard{ 679a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard 689a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard DebugLoc DL = Op.getDebugLoc(); 699a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard EVT VT = Op.getValueType(); 709a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), 719a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard Op.getOperand(1)); 729a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard 739a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1)); 749a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard} 759a020092aedc6310d5bfc72b2aa6fc4348fe5c32Tom Stellard 76a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardvoid AMDGPUTargetLowering::addLiveIn(MachineInstr * MI, 77a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineFunction * MF, MachineRegisterInfo & MRI, 78bcfc97dbf40c256ed59c2424e0c55b845f0f2569Tom Stellard const TargetInstrInfo * TII, unsigned reg) const 79a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 80bcfc97dbf40c256ed59c2424e0c55b845f0f2569Tom Stellard AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg()); 81a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 82a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 83431bb79a41bd5e7402954385daea1594c3e750abTom Stellard#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node; 84431bb79a41bd5e7402954385daea1594c3e750abTom Stellard 85431bb79a41bd5e7402954385daea1594c3e750abTom Stellardconst char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const 86431bb79a41bd5e7402954385daea1594c3e750abTom Stellard{ 87431bb79a41bd5e7402954385daea1594c3e750abTom Stellard switch (Opcode) { 88431bb79a41bd5e7402954385daea1594c3e750abTom Stellard default: return AMDILTargetLowering::getTargetNodeName(Opcode); 89431bb79a41bd5e7402954385daea1594c3e750abTom Stellard 90431bb79a41bd5e7402954385daea1594c3e750abTom Stellard NODE_NAME_CASE(FMAX) 91431bb79a41bd5e7402954385daea1594c3e750abTom Stellard NODE_NAME_CASE(SMAX) 92431bb79a41bd5e7402954385daea1594c3e750abTom Stellard NODE_NAME_CASE(UMAX) 93431bb79a41bd5e7402954385daea1594c3e750abTom Stellard } 94431bb79a41bd5e7402954385daea1594c3e750abTom Stellard} 95