intel_batchbuffer.c revision b76164dcedad257f37af57358b102e14fdea8381
1/**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "intel_context.h"
29#include "intel_batchbuffer.h"
30#include "intel_decode.h"
31#include "intel_reg.h"
32#include "intel_bufmgr.h"
33#include "intel_buffers.h"
34
35void
36intel_batchbuffer_reset(struct intel_batchbuffer *batch)
37{
38   struct intel_context *intel = batch->intel;
39
40   if (batch->buf != NULL) {
41      dri_bo_unreference(batch->buf);
42      batch->buf = NULL;
43   }
44
45   if (!batch->buffer)
46      batch->buffer = malloc (intel->maxBatchSize);
47
48   batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
49			     intel->maxBatchSize, 4096);
50   if (batch->buffer)
51      batch->map = batch->buffer;
52   else {
53      dri_bo_map(batch->buf, GL_TRUE);
54      batch->map = batch->buf->virtual;
55   }
56   batch->size = intel->maxBatchSize;
57   batch->ptr = batch->map;
58   batch->dirty_state = ~0;
59}
60
61struct intel_batchbuffer *
62intel_batchbuffer_alloc(struct intel_context *intel)
63{
64   struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
65
66   batch->intel = intel;
67   intel_batchbuffer_reset(batch);
68
69   return batch;
70}
71
72void
73intel_batchbuffer_free(struct intel_batchbuffer *batch)
74{
75   if (batch->buffer)
76      free (batch->buffer);
77   else {
78      if (batch->map) {
79	 dri_bo_unmap(batch->buf);
80	 batch->map = NULL;
81      }
82   }
83   dri_bo_unreference(batch->buf);
84   batch->buf = NULL;
85   free(batch);
86}
87
88
89
90/* TODO: Push this whole function into bufmgr.
91 */
92static void
93do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
94{
95   struct intel_context *intel = batch->intel;
96   int ret = 0;
97   int x_off = 0, y_off = 0;
98
99   if (batch->buffer)
100      dri_bo_subdata (batch->buf, 0, used, batch->buffer);
101   else
102      dri_bo_unmap(batch->buf);
103
104   batch->map = NULL;
105   batch->ptr = NULL;
106
107   dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16));
108
109   if (INTEL_DEBUG & DEBUG_BATCH) {
110      dri_bo_map(batch->buf, GL_FALSE);
111      intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
112		   intel->intelScreen->deviceID);
113      dri_bo_unmap(batch->buf);
114
115      if (intel->vtbl.debug_batch != NULL)
116	 intel->vtbl.debug_batch(intel);
117   }
118
119   if (ret != 0) {
120      exit(1);
121   }
122   intel->vtbl.new_batch(intel);
123}
124
125void
126_intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
127			 int line)
128{
129   struct intel_context *intel = batch->intel;
130   GLuint used = batch->ptr - batch->map;
131
132   if (!intel->using_dri2_swapbuffers &&
133       intel->first_post_swapbuffers_batch == NULL) {
134      intel->first_post_swapbuffers_batch = intel->batch->buf;
135      drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
136   }
137
138   if (used == 0)
139      return;
140
141   if (INTEL_DEBUG & DEBUG_BATCH)
142      fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
143	      used);
144
145   batch->reserved_space = 0;
146   /* Emit a flush if the bufmgr doesn't do it for us. */
147   if (intel->always_flush_cache) {
148      intel_batchbuffer_emit_mi_flush(batch);
149      used = batch->ptr - batch->map;
150   }
151
152   /* Round batchbuffer usage to 2 DWORDs. */
153
154   if ((used & 4) == 0) {
155      *(GLuint *) (batch->ptr) = 0; /* noop */
156      batch->ptr += 4;
157      used = batch->ptr - batch->map;
158   }
159
160   /* Mark the end of the buffer. */
161   *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
162   batch->ptr += 4;
163   used = batch->ptr - batch->map;
164
165   /* Workaround for recursive batchbuffer flushing: If the window is
166    * moved, we can get into a case where we try to flush during a
167    * flush.  What happens is that when we try to grab the lock for
168    * the first flush, we detect that the window moved which then
169    * causes another flush (from the intel_draw_buffer() call in
170    * intelUpdatePageFlipping()).  To work around this we reset the
171    * batchbuffer tail pointer before trying to get the lock.  This
172    * prevent the nested buffer flush, but a better fix would be to
173    * avoid that in the first place. */
174   batch->ptr = batch->map;
175
176   if (intel->vtbl.finish_batch)
177      intel->vtbl.finish_batch(intel);
178
179   /* Check that we didn't just wrap our batchbuffer at a bad time. */
180   assert(!intel->no_batch_wrap);
181
182   batch->reserved_space = BATCH_RESERVED;
183
184   /* TODO: Just pass the relocation list and dma buffer up to the
185    * kernel.
186    */
187   do_flush_locked(batch, used);
188
189   if (INTEL_DEBUG & DEBUG_SYNC) {
190      fprintf(stderr, "waiting for idle\n");
191      dri_bo_map(batch->buf, GL_TRUE);
192      dri_bo_unmap(batch->buf);
193   }
194
195   /* Reset the buffer:
196    */
197   intel_batchbuffer_reset(batch);
198}
199
200
201/*  This is the only way buffers get added to the validate list.
202 */
203GLboolean
204intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
205                             dri_bo *buffer,
206                             uint32_t read_domains, uint32_t write_domain,
207			     uint32_t delta)
208{
209   int ret;
210
211   if (batch->ptr - batch->map > batch->buf->size)
212    printf ("bad relocation ptr %p map %p offset %d size %lu\n",
213	    batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
214   ret = dri_bo_emit_reloc(batch->buf, read_domains, write_domain,
215			   delta, batch->ptr - batch->map, buffer);
216
217   /*
218    * Using the old buffer offset, write in what the right data would be, in case
219    * the buffer doesn't move and we can short-circuit the relocation processing
220    * in the kernel
221    */
222   intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
223
224   return GL_TRUE;
225}
226
227void
228intel_batchbuffer_data(struct intel_batchbuffer *batch,
229                       const void *data, GLuint bytes)
230{
231   assert((bytes & 3) == 0);
232   intel_batchbuffer_require_space(batch, bytes);
233   __memcpy(batch->ptr, data, bytes);
234   batch->ptr += bytes;
235}
236
237/* Emit a pipelined flush to either flush render and texture cache for
238 * reading from a FBO-drawn texture, or flush so that frontbuffer
239 * render appears on the screen in DRI1.
240 *
241 * This is also used for the always_flush_cache driconf debug option.
242 */
243void
244intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
245{
246   struct intel_context *intel = batch->intel;
247
248   if (intel->gen >= 4) {
249      BEGIN_BATCH(4);
250      OUT_BATCH(_3DSTATE_PIPE_CONTROL |
251		PIPE_CONTROL_INSTRUCTION_FLUSH |
252		PIPE_CONTROL_WRITE_FLUSH |
253		PIPE_CONTROL_NO_WRITE);
254      OUT_BATCH(0); /* write address */
255      OUT_BATCH(0); /* write data */
256      OUT_BATCH(0); /* write data */
257      ADVANCE_BATCH();
258   } else {
259      BEGIN_BATCH(1);
260      OUT_BATCH(MI_FLUSH);
261      ADVANCE_BATCH();
262   }
263}
264