r200_reg.h revision 6c2e82b601268680c4c950e95e5c09c7b13141c2
1/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_reg.h,v 1.2 2002/12/16 16:18:54 dawes Exp $ */ 2/* 3Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 4 5The Weather Channel (TM) funded Tungsten Graphics to develop the 6initial release of the Radeon 8500 driver under the XFree86 license. 7This notice must be preserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28*/ 29 30#ifndef _R200_REG_H_ 31#define _R200_REG_H_ 32 33#define R200_PP_MISC 0x1c14 34#define R200_REF_ALPHA_MASK 0x000000ff 35#define R200_ALPHA_TEST_FAIL (0 << 8) 36#define R200_ALPHA_TEST_LESS (1 << 8) 37#define R200_ALPHA_TEST_LEQUAL (2 << 8) 38#define R200_ALPHA_TEST_EQUAL (3 << 8) 39#define R200_ALPHA_TEST_GEQUAL (4 << 8) 40#define R200_ALPHA_TEST_GREATER (5 << 8) 41#define R200_ALPHA_TEST_NEQUAL (6 << 8) 42#define R200_ALPHA_TEST_PASS (7 << 8) 43#define R200_ALPHA_TEST_OP_MASK (7 << 8) 44#define R200_CHROMA_FUNC_FAIL (0 << 16) 45#define R200_CHROMA_FUNC_PASS (1 << 16) 46#define R200_CHROMA_FUNC_NEQUAL (2 << 16) 47#define R200_CHROMA_FUNC_EQUAL (3 << 16) 48#define R200_CHROMA_KEY_NEAREST (0 << 18) 49#define R200_CHROMA_KEY_ZERO (1 << 18) 50#define R200_RIGHT_HAND_CUBE_D3D (0 << 24) 51#define R200_RIGHT_HAND_CUBE_OGL (1 << 24) 52#define R200_PP_FOG_COLOR 0x1c18 53#define R200_FOG_COLOR_MASK 0x00ffffff 54#define R200_FOG_VERTEX (0 << 24) 55#define R200_FOG_TABLE (1 << 24) 56#define R200_FOG_USE_DEPTH (0 << 25) 57#define R200_FOG_USE_W (1 << 25) 58#define R200_FOG_USE_DIFFUSE_ALPHA (2 << 25) 59#define R200_FOG_USE_SPEC_ALPHA (3 << 25) 60#define R200_FOG_USE_VTX_FOG (4 << 25) 61#define R200_FOG_USE_MASK (7 << 25) 62#define R200_RE_SOLID_COLOR 0x1c1c 63#define R200_RB3D_BLENDCNTL 0x1c20 64#define R200_COMB_FCN_MASK (7 << 12) 65#define R200_COMB_FCN_ADD_CLAMP (0 << 12) 66#define R200_COMB_FCN_ADD_NOCLAMP (1 << 12) 67#define R200_COMB_FCN_SUB_CLAMP (2 << 12) 68#define R200_COMB_FCN_SUB_NOCLAMP (3 << 12) 69#define R200_COMB_FCN_MIN (4 << 12) 70#define R200_COMB_FCN_MAX (5 << 12) 71#define R200_COMB_FCN_RSUB_CLAMP (6 << 12) 72#define R200_COMB_FCN_RSUB_NOCLAMP (7 << 12) 73#define R200_BLEND_GL_ZERO (32) 74#define R200_BLEND_GL_ONE (33) 75#define R200_BLEND_GL_SRC_COLOR (34) 76#define R200_BLEND_GL_ONE_MINUS_SRC_COLOR (35) 77#define R200_BLEND_GL_DST_COLOR (36) 78#define R200_BLEND_GL_ONE_MINUS_DST_COLOR (37) 79#define R200_BLEND_GL_SRC_ALPHA (38) 80#define R200_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) 81#define R200_BLEND_GL_DST_ALPHA (40) 82#define R200_BLEND_GL_ONE_MINUS_DST_ALPHA (41) 83#define R200_BLEND_GL_SRC_ALPHA_SATURATE (42) /* src factor only */ 84#define R200_BLEND_GL_CONST_COLOR (43) 85#define R200_BLEND_GL_ONE_MINUS_CONST_COLOR (44) 86#define R200_BLEND_GL_CONST_ALPHA (45) 87#define R200_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) 88#define R200_BLEND_MASK (63) 89#define R200_SRC_BLEND_SHIFT (16) 90#define R200_DST_BLEND_SHIFT (24) 91#define R200_RB3D_DEPTHOFFSET 0x1c24 92#define R200_RB3D_DEPTHPITCH 0x1c28 93#define R200_DEPTHPITCH_MASK 0x00001ff8 94#define R200_DEPTH_HYPERZ (3 << 16) 95#define R200_DEPTH_ENDIAN_NO_SWAP (0 << 18) 96#define R200_DEPTH_ENDIAN_WORD_SWAP (1 << 18) 97#define R200_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) 98#define R200_RB3D_ZSTENCILCNTL 0x1c2c 99#define R200_DEPTH_FORMAT_MASK (0xf << 0) 100#define R200_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 101#define R200_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 102#define R200_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) 103#define R200_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) 104#define R200_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) 105#define R200_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) 106#define R200_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) 107#define R200_Z_TEST_NEVER (0 << 4) 108#define R200_Z_TEST_LESS (1 << 4) 109#define R200_Z_TEST_LEQUAL (2 << 4) 110#define R200_Z_TEST_EQUAL (3 << 4) 111#define R200_Z_TEST_GEQUAL (4 << 4) 112#define R200_Z_TEST_GREATER (5 << 4) 113#define R200_Z_TEST_NEQUAL (6 << 4) 114#define R200_Z_TEST_ALWAYS (7 << 4) 115#define R200_Z_TEST_MASK (7 << 4) 116#define R200_Z_HIERARCHY_ENABLE (1 << 8) 117#define R200_STENCIL_TEST_NEVER (0 << 12) 118#define R200_STENCIL_TEST_LESS (1 << 12) 119#define R200_STENCIL_TEST_LEQUAL (2 << 12) 120#define R200_STENCIL_TEST_EQUAL (3 << 12) 121#define R200_STENCIL_TEST_GEQUAL (4 << 12) 122#define R200_STENCIL_TEST_GREATER (5 << 12) 123#define R200_STENCIL_TEST_NEQUAL (6 << 12) 124#define R200_STENCIL_TEST_ALWAYS (7 << 12) 125#define R200_STENCIL_TEST_MASK (0x7 << 12) 126#define R200_STENCIL_FAIL_KEEP (0 << 16) 127#define R200_STENCIL_FAIL_ZERO (1 << 16) 128#define R200_STENCIL_FAIL_REPLACE (2 << 16) 129#define R200_STENCIL_FAIL_INC (3 << 16) 130#define R200_STENCIL_FAIL_DEC (4 << 16) 131#define R200_STENCIL_FAIL_INVERT (5 << 16) 132#define R200_STENCIL_FAIL_INC_WRAP (6 << 16) 133#define R200_STENCIL_FAIL_DEC_WRAP (7 << 16) 134#define R200_STENCIL_FAIL_MASK (0x7 << 16) 135#define R200_STENCIL_ZPASS_KEEP (0 << 20) 136#define R200_STENCIL_ZPASS_ZERO (1 << 20) 137#define R200_STENCIL_ZPASS_REPLACE (2 << 20) 138#define R200_STENCIL_ZPASS_INC (3 << 20) 139#define R200_STENCIL_ZPASS_DEC (4 << 20) 140#define R200_STENCIL_ZPASS_INVERT (5 << 20) 141#define R200_STENCIL_ZPASS_INC_WRAP (6 << 20) 142#define R200_STENCIL_ZPASS_DEC_WRAP (7 << 20) 143#define R200_STENCIL_ZPASS_MASK (0x7 << 20) 144#define R200_STENCIL_ZFAIL_KEEP (0 << 24) 145#define R200_STENCIL_ZFAIL_ZERO (1 << 24) 146#define R200_STENCIL_ZFAIL_REPLACE (2 << 24) 147#define R200_STENCIL_ZFAIL_INC (3 << 24) 148#define R200_STENCIL_ZFAIL_DEC (4 << 24) 149#define R200_STENCIL_ZFAIL_INVERT (5 << 24) 150#define R200_STENCIL_ZFAIL_INC_WRAP (6 << 24) 151#define R200_STENCIL_ZFAIL_DEC_WRAP (7 << 24) 152#define R200_STENCIL_ZFAIL_MASK (0x7 << 24) 153#define R200_Z_COMPRESSION_ENABLE (1 << 28) 154#define R200_FORCE_Z_DIRTY (1 << 29) 155#define R200_Z_WRITE_ENABLE (1 << 30) 156#define R200_Z_DECOMPRESSION_ENABLE (1 << 31) 157/*gap*/ 158#define R200_PP_CNTL 0x1c38 159#define R200_TEX_0_ENABLE 0x00000010 160#define R200_TEX_1_ENABLE 0x00000020 161#define R200_TEX_2_ENABLE 0x00000040 162#define R200_TEX_3_ENABLE 0x00000080 163#define R200_TEX_4_ENABLE 0x00000100 164#define R200_TEX_5_ENABLE 0x00000200 165#define R200_TEX_ENABLE_MASK 0x000003f0 166#define R200_FILTER_ROUND_MODE_MASK 0x00000400 167#define R200_TEX_BLEND_7_ENABLE 0x00000800 168#define R200_TEX_BLEND_0_ENABLE 0x00001000 169#define R200_TEX_BLEND_1_ENABLE 0x00002000 170#define R200_TEX_BLEND_2_ENABLE 0x00004000 171#define R200_TEX_BLEND_3_ENABLE 0x00008000 172#define R200_TEX_BLEND_4_ENABLE 0x00010000 173#define R200_TEX_BLEND_5_ENABLE 0x00020000 174#define R200_TEX_BLEND_6_ENABLE 0x00040000 175#define R200_TEX_BLEND_ENABLE_MASK 0x0007f800 176#define R200_TEX_BLEND_0_ENABLE_SHIFT (12) 177#define R200_MULTI_PASS_ENABLE 0x00080000 178#define R200_SPECULAR_ENABLE 0x00200000 179#define R200_FOG_ENABLE 0x00400000 180#define R200_ALPHA_TEST_ENABLE 0x00800000 181#define R200_ANTI_ALIAS_NONE 0x00000000 182#define R200_ANTI_ALIAS_LINE 0x01000000 183#define R200_ANTI_ALIAS_POLY 0x02000000 184#define R200_ANTI_ALIAS_MASK 0x03000000 185#define R200_RB3D_CNTL 0x1c3c 186#define R200_ALPHA_BLEND_ENABLE (1 << 0) 187#define R200_PLANE_MASK_ENABLE (1 << 1) 188#define R200_DITHER_ENABLE (1 << 2) 189#define R200_ROUND_ENABLE (1 << 3) 190#define R200_SCALE_DITHER_ENABLE (1 << 4) 191#define R200_DITHER_INIT (1 << 5) 192#define R200_ROP_ENABLE (1 << 6) 193#define R200_STENCIL_ENABLE (1 << 7) 194#define R200_Z_ENABLE (1 << 8) 195#define R200_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 196#define R200_COLOR_FORMAT_ARGB1555 (3 << 10) 197#define R200_COLOR_FORMAT_RGB565 (4 << 10) 198#define R200_COLOR_FORMAT_ARGB8888 (6 << 10) 199#define R200_COLOR_FORMAT_RGB332 (7 << 10) 200#define R200_COLOR_FORMAT_Y8 (8 << 10) 201#define R200_COLOR_FORMAT_RGB8 (9 << 10) 202#define R200_COLOR_FORMAT_YUV422_VYUY (11 << 10) 203#define R200_COLOR_FORMAT_YUV422_YVYU (12 << 10) 204#define R200_COLOR_FORMAT_aYUV444 (14 << 10) 205#define R200_COLOR_FORMAT_ARGB4444 (15 << 10) 206#define R200_CLRCMP_FLIP_ENABLE (1 << 14) 207#define R200_SEPARATE_ALPHA_ENABLE (1 << 16) 208#define R200_RB3D_COLOROFFSET 0x1c40 209#define R200_COLOROFFSET_MASK 0xfffffff0 210#define R200_RE_WIDTH_HEIGHT 0x1c44 211#define R200_RE_WIDTH_SHIFT 0 212#define R200_RE_HEIGHT_SHIFT 16 213#define R200_RB3D_COLORPITCH 0x1c48 214#define R200_COLORPITCH_MASK 0x000001ff8 215#define R200_COLOR_TILE_ENABLE (1 << 16) 216#define R200_COLOR_MICROTILE_ENABLE (1 << 17) 217#define R200_COLOR_ENDIAN_NO_SWAP (0 << 18) 218#define R200_COLOR_ENDIAN_WORD_SWAP (1 << 18) 219#define R200_COLOR_ENDIAN_DWORD_SWAP (2 << 18) 220#define R200_SE_CNTL 0x1c4c 221#define R200_FFACE_CULL_CW (0 << 0) 222#define R200_FFACE_CULL_CCW (1 << 0) 223#define R200_FFACE_CULL_DIR_MASK (1 << 0) 224#define R200_BFACE_CULL (0 << 1) 225#define R200_BFACE_SOLID (3 << 1) 226#define R200_FFACE_CULL (0 << 3) 227#define R200_FFACE_SOLID (3 << 3) 228#define R200_FFACE_CULL_MASK (3 << 3) 229#define R200_FLAT_SHADE_VTX_0 (0 << 6) 230#define R200_FLAT_SHADE_VTX_1 (1 << 6) 231#define R200_FLAT_SHADE_VTX_2 (2 << 6) 232#define R200_FLAT_SHADE_VTX_LAST (3 << 6) 233#define R200_DIFFUSE_SHADE_SOLID (0 << 8) 234#define R200_DIFFUSE_SHADE_FLAT (1 << 8) 235#define R200_DIFFUSE_SHADE_GOURAUD (2 << 8) 236#define R200_DIFFUSE_SHADE_MASK (3 << 8) 237#define R200_ALPHA_SHADE_SOLID (0 << 10) 238#define R200_ALPHA_SHADE_FLAT (1 << 10) 239#define R200_ALPHA_SHADE_GOURAUD (2 << 10) 240#define R200_ALPHA_SHADE_MASK (3 << 10) 241#define R200_SPECULAR_SHADE_SOLID (0 << 12) 242#define R200_SPECULAR_SHADE_FLAT (1 << 12) 243#define R200_SPECULAR_SHADE_GOURAUD (2 << 12) 244#define R200_SPECULAR_SHADE_MASK (3 << 12) 245#define R200_FOG_SHADE_SOLID (0 << 14) 246#define R200_FOG_SHADE_FLAT (1 << 14) 247#define R200_FOG_SHADE_GOURAUD (2 << 14) 248#define R200_FOG_SHADE_MASK (3 << 14) 249#define R200_ZBIAS_ENABLE_POINT (1 << 16) 250#define R200_ZBIAS_ENABLE_LINE (1 << 17) 251#define R200_ZBIAS_ENABLE_TRI (1 << 18) 252#define R200_WIDELINE_ENABLE (1 << 20) 253#define R200_VTX_PIX_CENTER_D3D (0 << 27) 254#define R200_VTX_PIX_CENTER_OGL (1 << 27) 255#define R200_ROUND_MODE_TRUNC (0 << 28) 256#define R200_ROUND_MODE_ROUND (1 << 28) 257#define R200_ROUND_MODE_ROUND_EVEN (2 << 28) 258#define R200_ROUND_MODE_ROUND_ODD (3 << 28) 259#define R200_ROUND_PREC_16TH_PIX (0 << 30) 260#define R200_ROUND_PREC_8TH_PIX (1 << 30) 261#define R200_ROUND_PREC_4TH_PIX (2 << 30) 262#define R200_ROUND_PREC_HALF_PIX (3 << 30) 263#define R200_RE_CNTL 0x1c50 264#define R200_STIPPLE_ENABLE 0x1 265#define R200_SCISSOR_ENABLE 0x2 266#define R200_PATTERN_ENABLE 0x4 267#define R200_PERSPECTIVE_ENABLE 0x8 268#define R200_POINT_SMOOTH 0x20 269#define R200_VTX_STQ0_D3D 0x00010000 270#define R200_VTX_STQ1_D3D 0x00040000 271#define R200_VTX_STQ2_D3D 0x00100000 272#define R200_VTX_STQ3_D3D 0x00400000 273#define R200_VTX_STQ4_D3D 0x01000000 274#define R200_VTX_STQ5_D3D 0x04000000 275/* gap */ 276#define R200_RE_STIPPLE_ADDR 0x1cc8 277#define R200_RE_STIPPLE_DATA 0x1ccc 278#define R200_RE_LINE_PATTERN 0x1cd0 279#define R200_LINE_PATTERN_MASK 0x0000ffff 280#define R200_LINE_REPEAT_COUNT_SHIFT 16 281#define R200_LINE_PATTERN_START_SHIFT 24 282#define R200_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) 283#define R200_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) 284#define R200_LINE_PATTERN_AUTO_RESET (1 << 29) 285#define R200_RE_LINE_STATE 0x1cd4 286#define R200_LINE_CURRENT_PTR_SHIFT 0 287#define R200_LINE_CURRENT_COUNT_SHIFT 8 288#define R200_RE_SCISSOR_TL_0 0x1cd8 289#define R200_RE_SCISSOR_BR_0 0x1cdc 290#define R200_RE_SCISSOR_TL_1 0x1ce0 291#define R200_RE_SCISSOR_BR_1 0x1ce4 292#define R200_RE_SCISSOR_TL_2 0x1ce8 293#define R200_RE_SCISSOR_BR_2 0x1cec 294/* gap */ 295#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 296#define R200_DEPTHX_SHIFT 0 297#define R200_DEPTHY_SHIFT 16 298/* gap */ 299#define R200_RB3D_STENCILREFMASK 0x1d7c 300#define R200_STENCIL_REF_SHIFT 0 301#define R200_STENCIL_REF_MASK (0xff << 0) 302#define R200_STENCIL_MASK_SHIFT 16 303#define R200_STENCIL_VALUE_MASK (0xff << 16) 304#define R200_STENCIL_WRITEMASK_SHIFT 24 305#define R200_STENCIL_WRITE_MASK (0xff << 24) 306#define R200_RB3D_ROPCNTL 0x1d80 307#define R200_ROP_MASK (15 << 8) 308#define R200_ROP_CLEAR (0 << 8) 309#define R200_ROP_NOR (1 << 8) 310#define R200_ROP_AND_INVERTED (2 << 8) 311#define R200_ROP_COPY_INVERTED (3 << 8) 312#define R200_ROP_AND_REVERSE (4 << 8) 313#define R200_ROP_INVERT (5 << 8) 314#define R200_ROP_XOR (6 << 8) 315#define R200_ROP_NAND (7 << 8) 316#define R200_ROP_AND (8 << 8) 317#define R200_ROP_EQUIV (9 << 8) 318#define R200_ROP_NOOP (10 << 8) 319#define R200_ROP_OR_INVERTED (11 << 8) 320#define R200_ROP_COPY (12 << 8) 321#define R200_ROP_OR_REVERSE (13 << 8) 322#define R200_ROP_OR (14 << 8) 323#define R200_ROP_SET (15 << 8) 324#define R200_RB3D_PLANEMASK 0x1d84 325/* gap */ 326#define R200_SE_VPORT_XSCALE 0x1d98 327#define R200_SE_VPORT_XOFFSET 0x1d9c 328#define R200_SE_VPORT_YSCALE 0x1da0 329#define R200_SE_VPORT_YOFFSET 0x1da4 330#define R200_SE_VPORT_ZSCALE 0x1da8 331#define R200_SE_VPORT_ZOFFSET 0x1dac 332#define R200_SE_ZBIAS_FACTOR 0x1db0 333#define R200_SE_ZBIAS_CONSTANT 0x1db4 334#define R200_SE_LINE_WIDTH 0x1db8 335#define R200_LINE_WIDTH_SHIFT 0x00000000 336#define R200_MINPOINTSIZE_SHIFT 0x00000010 337/* gap */ 338#define R200_SE_VAP_CNTL 0x2080 339#define R200_VAP_TCL_ENABLE 0x00000001 340#define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 341#define R200_VAP_FORCE_W_TO_ONE 0x00010000 342#define R200_VAP_D3D_TEX_DEFAULT 0x00020000 343#define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 344#define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 345#define R200_SE_VF_CNTL 0x2084 346#define R200_VF_PRIM_NONE 0x00000000 347#define R200_VF_PRIM_POINTS 0x00000001 348#define R200_VF_PRIM_LINES 0x00000002 349#define R200_VF_PRIM_LINE_STRIP 0x00000003 350#define R200_VF_PRIM_TRIANGLES 0x00000004 351#define R200_VF_PRIM_TRIANGLE_FAN 0x00000005 352#define R200_VF_PRIM_TRIANGLE_STRIP 0x00000006 353#define R200_VF_PRIM_RECT_LIST 0x00000008 354#define R200_VF_PRIM_3VRT_POINTS 0x00000009 355#define R200_VF_PRIM_3VRT_LINES 0x0000000a 356#define R200_VF_PRIM_POINT_SPRITES 0x0000000b 357#define R200_VF_PRIM_LINE_LOOP 0x0000000c 358#define R200_VF_PRIM_QUADS 0x0000000d 359#define R200_VF_PRIM_QUAD_STRIP 0x0000000e 360#define R200_VF_PRIM_POLYGON 0x0000000f 361#define R200_VF_PRIM_MASK 0x0000000f 362#define R200_VF_PRIM_WALK_IND 0x00000010 363#define R200_VF_PRIM_WALK_LIST 0x00000020 364#define R200_VF_PRIM_WALK_RING 0x00000030 365#define R200_VF_PRIM_WALK_MASK 0x00000030 366#define R200_VF_COLOR_ORDER_RGBA 0x00000040 367#define R200_VF_TCL_OUTPUT_VTX_ENABLE 0x00000200 368#define R200_VF_INDEX_SZ_4 0x00000800 369#define R200_VF_VERTEX_NUMBER_MASK 0xffff0000 370#define R200_VF_VERTEX_NUMBER_SHIFT 16 371#define R200_SE_VTX_FMT_0 0x2088 372#define R200_VTX_XY 0 /* always have xy */ 373#define R200_VTX_Z0 (1<<0) 374#define R200_VTX_W0 (1<<1) 375#define R200_VTX_WEIGHT_COUNT_SHIFT (2) 376#define R200_VTX_PV_MATRIX_SEL (1<<5) 377#define R200_VTX_N0 (1<<6) 378#define R200_VTX_POINT_SIZE (1<<7) 379#define R200_VTX_DISCRETE_FOG (1<<8) 380#define R200_VTX_SHININESS_0 (1<<9) 381#define R200_VTX_SHININESS_1 (1<<10) 382#define R200_VTX_COLOR_NOT_PRESENT 0 383#define R200_VTX_PK_RGBA 1 384#define R200_VTX_FP_RGB 2 385#define R200_VTX_FP_RGBA 3 386#define R200_VTX_COLOR_MASK 3 387#define R200_VTX_COLOR_0_SHIFT 11 388#define R200_VTX_COLOR_1_SHIFT 13 389#define R200_VTX_COLOR_2_SHIFT 15 390#define R200_VTX_COLOR_3_SHIFT 17 391#define R200_VTX_COLOR_4_SHIFT 19 392#define R200_VTX_COLOR_5_SHIFT 21 393#define R200_VTX_COLOR_6_SHIFT 23 394#define R200_VTX_COLOR_7_SHIFT 25 395#define R200_VTX_XY1 (1<<28) 396#define R200_VTX_Z1 (1<<29) 397#define R200_VTX_W1 (1<<30) 398#define R200_VTX_N1 (1<<31) 399#define R200_SE_VTX_FMT_1 0x208c 400#define R200_VTX_TEX0_COMP_CNT_SHIFT 0 401#define R200_VTX_TEX1_COMP_CNT_SHIFT 3 402#define R200_VTX_TEX2_COMP_CNT_SHIFT 6 403#define R200_VTX_TEX3_COMP_CNT_SHIFT 9 404#define R200_VTX_TEX4_COMP_CNT_SHIFT 12 405#define R200_VTX_TEX5_COMP_CNT_SHIFT 15 406#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 407#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 408/* gap */ 409#define R200_SE_VTE_CNTL 0x20b0 410#define R200_VPORT_X_SCALE_ENA 0x00000001 411#define R200_VPORT_X_OFFSET_ENA 0x00000002 412#define R200_VPORT_Y_SCALE_ENA 0x00000004 413#define R200_VPORT_Y_OFFSET_ENA 0x00000008 414#define R200_VPORT_Z_SCALE_ENA 0x00000010 415#define R200_VPORT_Z_OFFSET_ENA 0x00000020 416#define R200_VTX_XY_FMT 0x00000100 417#define R200_VTX_Z_FMT 0x00000200 418#define R200_VTX_W0_FMT 0x00000400 419#define R200_VTX_W0_NORMALIZE 0x00000800 420#define R200_VTX_ST_DENORMALIZED 0x00001000 421/* gap */ 422#define R200_SE_VTX_NUM_ARRAYS 0x20c0 423#define R200_SE_VTX_AOS_ATTR01 0x20c4 424#define R200_SE_VTX_AOS_ADDR0 0x20c8 425#define R200_SE_VTX_AOS_ADDR1 0x20cc 426#define R200_SE_VTX_AOS_ATTR23 0x20d0 427#define R200_SE_VTX_AOS_ADDR2 0x20d4 428#define R200_SE_VTX_AOS_ADDR3 0x20d8 429#define R200_SE_VTX_AOS_ATTR45 0x20dc 430#define R200_SE_VTX_AOS_ADDR4 0x20e0 431#define R200_SE_VTX_AOS_ADDR5 0x20e4 432#define R200_SE_VTX_AOS_ATTR67 0x20e8 433#define R200_SE_VTX_AOS_ADDR6 0x20ec 434#define R200_SE_VTX_AOS_ADDR7 0x20f0 435#define R200_SE_VTX_AOS_ATTR89 0x20f4 436#define R200_SE_VTX_AOS_ADDR8 0x20f8 437#define R200_SE_VTX_AOS_ADDR9 0x20fc 438#define R200_SE_VTX_AOS_ATTR1011 0x2100 439#define R200_SE_VTX_AOS_ADDR10 0x2104 440#define R200_SE_VTX_AOS_ADDR11 0x2108 441#define R200_SE_VF_MAX_VTX_INDX 0x210c 442#define R200_SE_VF_MIN_VTX_INDX 0x2110 443/* gap */ 444#define R200_SE_VAP_CNTL_STATUS 0x2140 445#define R200_VC_NO_SWAP (0 << 0) 446#define R200_VC_16BIT_SWAP (1 << 0) 447#define R200_VC_32BIT_SWAP (2 << 0) 448/* gap */ 449#define R200_SE_VTX_STATE_CNTL 0x2180 450#define R200_VSC_COLOR_0_ASSEMBLY_CNTL_SHIFT 0x00000000 451#define R200_VSC_COLOR_1_ASSEMBLY_CNTL_SHIFT 0x00000002 452#define R200_VSC_COLOR_2_ASSEMBLY_CNTL_SHIFT 0x00000004 453#define R200_VSC_COLOR_3_ASSEMBLY_CNTL_SHIFT 0x00000006 454#define R200_VSC_COLOR_4_ASSEMBLY_CNTL_SHIFT 0x00000008 455#define R200_VSC_COLOR_5_ASSEMBLY_CNTL_SHIFT 0x0000000a 456#define R200_VSC_COLOR_6_ASSEMBLY_CNTL_SHIFT 0x0000000c 457#define R200_VSC_COLOR_7_ASSEMBLY_CNTL_SHIFT 0x0000000e 458#define R200_VSC_UPDATE_USER_COLOR_0_ENABLE 0x00010000 459#define R200_VSC_UPDATE_USER_COLOR_1_ENABLE 0x00020000 460/* gap */ 461#define R200_SE_TCL_VECTOR_INDX_REG 0x2200 462#define R200_SE_TCL_VECTOR_DATA_REG 0x2204 463#define R200_SE_TCL_SCALAR_INDX_REG 0x2208 464#define R200_SE_TCL_SCALAR_DATA_REG 0x220c 465/* gap */ 466#define R200_SE_TCL_MATRIX_SEL_0 0x2230 467#define R200_MODELVIEW_0_SHIFT (0) 468#define R200_MODELVIEW_1_SHIFT (8) 469#define R200_MODELVIEW_2_SHIFT (16) 470#define R200_MODELVIEW_3_SHIFT (24) 471#define R200_SE_TCL_MATRIX_SEL_1 0x2234 472#define R200_IT_MODELVIEW_0_SHIFT (0) 473#define R200_IT_MODELVIEW_1_SHIFT (8) 474#define R200_IT_MODELVIEW_2_SHIFT (16) 475#define R200_IT_MODELVIEW_3_SHIFT (24) 476#define R200_SE_TCL_MATRIX_SEL_2 0x2238 477#define R200_MODELPROJECT_0_SHIFT (0) 478#define R200_MODELPROJECT_1_SHIFT (8) 479#define R200_MODELPROJECT_2_SHIFT (16) 480#define R200_MODELPROJECT_3_SHIFT (24) 481#define R200_SE_TCL_MATRIX_SEL_3 0x223c 482#define R200_TEXMAT_0_SHIFT 0 483#define R200_TEXMAT_1_SHIFT 8 484#define R200_TEXMAT_2_SHIFT 16 485#define R200_TEXMAT_3_SHIFT 24 486#define R200_SE_TCL_MATRIX_SEL_4 0x2240 487#define R200_TEXMAT_4_SHIFT 0 488#define R200_TEXMAT_5_SHIFT 8 489/* gap */ 490#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 491#define R200_OUTPUT_XYZW (1<<0) 492#define R200_OUTPUT_COLOR_0 (1<<8) 493#define R200_OUTPUT_COLOR_1 (1<<9) 494#define R200_OUTPUT_TEX_0 (1<<16) 495#define R200_OUTPUT_TEX_1 (1<<17) 496#define R200_OUTPUT_TEX_2 (1<<18) 497#define R200_OUTPUT_TEX_3 (1<<19) 498#define R200_OUTPUT_TEX_4 (1<<20) 499#define R200_OUTPUT_TEX_5 (1<<21) 500#define R200_OUTPUT_TEX_MASK (0x3f<<16) 501#define R200_OUTPUT_DISCRETE_FOG (1<<24) 502#define R200_OUTPUT_PT_SIZE (1<<25) 503#define R200_FORCE_INORDER_PROC (1<<31) 504#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 505#define R200_VERTEX_POSITION_ADDR__SHIFT 0x00000000 506#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1 0x2258 507#define R200_VTX_COLOR_0_ADDR__SHIFT 0x00000000 508#define R200_VTX_COLOR_1_ADDR__SHIFT 0x00000008 509#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2 0x225c 510#define R200_VTX_TEX_0_ADDR__SHIFT 0x00000000 511#define R200_VTX_TEX_1_ADDR__SHIFT 0x00000008 512#define R200_VTX_TEX_2_ADDR__SHIFT 0x00000010 513#define R200_VTX_TEX_3_ADDR__SHIFT 0x00000018 514#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3 0x2260 515#define R200_VTX_TEX_4_ADDR__SHIFT 0x00000000 516#define R200_VTX_TEX_5_ADDR__SHIFT 0x00000008 517 518/* gap */ 519#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 520#define R200_LIGHTING_ENABLE (1<<0) 521#define R200_LIGHT_IN_MODELSPACE (1<<1) 522#define R200_LOCAL_VIEWER (1<<2) 523#define R200_NORMALIZE_NORMALS (1<<3) 524#define R200_RESCALE_NORMALS (1<<4) 525#define R200_SPECULAR_LIGHTS (1<<5) 526#define R200_DIFFUSE_SPECULAR_COMBINE (1<<6) 527#define R200_LIGHT_ALPHA (1<<7) 528#define R200_LOCAL_LIGHT_VEC_GL (1<<8) 529#define R200_LIGHT_NO_NORMAL_AMBIENT_ONLY (1<<9) 530#define R200_LIGHT_TWOSIDE (1<<10) 531#define R200_FRONT_SHININESS_SOURCE_SHIFT (0xb) 532#define R200_BACK_SHININESS_SOURCE_SHIFT (0xd) 533#define R200_LM0_SOURCE_MATERIAL_0 (0) 534#define R200_LM0_SOURCE_MATERIAL_1 (1) 535#define R200_LM0_SOURCE_VERTEX_SHININESS_0 (2) 536#define R200_LM0_SOURCE_VERTEX_SHININESS_1 (3) 537#define R200_SE_TCL_LIGHT_MODEL_CTL_1 0x226c 538#define R200_LM1_SOURCE_LIGHT_PREMULT (0) 539#define R200_LM1_SOURCE_MATERIAL_0 (1) 540#define R200_LM1_SOURCE_VERTEX_COLOR_0 (2) 541#define R200_LM1_SOURCE_VERTEX_COLOR_1 (3) 542#define R200_LM1_SOURCE_VERTEX_COLOR_2 (4) 543#define R200_LM1_SOURCE_VERTEX_COLOR_3 (5) 544#define R200_LM1_SOURCE_VERTEX_COLOR_4 (6) 545#define R200_LM1_SOURCE_VERTEX_COLOR_5 (7) 546#define R200_LM1_SOURCE_VERTEX_COLOR_6 (8) 547#define R200_LM1_SOURCE_VERTEX_COLOR_7 (9) 548#define R200_LM1_SOURCE_MATERIAL_1 (0xf) 549#define R200_FRONT_EMISSIVE_SOURCE_SHIFT (0) 550#define R200_FRONT_AMBIENT_SOURCE_SHIFT (4) 551#define R200_FRONT_DIFFUSE_SOURCE_SHIFT (8) 552#define R200_FRONT_SPECULAR_SOURCE_SHIFT (12) 553#define R200_BACK_EMISSIVE_SOURCE_SHIFT (16) 554#define R200_BACK_AMBIENT_SOURCE_SHIFT (20) 555#define R200_BACK_DIFFUSE_SOURCE_SHIFT (24) 556#define R200_BACK_SPECULAR_SOURCE_SHIFT (28) 557#define R200_SE_TCL_PER_LIGHT_CTL_0 0x2270 558#define R200_LIGHT_0_ENABLE (1<<0) 559#define R200_LIGHT_0_ENABLE_AMBIENT (1<<1) 560#define R200_LIGHT_0_ENABLE_SPECULAR (1<<2) 561#define R200_LIGHT_0_IS_LOCAL (1<<3) 562#define R200_LIGHT_0_IS_SPOT (1<<4) 563#define R200_LIGHT_0_DUAL_CONE (1<<5) 564#define R200_LIGHT_0_ENABLE_RANGE_ATTEN (1<<6) 565#define R200_LIGHT_0_CONSTANT_RANGE_ATTEN (1<<7) 566#define R200_LIGHT_1_ENABLE (1<<16) 567#define R200_LIGHT_1_ENABLE_AMBIENT (1<<17) 568#define R200_LIGHT_1_ENABLE_SPECULAR (1<<18) 569#define R200_LIGHT_1_IS_LOCAL (1<<19) 570#define R200_LIGHT_1_IS_SPOT (1<<20) 571#define R200_LIGHT_1_DUAL_CONE (1<<21) 572#define R200_LIGHT_1_ENABLE_RANGE_ATTEN (1<<22) 573#define R200_LIGHT_1_CONSTANT_RANGE_ATTEN (1<<23) 574#define R200_LIGHT_0_SHIFT (0) 575#define R200_LIGHT_1_SHIFT (16) 576#define R200_SE_TCL_PER_LIGHT_CTL_1 0x2274 577#define R200_LIGHT_2_SHIFT (0) 578#define R200_LIGHT_3_SHIFT (16) 579#define R200_SE_TCL_PER_LIGHT_CTL_2 0x2278 580#define R200_LIGHT_4_SHIFT (0) 581#define R200_LIGHT_5_SHIFT (16) 582#define R200_SE_TCL_PER_LIGHT_CTL_3 0x227c 583#define R200_LIGHT_6_SHIFT (0) 584#define R200_LIGHT_7_SHIFT (16) 585/* gap */ 586#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 587#define R200_TEXGEN_COMP_MASK (0xf) 588#define R200_TEXGEN_COMP_S (0x1) 589#define R200_TEXGEN_COMP_T (0x2) 590#define R200_TEXGEN_COMP_R (0x4) 591#define R200_TEXGEN_COMP_Q (0x8) 592#define R200_TEXGEN_0_COMP_MASK_SHIFT (0) 593#define R200_TEXGEN_1_COMP_MASK_SHIFT (4) 594#define R200_TEXGEN_2_COMP_MASK_SHIFT (8) 595#define R200_TEXGEN_3_COMP_MASK_SHIFT (12) 596#define R200_TEXGEN_4_COMP_MASK_SHIFT (16) 597#define R200_TEXGEN_5_COMP_MASK_SHIFT (20) 598#define R200_SE_TCL_TEX_PROC_CTL_3 0x22ac 599#define R200_TEXGEN_0_INPUT_TEX_SHIFT (0) 600#define R200_TEXGEN_1_INPUT_TEX_SHIFT (4) 601#define R200_TEXGEN_2_INPUT_TEX_SHIFT (8) 602#define R200_TEXGEN_3_INPUT_TEX_SHIFT (12) 603#define R200_TEXGEN_4_INPUT_TEX_SHIFT (16) 604#define R200_TEXGEN_5_INPUT_TEX_SHIFT (20) 605#define R200_SE_TCL_TEX_PROC_CTL_0 0x22b0 606#define R200_TEXGEN_TEXMAT_0_ENABLE (1<<0) 607#define R200_TEXGEN_TEXMAT_1_ENABLE (1<<1) 608#define R200_TEXGEN_TEXMAT_2_ENABLE (1<<2) 609#define R200_TEXGEN_TEXMAT_3_ENABLE (1<<3) 610#define R200_TEXGEN_TEXMAT_4_ENABLE (1<<4) 611#define R200_TEXGEN_TEXMAT_5_ENABLE (1<<5) 612#define R200_TEXMAT_0_ENABLE (1<<8) 613#define R200_TEXMAT_1_ENABLE (1<<9) 614#define R200_TEXMAT_2_ENABLE (1<<10) 615#define R200_TEXMAT_3_ENABLE (1<<11) 616#define R200_TEXMAT_4_ENABLE (1<<12) 617#define R200_TEXMAT_5_ENABLE (1<<13) 618#define R200_TEXGEN_FORCE_W_TO_ONE (1<<16) 619#define R200_SE_TCL_TEX_PROC_CTL_1 0x22b4 620#define R200_TEXGEN_INPUT_MASK (0xf) 621#define R200_TEXGEN_INPUT_TEXCOORD_0 (0) 622#define R200_TEXGEN_INPUT_TEXCOORD_1 (1) 623#define R200_TEXGEN_INPUT_TEXCOORD_2 (2) 624#define R200_TEXGEN_INPUT_TEXCOORD_3 (3) 625#define R200_TEXGEN_INPUT_TEXCOORD_4 (4) 626#define R200_TEXGEN_INPUT_TEXCOORD_5 (5) 627#define R200_TEXGEN_INPUT_OBJ (8) 628#define R200_TEXGEN_INPUT_EYE (9) 629#define R200_TEXGEN_INPUT_EYE_NORMAL (0xa) 630#define R200_TEXGEN_INPUT_EYE_REFLECT (0xb) 631#define R200_TEXGEN_INPUT_SPHERE (0xd) 632#define R200_TEXGEN_0_INPUT_SHIFT (0) 633#define R200_TEXGEN_1_INPUT_SHIFT (4) 634#define R200_TEXGEN_2_INPUT_SHIFT (8) 635#define R200_TEXGEN_3_INPUT_SHIFT (12) 636#define R200_TEXGEN_4_INPUT_SHIFT (16) 637#define R200_TEXGEN_5_INPUT_SHIFT (20) 638#define R200_SE_TC_TEX_CYL_WRAP_CTL 0x22b8 639/* gap */ 640#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 641#define R200_UCP_IN_CLIP_SPACE (1<<0) 642#define R200_UCP_IN_MODEL_SPACE (1<<1) 643#define R200_UCP_ENABLE_0 (1<<2) 644#define R200_UCP_ENABLE_1 (1<<3) 645#define R200_UCP_ENABLE_2 (1<<4) 646#define R200_UCP_ENABLE_3 (1<<5) 647#define R200_UCP_ENABLE_4 (1<<6) 648#define R200_UCP_ENABLE_5 (1<<7) 649#define R200_TCL_FOG_MASK (3<<8) 650#define R200_TCL_FOG_DISABLE (0<<8) 651#define R200_TCL_FOG_EXP (1<<8) 652#define R200_TCL_FOG_EXP2 (2<<8) 653#define R200_TCL_FOG_LINEAR (3<<8) 654#define R200_RNG_BASED_FOG (1<<10) 655#define R200_CLIP_DISABLE (1<<11) 656#define R200_CULL_FRONT_IS_CW (0<<28) 657#define R200_CULL_FRONT_IS_CCW (1<<28) 658#define R200_CULL_FRONT (1<<29) 659#define R200_CULL_BACK (1<<30) 660#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 661#define R200_POINTSIZE_SEL_STATE (1<<16) 662/* gap */ 663#define R200_SE_VTX_ST_POS_0_X_4 0x2300 664#define R200_SE_VTX_ST_POS_0_Y_4 0x2304 665#define R200_SE_VTX_ST_POS_0_Z_4 0x2308 666#define R200_SE_VTX_ST_POS_0_W_4 0x230c 667#define R200_SE_VTX_ST_NORM_0_X 0x2310 668#define R200_SE_VTX_ST_NORM_0_Y 0x2314 669#define R200_SE_VTX_ST_NORM_0_Z 0x2318 670#define R200_SE_VTX_ST_PVMS 0x231c 671#define R200_SE_VTX_ST_CLR_0_R 0x2320 672#define R200_SE_VTX_ST_CLR_0_G 0x2324 673#define R200_SE_VTX_ST_CLR_0_B 0x2328 674#define R200_SE_VTX_ST_CLR_0_A 0x232c 675#define R200_SE_VTX_ST_CLR_1_R 0x2330 676#define R200_SE_VTX_ST_CLR_1_G 0x2334 677#define R200_SE_VTX_ST_CLR_1_B 0x2338 678#define R200_SE_VTX_ST_CLR_1_A 0x233c 679#define R200_SE_VTX_ST_CLR_2_R 0x2340 680#define R200_SE_VTX_ST_CLR_2_G 0x2344 681#define R200_SE_VTX_ST_CLR_2_B 0x2348 682#define R200_SE_VTX_ST_CLR_2_A 0x234c 683#define R200_SE_VTX_ST_CLR_3_R 0x2350 684#define R200_SE_VTX_ST_CLR_3_G 0x2354 685#define R200_SE_VTX_ST_CLR_3_B 0x2358 686#define R200_SE_VTX_ST_CLR_3_A 0x235c 687#define R200_SE_VTX_ST_CLR_4_R 0x2360 688#define R200_SE_VTX_ST_CLR_4_G 0x2364 689#define R200_SE_VTX_ST_CLR_4_B 0x2368 690#define R200_SE_VTX_ST_CLR_4_A 0x236c 691#define R200_SE_VTX_ST_CLR_5_R 0x2370 692#define R200_SE_VTX_ST_CLR_5_G 0x2374 693#define R200_SE_VTX_ST_CLR_5_B 0x2378 694#define R200_SE_VTX_ST_CLR_5_A 0x237c 695#define R200_SE_VTX_ST_CLR_6_R 0x2380 696#define R200_SE_VTX_ST_CLR_6_G 0x2384 697#define R200_SE_VTX_ST_CLR_6_B 0x2388 698#define R200_SE_VTX_ST_CLR_6_A 0x238c 699#define R200_SE_VTX_ST_CLR_7_R 0x2390 700#define R200_SE_VTX_ST_CLR_7_G 0x2394 701#define R200_SE_VTX_ST_CLR_7_B 0x2398 702#define R200_SE_VTX_ST_CLR_7_A 0x239c 703#define R200_SE_VTX_ST_TEX_0_S 0x23a0 704#define R200_SE_VTX_ST_TEX_0_T 0x23a4 705#define R200_SE_VTX_ST_TEX_0_R 0x23a8 706#define R200_SE_VTX_ST_TEX_0_Q 0x23ac 707#define R200_SE_VTX_ST_TEX_1_S 0x23b0 708#define R200_SE_VTX_ST_TEX_1_T 0x23b4 709#define R200_SE_VTX_ST_TEX_1_R 0x23b8 710#define R200_SE_VTX_ST_TEX_1_Q 0x23bc 711#define R200_SE_VTX_ST_TEX_2_S 0x23c0 712#define R200_SE_VTX_ST_TEX_2_T 0x23c4 713#define R200_SE_VTX_ST_TEX_2_R 0x23c8 714#define R200_SE_VTX_ST_TEX_2_Q 0x23cc 715#define R200_SE_VTX_ST_TEX_3_S 0x23d0 716#define R200_SE_VTX_ST_TEX_3_T 0x23d4 717#define R200_SE_VTX_ST_TEX_3_R 0x23d8 718#define R200_SE_VTX_ST_TEX_3_Q 0x23dc 719#define R200_SE_VTX_ST_TEX_4_S 0x23e0 720#define R200_SE_VTX_ST_TEX_4_T 0x23e4 721#define R200_SE_VTX_ST_TEX_4_R 0x23e8 722#define R200_SE_VTX_ST_TEX_4_Q 0x23ec 723#define R200_SE_VTX_ST_TEX_5_S 0x23f0 724#define R200_SE_VTX_ST_TEX_5_T 0x23f4 725#define R200_SE_VTX_ST_TEX_5_R 0x23f8 726#define R200_SE_VTX_ST_TEX_5_Q 0x23fc 727#define R200_SE_VTX_ST_PNT_SPRT_SZ 0x2400 728#define R200_SE_VTX_ST_DISC_FOG 0x2404 729#define R200_SE_VTX_ST_SHININESS_0 0x2408 730#define R200_SE_VTX_ST_SHININESS_1 0x240c 731#define R200_SE_VTX_ST_BLND_WT_0 0x2410 732#define R200_SE_VTX_ST_BLND_WT_1 0x2414 733#define R200_SE_VTX_ST_BLND_WT_2 0x2418 734#define R200_SE_VTX_ST_BLND_WT_3 0x241c 735#define R200_SE_VTX_ST_POS_1_X 0x2420 736#define R200_SE_VTX_ST_POS_1_Y 0x2424 737#define R200_SE_VTX_ST_POS_1_Z 0x2428 738#define R200_SE_VTX_ST_POS_1_W 0x242c 739#define R200_SE_VTX_ST_NORM_1_X 0x2430 740#define R200_SE_VTX_ST_NORM_1_Y 0x2434 741#define R200_SE_VTX_ST_NORM_1_Z 0x2438 742#define R200_SE_VTX_ST_USR_CLR_0_R 0x2440 743#define R200_SE_VTX_ST_USR_CLR_0_G 0x2444 744#define R200_SE_VTX_ST_USR_CLR_0_B 0x2448 745#define R200_SE_VTX_ST_USR_CLR_0_A 0x244c 746#define R200_SE_VTX_ST_USR_CLR_1_R 0x2450 747#define R200_SE_VTX_ST_USR_CLR_1_G 0x2454 748#define R200_SE_VTX_ST_USR_CLR_1_B 0x2458 749#define R200_SE_VTX_ST_USR_CLR_1_A 0x245c 750#define R200_SE_VTX_ST_CLR_0_PKD 0x2460 751#define R200_SE_VTX_ST_CLR_1_PKD 0x2464 752#define R200_SE_VTX_ST_CLR_2_PKD 0x2468 753#define R200_SE_VTX_ST_CLR_3_PKD 0x246c 754#define R200_SE_VTX_ST_CLR_4_PKD 0x2470 755#define R200_SE_VTX_ST_CLR_5_PKD 0x2474 756#define R200_SE_VTX_ST_CLR_6_PKD 0x2478 757#define R200_SE_VTX_ST_CLR_7_PKD 0x247c 758#define R200_SE_VTX_ST_POS_0_X_2 0x2480 759#define R200_SE_VTX_ST_POS_0_Y_2 0x2484 760#define R200_SE_VTX_ST_PAR_CLR_LD 0x2488 761#define R200_SE_VTX_ST_USR_CLR_PKD 0x248c 762#define R200_SE_VTX_ST_POS_0_X_3 0x2490 763#define R200_SE_VTX_ST_POS_0_Y_3 0x2494 764#define R200_SE_VTX_ST_POS_0_Z_3 0x2498 765#define R200_SE_VTX_ST_END_OF_PKT 0x249c 766/* gap */ 767#define R200_RE_POINTSIZE 0x2648 768#define R200_POINTSIZE_SHIFT 0 769#define R200_MAXPOINTSIZE_SHIFT 16 770/* gap */ 771#define R200_RE_TOP_LEFT 0x26c0 772#define R200_RE_LEFT_SHIFT 0 773#define R200_RE_TOP_SHIFT 16 774#define R200_RE_MISC 0x26c4 775#define R200_STIPPLE_COORD_MASK 0x1f 776#define R200_STIPPLE_X_OFFSET_SHIFT 0 777#define R200_STIPPLE_X_OFFSET_MASK (0x1f << 0) 778#define R200_STIPPLE_Y_OFFSET_SHIFT 8 779#define R200_STIPPLE_Y_OFFSET_MASK (0x1f << 8) 780#define R200_STIPPLE_LITTLE_BIT_ORDER (0 << 16) 781#define R200_STIPPLE_BIG_BIT_ORDER (1 << 16) 782/* gap */ 783#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 784#define R200_EXCLUSIVE_SCISSOR_0 0x01000000 785#define R200_EXCLUSIVE_SCISSOR_1 0x02000000 786#define R200_EXCLUSIVE_SCISSOR_2 0x04000000 787#define R200_SCISSOR_ENABLE_0 0x10000000 788#define R200_SCISSOR_ENABLE_1 0x20000000 789#define R200_SCISSOR_ENABLE_2 0x40000000 790/* gap */ 791#define R200_PP_TXFILTER_0 0x2c00 792#define R200_MAG_FILTER_NEAREST (0 << 0) 793#define R200_MAG_FILTER_LINEAR (1 << 0) 794#define R200_MAG_FILTER_MASK (1 << 0) 795#define R200_MIN_FILTER_NEAREST (0 << 1) 796#define R200_MIN_FILTER_LINEAR (1 << 1) 797#define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 798#define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 799#define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 800#define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 801#define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) 802#define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) 803#define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 804#define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 805#define R200_MIN_FILTER_MASK (15 << 1) 806#define R200_MAX_ANISO_1_TO_1 (0 << 5) 807#define R200_MAX_ANISO_2_TO_1 (1 << 5) 808#define R200_MAX_ANISO_4_TO_1 (2 << 5) 809#define R200_MAX_ANISO_8_TO_1 (3 << 5) 810#define R200_MAX_ANISO_16_TO_1 (4 << 5) 811#define R200_MAX_ANISO_MASK (7 << 5) 812#define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) 813#define R200_MAX_MIP_LEVEL_SHIFT 16 814#define R200_YUV_TO_RGB (1 << 20) 815#define R200_YUV_TEMPERATURE_COOL (0 << 21) 816#define R200_YUV_TEMPERATURE_HOT (1 << 21) 817#define R200_YUV_TEMPERATURE_MASK (1 << 21) 818#define R200_WRAPEN_S (1 << 22) 819#define R200_CLAMP_S_WRAP (0 << 23) 820#define R200_CLAMP_S_MIRROR (1 << 23) 821#define R200_CLAMP_S_CLAMP_LAST (2 << 23) 822#define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 823#define R200_CLAMP_S_CLAMP_BORDER (4 << 23) 824#define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 825#define R200_CLAMP_S_CLAMP_GL (6 << 23) 826#define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 827#define R200_CLAMP_S_MASK (7 << 23) 828#define R200_WRAPEN_T (1 << 26) 829#define R200_CLAMP_T_WRAP (0 << 27) 830#define R200_CLAMP_T_MIRROR (1 << 27) 831#define R200_CLAMP_T_CLAMP_LAST (2 << 27) 832#define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 833#define R200_CLAMP_T_CLAMP_BORDER (4 << 27) 834#define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 835#define R200_CLAMP_T_CLAMP_GL (6 << 27) 836#define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 837#define R200_CLAMP_T_MASK (7 << 27) 838#define R200_KILL_LT_ZERO (1 << 30) 839#define R200_BORDER_MODE_OGL (0 << 31) 840#define R200_BORDER_MODE_D3D (1 << 31) 841#define R200_PP_TXFORMAT_0 0x2c04 842#define R200_TXFORMAT_I8 (0 << 0) 843#define R200_TXFORMAT_AI88 (1 << 0) 844#define R200_TXFORMAT_RGB332 (2 << 0) 845#define R200_TXFORMAT_ARGB1555 (3 << 0) 846#define R200_TXFORMAT_RGB565 (4 << 0) 847#define R200_TXFORMAT_ARGB4444 (5 << 0) 848#define R200_TXFORMAT_ARGB8888 (6 << 0) 849#define R200_TXFORMAT_RGBA8888 (7 << 0) 850#define R200_TXFORMAT_Y8 (8 << 0) 851#define R200_TXFORMAT_AVYU4444 (9 << 0) 852#define R200_TXFORMAT_VYUY422 (10 << 0) 853#define R200_TXFORMAT_YVYU422 (11 << 0) 854#define R200_TXFORMAT_DXT1 (12 << 0) 855#define R200_TXFORMAT_DXT23 (14 << 0) 856#define R200_TXFORMAT_DXT45 (15 << 0) 857#define R200_TXFORMAT_DVDU88 (18 << 0) 858#define R200_TXFORMAT_LDVDU655 (19 << 0) 859#define R200_TXFORMAT_LDVDU8888 (20 << 0) 860#define R200_TXFORMAT_GR1616 (21 << 0) 861#define R200_TXFORMAT_ABGR8888 (22 << 0) 862#define R200_TXFORMAT_BGR111110 (23 << 0) 863#define R200_TXFORMAT_FORMAT_MASK (31 << 0) 864#define R200_TXFORMAT_FORMAT_SHIFT 0 865#define R200_TXFORMAT_APPLE_YUV (1 << 5) 866#define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) 867#define R200_TXFORMAT_NON_POWER2 (1 << 7) 868#define R200_TXFORMAT_WIDTH_MASK (15 << 8) 869#define R200_TXFORMAT_WIDTH_SHIFT 8 870#define R200_TXFORMAT_HEIGHT_MASK (15 << 12) 871#define R200_TXFORMAT_HEIGHT_SHIFT 12 872#define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ 873#define R200_TXFORMAT_F5_WIDTH_SHIFT 16 874#define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) 875#define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 876#define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 877#define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 878#define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 879#define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) 880#define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) 881#define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) 882#define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) 883#define R200_TXFORMAT_ST_ROUTE_SHIFT 24 884#define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27) 885#define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 886#define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 887#define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 888#define R200_PP_TXFORMAT_X_0 0x2c08 889#define R200_DEPTH_LOG2_MASK (0xf << 0) 890#define R200_DEPTH_LOG2_SHIFT 0 891#define R200_VOLUME_FILTER_SHIFT 4 892#define R200_VOLUME_FILTER_MASK (1 << 4) 893#define R200_VOLUME_FILTER_NEAREST (0 << 4) 894#define R200_VOLUME_FILTER_LINEAR (1 << 4) 895#define R200_WRAPEN_Q (1 << 8) 896#define R200_CLAMP_Q_WRAP (0 << 9) 897#define R200_CLAMP_Q_MIRROR (1 << 9) 898#define R200_CLAMP_Q_CLAMP_LAST (2 << 9) 899#define R200_CLAMP_Q_MIRROR_CLAMP_LAST (3 << 9) 900#define R200_CLAMP_Q_CLAMP_BORDER (4 << 9) 901#define R200_CLAMP_Q_MIRROR_CLAMP_BORDER (5 << 9) 902#define R200_CLAMP_Q_CLAMP_GL (6 << 9) 903#define R200_CLAMP_Q_MIRROR_CLAMP_GL (7 << 9) 904#define R200_CLAMP_Q_MASK (7 << 9) 905#define R200_MIN_MIP_LEVEL_MASK (0xff << 12) 906#define R200_MIN_MIP_LEVEL_SHIFT 12 907#define R200_TEXCOORD_NONPROJ (0 << 16) 908#define R200_TEXCOORD_CUBIC_ENV (1 << 16) 909#define R200_TEXCOORD_VOLUME (2 << 16) 910#define R200_TEXCOORD_PROJ (3 << 16) 911#define R200_TEXCOORD_DEPTH (4 << 16) 912#define R200_TEXCOORD_1D_PROJ (5 << 16) 913#define R200_TEXCOORD_1D (6 << 16) 914#define R200_TEXCOORD_ZERO (7 << 16) 915#define R200_TEXCOORD_MASK (7 << 16) 916#define R200_LOD_BIAS_MASK (0xfff80000) 917#define R200_LOD_BIAS_SHIFT 19 918#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ 919#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ 920#define R200_PP_BORDER_COLOR_0 0x2c14 921#define R200_PP_CUBIC_FACES_0 0x2c18 922#define R200_FACE_WIDTH_1_SHIFT 0 923#define R200_FACE_HEIGHT_1_SHIFT 4 924#define R200_FACE_WIDTH_1_MASK (0xf << 0) 925#define R200_FACE_HEIGHT_1_MASK (0xf << 4) 926#define R200_FACE_WIDTH_2_SHIFT 8 927#define R200_FACE_HEIGHT_2_SHIFT 12 928#define R200_FACE_WIDTH_2_MASK (0xf << 8) 929#define R200_FACE_HEIGHT_2_MASK (0xf << 12) 930#define R200_FACE_WIDTH_3_SHIFT 16 931#define R200_FACE_HEIGHT_3_SHIFT 20 932#define R200_FACE_WIDTH_3_MASK (0xf << 16) 933#define R200_FACE_HEIGHT_3_MASK (0xf << 20) 934#define R200_FACE_WIDTH_4_SHIFT 24 935#define R200_FACE_HEIGHT_4_SHIFT 28 936#define R200_FACE_WIDTH_4_MASK (0xf << 24) 937#define R200_FACE_HEIGHT_4_MASK (0xf << 28) 938#define R200_PP_TXMULTI_CTL_0 0x2c1c /* name from ddx, rest RE... */ 939#define R200_PASS1_TXFORMAT_LOOKUP_DISABLE (1 << 0) 940#define R200_PASS1_TEXCOORD_NONPROJ (0 << 1) 941#define R200_PASS1_TEXCOORD_CUBIC_ENV (1 << 1) 942#define R200_PASS1_TEXCOORD_VOLUME (2 << 1) 943#define R200_PASS1_TEXCOORD_PROJ (3 << 1) 944#define R200_PASS1_TEXCOORD_DEPTH (4 << 1) 945#define R200_PASS1_TEXCOORD_1D_PROJ (5 << 1) 946#define R200_PASS1_TEXCOORD_1D (6 << 1) /* pass1 texcoords only */ 947#define R200_PASS1_TEXCOORD_ZERO (7 << 1) /* verifed for 2d targets! */ 948#define R200_PASS1_TEXCOORD_MASK (7 << 1) /* assumed same values as for pass2 */ 949#define R200_PASS1_ST_ROUTE_STQ0 (0 << 4) 950#define R200_PASS1_ST_ROUTE_STQ1 (1 << 4) 951#define R200_PASS1_ST_ROUTE_STQ2 (2 << 4) 952#define R200_PASS1_ST_ROUTE_STQ3 (3 << 4) 953#define R200_PASS1_ST_ROUTE_STQ4 (4 << 4) 954#define R200_PASS1_ST_ROUTE_STQ5 (5 << 4) 955#define R200_PASS1_ST_ROUTE_MASK (7 << 4) 956#define R200_PASS1_ST_ROUTE_SHIFT (4) 957#define R200_PASS2_COORDS_REG_0 (2 << 24) 958#define R200_PASS2_COORDS_REG_1 (3 << 24) 959#define R200_PASS2_COORDS_REG_2 (4 << 24) 960#define R200_PASS2_COORDS_REG_3 (5 << 24) 961#define R200_PASS2_COORDS_REG_4 (6 << 24) 962#define R200_PASS2_COORDS_REG_5 (7 << 24) 963#define R200_PASS2_COORDS_REG_MASK (0x7 << 24) 964#define R200_PASS2_COORDS_REG_SHIFT (24) 965#define R200_PP_TXFILTER_1 0x2c20 966#define R200_PP_TXFORMAT_1 0x2c24 967#define R200_PP_TXFORMAT_X_1 0x2c28 968#define R200_PP_TXSIZE_1 0x2c2c 969#define R200_PP_TXPITCH_1 0x2c30 970#define R200_PP_BORDER_COLOR_1 0x2c34 971#define R200_PP_CUBIC_FACES_1 0x2c38 972#define R200_PP_TXMULTI_CTL_1 0x2c3c 973#define R200_PP_TXFILTER_2 0x2c40 974#define R200_PP_TXFORMAT_2 0x2c44 975#define R200_PP_TXSIZE_2 0x2c4c 976#define R200_PP_TXFORMAT_X_2 0x2c48 977#define R200_PP_TXPITCH_2 0x2c50 978#define R200_PP_BORDER_COLOR_2 0x2c54 979#define R200_PP_CUBIC_FACES_2 0x2c58 980#define R200_PP_TXMULTI_CTL_2 0x2c5c 981#define R200_PP_TXFILTER_3 0x2c60 982#define R200_PP_TXFORMAT_3 0x2c64 983#define R200_PP_TXSIZE_3 0x2c6c 984#define R200_PP_TXFORMAT_X_3 0x2c68 985#define R200_PP_TXPITCH_3 0x2c70 986#define R200_PP_BORDER_COLOR_3 0x2c74 987#define R200_PP_CUBIC_FACES_3 0x2c78 988#define R200_PP_TXMULTI_CTL_3 0x2c7c 989#define R200_PP_TXFILTER_4 0x2c80 990#define R200_PP_TXFORMAT_4 0x2c84 991#define R200_PP_TXSIZE_4 0x2c8c 992#define R200_PP_TXFORMAT_X_4 0x2c88 993#define R200_PP_TXPITCH_4 0x2c90 994#define R200_PP_BORDER_COLOR_4 0x2c94 995#define R200_PP_CUBIC_FACES_4 0x2c98 996#define R200_PP_TXMULTI_CTL_4 0x2c9c 997#define R200_PP_TXFILTER_5 0x2ca0 998#define R200_PP_TXFORMAT_5 0x2ca4 999#define R200_PP_TXSIZE_5 0x2cac 1000#define R200_PP_TXFORMAT_X_5 0x2ca8 1001#define R200_PP_TXPITCH_5 0x2cb0 1002#define R200_PP_BORDER_COLOR_5 0x2cb4 1003#define R200_PP_CUBIC_FACES_5 0x2cb8 1004#define R200_PP_TXMULTI_CTL_5 0x2cbc 1005/* gap */ 1006#define R200_PP_CNTL_X 0x2cc4 /* Reveree engineered from fglrx */ 1007#define R200_PPX_TEX_0_ENABLE (1 << 0) 1008#define R200_PPX_TEX_1_ENABLE (1 << 1) 1009#define R200_PPX_TEX_2_ENABLE (1 << 2) 1010#define R200_PPX_TEX_3_ENABLE (1 << 3) 1011#define R200_PPX_TEX_4_ENABLE (1 << 4) 1012#define R200_PPX_TEX_5_ENABLE (1 << 5) 1013#define R200_PPX_TEX_ENABLE_MASK (0x3f << 0) 1014#define R200_PPX_OUTPUT_REG_0 (1 << 6) 1015#define R200_PPX_OUTPUT_REG_1 (1 << 7) 1016#define R200_PPX_OUTPUT_REG_2 (1 << 8) 1017#define R200_PPX_OUTPUT_REG_3 (1 << 9) 1018#define R200_PPX_OUTPUT_REG_4 (1 << 10) 1019#define R200_PPX_OUTPUT_REG_5 (1 << 11) 1020#define R200_PPX_OUTPUT_REG_MASK (0x3f << 6) 1021#define R200_PPX_OUTPUT_REG_0_SHIFT (6) 1022#define R200_PPX_PFS_INST0_ENABLE (1 << 12) 1023#define R200_PPX_PFS_INST1_ENABLE (1 << 13) 1024#define R200_PPX_PFS_INST2_ENABLE (1 << 14) 1025#define R200_PPX_PFS_INST3_ENABLE (1 << 15) 1026#define R200_PPX_PFS_INST4_ENABLE (1 << 16) 1027#define R200_PPX_PFS_INST5_ENABLE (1 << 17) 1028#define R200_PPX_PFS_INST6_ENABLE (1 << 18) 1029#define R200_PPX_PFS_INST7_ENABLE (1 << 19) 1030#define R200_PPX_PFS_INST_ENABLE_MASK (0xff << 12) 1031#define R200_PPX_FPS_INST0_ENABLE_SHIFT (12) 1032/* gap */ 1033#define R200_PP_TRI_PERF 0x2cf8 1034#define R200_TRI_CUTOFF_MASK (0x1f << 0) 1035#define R200_PP_PERF_CNTL 0x2cfc 1036#define R200_PP_TXOFFSET_0 0x2d00 1037#define R200_TXO_ENDIAN_NO_SWAP (0 << 0) 1038#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) 1039#define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) 1040#define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 1041#define R200_TXO_MACRO_TILE (1 << 2) 1042#define R200_TXO_MICRO_TILE (1 << 3) 1043#define R200_TXO_OFFSET_MASK 0xffffffe0 1044#define R200_TXO_OFFSET_SHIFT 5 1045#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1046#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1047#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1048#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1049#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1050#define R200_PP_TXOFFSET_1 0x2d18 1051#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1052#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1053#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1054#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1055#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1056#define R200_PP_TXOFFSET_2 0x2d30 1057#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1058#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1059#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1060#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1061#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1062#define R200_PP_TXOFFSET_3 0x2d48 1063#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1064#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1065#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1066#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1067#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1068#define R200_PP_TXOFFSET_4 0x2d60 1069#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1070#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1071#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1072#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1073#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1074#define R200_PP_TXOFFSET_5 0x2d78 1075#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1076#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1077#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1078#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1079#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1080/* gap */ 1081#define R200_PP_TAM_DEBUG3 0x2d9c 1082/* gap */ 1083#define R200_PP_TFACTOR_0 0x2ee0 1084#define R200_PP_TFACTOR_1 0x2ee4 1085#define R200_PP_TFACTOR_2 0x2ee8 1086#define R200_PP_TFACTOR_3 0x2eec 1087#define R200_PP_TFACTOR_4 0x2ef0 1088#define R200_PP_TFACTOR_5 0x2ef4 1089#define R200_PP_TFACTOR_6 0x2ef8 1090#define R200_PP_TFACTOR_7 0x2efc 1091#define R200_PP_TXCBLEND_0 0x2f00 1092#define R200_TXC_ARG_A_ZERO (0) 1093#define R200_TXC_ARG_A_CURRENT_COLOR (2) 1094#define R200_TXC_ARG_A_CURRENT_ALPHA (3) 1095#define R200_TXC_ARG_A_DIFFUSE_COLOR (4) 1096#define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) 1097#define R200_TXC_ARG_A_SPECULAR_COLOR (6) 1098#define R200_TXC_ARG_A_SPECULAR_ALPHA (7) 1099#define R200_TXC_ARG_A_TFACTOR_COLOR (8) 1100#define R200_TXC_ARG_A_TFACTOR_ALPHA (9) 1101#define R200_TXC_ARG_A_R0_COLOR (10) 1102#define R200_TXC_ARG_A_R0_ALPHA (11) 1103#define R200_TXC_ARG_A_R1_COLOR (12) 1104#define R200_TXC_ARG_A_R1_ALPHA (13) 1105#define R200_TXC_ARG_A_R2_COLOR (14) 1106#define R200_TXC_ARG_A_R2_ALPHA (15) 1107#define R200_TXC_ARG_A_R3_COLOR (16) 1108#define R200_TXC_ARG_A_R3_ALPHA (17) 1109#define R200_TXC_ARG_A_R4_COLOR (18) 1110#define R200_TXC_ARG_A_R4_ALPHA (19) 1111#define R200_TXC_ARG_A_R5_COLOR (20) 1112#define R200_TXC_ARG_A_R5_ALPHA (21) 1113#define R200_TXC_ARG_A_TFACTOR1_COLOR (26) 1114#define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) 1115#define R200_TXC_ARG_A_MASK (31 << 0) 1116#define R200_TXC_ARG_A_SHIFT 0 1117#define R200_TXC_ARG_B_ZERO (0<<5) 1118#define R200_TXC_ARG_B_CURRENT_COLOR (2<<5) 1119#define R200_TXC_ARG_B_CURRENT_ALPHA (3<<5) 1120#define R200_TXC_ARG_B_DIFFUSE_COLOR (4<<5) 1121#define R200_TXC_ARG_B_DIFFUSE_ALPHA (5<<5) 1122#define R200_TXC_ARG_B_SPECULAR_COLOR (6<<5) 1123#define R200_TXC_ARG_B_SPECULAR_ALPHA (7<<5) 1124#define R200_TXC_ARG_B_TFACTOR_COLOR (8<<5) 1125#define R200_TXC_ARG_B_TFACTOR_ALPHA (9<<5) 1126#define R200_TXC_ARG_B_R0_COLOR (10<<5) 1127#define R200_TXC_ARG_B_R0_ALPHA (11<<5) 1128#define R200_TXC_ARG_B_R1_COLOR (12<<5) 1129#define R200_TXC_ARG_B_R1_ALPHA (13<<5) 1130#define R200_TXC_ARG_B_R2_COLOR (14<<5) 1131#define R200_TXC_ARG_B_R2_ALPHA (15<<5) 1132#define R200_TXC_ARG_B_R3_COLOR (16<<5) 1133#define R200_TXC_ARG_B_R3_ALPHA (17<<5) 1134#define R200_TXC_ARG_B_R4_COLOR (18<<5) 1135#define R200_TXC_ARG_B_R4_ALPHA (19<<5) 1136#define R200_TXC_ARG_B_R5_COLOR (20<<5) 1137#define R200_TXC_ARG_B_R5_ALPHA (21<<5) 1138#define R200_TXC_ARG_B_TFACTOR1_COLOR (26<<5) 1139#define R200_TXC_ARG_B_TFACTOR1_ALPHA (27<<5) 1140#define R200_TXC_ARG_B_MASK (31 << 5) 1141#define R200_TXC_ARG_B_SHIFT 5 1142#define R200_TXC_ARG_C_ZERO (0<<10) 1143#define R200_TXC_ARG_C_CURRENT_COLOR (2<<10) 1144#define R200_TXC_ARG_C_CURRENT_ALPHA (3<<10) 1145#define R200_TXC_ARG_C_DIFFUSE_COLOR (4<<10) 1146#define R200_TXC_ARG_C_DIFFUSE_ALPHA (5<<10) 1147#define R200_TXC_ARG_C_SPECULAR_COLOR (6<<10) 1148#define R200_TXC_ARG_C_SPECULAR_ALPHA (7<<10) 1149#define R200_TXC_ARG_C_TFACTOR_COLOR (8<<10) 1150#define R200_TXC_ARG_C_TFACTOR_ALPHA (9<<10) 1151#define R200_TXC_ARG_C_R0_COLOR (10<<10) 1152#define R200_TXC_ARG_C_R0_ALPHA (11<<10) 1153#define R200_TXC_ARG_C_R1_COLOR (12<<10) 1154#define R200_TXC_ARG_C_R1_ALPHA (13<<10) 1155#define R200_TXC_ARG_C_R2_COLOR (14<<10) 1156#define R200_TXC_ARG_C_R2_ALPHA (15<<10) 1157#define R200_TXC_ARG_C_R3_COLOR (16<<10) 1158#define R200_TXC_ARG_C_R3_ALPHA (17<<10) 1159#define R200_TXC_ARG_C_R4_COLOR (18<<10) 1160#define R200_TXC_ARG_C_R4_ALPHA (19<<10) 1161#define R200_TXC_ARG_C_R5_COLOR (20<<10) 1162#define R200_TXC_ARG_C_R5_ALPHA (21<<10) 1163#define R200_TXC_ARG_C_TFACTOR1_COLOR (26<<10) 1164#define R200_TXC_ARG_C_TFACTOR1_ALPHA (27<<10) 1165#define R200_TXC_ARG_C_MASK (31 << 10) 1166#define R200_TXC_ARG_C_SHIFT 10 1167#define R200_TXC_COMP_ARG_A (1 << 16) 1168#define R200_TXC_COMP_ARG_A_SHIFT (16) 1169#define R200_TXC_BIAS_ARG_A (1 << 17) 1170#define R200_TXC_SCALE_ARG_A (1 << 18) 1171#define R200_TXC_NEG_ARG_A (1 << 19) 1172#define R200_TXC_COMP_ARG_B (1 << 20) 1173#define R200_TXC_COMP_ARG_B_SHIFT (20) 1174#define R200_TXC_BIAS_ARG_B (1 << 21) 1175#define R200_TXC_SCALE_ARG_B (1 << 22) 1176#define R200_TXC_NEG_ARG_B (1 << 23) 1177#define R200_TXC_COMP_ARG_C (1 << 24) 1178#define R200_TXC_COMP_ARG_C_SHIFT (24) 1179#define R200_TXC_BIAS_ARG_C (1 << 25) 1180#define R200_TXC_SCALE_ARG_C (1 << 26) 1181#define R200_TXC_NEG_ARG_C (1 << 27) 1182#define R200_TXC_OP_MADD (0 << 28) 1183#define R200_TXC_OP_CND0 (2 << 28) 1184#define R200_TXC_OP_LERP (3 << 28) 1185#define R200_TXC_OP_DOT3 (4 << 28) 1186#define R200_TXC_OP_DOT4 (5 << 28) 1187#define R200_TXC_OP_CONDITIONAL (6 << 28) 1188#define R200_TXC_OP_DOT2_ADD (7 << 28) 1189#define R200_TXC_OP_MASK (7 << 28) 1190#define R200_PP_TXCBLEND2_0 0x2f04 1191#define R200_TXC_TFACTOR_SEL_SHIFT 0 1192#define R200_TXC_TFACTOR_SEL_MASK 0x7 1193#define R200_TXC_TFACTOR1_SEL_SHIFT 4 1194#define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) 1195#define R200_TXC_SCALE_SHIFT 8 1196#define R200_TXC_SCALE_MASK (7 << 8) 1197#define R200_TXC_SCALE_1X (0 << 8) 1198#define R200_TXC_SCALE_2X (1 << 8) 1199#define R200_TXC_SCALE_4X (2 << 8) 1200#define R200_TXC_SCALE_8X (3 << 8) 1201#define R200_TXC_SCALE_INV2 (5 << 8) 1202#define R200_TXC_SCALE_INV4 (6 << 8) 1203#define R200_TXC_SCALE_INV8 (7 << 8) 1204#define R200_TXC_CLAMP_SHIFT 12 1205#define R200_TXC_CLAMP_MASK (3 << 12) 1206#define R200_TXC_CLAMP_WRAP (0 << 12) 1207#define R200_TXC_CLAMP_0_1 (1 << 12) 1208#define R200_TXC_CLAMP_8_8 (2 << 12) 1209#define R200_TXC_OUTPUT_REG_SHIFT 16 1210#define R200_TXC_OUTPUT_REG_MASK (7 << 16) 1211#define R200_TXC_OUTPUT_REG_NONE (0 << 16) 1212#define R200_TXC_OUTPUT_REG_R0 (1 << 16) 1213#define R200_TXC_OUTPUT_REG_R1 (2 << 16) 1214#define R200_TXC_OUTPUT_REG_R2 (3 << 16) 1215#define R200_TXC_OUTPUT_REG_R3 (4 << 16) 1216#define R200_TXC_OUTPUT_REG_R4 (5 << 16) 1217#define R200_TXC_OUTPUT_REG_R5 (6 << 16) 1218#define R200_TXC_OUTPUT_MASK_MASK (7 << 20) 1219#define R200_TXC_OUTPUT_MASK_RGB (0 << 20) 1220#define R200_TXC_OUTPUT_MASK_RG (1 << 20) 1221#define R200_TXC_OUTPUT_MASK_RB (2 << 20) 1222#define R200_TXC_OUTPUT_MASK_R (3 << 20) 1223#define R200_TXC_OUTPUT_MASK_GB (4 << 20) 1224#define R200_TXC_OUTPUT_MASK_G (5 << 20) 1225#define R200_TXC_OUTPUT_MASK_B (6 << 20) 1226#define R200_TXC_OUTPUT_MASK_NONE (7 << 20) 1227#define R200_TXC_REPL_NORMAL 0 1228#define R200_TXC_REPL_RED 1 1229#define R200_TXC_REPL_GREEN 2 1230#define R200_TXC_REPL_BLUE 3 1231#define R200_TXC_REPL_ARG_A_SHIFT 26 1232#define R200_TXC_REPL_ARG_A_MASK (3 << 26) 1233#define R200_TXC_REPL_ARG_B_SHIFT 28 1234#define R200_TXC_REPL_ARG_B_MASK (3 << 28) 1235#define R200_TXC_REPL_ARG_C_SHIFT 30 1236#define R200_TXC_REPL_ARG_C_MASK (3 << 30) 1237#define R200_PP_TXABLEND_0 0x2f08 1238#define R200_TXA_ARG_A_ZERO (0) 1239#define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ 1240#define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ 1241#define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) 1242#define R200_TXA_ARG_A_DIFFUSE_BLUE (5) 1243#define R200_TXA_ARG_A_SPECULAR_ALPHA (6) 1244#define R200_TXA_ARG_A_SPECULAR_BLUE (7) 1245#define R200_TXA_ARG_A_TFACTOR_ALPHA (8) 1246#define R200_TXA_ARG_A_TFACTOR_BLUE (9) 1247#define R200_TXA_ARG_A_R0_ALPHA (10) 1248#define R200_TXA_ARG_A_R0_BLUE (11) 1249#define R200_TXA_ARG_A_R1_ALPHA (12) 1250#define R200_TXA_ARG_A_R1_BLUE (13) 1251#define R200_TXA_ARG_A_R2_ALPHA (14) 1252#define R200_TXA_ARG_A_R2_BLUE (15) 1253#define R200_TXA_ARG_A_R3_ALPHA (16) 1254#define R200_TXA_ARG_A_R3_BLUE (17) 1255#define R200_TXA_ARG_A_R4_ALPHA (18) 1256#define R200_TXA_ARG_A_R4_BLUE (19) 1257#define R200_TXA_ARG_A_R5_ALPHA (20) 1258#define R200_TXA_ARG_A_R5_BLUE (21) 1259#define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) 1260#define R200_TXA_ARG_A_TFACTOR1_BLUE (27) 1261#define R200_TXA_ARG_A_MASK (31 << 0) 1262#define R200_TXA_ARG_A_SHIFT 0 1263#define R200_TXA_ARG_B_ZERO (0<<5) 1264#define R200_TXA_ARG_B_CURRENT_ALPHA (2<<5) /* guess */ 1265#define R200_TXA_ARG_B_CURRENT_BLUE (3<<5) /* guess */ 1266#define R200_TXA_ARG_B_DIFFUSE_ALPHA (4<<5) 1267#define R200_TXA_ARG_B_DIFFUSE_BLUE (5<<5) 1268#define R200_TXA_ARG_B_SPECULAR_ALPHA (6<<5) 1269#define R200_TXA_ARG_B_SPECULAR_BLUE (7<<5) 1270#define R200_TXA_ARG_B_TFACTOR_ALPHA (8<<5) 1271#define R200_TXA_ARG_B_TFACTOR_BLUE (9<<5) 1272#define R200_TXA_ARG_B_R0_ALPHA (10<<5) 1273#define R200_TXA_ARG_B_R0_BLUE (11<<5) 1274#define R200_TXA_ARG_B_R1_ALPHA (12<<5) 1275#define R200_TXA_ARG_B_R1_BLUE (13<<5) 1276#define R200_TXA_ARG_B_R2_ALPHA (14<<5) 1277#define R200_TXA_ARG_B_R2_BLUE (15<<5) 1278#define R200_TXA_ARG_B_R3_ALPHA (16<<5) 1279#define R200_TXA_ARG_B_R3_BLUE (17<<5) 1280#define R200_TXA_ARG_B_R4_ALPHA (18<<5) 1281#define R200_TXA_ARG_B_R4_BLUE (19<<5) 1282#define R200_TXA_ARG_B_R5_ALPHA (20<<5) 1283#define R200_TXA_ARG_B_R5_BLUE (21<<5) 1284#define R200_TXA_ARG_B_TFACTOR1_ALPHA (26<<5) 1285#define R200_TXA_ARG_B_TFACTOR1_BLUE (27<<5) 1286#define R200_TXA_ARG_B_MASK (31 << 5) 1287#define R200_TXA_ARG_B_SHIFT 5 1288#define R200_TXA_ARG_C_ZERO (0<<10) 1289#define R200_TXA_ARG_C_CURRENT_ALPHA (2<<10) /* guess */ 1290#define R200_TXA_ARG_C_CURRENT_BLUE (3<<10) /* guess */ 1291#define R200_TXA_ARG_C_DIFFUSE_ALPHA (4<<10) 1292#define R200_TXA_ARG_C_DIFFUSE_BLUE (5<<10) 1293#define R200_TXA_ARG_C_SPECULAR_ALPHA (6<<10) 1294#define R200_TXA_ARG_C_SPECULAR_BLUE (7<<10) 1295#define R200_TXA_ARG_C_TFACTOR_ALPHA (8<<10) 1296#define R200_TXA_ARG_C_TFACTOR_BLUE (9<<10) 1297#define R200_TXA_ARG_C_R0_ALPHA (10<<10) 1298#define R200_TXA_ARG_C_R0_BLUE (11<<10) 1299#define R200_TXA_ARG_C_R1_ALPHA (12<<10) 1300#define R200_TXA_ARG_C_R1_BLUE (13<<10) 1301#define R200_TXA_ARG_C_R2_ALPHA (14<<10) 1302#define R200_TXA_ARG_C_R2_BLUE (15<<10) 1303#define R200_TXA_ARG_C_R3_ALPHA (16<<10) 1304#define R200_TXA_ARG_C_R3_BLUE (17<<10) 1305#define R200_TXA_ARG_C_R4_ALPHA (18<<10) 1306#define R200_TXA_ARG_C_R4_BLUE (19<<10) 1307#define R200_TXA_ARG_C_R5_ALPHA (20<<10) 1308#define R200_TXA_ARG_C_R5_BLUE (21<<10) 1309#define R200_TXA_ARG_C_TFACTOR1_ALPHA (26<<10) 1310#define R200_TXA_ARG_C_TFACTOR1_BLUE (27<<10) 1311#define R200_TXA_ARG_C_MASK (31 << 10) 1312#define R200_TXA_ARG_C_SHIFT 10 1313#define R200_TXA_COMP_ARG_A (1 << 16) 1314#define R200_TXA_COMP_ARG_A_SHIFT (16) 1315#define R200_TXA_BIAS_ARG_A (1 << 17) 1316#define R200_TXA_SCALE_ARG_A (1 << 18) 1317#define R200_TXA_NEG_ARG_A (1 << 19) 1318#define R200_TXA_COMP_ARG_B (1 << 20) 1319#define R200_TXA_COMP_ARG_B_SHIFT (20) 1320#define R200_TXA_BIAS_ARG_B (1 << 21) 1321#define R200_TXA_SCALE_ARG_B (1 << 22) 1322#define R200_TXA_NEG_ARG_B (1 << 23) 1323#define R200_TXA_COMP_ARG_C (1 << 24) 1324#define R200_TXA_COMP_ARG_C_SHIFT (24) 1325#define R200_TXA_BIAS_ARG_C (1 << 25) 1326#define R200_TXA_SCALE_ARG_C (1 << 26) 1327#define R200_TXA_NEG_ARG_C (1 << 27) 1328#define R200_TXA_OP_MADD (0 << 28) 1329#define R200_TXA_OP_CND0 (2 << 28) 1330#define R200_TXA_OP_LERP (3 << 28) 1331#define R200_TXA_OP_CONDITIONAL (6 << 28) 1332#define R200_TXA_OP_MASK (7 << 28) 1333#define R200_PP_TXABLEND2_0 0x2f0c 1334#define R200_TXA_TFACTOR_SEL_SHIFT 0 1335#define R200_TXA_TFACTOR_SEL_MASK 0x7 1336#define R200_TXA_TFACTOR1_SEL_SHIFT 4 1337#define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) 1338#define R200_TXA_SCALE_SHIFT 8 1339#define R200_TXA_SCALE_MASK (7 << 8) 1340#define R200_TXA_SCALE_1X (0 << 8) 1341#define R200_TXA_SCALE_2X (1 << 8) 1342#define R200_TXA_SCALE_4X (2 << 8) 1343#define R200_TXA_SCALE_8X (3 << 8) 1344#define R200_TXA_SCALE_INV2 (5 << 8) 1345#define R200_TXA_SCALE_INV4 (6 << 8) 1346#define R200_TXA_SCALE_INV8 (7 << 8) 1347#define R200_TXA_CLAMP_SHIFT 12 1348#define R200_TXA_CLAMP_MASK (3 << 12) 1349#define R200_TXA_CLAMP_WRAP (0 << 12) 1350#define R200_TXA_CLAMP_0_1 (1 << 12) 1351#define R200_TXA_CLAMP_8_8 (2 << 12) 1352#define R200_TXA_OUTPUT_REG_SHIFT 16 1353#define R200_TXA_OUTPUT_REG_MASK (7 << 16) 1354#define R200_TXA_OUTPUT_REG_NONE (0 << 16) 1355#define R200_TXA_OUTPUT_REG_R0 (1 << 16) 1356#define R200_TXA_OUTPUT_REG_R1 (2 << 16) 1357#define R200_TXA_OUTPUT_REG_R2 (3 << 16) 1358#define R200_TXA_OUTPUT_REG_R3 (4 << 16) 1359#define R200_TXA_OUTPUT_REG_R4 (5 << 16) 1360#define R200_TXA_OUTPUT_REG_R5 (6 << 16) 1361#define R200_TXA_DOT_ALPHA (1 << 20) 1362#define R200_TXA_REPL_NORMAL 0 1363#define R200_TXA_REPL_RED 1 1364#define R200_TXA_REPL_GREEN 2 1365#define R200_TXA_REPL_ARG_A_SHIFT 26 1366#define R200_TXA_REPL_ARG_A_MASK (3 << 26) 1367#define R200_TXA_REPL_ARG_B_SHIFT 28 1368#define R200_TXA_REPL_ARG_B_MASK (3 << 28) 1369#define R200_TXA_REPL_ARG_C_SHIFT 30 1370#define R200_TXA_REPL_ARG_C_MASK (3 << 30) 1371#define R200_PP_TXCBLEND_1 0x2f10 1372#define R200_PP_TXCBLEND2_1 0x2f14 1373#define R200_PP_TXABLEND_1 0x2f18 1374#define R200_PP_TXABLEND2_1 0x2f1c 1375#define R200_PP_TXCBLEND_2 0x2f20 1376#define R200_PP_TXCBLEND2_2 0x2f24 1377#define R200_PP_TXABLEND_2 0x2f28 1378#define R200_PP_TXABLEND2_2 0x2f2c 1379#define R200_PP_TXCBLEND_3 0x2f30 1380#define R200_PP_TXCBLEND2_3 0x2f34 1381#define R200_PP_TXABLEND_3 0x2f38 1382#define R200_PP_TXABLEND2_3 0x2f3c 1383#define R200_PP_TXCBLEND_4 0x2f40 1384#define R200_PP_TXCBLEND2_4 0x2f44 1385#define R200_PP_TXABLEND_4 0x2f48 1386#define R200_PP_TXABLEND2_4 0x2f4c 1387#define R200_PP_TXCBLEND_5 0x2f50 1388#define R200_PP_TXCBLEND2_5 0x2f54 1389#define R200_PP_TXABLEND_5 0x2f58 1390#define R200_PP_TXABLEND2_5 0x2f5c 1391#define R200_PP_TXCBLEND_6 0x2f60 1392#define R200_PP_TXCBLEND2_6 0x2f64 1393#define R200_PP_TXABLEND_6 0x2f68 1394#define R200_PP_TXABLEND2_6 0x2f6c 1395#define R200_PP_TXCBLEND_7 0x2f70 1396#define R200_PP_TXCBLEND2_7 0x2f74 1397#define R200_PP_TXABLEND_7 0x2f78 1398#define R200_PP_TXABLEND2_7 0x2f7c 1399#define R200_PP_TXCBLEND_8 0x2f80 1400#define R200_PP_TXCBLEND2_8 0x2f84 1401#define R200_PP_TXABLEND_8 0x2f88 1402#define R200_PP_TXABLEND2_8 0x2f8c 1403#define R200_PP_TXCBLEND_9 0x2f90 1404#define R200_PP_TXCBLEND2_9 0x2f94 1405#define R200_PP_TXABLEND_9 0x2f98 1406#define R200_PP_TXABLEND2_9 0x2f9c 1407#define R200_PP_TXCBLEND_10 0x2fa0 1408#define R200_PP_TXCBLEND2_10 0x2fa4 1409#define R200_PP_TXABLEND_10 0x2fa8 1410#define R200_PP_TXABLEND2_10 0x2fac 1411#define R200_PP_TXCBLEND_11 0x2fb0 1412#define R200_PP_TXCBLEND2_11 0x2fb4 1413#define R200_PP_TXABLEND_11 0x2fb8 1414#define R200_PP_TXABLEND2_11 0x2fbc 1415#define R200_PP_TXCBLEND_12 0x2fc0 1416#define R200_PP_TXCBLEND2_12 0x2fc4 1417#define R200_PP_TXABLEND_12 0x2fc8 1418#define R200_PP_TXABLEND2_12 0x2fcc 1419#define R200_PP_TXCBLEND_13 0x2fd0 1420#define R200_PP_TXCBLEND2_13 0x2fd4 1421#define R200_PP_TXABLEND_13 0x2fd8 1422#define R200_PP_TXABLEND2_13 0x2fdc 1423#define R200_PP_TXCBLEND_14 0x2fe0 1424#define R200_PP_TXCBLEND2_14 0x2fe4 1425#define R200_PP_TXABLEND_14 0x2fe8 1426#define R200_PP_TXABLEND2_14 0x2fec 1427#define R200_PP_TXCBLEND_15 0x2ff0 1428#define R200_PP_TXCBLEND2_15 0x2ff4 1429#define R200_PP_TXABLEND_15 0x2ff8 1430#define R200_PP_TXABLEND2_15 0x2ffc 1431/* gap */ 1432#define R200_RB3D_BLENDCOLOR 0x3218 /* ARGB 8888 */ 1433#define R200_RB3D_ABLENDCNTL 0x321C /* see BLENDCTL */ 1434#define R200_RB3D_CBLENDCNTL 0x3220 /* see BLENDCTL */ 1435 1436 1437/* 1438 * Offsets in TCL vector state. NOTE: Hardwiring matrix positions. 1439 * Multiple contexts could collaberate to eliminate state bouncing. 1440 */ 1441#define R200_VS_LIGHT_AMBIENT_ADDR 0x00000028 1442#define R200_VS_LIGHT_DIFFUSE_ADDR 0x00000030 1443#define R200_VS_LIGHT_SPECULAR_ADDR 0x00000038 1444#define R200_VS_LIGHT_DIRPOS_ADDR 0x00000040 1445#define R200_VS_LIGHT_HWVSPOT_ADDR 0x00000048 1446#define R200_VS_LIGHT_ATTENUATION_ADDR 0x00000050 1447#define R200_VS_SPOT_DUAL_CONE 0x00000058 1448#define R200_VS_GLOBAL_AMBIENT_ADDR 0x0000005C 1449#define R200_VS_FOG_PARAM_ADDR 0x0000005D 1450#define R200_VS_EYE_VECTOR_ADDR 0x0000005E 1451#define R200_VS_UCP_ADDR 0x00000060 1452#define R200_VS_PNT_SPRITE_VPORT_SCALE 0x00000068 1453#define R200_VS_MATRIX_0_MV 0x00000080 1454#define R200_VS_MATRIX_1_INV_MV 0x00000084 1455#define R200_VS_MATRIX_2_MVP 0x00000088 1456#define R200_VS_MATRIX_3_TEX0 0x0000008C 1457#define R200_VS_MATRIX_4_TEX1 0x00000090 1458#define R200_VS_MATRIX_5_TEX2 0x00000094 1459#define R200_VS_MATRIX_6_TEX3 0x00000098 1460#define R200_VS_MATRIX_7_TEX4 0x0000009C 1461#define R200_VS_MATRIX_8_TEX5 0x000000A0 1462#define R200_VS_MAT_0_EMISS 0x000000B0 1463#define R200_VS_MAT_0_AMB 0x000000B1 1464#define R200_VS_MAT_0_DIF 0x000000B2 1465#define R200_VS_MAT_0_SPEC 0x000000B3 1466#define R200_VS_MAT_1_EMISS 0x000000B4 1467#define R200_VS_MAT_1_AMB 0x000000B5 1468#define R200_VS_MAT_1_DIF 0x000000B6 1469#define R200_VS_MAT_1_SPEC 0x000000B7 1470#define R200_VS_EYE2CLIP_MTX 0x000000B8 1471#define R200_VS_PNT_SPRITE_ATT_CONST 0x000000BC 1472#define R200_VS_PNT_SPRITE_EYE_IN_MODEL 0x000000BD 1473#define R200_VS_PNT_SPRITE_CLAMP 0x000000BE 1474#define R200_VS_MAX 0x000001C0 1475 1476 1477/* 1478 * Offsets in TCL scalar state 1479 */ 1480#define R200_SS_LIGHT_DCD_ADDR 0x00000000 1481#define R200_SS_LIGHT_DCM_ADDR 0x00000008 1482#define R200_SS_LIGHT_SPOT_EXPONENT_ADDR 0x00000010 1483#define R200_SS_LIGHT_SPOT_CUTOFF_ADDR 0x00000018 1484#define R200_SS_LIGHT_SPECULAR_THRESH_ADDR 0x00000020 1485#define R200_SS_LIGHT_RANGE_CUTOFF_SQRD 0x00000028 1486#define R200_SS_LIGHT_RANGE_ATT_CONST 0x00000030 1487#define R200_SS_VERT_GUARD_CLIP_ADJ_ADDR 0x00000080 1488#define R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR 0x00000081 1489#define R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR 0x00000082 1490#define R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 0x00000083 1491#define R200_SS_MAT_0_SHININESS 0x00000100 1492#define R200_SS_MAT_1_SHININESS 0x00000101 1493 1494 1495/* 1496 * Matrix indices 1497 */ 1498#define R200_MTX_MV 0 1499#define R200_MTX_IMV 1 1500#define R200_MTX_MVP 2 1501#define R200_MTX_TEX0 3 1502#define R200_MTX_TEX1 4 1503#define R200_MTX_TEX2 5 1504#define R200_MTX_TEX3 6 1505#define R200_MTX_TEX4 7 1506#define R200_MTX_TEX5 8 1507 1508/* Color formats for 2d packets 1509 */ 1510#define R200_CP_COLOR_FORMAT_CI8 2 1511#define R200_CP_COLOR_FORMAT_ARGB1555 3 1512#define R200_CP_COLOR_FORMAT_RGB565 4 1513#define R200_CP_COLOR_FORMAT_ARGB8888 6 1514#define R200_CP_COLOR_FORMAT_RGB332 7 1515#define R200_CP_COLOR_FORMAT_RGB8 9 1516#define R200_CP_COLOR_FORMAT_ARGB4444 15 1517 1518 1519/* 1520 * CP type-3 packets 1521 */ 1522#define R200_CP_CMD_NOP 0xC0001000 1523#define R200_CP_CMD_NEXT_CHAR 0xC0001900 1524#define R200_CP_CMD_PLY_NEXTSCAN 0xC0001D00 1525#define R200_CP_CMD_SET_SCISSORS 0xC0001E00 1526#define R200_CP_CMD_LOAD_MICROCODE 0xC0002400 1527#define R200_CP_CMD_WAIT_FOR_IDLE 0xC0002600 1528#define R200_CP_CMD_3D_DRAW_VBUF 0xC0002800 1529#define R200_CP_CMD_3D_DRAW_IMMD 0xC0002900 1530#define R200_CP_CMD_3D_DRAW_INDX 0xC0002A00 1531#define R200_CP_CMD_LOAD_PALETTE 0xC0002C00 1532#define R200_CP_CMD_3D_LOAD_VBPNTR 0xC0002F00 1533#define R200_CP_CMD_INDX_BUFFER 0xC0003300 1534#define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400 1535#define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500 1536#define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600 1537#define R200_CP_CMD_PAINT 0xC0009100 1538#define R200_CP_CMD_BITBLT 0xC0009200 1539#define R200_CP_CMD_SMALLTEXT 0xC0009300 1540#define R200_CP_CMD_HOSTDATA_BLT 0xC0009400 1541#define R200_CP_CMD_POLYLINE 0xC0009500 1542#define R200_CP_CMD_POLYSCANLINES 0xC0009800 1543#define R200_CP_CMD_PAINT_MULTI 0xC0009A00 1544#define R200_CP_CMD_BITBLT_MULTI 0xC0009B00 1545#define R200_CP_CMD_TRANS_BITBLT 0xC0009C00 1546 1547#endif 1548 1549