r200_sanity.c revision 239105c6c87da0b0c5c15ae54b19fe39492b0f29
1/************************************************************************** 2 3Copyright 2002 ATI Technologies Inc., Ontario, Canada, and 4 Tungsten Graphics Inc, Cedar Park, TX. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining a 9copy of this software and associated documentation files (the "Software"), 10to deal in the Software without restriction, including without limitation 11on the rights to use, copy, modify, merge, publish, distribute, sub 12license, and/or sell copies of the Software, and to permit persons to whom 13the Software is furnished to do so, subject to the following conditions: 14 15The above copyright notice and this permission notice (including the next 16paragraph) shall be included in all copies or substantial portions of the 17Software. 18 19THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 22ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 23DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 24OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 25USE OR OTHER DEALINGS IN THE SOFTWARE. 26 27**************************************************************************/ 28 29/* 30 * Authors: 31 * Keith Whitwell <keith@tungstengraphics.com> 32 * 33 */ 34 35#include <errno.h> 36 37#include "main/glheader.h" 38#include "main/imports.h" 39 40#include "r200_context.h" 41#include "r200_ioctl.h" 42#include "r200_sanity.h" 43#include "radeon_reg.h" 44#include "r200_reg.h" 45 46/* Set this '1' to get more verbiage. 47 */ 48#define MORE_VERBOSE 1 49 50#if MORE_VERBOSE 51#define VERBOSE (R200_DEBUG & RADEON_VERBOSE) 52#define NORMAL (1) 53#else 54#define VERBOSE 0 55#define NORMAL (R200_DEBUG & RADEON_VERBOSE) 56#endif 57 58 59/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 60 * 1.3 cmdbuffers allow all previous state to be updated as well as 61 * the tcl scalar and vector areas. 62 */ 63static struct { 64 int start; 65 int len; 66 const char *name; 67} packet[RADEON_MAX_STATE_PACKETS] = { 68 { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, 69 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, 70 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, 71 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, 72 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, 73 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, 74 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, 75 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, 76 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, 77 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, 78 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, 79 { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, 80 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, 81 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, 82 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, 83 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, 84 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, 85 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, 86 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, 87 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, 88 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, 89 { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" }, 90 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, 91 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, 92 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, 93 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, 94 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, 95 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, 96 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, 97 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 98 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, 99 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, 100 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, 101 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, 102 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, 103 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 104 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, 105 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, 106 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, 107 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, 108 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, 109 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, 110 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, 111 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, 112 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, 113 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, 114 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, 115 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, 116 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, 117 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 118 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, 119 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 120 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 121 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 122 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 123 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 124 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 125 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 126 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 127 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 128 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 129 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ 130 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ 131 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, 132 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, 133 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, 134 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, 135 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, 136 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, 137 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, 138 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, 139 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, 140 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, 141 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, 142 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, 143 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, 144 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, 145 { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 146 { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" }, 147 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" }, 148 { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" }, 149 { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" }, 150 { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" }, 151 { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" }, 152 { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" }, 153 { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 154 { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 155 { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 156 { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 157 { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 158 { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 159 { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 160 { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 161 { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 162 { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 163}; 164 165struct reg_names { 166 int idx; 167 const char *name; 168}; 169 170static struct reg_names reg_names[] = { 171 { R200_PP_MISC, "R200_PP_MISC" }, 172 { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" }, 173 { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" }, 174 { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" }, 175 { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" }, 176 { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" }, 177 { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" }, 178 { R200_PP_CNTL, "R200_PP_CNTL" }, 179 { R200_RB3D_CNTL, "R200_RB3D_CNTL" }, 180 { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" }, 181 { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" }, 182 { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" }, 183 { R200_SE_CNTL, "R200_SE_CNTL" }, 184 { R200_RE_CNTL, "R200_RE_CNTL" }, 185 { R200_RE_MISC, "R200_RE_MISC" }, 186 { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" }, 187 { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" }, 188 { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" }, 189 { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" }, 190 { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" }, 191 { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" }, 192 { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" }, 193 { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" }, 194 { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" }, 195 { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" }, 196 { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" }, 197 { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" }, 198 { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" }, 199 { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" }, 200 { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" }, 201 { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" }, 202 { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" }, 203 { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" }, 204 { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" }, 205 { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" }, 206 { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" }, 207 { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" }, 208 { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" }, 209 { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" }, 210 { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" }, 211 { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" }, 212 { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" }, 213 { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" }, 214 { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" }, 215 { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" }, 216 { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" }, 217 { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" }, 218 { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" }, 219 { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" }, 220 { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" }, 221 { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" }, 222 { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" }, 223 { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" }, 224 { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" }, 225 { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" }, 226 { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" }, 227 { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" }, 228 { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" }, 229 { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" }, 230 { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" }, 231 { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" }, 232 { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" }, 233 { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" }, 234 { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" }, 235 { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" }, 236 { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" }, 237 { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" }, 238 { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" }, 239 { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" }, 240 { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" }, 241 { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" }, 242 { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" }, 243 { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" }, 244 { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" }, 245 { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" }, 246 { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" }, 247 { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 248 { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" }, 249 { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" }, 250 { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" }, 251 { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" }, 252 { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" }, 253 { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" }, 254 { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" }, 255 { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" }, 256 { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" }, 257 { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" }, 258 { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 259 { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 260 { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" }, 261 { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" }, 262 { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" }, 263 { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" }, 264 { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" }, 265 { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" }, 266 { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" }, 267 { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" }, 268 { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" }, 269 { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" }, 270 { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" }, 271 { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" }, 272 { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" }, 273 { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" }, 274 { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" }, 275 { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" }, 276 { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" }, 277 { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" }, 278 { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" }, 279 { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" }, 280 { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" }, 281 { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" }, 282 { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" }, 283 { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" }, 284 { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" }, 285 { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" }, 286 { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" }, 287 { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" }, 288 { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" }, 289 { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" }, 290 { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" }, 291 { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" }, 292 { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" }, 293 { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" }, 294 { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" }, 295 { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" }, 296 { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" }, 297 { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" }, 298 { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" }, 299 { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" }, 300 { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" }, 301 { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" }, 302 { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" }, 303 { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" }, 304 { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" }, 305 { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" }, 306 { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" }, 307 { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" }, 308 { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" }, 309 { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" }, 310 { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" }, 311 { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" }, 312 { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" }, 313 { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" }, 314 { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" }, 315 { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" }, 316 { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" }, 317 { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" }, 318 { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" }, 319 { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" }, 320 { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" }, 321 { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" }, 322 { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" }, 323 { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" }, 324 { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" }, 325 { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" }, 326 { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" }, 327 { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" }, 328 { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" }, 329 { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" }, 330 { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" }, 331 { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" }, 332 { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" }, 333 { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" }, 334 { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" }, 335 { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" }, 336 { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" }, 337 { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" }, 338 { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" }, 339 { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" }, 340 { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" }, 341 { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" }, 342 { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" }, 343 { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" }, 344 { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" }, 345 { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" }, 346 { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" }, 347 { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" }, 348 { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" }, 349 { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" }, 350 { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" }, 351 { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" }, 352 { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" }, 353 { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" }, 354 { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" }, 355 { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" }, 356 { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" }, 357 { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" }, 358 { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" }, 359 { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" }, 360 { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" }, 361 { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" }, 362 { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" }, 363 { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" }, 364 { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" }, 365 { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" }, 366 { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" }, 367 { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" }, 368 { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" }, 369 { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" }, 370 { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" }, 371 { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" }, 372 { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" }, 373 { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" }, 374 { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" }, 375 { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" }, 376 { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" }, 377 { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" }, 378 { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" }, 379 { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" }, 380 { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" }, 381 { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" }, 382 { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" }, 383 { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" }, 384 { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" }, 385 { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" }, 386 { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" }, 387 { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" }, 388 { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" }, 389 { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" }, 390 { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" }, 391 { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" }, 392 { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" }, 393 { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" }, 394 { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" }, 395 { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" }, 396 { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" }, 397 { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" }, 398 { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" }, 399 { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" }, 400 { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" }, 401 { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" }, 402 { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" }, 403 { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" }, 404 { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" }, 405 { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" }, 406 { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" }, 407 { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" }, 408 { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" }, 409 { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" }, 410 { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" }, 411 { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" }, 412 { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" }, 413 { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" }, 414 { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" }, 415 { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" }, 416 { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" }, 417 { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" }, 418 { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" }, 419 { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" }, 420 { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" }, 421 { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" }, 422 { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" }, 423 { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" }, 424 { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" }, 425 { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" }, 426 { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" }, 427 { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" }, 428 { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" }, 429 { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" }, 430 { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" }, 431 { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" }, 432 { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" }, 433 { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" }, 434 { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" }, 435 { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" }, 436 { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" }, 437 { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" }, 438 { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" }, 439 { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" }, 440 { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" }, 441 { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" }, 442 { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" }, 443 { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" }, 444 { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" }, 445 { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" }, 446 { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" }, 447 { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" }, 448 { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" }, 449 { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" }, 450 { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" }, 451 { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" }, 452 { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" }, 453 { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" }, 454 { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" }, 455 { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" }, 456 { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" }, 457 { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" }, 458 { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" }, 459 { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" }, 460 { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" }, 461 { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" }, 462 { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" }, 463 { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" }, 464 { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" }, 465 { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" }, 466 { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" }, 467 { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" }, 468 { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" }, 469 { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" }, 470 { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" }, 471 { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" }, 472 { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" }, 473 { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" }, 474 { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" }, 475 { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" }, 476 { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" }, 477 { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" }, 478 { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" }, 479 { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" }, 480 { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" }, 481 { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" }, 482 { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" }, 483 { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" }, 484 { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" }, 485 { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" }, 486 { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" }, 487 { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" }, 488 { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" }, 489 { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" }, 490 { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" }, 491 { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" }, 492 { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" }, 493 { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" }, 494 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 495 { R200_PP_CNTL_X, "R200_PP_CNTL_X" }, 496 { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" }, 497 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 498 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" }, 499 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" }, 500 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" }, 501 { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" }, 502 { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" }, 503 { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" }, 504 { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" }, 505 { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" }, 506 { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" }, 507 { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" }, 508 { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" }, 509 { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" }, 510 { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" }, 511 { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" }, 512 { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" }, 513 { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" }, 514 { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" }, 515 { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" }, 516 { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" }, 517 { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" }, 518 { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" }, 519 { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" }, 520 { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" }, 521 { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" }, 522 { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" }, 523 { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" }, 524 { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" }, 525 { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" }, 526 { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" }, 527 { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" }, 528 { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" }, 529 { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" }, 530 { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" }, 531 { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" }, 532 { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" }, 533 { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" }, 534 { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" }, 535 { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" }, 536 { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" }, 537}; 538 539static struct reg_names scalar_names[] = { 540 { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" }, 541 { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" }, 542 { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" }, 543 { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" }, 544 { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" }, 545 { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" }, 546 { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" }, 547 { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" }, 548 { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" }, 549 { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" }, 550 { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" }, 551 { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" }, 552 { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" }, 553 { 1000, "" }, 554}; 555 556/* Puff these out to make them look like normal (dword) registers. 557 */ 558static struct reg_names vector_names[] = { 559 { 0, "start" }, 560 { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" }, 561 { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" }, 562 { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" }, 563 { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" }, 564 { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" }, 565 { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" }, 566 { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" }, 567 { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" }, 568 { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" }, 569 { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" }, 570 { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" }, 571 { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" }, 572 { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" }, 573 { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" }, 574 { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" }, 575 { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" }, 576 { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" }, 577 { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" }, 578 { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" }, 579 { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" }, 580 { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" }, 581 { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" }, 582 { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" }, 583 { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" }, 584 { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" }, 585 { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" }, 586 { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" }, 587 { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" }, 588 { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" }, 589 { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" }, 590 { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" }, 591 { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" }, 592 { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" }, 593 { R200_VS_MAX, "R200_VS_MAX" }, 594 { 1000, "" }, 595}; 596 597union fi { float f; int i; }; 598 599#define ISVEC 1 600#define ISFLOAT 2 601#define TOUCHED 4 602 603struct reg { 604 int idx; 605 struct reg_names *closest; 606 int flags; 607 union fi current; 608 union fi *values; 609 int nvalues; 610 int nalloc; 611 float vmin, vmax; 612}; 613 614 615static struct reg regs[Elements(reg_names)+1]; 616static struct reg scalars[512+1]; 617static struct reg vectors[512*4+1]; 618 619static int total, total_changed, bufs; 620 621static void init_regs( void ) 622{ 623 struct reg_names *tmp; 624 int i; 625 626 for (i = 0 ; i < Elements(regs) ; i++) { 627 regs[i].idx = reg_names[i].idx; 628 regs[i].closest = ®_names[i]; 629 regs[i].flags = 0; 630 } 631 632 for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) { 633 if (tmp[1].idx == i) tmp++; 634 scalars[i].idx = i; 635 scalars[i].closest = tmp; 636 scalars[i].flags = ISFLOAT; 637 } 638 639 for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) { 640 if (tmp[1].idx*4 == i) tmp++; 641 vectors[i].idx = i; 642 vectors[i].closest = tmp; 643 vectors[i].flags = ISFLOAT|ISVEC; 644 } 645 646 regs[Elements(regs)-1].idx = -1; 647 scalars[Elements(scalars)-1].idx = -1; 648 vectors[Elements(vectors)-1].idx = -1; 649} 650 651static int find_or_add_value( struct reg *reg, int val ) 652{ 653 int j; 654 655 for ( j = 0 ; j < reg->nvalues ; j++) 656 if ( val == reg->values[j].i ) 657 return 1; 658 659 if (j == reg->nalloc) { 660 reg->nalloc += 5; 661 reg->nalloc *= 2; 662 reg->values = (union fi *) realloc( reg->values, 663 reg->nalloc * sizeof(union fi) ); 664 } 665 666 reg->values[reg->nvalues++].i = val; 667 return 0; 668} 669 670static struct reg *lookup_reg( struct reg *tab, int reg ) 671{ 672 int i; 673 674 for (i = 0 ; tab[i].idx != -1 ; i++) { 675 if (tab[i].idx == reg) 676 return &tab[i]; 677 } 678 679 fprintf(stderr, "*** unknown reg 0x%x\n", reg); 680 return NULL; 681} 682 683 684static const char *get_reg_name( struct reg *reg ) 685{ 686 static char tmp[80]; 687 688 if (reg->idx == reg->closest->idx) 689 return reg->closest->name; 690 691 692 if (reg->flags & ISVEC) { 693 if (reg->idx/4 != reg->closest->idx) 694 sprintf(tmp, "%s+%d[%d]", 695 reg->closest->name, 696 (reg->idx/4) - reg->closest->idx, 697 reg->idx%4); 698 else 699 sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4); 700 } 701 else { 702 if (reg->idx != reg->closest->idx) 703 sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx); 704 else 705 sprintf(tmp, "%s", reg->closest->name); 706 } 707 708 return tmp; 709} 710 711static int print_int_reg_assignment( struct reg *reg, int data ) 712{ 713 int changed = (reg->current.i != data); 714 int ever_seen = find_or_add_value( reg, data ); 715 716 if (VERBOSE || (NORMAL && (changed || !ever_seen))) 717 fprintf(stderr, " %s <-- 0x%x", get_reg_name(reg), data); 718 719 if (NORMAL) { 720 if (!ever_seen) 721 fprintf(stderr, " *** BRAND NEW VALUE"); 722 else if (changed) 723 fprintf(stderr, " *** CHANGED"); 724 } 725 726 reg->current.i = data; 727 728 if (VERBOSE || (NORMAL && (changed || !ever_seen))) 729 fprintf(stderr, "\n"); 730 731 return changed; 732} 733 734 735static int print_float_reg_assignment( struct reg *reg, float data ) 736{ 737 int changed = (reg->current.f != data); 738 int newmin = (data < reg->vmin); 739 int newmax = (data > reg->vmax); 740 741 if (VERBOSE || (NORMAL && (newmin || newmax || changed))) 742 fprintf(stderr, " %s <-- %.3f", get_reg_name(reg), data); 743 744 if (NORMAL) { 745 if (newmin) { 746 fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin); 747 reg->vmin = data; 748 } 749 else if (newmax) { 750 fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax); 751 reg->vmax = data; 752 } 753 else if (changed) { 754 fprintf(stderr, " *** CHANGED"); 755 } 756 } 757 758 reg->current.f = data; 759 760 if (VERBOSE || (NORMAL && (newmin || newmax || changed))) 761 fprintf(stderr, "\n"); 762 763 return changed; 764} 765 766static int print_reg_assignment( struct reg *reg, int data ) 767{ 768 float_ui32_type datau; 769 datau.ui32 = data; 770 reg->flags |= TOUCHED; 771 if (reg->flags & ISFLOAT) 772 return print_float_reg_assignment( reg, datau.f ); 773 else 774 return print_int_reg_assignment( reg, data ); 775} 776 777static void print_reg( struct reg *reg ) 778{ 779 if (reg->flags & TOUCHED) { 780 if (reg->flags & ISFLOAT) { 781 fprintf(stderr, " %s == %f\n", get_reg_name(reg), reg->current.f); 782 } else { 783 fprintf(stderr, " %s == 0x%x\n", get_reg_name(reg), reg->current.i); 784 } 785 } 786} 787 788 789static void dump_state( void ) 790{ 791 int i; 792 793 for (i = 0 ; i < Elements(regs) ; i++) 794 print_reg( ®s[i] ); 795 796 for (i = 0 ; i < Elements(scalars) ; i++) 797 print_reg( &scalars[i] ); 798 799 for (i = 0 ; i < Elements(vectors) ; i++) 800 print_reg( &vectors[i] ); 801} 802 803 804 805static int radeon_emit_packets( 806 drm_radeon_cmd_header_t header, 807 drm_radeon_cmd_buffer_t *cmdbuf ) 808{ 809 int id = (int)header.packet.packet_id; 810 int sz = packet[id].len; 811 int *data = (int *)cmdbuf->buf; 812 int i; 813 814 if (sz * sizeof(int) > cmdbuf->bufsz) { 815 fprintf(stderr, "Packet overflows cmdbuf\n"); 816 return -EINVAL; 817 } 818 819 if (!packet[id].name) { 820 fprintf(stderr, "*** Unknown packet 0 nr %d\n", id ); 821 return -EINVAL; 822 } 823 824 825 if (VERBOSE) 826 fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz ); 827 828 for ( i = 0 ; i < sz ; i++) { 829 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); 830 if (print_reg_assignment( reg, data[i] )) 831 total_changed++; 832 total++; 833 } 834 835 cmdbuf->buf += sz * sizeof(int); 836 cmdbuf->bufsz -= sz * sizeof(int); 837 return 0; 838} 839 840 841static int radeon_emit_scalars( 842 drm_radeon_cmd_header_t header, 843 drm_radeon_cmd_buffer_t *cmdbuf ) 844{ 845 int sz = header.scalars.count; 846 int *data = (int *)cmdbuf->buf; 847 int start = header.scalars.offset; 848 int stride = header.scalars.stride; 849 int i; 850 851 if (VERBOSE) 852 fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n", 853 start, stride, sz, start + stride * sz); 854 855 856 for (i = 0 ; i < sz ; i++, start += stride) { 857 struct reg *reg = lookup_reg( scalars, start ); 858 if (print_reg_assignment( reg, data[i] )) 859 total_changed++; 860 total++; 861 } 862 863 cmdbuf->buf += sz * sizeof(int); 864 cmdbuf->bufsz -= sz * sizeof(int); 865 return 0; 866} 867 868 869static int radeon_emit_scalars2( 870 drm_radeon_cmd_header_t header, 871 drm_radeon_cmd_buffer_t *cmdbuf ) 872{ 873 int sz = header.scalars.count; 874 int *data = (int *)cmdbuf->buf; 875 int start = header.scalars.offset + 0x100; 876 int stride = header.scalars.stride; 877 int i; 878 879 if (VERBOSE) 880 fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n", 881 start, stride, sz, start + stride * sz); 882 883 if (start + stride * sz > 258) { 884 fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz); 885 return -1; 886 } 887 888 for (i = 0 ; i < sz ; i++, start += stride) { 889 struct reg *reg = lookup_reg( scalars, start ); 890 if (print_reg_assignment( reg, data[i] )) 891 total_changed++; 892 total++; 893 } 894 895 cmdbuf->buf += sz * sizeof(int); 896 cmdbuf->bufsz -= sz * sizeof(int); 897 return 0; 898} 899 900/* Check: inf/nan/extreme-size? 901 * Check: table start, end, nr, etc. 902 */ 903static int radeon_emit_vectors( 904 drm_radeon_cmd_header_t header, 905 drm_radeon_cmd_buffer_t *cmdbuf ) 906{ 907 int sz = header.vectors.count; 908 int *data = (int *)cmdbuf->buf; 909 int start = header.vectors.offset; 910 int stride = header.vectors.stride; 911 int i,j; 912 913 if (VERBOSE) 914 fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n", 915 start, stride, sz, start + stride * sz, header.i); 916 917/* if (start + stride * (sz/4) > 128) { */ 918/* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */ 919/* return -1; */ 920/* } */ 921 922 for (i = 0 ; i < sz ; start += stride) { 923 int changed = 0; 924 for (j = 0 ; j < 4 ; i++,j++) { 925 struct reg *reg = lookup_reg( vectors, start*4+j ); 926 if (print_reg_assignment( reg, data[i] )) 927 changed = 1; 928 } 929 if (changed) 930 total_changed += 4; 931 total += 4; 932 } 933 934 935 cmdbuf->buf += sz * sizeof(int); 936 cmdbuf->bufsz -= sz * sizeof(int); 937 return 0; 938} 939 940static int radeon_emit_veclinear( 941 drm_radeon_cmd_header_t header, 942 drm_radeon_cmd_buffer_t *cmdbuf ) 943{ 944 int sz = header.veclinear.count * 4; 945 int *data = (int *)cmdbuf->buf; 946 float *fdata =(float *)cmdbuf->buf; 947 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); 948 int i; 949 950 if (1||VERBOSE) 951 fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n", 952 start, sz >> 2, start + (sz >> 2), header.i); 953 954 955 if (start < 0x60) { 956 for (i = 0 ; i < sz ; i += 4) { 957 fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start, fdata[i]); 958 fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]); 959 fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]); 960 fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]); 961 } 962 } 963 else if ((start >= 0x100) && (start < 0x160)) { 964 for (i = 0 ; i < sz ; i += 4) { 965 fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]); 966 fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]); 967 fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]); 968 fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]); 969 } 970 } 971 else if ((start >= 0x80) && (start < 0xc0)) { 972 for (i = 0 ; i < sz ; i += 4) { 973 fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]); 974 fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x80, data[i+1]); 975 fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x80, data[i+2]); 976 fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x80, data[i+3]); 977 } 978 } 979 else if ((start >= 0x180) && (start < 0x1c0)) { 980 for (i = 0 ; i < sz ; i += 4) { 981 fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]); 982 fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]); 983 fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]); 984 fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]); 985 } 986 } 987 else { 988 fprintf(stderr, "write to unknown vector area\n"); 989 } 990 991 cmdbuf->buf += sz * sizeof(int); 992 cmdbuf->bufsz -= sz * sizeof(int); 993 return 0; 994} 995 996#if 0 997static int print_vertex_format( int vfmt ) 998{ 999 if (NORMAL) { 1000 fprintf(stderr, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 1001 "vertex format", 1002 vfmt, 1003 "xy,", 1004 (vfmt & R200_VTX_Z0) ? "z," : "", 1005 (vfmt & R200_VTX_W0) ? "w0," : "", 1006 (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "", 1007 (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "", 1008 (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "", 1009 (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "", 1010 (vfmt & R200_VTX_FPFOG) ? "fpfog," : "", 1011 (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "", 1012 (vfmt & R200_VTX_ST0) ? "st0," : "", 1013 (vfmt & R200_VTX_ST1) ? "st1," : "", 1014 (vfmt & R200_VTX_Q1) ? "q1," : "", 1015 (vfmt & R200_VTX_ST2) ? "st2," : "", 1016 (vfmt & R200_VTX_Q2) ? "q2," : "", 1017 (vfmt & R200_VTX_ST3) ? "st3," : "", 1018 (vfmt & R200_VTX_Q3) ? "q3," : "", 1019 (vfmt & R200_VTX_Q0) ? "q0," : "", 1020 (vfmt & R200_VTX_N0) ? "n0," : "", 1021 (vfmt & R200_VTX_XY1) ? "xy1," : "", 1022 (vfmt & R200_VTX_Z1) ? "z1," : "", 1023 (vfmt & R200_VTX_W1) ? "w1," : "", 1024 (vfmt & R200_VTX_N1) ? "n1," : ""); 1025 1026 1027 if (!find_or_add_value( &others[V_VTXFMT], vfmt )) 1028 fprintf(stderr, " *** NEW VALUE"); 1029 1030 fprintf(stderr, "\n"); 1031 } 1032 1033 return 0; 1034} 1035#endif 1036 1037static char *primname[0x10] = { 1038 "NONE", 1039 "POINTS", 1040 "LINES", 1041 "LINE_STRIP", 1042 "TRIANGLES", 1043 "TRIANGLE_FAN", 1044 "TRIANGLE_STRIP", 1045 "RECT_LIST", 1046 NULL, 1047 "3VRT_POINTS", 1048 "3VRT_LINES", 1049 "POINT_SPRITES", 1050 "LINE_LOOP", 1051 "QUADS", 1052 "QUAD_STRIP", 1053 "POLYGON", 1054}; 1055 1056static int print_prim_and_flags( int prim ) 1057{ 1058 int numverts; 1059 1060 if (NORMAL) 1061 fprintf(stderr, " %s(%x): %s%s%s%s%s%s\n", 1062 "prim flags", 1063 prim, 1064 ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "", 1065 ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "", 1066 ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "", 1067 (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ", 1068 (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "", 1069 (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : ""); 1070 1071 numverts = prim>>16; 1072 1073 if (NORMAL) 1074 fprintf(stderr, " prim: %s numverts %d\n", primname[prim&0xf], numverts); 1075 1076 switch (prim & 0xf) { 1077 case R200_VF_PRIM_NONE: 1078 case R200_VF_PRIM_POINTS: 1079 if (numverts < 1) { 1080 fprintf(stderr, "Bad nr verts for line %d\n", numverts); 1081 return -1; 1082 } 1083 break; 1084 case R200_VF_PRIM_LINES: 1085 case R200_VF_PRIM_POINT_SPRITES: 1086 if ((numverts & 1) || numverts == 0) { 1087 fprintf(stderr, "Bad nr verts for line %d\n", numverts); 1088 return -1; 1089 } 1090 break; 1091 case R200_VF_PRIM_LINE_STRIP: 1092 case R200_VF_PRIM_LINE_LOOP: 1093 if (numverts < 2) { 1094 fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts); 1095 return -1; 1096 } 1097 break; 1098 case R200_VF_PRIM_TRIANGLES: 1099 case R200_VF_PRIM_3VRT_POINTS: 1100 case R200_VF_PRIM_3VRT_LINES: 1101 case R200_VF_PRIM_RECT_LIST: 1102 if (numverts % 3 || numverts == 0) { 1103 fprintf(stderr, "Bad nr verts for tri %d\n", numverts); 1104 return -1; 1105 } 1106 break; 1107 case R200_VF_PRIM_TRIANGLE_FAN: 1108 case R200_VF_PRIM_TRIANGLE_STRIP: 1109 case R200_VF_PRIM_POLYGON: 1110 if (numverts < 3) { 1111 fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts); 1112 return -1; 1113 } 1114 break; 1115 case R200_VF_PRIM_QUADS: 1116 if (numverts % 4 || numverts == 0) { 1117 fprintf(stderr, "Bad nr verts for quad %d\n", numverts); 1118 return -1; 1119 } 1120 break; 1121 case R200_VF_PRIM_QUAD_STRIP: 1122 if (numverts % 2 || numverts < 4) { 1123 fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts); 1124 return -1; 1125 } 1126 break; 1127 default: 1128 fprintf(stderr, "Bad primitive\n"); 1129 return -1; 1130 } 1131 return 0; 1132} 1133 1134/* build in knowledge about each packet type 1135 */ 1136static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) 1137{ 1138 int cmdsz; 1139 int *cmd = (int *)cmdbuf->buf; 1140 int *tmp; 1141 int i, stride, size, start; 1142 1143 cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); 1144 1145 if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 || 1146 cmdsz * 4 > cmdbuf->bufsz || 1147 cmdsz > RADEON_CP_PACKET_MAX_DWORDS) { 1148 fprintf(stderr, "Bad packet\n"); 1149 return -EINVAL; 1150 } 1151 1152 switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) { 1153 case R200_CP_CMD_NOP: 1154 if (NORMAL) 1155 fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz); 1156 break; 1157 case R200_CP_CMD_NEXT_CHAR: 1158 if (NORMAL) 1159 fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz); 1160 break; 1161 case R200_CP_CMD_PLY_NEXTSCAN: 1162 if (NORMAL) 1163 fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz); 1164 break; 1165 case R200_CP_CMD_SET_SCISSORS: 1166 if (NORMAL) 1167 fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz); 1168 break; 1169 case R200_CP_CMD_LOAD_MICROCODE: 1170 if (NORMAL) 1171 fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz); 1172 break; 1173 case R200_CP_CMD_WAIT_FOR_IDLE: 1174 if (NORMAL) 1175 fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz); 1176 break; 1177 1178 case R200_CP_CMD_3D_DRAW_VBUF: 1179 if (NORMAL) 1180 fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz); 1181/* print_vertex_format(cmd[1]); */ 1182 if (print_prim_and_flags(cmd[2])) 1183 return -EINVAL; 1184 break; 1185 1186 case R200_CP_CMD_3D_DRAW_IMMD: 1187 if (NORMAL) 1188 fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz); 1189 break; 1190 case R200_CP_CMD_3D_DRAW_INDX: { 1191 int neltdwords; 1192 if (NORMAL) 1193 fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz); 1194/* print_vertex_format(cmd[1]); */ 1195 if (print_prim_and_flags(cmd[2])) 1196 return -EINVAL; 1197 neltdwords = cmd[2]>>16; 1198 neltdwords += neltdwords & 1; 1199 neltdwords /= 2; 1200 if (neltdwords + 3 != cmdsz) 1201 fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n", 1202 neltdwords, cmdsz); 1203 break; 1204 } 1205 case R200_CP_CMD_LOAD_PALETTE: 1206 if (NORMAL) 1207 fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz); 1208 break; 1209 case R200_CP_CMD_3D_LOAD_VBPNTR: 1210 if (NORMAL) { 1211 fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz); 1212 fprintf(stderr, " nr arrays: %d\n", cmd[1]); 1213 } 1214 1215 if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) { 1216 fprintf(stderr, " ****** MISMATCH %d/%d *******\n", 1217 ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz); 1218 return -EINVAL; 1219 } 1220 1221 if (NORMAL) { 1222 tmp = cmd+2; 1223 for (i = 0 ; i < cmd[1] ; i++) { 1224 if (i & 1) { 1225 stride = (tmp[0]>>24) & 0xff; 1226 size = (tmp[0]>>16) & 0xff; 1227 start = tmp[2]; 1228 tmp += 3; 1229 } 1230 else { 1231 stride = (tmp[0]>>8) & 0xff; 1232 size = (tmp[0]) & 0xff; 1233 start = tmp[1]; 1234 } 1235 fprintf(stderr, " array %d: start 0x%x vsize %d vstride %d\n", 1236 i, start, size, stride ); 1237 } 1238 } 1239 break; 1240 case R200_CP_CMD_PAINT: 1241 if (NORMAL) 1242 fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz); 1243 break; 1244 case R200_CP_CMD_BITBLT: 1245 if (NORMAL) 1246 fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz); 1247 break; 1248 case R200_CP_CMD_SMALLTEXT: 1249 if (NORMAL) 1250 fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz); 1251 break; 1252 case R200_CP_CMD_HOSTDATA_BLT: 1253 if (NORMAL) 1254 fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n", 1255 cmdsz); 1256 break; 1257 case R200_CP_CMD_POLYLINE: 1258 if (NORMAL) 1259 fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz); 1260 break; 1261 case R200_CP_CMD_POLYSCANLINES: 1262 if (NORMAL) 1263 fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n", 1264 cmdsz); 1265 break; 1266 case R200_CP_CMD_PAINT_MULTI: 1267 if (NORMAL) 1268 fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n", 1269 cmdsz); 1270 break; 1271 case R200_CP_CMD_BITBLT_MULTI: 1272 if (NORMAL) 1273 fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n", 1274 cmdsz); 1275 break; 1276 case R200_CP_CMD_TRANS_BITBLT: 1277 if (NORMAL) 1278 fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n", 1279 cmdsz); 1280 break; 1281 case R200_CP_CMD_3D_DRAW_VBUF_2: 1282 if (NORMAL) 1283 fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n", 1284 cmdsz); 1285 if (print_prim_and_flags(cmd[1])) 1286 return -EINVAL; 1287 break; 1288 case R200_CP_CMD_3D_DRAW_IMMD_2: 1289 if (NORMAL) 1290 fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n", 1291 cmdsz); 1292 if (print_prim_and_flags(cmd[1])) 1293 return -EINVAL; 1294 break; 1295 case R200_CP_CMD_3D_DRAW_INDX_2: 1296 if (NORMAL) 1297 fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n", 1298 cmdsz); 1299 if (print_prim_and_flags(cmd[1])) 1300 return -EINVAL; 1301 break; 1302 default: 1303 fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz); 1304 break; 1305 } 1306 1307 cmdbuf->buf += cmdsz * 4; 1308 cmdbuf->bufsz -= cmdsz * 4; 1309 return 0; 1310} 1311 1312 1313/* Check cliprects for bounds, then pass on to above: 1314 */ 1315static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf ) 1316{ 1317 drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes; 1318 int i = 0; 1319 1320 if (VERBOSE && total_changed) { 1321 dump_state(); 1322 total_changed = 0; 1323 } 1324 1325 if (NORMAL) { 1326 do { 1327 if ( i < cmdbuf->nbox ) { 1328 fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n", 1329 i, cmdbuf->nbox, 1330 boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2); 1331 } 1332 } while ( ++i < cmdbuf->nbox ); 1333 } 1334 1335 if (cmdbuf->nbox == 1) 1336 cmdbuf->nbox = 0; 1337 1338 return radeon_emit_packet3( cmdbuf ); 1339} 1340 1341 1342int r200SanityCmdBuffer( r200ContextPtr rmesa, 1343 int nbox, 1344 drm_clip_rect_t *boxes ) 1345{ 1346 int idx; 1347 drm_radeon_cmd_buffer_t cmdbuf; 1348 drm_radeon_cmd_header_t header; 1349 static int inited = 0; 1350 1351 if (!inited) { 1352 init_regs(); 1353 inited = 1; 1354 } 1355 1356 1357 cmdbuf.buf = rmesa->store.cmd_buf; 1358 cmdbuf.bufsz = rmesa->store.cmd_used; 1359 cmdbuf.boxes = (drm_clip_rect_t *)boxes; 1360 cmdbuf.nbox = nbox; 1361 1362 while ( cmdbuf.bufsz >= sizeof(header) ) { 1363 1364 header.i = *(int *)cmdbuf.buf; 1365 cmdbuf.buf += sizeof(header); 1366 cmdbuf.bufsz -= sizeof(header); 1367 1368 switch (header.header.cmd_type) { 1369 case RADEON_CMD_PACKET: 1370 if (radeon_emit_packets( header, &cmdbuf )) { 1371 fprintf(stderr,"radeon_emit_packets failed\n"); 1372 return -EINVAL; 1373 } 1374 break; 1375 1376 case RADEON_CMD_SCALARS: 1377 if (radeon_emit_scalars( header, &cmdbuf )) { 1378 fprintf(stderr,"radeon_emit_scalars failed\n"); 1379 return -EINVAL; 1380 } 1381 break; 1382 1383 case RADEON_CMD_SCALARS2: 1384 if (radeon_emit_scalars2( header, &cmdbuf )) { 1385 fprintf(stderr,"radeon_emit_scalars failed\n"); 1386 return -EINVAL; 1387 } 1388 break; 1389 1390 case RADEON_CMD_VECTORS: 1391 if (radeon_emit_vectors( header, &cmdbuf )) { 1392 fprintf(stderr,"radeon_emit_vectors failed\n"); 1393 return -EINVAL; 1394 } 1395 break; 1396 1397 case RADEON_CMD_DMA_DISCARD: 1398 idx = header.dma.buf_idx; 1399 if (NORMAL) 1400 fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx); 1401 bufs++; 1402 break; 1403 1404 case RADEON_CMD_PACKET3: 1405 if (radeon_emit_packet3( &cmdbuf )) { 1406 fprintf(stderr,"radeon_emit_packet3 failed\n"); 1407 return -EINVAL; 1408 } 1409 break; 1410 1411 case RADEON_CMD_PACKET3_CLIP: 1412 if (radeon_emit_packet3_cliprect( &cmdbuf )) { 1413 fprintf(stderr,"radeon_emit_packet3_clip failed\n"); 1414 return -EINVAL; 1415 } 1416 break; 1417 1418 case RADEON_CMD_WAIT: 1419 break; 1420 1421 case RADEON_CMD_VECLINEAR: 1422 if (radeon_emit_veclinear( header, &cmdbuf )) { 1423 fprintf(stderr,"radeon_emit_veclinear failed\n"); 1424 return -EINVAL; 1425 } 1426 break; 1427 1428 default: 1429 fprintf(stderr,"bad cmd_type %d at %p\n", 1430 header.header.cmd_type, 1431 cmdbuf.buf - sizeof(header)); 1432 return -EINVAL; 1433 } 1434 } 1435 1436 if (0) 1437 { 1438 static int n = 0; 1439 n++; 1440 if (n == 10) { 1441 fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n", 1442 bufs, 1443 total, total_changed, 1444 ((float)total_changed/(float)total*100.0)); 1445 fprintf(stderr, "Total emitted per buf: %.2f\n", 1446 (float)total/(float)bufs); 1447 fprintf(stderr, "Real changes per buf: %.2f\n", 1448 (float)total_changed/(float)bufs); 1449 1450 bufs = n = total = total_changed = 0; 1451 } 1452 } 1453 1454 fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__); 1455 1456 return 0; 1457} 1458