radeon_span.c revision cf5b2f7419b28cdd533c60e205d5a90d96e85c8e 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/*
32 * Authors:
33 *   Kevin E. Martin <martin@valinux.com>
34 *   Gareth Hughes <gareth@valinux.com>
35 *   Keith Whitwell <keith@tungstengraphics.com>
36 *
37 */
38
39#include "glheader.h"
40#include "swrast/swrast.h"
41
42#include "radeon_context.h"
43#include "radeon_ioctl.h"
44#include "radeon_state.h"
45#include "radeon_span.h"
46#include "radeon_tex.h"
47
48#define DBG 0
49
50#define LOCAL_VARS							\
51   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);			\
52   radeonScreenPtr radeonScreen = rmesa->radeonScreen;			\
53   __DRIscreenPrivate *sPriv = rmesa->dri.screen;			\
54   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;			\
55   GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp;		\
56   GLuint height = dPriv->h;						\
57   char *buf = (char *)(sPriv->pFB +					\
58			rmesa->state.color.drawOffset +			\
59			(dPriv->x * radeonScreen->cpp) +		\
60			(dPriv->y * pitch));				\
61   char *read_buf = (char *)(sPriv->pFB +				\
62			     rmesa->state.pixel.readOffset +		\
63			     (dPriv->x * radeonScreen->cpp) +		\
64			     (dPriv->y * pitch));			\
65   GLuint p;								\
66   (void) read_buf; (void) buf; (void) p
67
68#define LOCAL_DEPTH_VARS						\
69   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);			\
70   radeonScreenPtr radeonScreen = rmesa->radeonScreen;			\
71   __DRIscreenPrivate *sPriv = rmesa->dri.screen;			\
72   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;			\
73   GLuint height = dPriv->h;						\
74   GLuint xo = dPriv->x;						\
75   GLuint yo = dPriv->y;						\
76   char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset);	\
77   (void) buf
78
79#define LOCAL_STENCIL_VARS	LOCAL_DEPTH_VARS
80
81#define Y_FLIP( _y )		(height - _y - 1)
82
83#define HW_LOCK()
84
85#define HW_UNLOCK()
86
87
88
89/* ================================================================
90 * Color buffer
91 */
92
93/* 16 bit, RGB565 color spanline and pixel functions
94 */
95#define INIT_MONO_PIXEL(p, color) \
96  p = PACK_COLOR_565( color[0], color[1], color[2] )
97
98#define WRITE_RGBA( _x, _y, r, g, b, a )				\
99   *(GLushort *)(buf + _x*2 + _y*pitch) = ((((int)r & 0xf8) << 8) |	\
100					   (((int)g & 0xfc) << 3) |	\
101					   (((int)b & 0xf8) >> 3))
102
103#define WRITE_PIXEL( _x, _y, p )					\
104   *(GLushort *)(buf + _x*2 + _y*pitch) = p
105
106#define READ_RGBA( rgba, _x, _y )					\
107   do {									\
108      GLushort p = *(GLushort *)(read_buf + _x*2 + _y*pitch);		\
109      rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8;				\
110      rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc;				\
111      rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8;				\
112      rgba[3] = 0xff;							\
113   } while (0)
114
115#define TAG(x) radeon##x##_RGB565
116#include "spantmp.h"
117
118/* 32 bit, ARGB8888 color spanline and pixel functions
119 */
120#undef INIT_MONO_PIXEL
121#define INIT_MONO_PIXEL(p, color) \
122  p = PACK_COLOR_8888( color[3], color[0], color[1], color[2] )
123
124#define WRITE_RGBA( _x, _y, r, g, b, a )			\
125do {								\
126   *(GLuint *)(buf + _x*4 + _y*pitch) = ((b <<  0) |		\
127					 (g <<  8) |		\
128					 (r << 16) |		\
129					 (a << 24) );		\
130} while (0)
131
132#define WRITE_PIXEL( _x, _y, p ) 			\
133do {							\
134   *(GLuint *)(buf + _x*4 + _y*pitch) = p;		\
135} while (0)
136
137#define READ_RGBA( rgba, _x, _y )				\
138do {								\
139   volatile GLuint *ptr = (volatile GLuint *)(read_buf + _x*4 + _y*pitch); \
140   GLuint p = *ptr;					\
141   rgba[0] = (p >> 16) & 0xff;					\
142   rgba[1] = (p >>  8) & 0xff;					\
143   rgba[2] = (p >>  0) & 0xff;					\
144   rgba[3] = (p >> 24) & 0xff;					\
145} while (0)
146
147#define TAG(x) radeon##x##_ARGB8888
148#include "spantmp.h"
149
150
151
152/* ================================================================
153 * Depth buffer
154 */
155
156/* The Radeon family has depth tiling on all the time, so we have to convert
157 * the x,y coordinates into the memory bus address (mba) in the same
158 * manner as the engine.  In each case, the linear block address (ba)
159 * is calculated, and then wired with x and y to produce the final
160 * memory address.
161 * The chip will do address translation on its own if the surface registers
162 * are set up correctly. It is not quite enough to get it working with hyperz too...
163 */
164
165static GLuint radeon_mba_z32( radeonContextPtr rmesa,
166				       GLint x, GLint y )
167{
168   GLuint pitch = rmesa->radeonScreen->frontPitch;
169   if (rmesa->radeonScreen->depthHasSurface) {
170      return 4*(x + y*pitch);
171   }
172   else {
173      GLuint ba, address = 0;			/* a[0..1] = 0           */
174
175      ba = (y / 16) * (pitch / 16) + (x / 16);
176
177      address |= (x & 0x7) << 2;			/* a[2..4] = x[0..2]     */
178      address |= (y & 0x3) << 5;			/* a[5..6] = y[0..1]     */
179      address |=
180         (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;	/* a[7]    = x[4] ^ y[2] */
181      address |= (ba & 0x3) << 8;			/* a[8..9] = ba[0..1]    */
182
183      address |= (y & 0x8) << 7;			/* a[10]   = y[3]        */
184      address |=
185         (((x & 0x8) << 1) ^ (y & 0x10)) << 7;	/* a[11]   = x[3] ^ y[4] */
186      address |= (ba & ~0x3) << 10;		/* a[12..] = ba[2..]     */
187
188      return address;
189   }
190}
191
192static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y )
193{
194   GLuint pitch = rmesa->radeonScreen->frontPitch;
195   if (rmesa->radeonScreen->depthHasSurface) {
196      return 2*(x + y*pitch);
197   }
198   else {
199      GLuint ba, address = 0;			/* a[0]    = 0           */
200
201      ba = (y / 16) * (pitch / 32) + (x / 32);
202
203      address |= (x & 0x7) << 1;			/* a[1..3] = x[0..2]     */
204      address |= (y & 0x7) << 4;			/* a[4..6] = y[0..2]     */
205      address |= (x & 0x8) << 4;			/* a[7]    = x[3]        */
206      address |= (ba & 0x3) << 8;			/* a[8..9] = ba[0..1]    */
207      address |= (y & 0x8) << 7;			/* a[10]   = y[3]        */
208      address |= ((x & 0x10) ^ (y & 0x10)) << 7;	/* a[11]   = x[4] ^ y[4] */
209      address |= (ba & ~0x3) << 10;		/* a[12..] = ba[2..]     */
210
211      return address;
212   }
213}
214
215
216/* 16-bit depth buffer functions
217 */
218#define WRITE_DEPTH( _x, _y, d )					\
219   *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo )) = d;
220
221#define READ_DEPTH( d, _x, _y )						\
222   d = *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo ));
223
224#define TAG(x) radeon##x##_16
225#include "depthtmp.h"
226
227/* 24 bit depth, 8 bit stencil depthbuffer functions
228 */
229#define WRITE_DEPTH( _x, _y, d )					\
230do {									\
231   GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo );		\
232   GLuint tmp = *(GLuint *)(buf + offset);				\
233   tmp &= 0xff000000;							\
234   tmp |= ((d) & 0x00ffffff);						\
235   *(GLuint *)(buf + offset) = tmp;					\
236} while (0)
237
238#define READ_DEPTH( d, _x, _y )						\
239   d = *(GLuint *)(buf + radeon_mba_z32( rmesa, _x + xo,		\
240					 _y + yo )) & 0x00ffffff;
241
242#define TAG(x) radeon##x##_24_8
243#include "depthtmp.h"
244
245
246/* ================================================================
247 * Stencil buffer
248 */
249
250/* 24 bit depth, 8 bit stencil depthbuffer functions
251 */
252#define WRITE_STENCIL( _x, _y, d )					\
253do {									\
254   GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo );		\
255   GLuint tmp = *(GLuint *)(buf + offset);				\
256   tmp &= 0x00ffffff;							\
257   tmp |= (((d) & 0xff) << 24);						\
258   *(GLuint *)(buf + offset) = tmp;					\
259} while (0)
260
261#define READ_STENCIL( d, _x, _y )					\
262do {									\
263   GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo );		\
264   GLuint tmp = *(GLuint *)(buf + offset);				\
265   tmp &= 0xff000000;							\
266   d = tmp >> 24;							\
267} while (0)
268
269#define TAG(x) radeon##x##_24_8
270#include "stenciltmp.h"
271
272
273/*
274 * This function is called to specify which buffer to read and write
275 * for software rasterization (swrast) fallbacks.  This doesn't necessarily
276 * correspond to glDrawBuffer() or glReadBuffer() calls.
277 */
278static void radeonSetBuffer( GLcontext *ctx,
279                             GLframebuffer *colorBuffer,
280                             GLuint bufferBit )
281{
282   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
283
284   switch ( bufferBit ) {
285   case BUFFER_BIT_FRONT_LEFT:
286      if ( rmesa->sarea->pfCurrentPage == 1 ) {
287        rmesa->state.pixel.readOffset = rmesa->radeonScreen->backOffset;
288        rmesa->state.pixel.readPitch  = rmesa->radeonScreen->backPitch;
289        rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
290        rmesa->state.color.drawPitch  = rmesa->radeonScreen->backPitch;
291      } else {
292      	rmesa->state.pixel.readOffset = rmesa->radeonScreen->frontOffset;
293      	rmesa->state.pixel.readPitch  = rmesa->radeonScreen->frontPitch;
294      	rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
295      	rmesa->state.color.drawPitch  = rmesa->radeonScreen->frontPitch;
296      }
297      break;
298   case BUFFER_BIT_BACK_LEFT:
299      if ( rmesa->sarea->pfCurrentPage == 1 ) {
300      	rmesa->state.pixel.readOffset = rmesa->radeonScreen->frontOffset;
301      	rmesa->state.pixel.readPitch  = rmesa->radeonScreen->frontPitch;
302      	rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
303      	rmesa->state.color.drawPitch  = rmesa->radeonScreen->frontPitch;
304      } else {
305        rmesa->state.pixel.readOffset = rmesa->radeonScreen->backOffset;
306        rmesa->state.pixel.readPitch  = rmesa->radeonScreen->backPitch;
307        rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
308        rmesa->state.color.drawPitch  = rmesa->radeonScreen->backPitch;
309      }
310      break;
311   default:
312      assert(0);
313      break;
314   }
315}
316
317/* Move locking out to get reasonable span performance (10x better
318 * than doing this in HW_LOCK above).  WaitForIdle() is the main
319 * culprit.
320 */
321
322static void radeonSpanRenderStart( GLcontext *ctx )
323{
324   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
325
326   RADEON_FIREVERTICES( rmesa );
327   LOCK_HARDWARE( rmesa );
328   radeonWaitForIdleLocked( rmesa );
329}
330
331static void radeonSpanRenderFinish( GLcontext *ctx )
332{
333   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
334   _swrast_flush( ctx );
335   UNLOCK_HARDWARE( rmesa );
336}
337
338void radeonInitSpanFuncs( GLcontext *ctx )
339{
340   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
341   struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
342
343   swdd->SetBuffer = radeonSetBuffer;
344
345   switch ( rmesa->radeonScreen->cpp ) {
346   case 2:
347#if 0
348      swdd->WriteRGBASpan	= radeonWriteRGBASpan_RGB565;
349      swdd->WriteRGBSpan	= radeonWriteRGBSpan_RGB565;
350      swdd->WriteMonoRGBASpan	= radeonWriteMonoRGBASpan_RGB565;
351      swdd->WriteRGBAPixels	= radeonWriteRGBAPixels_RGB565;
352      swdd->WriteMonoRGBAPixels	= radeonWriteMonoRGBAPixels_RGB565;
353      swdd->ReadRGBASpan	= radeonReadRGBASpan_RGB565;
354      swdd->ReadRGBAPixels      = radeonReadRGBAPixels_RGB565;
355#endif
356      break;
357
358   case 4:
359#if 0
360      swdd->WriteRGBASpan	= radeonWriteRGBASpan_ARGB8888;
361      swdd->WriteRGBSpan	= radeonWriteRGBSpan_ARGB8888;
362      swdd->WriteMonoRGBASpan   = radeonWriteMonoRGBASpan_ARGB8888;
363      swdd->WriteRGBAPixels     = radeonWriteRGBAPixels_ARGB8888;
364      swdd->WriteMonoRGBAPixels = radeonWriteMonoRGBAPixels_ARGB8888;
365      swdd->ReadRGBASpan	= radeonReadRGBASpan_ARGB8888;
366      swdd->ReadRGBAPixels      = radeonReadRGBAPixels_ARGB8888;
367#endif
368      break;
369
370   default:
371      break;
372   }
373
374   switch ( rmesa->glCtx->Visual.depthBits ) {
375   case 16:
376#if 0
377      swdd->ReadDepthSpan	= radeonReadDepthSpan_16;
378      swdd->WriteDepthSpan	= radeonWriteDepthSpan_16;
379      swdd->ReadDepthPixels	= radeonReadDepthPixels_16;
380      swdd->WriteDepthPixels	= radeonWriteDepthPixels_16;
381#endif
382      break;
383
384   case 24:
385#if 0
386      swdd->ReadDepthSpan	= radeonReadDepthSpan_24_8;
387      swdd->WriteDepthSpan	= radeonWriteDepthSpan_24_8;
388      swdd->ReadDepthPixels	= radeonReadDepthPixels_24_8;
389      swdd->WriteDepthPixels	= radeonWriteDepthPixels_24_8;
390
391      swdd->ReadStencilSpan	= radeonReadStencilSpan_24_8;
392      swdd->WriteStencilSpan	= radeonWriteStencilSpan_24_8;
393      swdd->ReadStencilPixels	= radeonReadStencilPixels_24_8;
394      swdd->WriteStencilPixels	= radeonWriteStencilPixels_24_8;
395#endif
396      break;
397
398   default:
399      break;
400   }
401
402   swdd->SpanRenderStart          = radeonSpanRenderStart;
403   swdd->SpanRenderFinish         = radeonSpanRenderFinish;
404}
405
406
407/**
408 * Plug in the Get/Put routines for the given driRenderbuffer.
409 */
410void
411radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
412{
413   if (drb->Base.InternalFormat == GL_RGBA) {
414      if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
415         drb->Base.GetRow        = radeonReadRGBASpan_RGB565;
416         drb->Base.GetValues     = radeonReadRGBAPixels_RGB565;
417         drb->Base.PutRow        = radeonWriteRGBASpan_RGB565;
418         drb->Base.PutRowRGB     = radeonWriteRGBSpan_RGB565;
419         drb->Base.PutMonoRow    = radeonWriteMonoRGBASpan_RGB565;
420         drb->Base.PutValues     = radeonWriteRGBAPixels_RGB565;
421         drb->Base.PutMonoValues = radeonWriteMonoRGBAPixels_RGB565;
422      }
423      else {
424         drb->Base.GetRow        = radeonReadRGBASpan_ARGB8888;
425         drb->Base.GetValues     = radeonReadRGBAPixels_ARGB8888;
426         drb->Base.PutRow        = radeonWriteRGBASpan_ARGB8888;
427         drb->Base.PutRowRGB     = radeonWriteRGBSpan_ARGB8888;
428         drb->Base.PutMonoRow    = radeonWriteMonoRGBASpan_ARGB8888;
429         drb->Base.PutValues     = radeonWriteRGBAPixels_ARGB8888;
430         drb->Base.PutMonoValues = radeonWriteMonoRGBAPixels_ARGB8888;
431      }
432   }
433   else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
434      drb->Base.GetRow        = radeonReadDepthSpan_16;
435      drb->Base.GetValues     = radeonReadDepthPixels_16;
436      drb->Base.PutRow        = radeonWriteDepthSpan_16;
437      drb->Base.PutMonoRow    = radeonWriteMonoDepthSpan_16;
438      drb->Base.PutValues     = radeonWriteDepthPixels_16;
439      drb->Base.PutMonoValues = NULL;
440   }
441   else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
442      drb->Base.GetRow        = radeonReadDepthSpan_24_8;
443      drb->Base.GetValues     = radeonReadDepthPixels_24_8;
444      drb->Base.PutRow        = radeonWriteDepthSpan_24_8;
445      drb->Base.PutMonoRow    = radeonWriteMonoDepthSpan_24_8;
446      drb->Base.PutValues     = radeonWriteDepthPixels_24_8;
447      drb->Base.PutMonoValues = NULL;
448   }
449   else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
450      drb->Base.GetRow        = radeonReadStencilSpan_24_8;
451      drb->Base.GetValues     = radeonReadStencilPixels_24_8;
452      drb->Base.PutRow        = radeonWriteStencilSpan_24_8;
453      drb->Base.PutMonoRow    = radeonWriteMonoStencilSpan_24_8;
454      drb->Base.PutValues     = radeonWriteStencilPixels_24_8;
455      drb->Base.PutMonoValues = NULL;
456   }
457}
458