cpu.h revision bcde1092aca184dbd7860078af020de7d1e4e22f
1409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if !defined (__MIPS_CPU_H__) 2409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define __MIPS_CPU_H__ 3409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 4409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define TARGET_HAS_ICE 1 5409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 6409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ELF_MACHINE EM_MIPS 7409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 8409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPUState struct CPUMIPSState 9409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 10409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#include "config.h" 11409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#include "mips-defs.h" 12852088c7e08182c2de563872d558309815cbfa0dDavid 'Digit' Turner#include "exec/cpu-defs.h" 135425d40d2955e859097ded7a04913c3e7ee1a7b6David 'Digit' Turner#include "fpu/softfloat.h" 14409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 15409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// uint_fast8_t and uint_fast16_t not in <sys/int_types.h> 16409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// XXX: move that elsewhere 17409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 18409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef unsigned char uint_fast8_t; 19409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef unsigned int uint_fast16_t; 20409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 21409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 22409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSState; 23409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 24409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct r4k_tlb_t r4k_tlb_t; 25409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct r4k_tlb_t { 26409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong VPN; 27409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t PageMask; 28409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast8_t ASID; 29409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t G:1; 30409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t C0:3; 31409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t C1:3; 32409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t V0:1; 33409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t V1:1; 34409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t D0:1; 35409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t D1:1; 36409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong PFN[2]; 37409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 38409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 39409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 40409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSTLBContext { 41409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t nb_tlb; 42bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turner int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); 43409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli void (*helper_tlbwi) (void); 44409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli void (*helper_tlbwr) (void); 45409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli void (*helper_tlbp) (void); 46409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli void (*helper_tlbr) (void); 47409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli union { 48409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli struct { 49409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli r4k_tlb_t tlb[MIPS_TLB_MAX]; 50409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } r4k; 51409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } mmu; 52409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 53409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 54409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef union fpr_t fpr_t; 55409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliunion fpr_t { 56409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli float64 fd; /* ieee double precision */ 57409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli float32 fs[2];/* ieee single precision */ 58409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint64_t d; /* binary double fixed-point */ 59409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t w[2]; /* binary single fixed-point */ 60409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 61409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* define FP_ENDIAN_IDX to access the same location 62409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * in the fpr_t union regardless of the host endianess 63409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli */ 64409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if defined(HOST_WORDS_BIGENDIAN) 65409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli# define FP_ENDIAN_IDX 1 66409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#else 67409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli# define FP_ENDIAN_IDX 0 68409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 69409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 70409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 71409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSFPUContext { 72409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Floating point registers */ 73409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli fpr_t fpr[32]; 74409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli float_status fp_status; 75409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* fpu implementation/revision register (fir) */ 76409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t fcr0; 77409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_F64 22 78409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_L 21 79409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_W 20 80409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_3D 19 81409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_PS 18 82409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_D 17 83409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_S 16 84409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_PRID 8 85409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_REV 0 86409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* fcsr */ 87409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t fcr31; 88409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) 89409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) 90409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) 91409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 92409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 93409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 94409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) 95409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) 96409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) 97409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) 98409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_INEXACT 1 99409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_UNDERFLOW 2 100409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_OVERFLOW 4 101409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_DIV0 8 102409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_INVALID 16 103409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_UNIMPLEMENTED 32 104409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 105409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 106409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define NB_MMU_MODES 3 107409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 108409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 109409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSMVPContext { 110409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_MVPControl; 111409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_CPA 3 112409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_STLB 2 113409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_VPC 1 114409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_EVP 0 115409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_MVPConf0; 116409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_M 31 117409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_TLBS 29 118409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_GS 28 119409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PCP 27 120409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PTLBE 16 121409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_TCA 15 122409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PVPE 10 123409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PTC 0 124409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_MVPConf1; 125409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_CIM 31 126409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_CIF 30 127409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_PCX 20 128409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_PCP2 10 129409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_PCP1 0 130409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 131409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 132409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct mips_def_t mips_def_t; 133409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 134409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_SHADOW_SET_MAX 16 135409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_TC_MAX 5 136409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_FPU_MAX 1 137409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_DSP_ACC 4 138409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 139409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct TCState TCState; 140409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct TCState { 141409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong gpr[32]; 142409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong PC; 143409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong HI[MIPS_DSP_ACC]; 144409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong LO[MIPS_DSP_ACC]; 145409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong ACX[MIPS_DSP_ACC]; 146409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong DSPControl; 147409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TCStatus; 148409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU3 31 149409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU2 30 150409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU1 29 151409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU0 28 152409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TMX 27 153409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_RNST 23 154409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TDS 21 155409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_DT 20 156409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_DA 15 157409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_A 13 158409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TKSU 11 159409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_IXMT 10 160409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TASID 0 161409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TCBind; 162409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCBd_CurTC 21 163409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCBd_TBE 17 164409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCBd_CurVPE 0 165409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCHalt; 166409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCContext; 167409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCSchedule; 168409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCScheFBack; 169409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Debug_tcstatus; 170409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 171409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 172409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSState CPUMIPSState; 173409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSState { 174409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli TCState active_tc; 175409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSFPUContext active_fpu; 176409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 177409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t current_tc; 178409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t current_fpu; 179409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 180409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t SEGBITS; 181409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t PABITS; 182409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong SEGMask; 183409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong PAMask; 184409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 185409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Index; 186409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* CP0_MVP* are per MVP registers. */ 187409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Random; 188409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEControl; 189409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_YSI 21 190409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_GSI 20 191409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_EXCPT 16 192409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_TE 15 193409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_TargTC 0 194409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEConf0; 195409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_M 31 196409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_XTC 21 197409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_TCS 19 198409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_SCS 18 199409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_DSC 17 200409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_ICS 16 201409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_MVP 1 202409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_VPA 0 203409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEConf1; 204409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC1_NCX 20 205409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC1_NCP2 10 206409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC1_NCP1 0 207409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_YQMask; 208409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_VPESchedule; 209409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_VPEScheFBack; 210409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEOpt; 211409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX7 15 212409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX6 14 213409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX5 13 214409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX4 12 215409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX3 11 216409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX2 10 217409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX1 9 218409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX0 8 219409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX7 7 220409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX6 6 221409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX5 5 222409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX4 4 223409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX3 3 224409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX2 2 225409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX1 1 226409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX0 0 227409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EntryLo0; 228409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EntryLo1; 229409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_Context; 230409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PageMask; 231409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PageGrain; 232409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Wired; 233409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf0_rw_bitmask; 234409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf0; 235409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_M 31 236409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_SRS3 20 237409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_SRS2 10 238409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_SRS1 0 239409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf1_rw_bitmask; 240409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf1; 241409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_M 31 242409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_SRS6 20 243409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_SRS5 10 244409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_SRS4 0 245409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf2_rw_bitmask; 246409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf2; 247409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_M 31 248409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_SRS9 20 249409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_SRS8 10 250409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_SRS7 0 251409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf3_rw_bitmask; 252409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf3; 253409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_M 31 254409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_SRS12 20 255409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_SRS11 10 256409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_SRS10 0 257409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf4_rw_bitmask; 258409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf4; 259409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC4_SRS15 20 260409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC4_SRS14 10 261409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC4_SRS13 0 262409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_HWREna; 263409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_BadVAddr; 264409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Count; 265409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EntryHi; 266409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Compare; 267409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Status; 268409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU3 31 269409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU2 30 270409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU1 29 271409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU0 28 272409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_RP 27 273409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_FR 26 274409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_RE 25 275409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_MX 24 276409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_PX 23 277409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_BEV 22 278409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_TS 21 279409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_SR 20 280409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_NMI 19 281409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_IM 8 282409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_KX 7 283409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_SX 6 284409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_UX 5 285409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_KSU 3 286409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_ERL 2 287409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_EXL 1 288409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_IE 0 289409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_IntCtl; 290409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0IntCtl_IPTI 29 291409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0IntCtl_IPPC1 26 292409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0IntCtl_VS 5 293409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSCtl; 294409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_HSS 26 295409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_EICSS 18 296409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_ESS 12 297409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_PSS 6 298409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_CSS 0 299409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSMap; 300409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV7 28 301409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV6 24 302409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV5 20 303409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV4 16 304409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV3 12 305409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV2 8 306409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV1 4 307409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV0 0 308409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Cause; 309409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_BD 31 310409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_TI 30 311409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_CE 28 312409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_DC 27 313409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_PCI 26 314409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_IV 23 315409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_WP 22 316409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_IP 8 317409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_IP_mask 0x0000FF00 318409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_EC 2 319409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EPC; 320409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PRid; 321409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_EBase; 322409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config0; 323409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_M 31 324409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_K23 28 325409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_KU 25 326409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_MDU 20 327409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_MM 17 328409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_BM 16 329409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_BE 15 330409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_AT 13 331409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_AR 10 332409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_MT 7 333409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_VI 3 334409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_K0 0 335409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config1; 336409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_M 31 337409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_MMU 25 338409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_IS 22 339409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_IL 19 340409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_IA 16 341409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_DS 13 342409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_DL 10 343409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_DA 7 344409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_C2 6 345409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_MD 5 346409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_PC 4 347409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_WR 3 348409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_CA 2 349409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_EP 1 350409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_FP 0 351409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config2; 352409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_M 31 353409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TU 28 354409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TS 24 355409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TL 20 356409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TA 16 357409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SU 12 358409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SS 8 359409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SL 4 360409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SA 0 361409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config3; 362409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_M 31 363409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_DSPP 10 364409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_LPA 7 365409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_VEIC 6 366409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_VInt 5 367409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_SP 4 368409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_MT 2 369409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_SM 1 370409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_TL 0 371409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config6; 372409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config7; 373409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* XXX: Maybe make LLAddr per-TC? */ 374409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong lladdr; 375409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong llval; 376409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong llnewval; 377409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong llreg; 378409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_LLAddr_rw_bitmask; 379409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int CP0_LLAddr_shift; 380409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_WatchLo[8]; 381409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_WatchHi[8]; 382409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_XContext; 383409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Framemask; 384409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Debug; 385409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DBD 31 386409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DM 30 387409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_LSNM 28 388409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_Doze 27 389409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_Halt 26 390409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_CNT 25 391409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_IBEP 24 392409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DBEP 21 393409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_IEXI 20 394409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_VER 15 395409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DEC 10 396409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_SSt 8 397409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DINT 5 398409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DIB 4 399409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DDBS 3 400409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DDBL 2 401409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DBp 1 402409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DSS 0 403409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_DEPC; 404409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Performance0; 405409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TagLo; 406409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_DataLo; 407409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TagHi; 408409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_DataHi; 409409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_ErrorEPC; 410409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_DESAVE; 411409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* We waste some space so we can handle shadow registers like TCs. */ 412409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli TCState tcs[MIPS_SHADOW_SET_MAX]; 413409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 414409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Qemu */ 415409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int error_code; 416409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t hflags; /* CPU State */ 417409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* TMASK defines different execution modes */ 418409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_TMASK 0x03FF 419409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_MODE 0x0007 /* execution modes */ 420409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The KSU flags must be the lowest bits in hflags. The flag order 421409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli must be the same as defined for CP0 Status. This allows to use 422409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli the bits as the value of mmu_idx. */ 423409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */ 424409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_UM 0x0002 /* user mode flag */ 425409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */ 426409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */ 427409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_DM 0x0004 /* Debug mode */ 428409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */ 429409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */ 430409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */ 431409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */ 432409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* True if the MIPS IV COP1X instructions can be used. This also 433409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 434409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli and RSQRT.D. */ 435409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ 436409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ 437409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ 438409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* If translation is interrupted between the branch instruction and 439409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * the delay slot, record what type of branch it is so that we can 440409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * resume translation properly. It might be possible to reduce 441409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * this from three bits to two. */ 442409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BMASK 0x1C00 443409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ 444409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ 445409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ 446409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ 447409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong btarget; /* Jump / branch target */ 448409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong bcond; /* Branch condition (if needed) */ 449409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 450409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int SYNCI_Step; /* Address step size for SYNCI */ 451409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int CCRes; /* Cycle count resolution/divisor */ 452409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 453409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 454409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int insn_flags; /* Supported instruction set */ 455409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 456409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong tls_value; /* For usermode emulation */ 457409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 458409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPU_COMMON 459409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 460409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSMVPContext *mvp; 461409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSTLBContext *tlb; 462409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 463409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli const mips_def_t *cpu_model; 464409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli void *irq[8]; 465409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli struct QEMUTimer *timer; /* Internal timer */ 466409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 467409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 468bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerint no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 469409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong address, int rw, int access_type); 470bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerint fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 471409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong address, int rw, int access_type); 472bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerint r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 473409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong address, int rw, int access_type); 474409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid r4k_helper_tlbwi (void); 475409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid r4k_helper_tlbwr (void); 476409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid r4k_helper_tlbp (void); 477409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid r4k_helper_tlbr (void); 478409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); 479409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 480bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnervoid do_unassigned_access(hwaddr addr, int is_write, int is_exec, 481409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int unused, int size); 482409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 483409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_init cpu_mips_init 484409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_exec cpu_mips_exec 485409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_gen_code cpu_mips_gen_code 486409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_signal_handler cpu_mips_signal_handler 487409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_list mips_cpu_list 488409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 489409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_SAVE_VERSION 3 490409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 491409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MMU modes definitions. We carefully match the indices with our 492409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli hflags layout. */ 493409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_MODE0_SUFFIX _kernel 494409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_MODE1_SUFFIX _super 495409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_MODE2_SUFFIX _user 496409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_USER_IDX 2 497409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic inline int cpu_mmu_index (CPUState *env) 498409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 499409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli return env->hflags & MIPS_HFLAG_KSU; 500409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 501409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 502325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapallistatic inline int is_cpu_user (CPUState *env) 503325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli{ 504325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli#ifdef CONFIG_USER_ONLY 505325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli return 1; 506325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli#else 507325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli return ((env->CP0_Status & 508325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli ((3 << CP0St_KSU) | (1 << CP0St_ERL) | (1 << CP0St_EXL))) == (3 << CP0St_KSU)); 509325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli#endif // CONFIG_USER_ONLY 510325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli} 511325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli 512409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic inline void cpu_clone_regs(CPUState *env, target_ulong newsp) 513409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 514409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli if (newsp) 515409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.gpr[29] = newsp; 516409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.gpr[7] = 0; 517409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.gpr[2] = 0; 518409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 519409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 520741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapallistatic inline int cpu_mips_hw_interrupts_pending(CPUState *env) 521741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli{ 522741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int32_t pending; 523741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int32_t status; 524741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int r; 525741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 526741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli if (!(env->CP0_Status & (1 << CP0St_IE)) || 527741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli (env->CP0_Status & (1 << CP0St_EXL)) || 528741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli (env->CP0_Status & (1 << CP0St_ERL)) || 529741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli (env->hflags & MIPS_HFLAG_DM)) { 530741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli /* Interrupts are disabled */ 531741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli return 0; 532741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } 533741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 534741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli pending = env->CP0_Cause & CP0Ca_IP_mask; 535741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli status = env->CP0_Status & CP0Ca_IP_mask; 536741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 537741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 538741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli /* A MIPS configured with a vectorizing external interrupt controller 539741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli will feed a vector into the Cause pending lines. The core treats 540741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli the status lines as a vector level, not as indiviual masks. */ 541741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli r = pending > status; 542741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } else { 543741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli /* A MIPS configured with compatibility or VInt (Vectored Interrupts) 544741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli treats the pending lines as individual interrupt lines, the status 545741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli lines are individual masks. */ 546741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli r = pending & status; 547741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } 548741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli return r; 549741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli} 550741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 551852088c7e08182c2de563872d558309815cbfa0dDavid 'Digit' Turner#include "exec/cpu-all.h" 552852088c7e08182c2de563872d558309815cbfa0dDavid 'Digit' Turner#include "exec/exec-all.h" 553409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 554409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Memory access type : 555409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * may be needed for precise access rights control and precise exceptions. 556409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli */ 557409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallienum { 558409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* 1 bit to define user level / supervisor access */ 559409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_USER = 0x00, 560409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_SUPER = 0x01, 561409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* 1 bit to indicate direction */ 562409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_STORE = 0x02, 563409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Type of instruction that generated the access */ 564409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_CODE = 0x10, /* Code fetch access */ 565409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_INT = 0x20, /* Integer load/store access */ 566409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_FLOAT = 0x30, /* floating point load/store access */ 567409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 568409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 569409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Exceptions */ 570409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallienum { 571409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_NONE = -1, 572409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_RESET = 0, 573409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_SRESET, 574409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DSS, 575409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DINT, 576409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DDBL, 577409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DDBS, 578409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_NMI, 579409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_MCHECK, 580409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_EXT_INTERRUPT, /* 8 */ 581409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DFWATCH, 582409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DIB, 583409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_IWATCH, 584409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_AdEL, 585409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_AdES, 586409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TLBF, 587409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_IBE, 588409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DBp, /* 16 */ 589409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_SYSCALL, 590409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_BREAK, 591409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_CpU, 592409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_RI, 593409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_OVERFLOW, 594409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TRAP, 595409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_FPE, 596409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DWATCH, /* 24 */ 597409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_LTLBL, 598409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TLBL, 599409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TLBS, 600409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DBE, 601409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_THREAD, 602409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_MDMX, 603409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_C2E, 604409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_CACHE, /* 32 */ 605409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 606409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_LAST = EXCP_CACHE, 607409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 608409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Dummy exception for conditional stores. */ 609409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define EXCP_SC 0x100 610409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 611409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliint cpu_mips_exec(CPUMIPSState *s); 612409c7b66435cf5947cab6bf0710f92507317f22eBhanu ChetlapalliCPUMIPSState *cpu_mips_init(const char *cpu_model); 613409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli//~ uint32_t cpu_mips_get_clock (void); 614409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliint cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 615409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 616409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* mips_timer.c */ 617409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliuint32_t cpu_mips_get_random (CPUState *env); 618409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliuint32_t cpu_mips_get_count (CPUState *env); 619409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid cpu_mips_store_count (CPUState *env, uint32_t value); 620409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid cpu_mips_store_compare (CPUState *env, uint32_t value); 621409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid cpu_mips_start_count(CPUState *env); 622409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid cpu_mips_stop_count(CPUState *env); 623409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 624409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* mips_int.c */ 625409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid cpu_mips_update_irq (CPUState *env); 626409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 627409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* helper.c */ 628409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliint cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, 629409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int mmu_idx, int is_softmmu); 630409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault 631409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid do_interrupt (CPUState *env); 632bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerhwaddr cpu_mips_translate_address (CPUState *env, target_ulong address, 633409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int rw); 634409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 635409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) 636409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 637409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.PC = tb->pc; 638409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->hflags &= ~MIPS_HFLAG_BMASK; 639409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->hflags |= tb->flags & MIPS_HFLAG_BMASK; 640409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 641409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 642409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, 643409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong *cs_base, int *flags) 644409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 645409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli *pc = env->active_tc.PC; 646409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli *cs_base = 0; 647409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); 648409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 649409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 650409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic inline void cpu_set_tls(CPUState *env, target_ulong newtls) 651409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 652409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tls_value = newtls; 653409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 654409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 655409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif /* !defined (__MIPS_CPU_H__) */ 656