1ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 2ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 3ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*--- begin host_amd64_defs.h ---*/ 4ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 5ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 6ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* 7ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown This file is part of Valgrind, a dynamic binary instrumentation 8ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown framework. 9ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 10436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Copyright (C) 2004-2013 OpenWorks LLP 11ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown info@open-works.net 12ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 13ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown This program is free software; you can redistribute it and/or 14ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown modify it under the terms of the GNU General Public License as 15ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown published by the Free Software Foundation; either version 2 of the 16ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown License, or (at your option) any later version. 17ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 18ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown This program is distributed in the hope that it will be useful, but 19ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown WITHOUT ANY WARRANTY; without even the implied warranty of 20ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown General Public License for more details. 22ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 23ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown You should have received a copy of the GNU General Public License 24ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown along with this program; if not, write to the Free Software 25ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 02110-1301, USA. 27ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 28ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown The GNU General Public License is contained in the file COPYING. 29ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 30ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Neither the names of the U.S. Department of Energy nor the 31ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown University of California nor the names of its contributors may be 32ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown used to endorse or promote products derived from this software 33ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown without prior written permission. 34ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown*/ 35ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 36ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#ifndef __VEX_HOST_AMD64_DEFS_H 37ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#define __VEX_HOST_AMD64_DEFS_H 38ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 39436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#include "libvex_basictypes.h" 40436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#include "libvex.h" // VexArch 41436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#include "host_generic_regs.h" // HReg 42ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 43ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Registers. --------- */ 44ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 45ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* The usual HReg abstraction. There are 16 real int regs, 6 real 46ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown float regs, and 16 real vector regs. 47ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown*/ 48ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 49ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppHRegAMD64 ( HReg ); 50ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 51ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RAX ( void ); 52ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RBX ( void ); 53ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RCX ( void ); 54ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RDX ( void ); 55ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RSP ( void ); 56ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RBP ( void ); 57ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RSI ( void ); 58ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RDI ( void ); 59ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R8 ( void ); 60ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R9 ( void ); 61ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R10 ( void ); 62ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R11 ( void ); 63ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R12 ( void ); 64ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R13 ( void ); 65ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R14 ( void ); 66ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R15 ( void ); 67ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 68ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE0 ( void ); 69ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE1 ( void ); 70ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE2 ( void ); 71ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE3 ( void ); 72ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE4 ( void ); 73ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE5 ( void ); 74ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 75ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM0 ( void ); 76ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM1 ( void ); 77ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM3 ( void ); 78ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM4 ( void ); 79ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM5 ( void ); 80ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM6 ( void ); 81ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM7 ( void ); 82ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM8 ( void ); 83ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM9 ( void ); 84ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM10 ( void ); 85ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM11 ( void ); 86ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM12 ( void ); 87ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 88ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 89ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Condition codes, AMD encoding. --------- */ 90ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 91ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 92ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 93ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_O = 0, /* overflow */ 94ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NO = 1, /* no overflow */ 95ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 96ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_B = 2, /* below */ 97ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NB = 3, /* not below */ 98ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 99ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_Z = 4, /* zero */ 100ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NZ = 5, /* not zero */ 101ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 102ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_BE = 6, /* below or equal */ 103ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NBE = 7, /* not below or equal */ 104ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 105ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_S = 8, /* negative */ 106ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NS = 9, /* not negative */ 107ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 108ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_P = 10, /* parity even */ 109ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NP = 11, /* not parity even */ 110ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 111ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_L = 12, /* jump less */ 112ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NL = 13, /* not less */ 113ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 114ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_LE = 14, /* less or equal */ 115ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NLE = 15, /* not less or equal */ 116ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 117ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_ALWAYS = 16 /* the usual hack */ 118ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 119ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode; 120ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 121436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar* showAMD64CondCode ( AMD64CondCode ); 122ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 123ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 124ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Memory address expressions (amodes). --------- */ 125ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 126ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 127ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 128ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aam_IR, /* Immediate + Reg */ 129ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ 130ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 131ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AModeTag; 132ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 133ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 134ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 135ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AModeTag tag; 136ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 137ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 138ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm; 139ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 140ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } IR; 141ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 142ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm; 143ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg base; 144ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg index; 145ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int shift; /* 0, 1, 2 or 3 only */ 146ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } IRRS; 147ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Aam; 148ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 149ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode; 150ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 151ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64AMode* AMD64AMode_IR ( UInt, HReg ); 152ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int ); 153ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 154ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64AMode* dopyAMD64AMode ( AMD64AMode* ); 155ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 156ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64AMode ( AMD64AMode* ); 157ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 158ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 159ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Operand, which can be reg, immediate or memory. --------- */ 160ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 161ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 162ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 163ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi_Imm, 164ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi_Reg, 165ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi_Mem 166ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 167ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMITag; 168ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 169ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 170ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 171ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMITag tag; 172ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 173ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 174ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm32; 175ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Imm; 176ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 177ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 178ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Reg; 179ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 180ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* am; 181ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Mem; 182ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 183ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi; 184ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 185ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMI; 186ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 187ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RMI* AMD64RMI_Imm ( UInt ); 188ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RMI* AMD64RMI_Reg ( HReg ); 189ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* ); 190ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 191b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanovextern void ppAMD64RMI ( AMD64RMI* ); 192b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanovextern void ppAMD64RMI_lo32 ( AMD64RMI* ); 193ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 194ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 195ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Operand, which can be reg or immediate only. --------- */ 196ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 197ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 198ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 199ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ari_Imm, 200ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ari_Reg 201ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 202ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RITag; 203ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 204ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 205ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 206ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RITag tag; 207ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 208ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 209ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm32; 210ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Imm; 211ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 212ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 213ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Reg; 214ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 215ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ari; 216ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 217ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RI; 218ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 219ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RI* AMD64RI_Imm ( UInt ); 220ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RI* AMD64RI_Reg ( HReg ); 221ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 222ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64RI ( AMD64RI* ); 223ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 224ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 225ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Operand, which can be reg or memory only. --------- */ 226ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 227ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 228ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 229ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Arm_Reg, 230ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Arm_Mem 231ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 232ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMTag; 233ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 234ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 235ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 236ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMTag tag; 237ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 238ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 239ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 240ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Reg; 241ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 242ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* am; 243ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Mem; 244ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 245ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Arm; 246ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 247ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM; 248ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 249ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RM* AMD64RM_Reg ( HReg ); 250ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RM* AMD64RM_Mem ( AMD64AMode* ); 251ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 252ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64RM ( AMD64RM* ); 253ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 254ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 255ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Instructions. --------- */ 256ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 257ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 258ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 259ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 260ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aun_NEG, 261ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aun_NOT 262ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 263ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64UnaryOp; 264ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 265436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar* showAMD64UnaryOp ( AMD64UnaryOp ); 266ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 267ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 268ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 269ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 270ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 271ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_INVALID, 272ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_MOV, 273ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_CMP, 274ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB, 275ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_AND, Aalu_OR, Aalu_XOR, 276ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_MUL 277ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 278ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AluOp; 279ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 280436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar* showAMD64AluOp ( AMD64AluOp ); 281ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 282ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 283ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 284ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 285ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 286ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ash_INVALID, 287ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ash_SHL, Ash_SHR, Ash_SAR 288ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 289ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64ShiftOp; 290ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 291436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar* showAMD64ShiftOp ( AMD64ShiftOp ); 292ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 293ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 294ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 295ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 296ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 297ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_INVALID, 298ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Binary */ 299ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_SCALE, Afp_ATAN, Afp_YL2X, Afp_YL2XP1, Afp_PREM, Afp_PREM1, 300ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Unary */ 301ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_SQRT, 302ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_SIN, Afp_COS, Afp_TAN, 303ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_ROUND, Afp_2XM1 304ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 305ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown A87FpOp; 306ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 307436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar* showA87FpOp ( A87FpOp ); 308ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 309ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 310ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 311ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 312ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 313ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_INVALID, 314ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* mov */ 315ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MOV, 316ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Floating point binary */ 317ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF, 318ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MAXF, Asse_MINF, 319ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_CMPEQF, Asse_CMPLTF, Asse_CMPLEF, Asse_CMPUNF, 320ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Floating point unary */ 321ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_RCPF, Asse_RSQRTF, Asse_SQRTF, 322ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Bitwise */ 323ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN, 324ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_ADD8, Asse_ADD16, Asse_ADD32, Asse_ADD64, 325ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QADD8U, Asse_QADD16U, 326ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QADD8S, Asse_QADD16S, 327ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SUB8, Asse_SUB16, Asse_SUB32, Asse_SUB64, 328ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QSUB8U, Asse_QSUB16U, 329ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QSUB8S, Asse_QSUB16S, 330ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MUL16, 331ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MULHI16U, 332ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MULHI16S, 333ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_AVG8U, Asse_AVG16U, 334ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MAX16S, 335ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MAX8U, 336ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MIN16S, 337ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MIN8U, 338ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_CMPEQ8, Asse_CMPEQ16, Asse_CMPEQ32, 339ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_CMPGT8S, Asse_CMPGT16S, Asse_CMPGT32S, 340ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SHL16, Asse_SHL32, Asse_SHL64, 341ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SHR16, Asse_SHR32, Asse_SHR64, 342ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SAR16, Asse_SAR32, 343ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_PACKSSD, Asse_PACKSSW, Asse_PACKUSW, 344ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_UNPCKHB, Asse_UNPCKHW, Asse_UNPCKHD, Asse_UNPCKHQ, 345ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_UNPCKLB, Asse_UNPCKLW, Asse_UNPCKLD, Asse_UNPCKLQ 346ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 347ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp; 348ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 349436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar* showAMD64SseOp ( AMD64SseOp ); 350ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 351ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 352ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 353ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 354ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 355ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Imm64, /* Generate 64-bit literal to register */ 356ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Alu64R, /* 64-bit mov/arith/logical, dst=REG */ 357ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Alu64M, /* 64-bit mov/arith/logical, dst=MEM */ 358ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sh64, /* 64-bit shift/rotate, dst=REG or MEM */ 359ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Test64, /* 64-bit test (AND, set flags, discard result) */ 360ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Unary64, /* 64-bit not and neg */ 361ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Lea64, /* 64-bit compute EA into a reg */ 362b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov Ain_Alu32R, /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */ 363ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_MulL, /* widening multiply */ 364ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Div, /* div and mod */ 365ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Push, /* push 64-bit value on stack */ 366ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Call, /* call to address in register */ 367663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_XDirect, /* direct transfer to GA */ 368663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_XIndir, /* indirect transfer to GA */ 369663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_XAssisted, /* assisted transfer to GA */ 370ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_CMov64, /* conditional move */ 371ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_MovxLQ, /* reg-reg move, zx-ing/sx-ing top half */ 372ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ 373ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Store, /* store 32/16/8 bit value in memory */ 374ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Set64, /* convert condition code to 64-bit value */ 375ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Bsfr64, /* 64-bit bsf/bsr */ 376ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_MFence, /* mem fence */ 377ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_ACAS, /* 8/16/32/64-bit lock;cmpxchg */ 378ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_DACAS, /* lock;cmpxchg8b/16b (doubleword ACAS, 2 x 379ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 32-bit or 2 x 64-bit only) */ 380ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87Free, /* free up x87 registers */ 381ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87PushPop, /* x87 loads/stores */ 382ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87FpOp, /* x87 operations */ 383ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87LdCW, /* load x87 control word */ 384ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87StSW, /* store x87 status word */ 385ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_LdMXCSR, /* load %mxcsr */ 386ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int 387ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown register */ 388ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseSI2SF, /* scalar 32/64 int to 32/64 float conversion */ 389ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseSF2SI, /* scalar 32/64 float to 32/64 int conversion */ 390ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseSDSS, /* scalar float32 to/from float64 */ 391ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment 392ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown constraints, upper 96/64/0 bits arbitrary */ 393ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ 394ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse32Fx4, /* SSE binary, 32Fx4 */ 395ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */ 396ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse64Fx2, /* SSE binary, 64Fx2 */ 397ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */ 398ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */ 399ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseCMov, /* SSE conditional move */ 400663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_SseShuf, /* SSE2 shuffle (pshufd) */ 401663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu Ain_AvxLdSt, /* AVX load/store 256 bits, 402663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu no alignment constraints */ 403663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu Ain_AvxReRg, /* AVX binary general reg-reg, Re, Rg */ 404663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_EvCheck, /* Event check */ 405663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_ProfInc /* 64-bit profile counter increment */ 406ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 407ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64InstrTag; 408ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 409ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* Destinations are on the RIGHT (second operand) */ 410ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 411ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 412ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 413ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64InstrTag tag; 414ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 415ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 416ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown ULong imm64; 417ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 418ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Imm64; 419ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 420ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AluOp op; 421ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMI* src; 422ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 423ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Alu64R; 424ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 425ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AluOp op; 426ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RI* src; 427ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* dst; 428ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Alu64M; 429ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 430ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64ShiftOp op; 431ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt src; /* shift amount, or 0 means %cl */ 432ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 433ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sh64; 434ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 435ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm32; 436ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 437ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Test64; 438ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Not and Neg */ 439ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 440ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64UnaryOp op; 441ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 442ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Unary64; 443ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 64-bit compute EA into a reg */ 444ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 445ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* am; 446ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 447ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Lea64; 448b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */ 449b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov struct { 450b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov AMD64AluOp op; 451b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov AMD64RMI* src; 452b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov HReg dst; 453b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov } Alu32R; 454ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 64 x 64 -> 128 bit widening multiply: RDX:RAX = RAX *s/u 455ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown r/m64 */ 456ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 457ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 458ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM* src; 459ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } MulL; 460ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* amd64 div/idiv instruction. Modifies RDX and RAX and 461ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown reads src. */ 462ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 463ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 464ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int sz; /* 4 or 8 only */ 465ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM* src; 466ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Div; 467ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 468ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMI* src; 469ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Push; 470ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Pseudo-insn. Call target (an absolute address), on given 471ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown condition (which could be Xcc_ALWAYS). */ 472ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 473ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 474ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Addr64 target; 475ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int regparms; /* 0 .. 6 */ 476436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov RetLoc rloc; /* where the return value will be */ 477ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Call; 478663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Update the guest RIP value, then exit requesting to chain 479663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng to it. May be conditional. */ 480663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 481663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Addr64 dstGA; /* next guest address */ 482663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amRIP; /* amode in guest state for RIP */ 483663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond; /* can be Acc_ALWAYS */ 484663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool toFastEP; /* chain to the slow or fast point? */ 485663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XDirect; 486663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Boring transfer to a guest address not known at JIT time. 487663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Not chainable. May be conditional. */ 488663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 489663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dstGA; 490663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amRIP; 491663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond; /* can be Acc_ALWAYS */ 492663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XIndir; 493663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Assisted transfer to a guest address, most general case. 494663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Not chainable. May be conditional. */ 495663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 496663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dstGA; 497663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amRIP; 498663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond; /* can be Acc_ALWAYS */ 499ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown IRJumpKind jk; 500663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XAssisted; 501ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Mov src to dst on the given condition, which may not 502ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown be the bogus Acc_ALWAYS. */ 503ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 504ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 505ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM* src; 506ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 507ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } CMov64; 508ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* reg-reg move, sx-ing/zx-ing top half */ 509ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 510ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 511ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 512ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 513ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } MovxLQ; 514ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Sign/Zero extending loads. Dst size is always 64 bits. */ 515ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 516ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szSmall; /* only 1, 2 or 4 */ 517ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 518ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* src; 519ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 520ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } LoadEX; 521ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 32/16/8 bit stores. */ 522ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 523ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* only 1, 2 or 4 */ 524ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 525ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* dst; 526ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Store; 527ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Convert an amd64 condition code to a 64-bit value (0 or 1). */ 528ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 529ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 530ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 531ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Set64; 532ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 64-bit bsf or bsr. */ 533ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 534ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool isFwds; 535ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 536ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 537ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Bsfr64; 538ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Mem fence. In short, an insn which flushes all preceding 539ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown loads and stores as much as possible before continuing. 540ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown On AMD64 we emit a real "mfence". */ 541ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 542ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } MFence; 543ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 544ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 545ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 1, 2, 4 or 8 */ 546ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } ACAS; 547ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 548ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 549ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 4 or 8 only */ 550ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } DACAS; 551ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 552ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* --- X87 --- */ 553ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 554ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* A very minimal set of x87 insns, that operate exactly in a 555ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown stack-like way so no need to think about x87 registers. */ 556ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 557ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Do 'ffree' on %st(7) .. %st(7-nregs) */ 558ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 559ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int nregs; /* 1 <= nregs <= 7 */ 560ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87Free; 561ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 562ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Push a 32- or 64-bit FP value from memory onto the stack, 563ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown or move a value from the stack to memory and remove it 564ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown from the stack. */ 565ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 566ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 567ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool isPush; 568ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szB; /* 4 or 8 */ 569ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87PushPop; 570ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 571ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Do an operation on the top-of-stack. This can be unary, in 572ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown which case it is %st0 = OP( %st0 ), or binary: %st0 = OP( 573ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown %st0, %st1 ). */ 574ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 575ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown A87FpOp op; 576ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87FpOp; 577ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 578ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Load the FPU control word. */ 579ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 580ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 581ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87LdCW; 582ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 583ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Store the FPU status word (fstsw m16) */ 584ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 585ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 586ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87StSW; 587ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 588ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* --- SSE --- */ 589ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 590ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Load 32 bits into %mxcsr. */ 591ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 592ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 593ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 594ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown LdMXCSR; 595ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* ucomisd/ucomiss, then get %rflags into int register */ 596ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 597ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 4 or 8 only */ 598ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg srcL; /* xmm */ 599ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg srcR; /* xmm */ 600ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; /* int */ 601ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseUComIS; 602ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* scalar 32/64 int to 32/64 float conversion */ 603ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 604ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szS; /* 4 or 8 */ 605ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szD; /* 4 or 8 */ 606ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; /* i class */ 607ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; /* v class */ 608ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseSI2SF; 609ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* scalar 32/64 float to 32/64 int conversion */ 610ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 611ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szS; /* 4 or 8 */ 612ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szD; /* 4 or 8 */ 613ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; /* v class */ 614ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; /* i class */ 615ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseSF2SI; 616ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* scalar float32 to/from float64 */ 617ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 618ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool from64; /* True: 64->32; False: 32->64 */ 619ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 620ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 621ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseSDSS; 622ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 623ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool isLoad; 624ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 4, 8 or 16 only */ 625ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 626ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 627ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseLdSt; 628ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 629ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int sz; /* 4 or 8 only */ 630ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 631ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 632ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseLdzLO; 633ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 634ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 635ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 636ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 637ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse32Fx4; 638ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 639ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 640ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 641ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 642ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse32FLo; 643ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 644ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 645ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 646ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 647ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse64Fx2; 648ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 649ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 650ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 651ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 652ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse64FLo; 653ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 654ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 655ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 656ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 657ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseReRg; 658ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Mov src to dst on the given condition, which may not 659ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown be the bogus Xcc_ALWAYS. */ 660ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 661ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 662ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 663ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 664ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseCMov; 665ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 666ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int order; /* 0 <= order <= 0xFF */ 667ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 668ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 669ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseShuf; 670663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu struct { 671663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu Bool isLoad; 672663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu HReg reg; 673663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu AMD64AMode* addr; 674663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu } AvxLdSt; 675663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu struct { 676663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu AMD64SseOp op; 677663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu HReg src; 678663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu HReg dst; 679663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu } AvxReRg; 680663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 681663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amCounter; 682663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amFailAddr; 683663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } EvCheck; 684663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 685663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* No fields. The address of the counter to inc is 686663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng installed later, post-translation, by patching it in, 687663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng as it is not known at translation time. */ 688663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } ProfInc; 689ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 690ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Ain; 691ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 692ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64Instr; 693ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 694ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ); 695ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg ); 696ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64AMode* ); 697ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst ); 698ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Lea64 ( AMD64AMode* am, HReg dst ); 699b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanovextern AMD64Instr* AMD64Instr_Alu32R ( AMD64AluOp, AMD64RMI*, HReg ); 700ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, HReg ); 701ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst ); 702ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* ); 703ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* ); 704ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); 705436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int, RetLoc ); 706663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP, 707663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond, Bool toFastEP ); 708663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_XIndir ( HReg dstGA, AMD64AMode* amRIP, 709663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond ); 710663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_XAssisted ( HReg dstGA, AMD64AMode* amRIP, 711663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond, IRJumpKind jk ); 712ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst ); 713ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst ); 714ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, 715ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* src, HReg dst ); 716ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); 717ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Set64 ( AMD64CondCode cond, HReg dst ); 718ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Bsfr64 ( Bool isFwds, HReg src, HReg dst ); 719ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_MFence ( void ); 720ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_ACAS ( AMD64AMode* addr, UChar sz ); 721ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_DACAS ( AMD64AMode* addr, UChar sz ); 722ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 723ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87Free ( Int nregs ); 724ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB ); 725ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op ); 726ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr ); 727ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr ); 728ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* ); 729ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ); 730ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst ); 731ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst ); 732ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst ); 733ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* ); 734ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* ); 735ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg ); 736ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg ); 737ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg ); 738ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg ); 739ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg ); 740ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst ); 741ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ); 742663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng//uu extern AMD64Instr* AMD64Instr_AvxLdSt ( Bool isLoad, HReg, AMD64AMode* ); 743663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng//uu extern AMD64Instr* AMD64Instr_AvxReRg ( AMD64SseOp, HReg, HReg ); 744663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_EvCheck ( AMD64AMode* amCounter, 745663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amFailAddr ); 746663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_ProfInc ( void ); 747ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 748ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 749ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64Instr ( AMD64Instr*, Bool ); 750ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 751ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* Some functions that insulate the register allocator from details 752ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown of the underlying instruction set. */ 753ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bool ); 754ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); 755ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); 756663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, 757663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar* buf, Int nbuf, AMD64Instr* i, 758663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64, 759663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_to_slowEP, 760663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_to_fastEP, 761663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_xindir, 762663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_xassisted ); 763ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 764ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 765ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg rreg, Int offset, Bool ); 766ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 767ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg rreg, Int offset, Bool ); 768ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 769ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void getAllocableRegs_AMD64 ( Int*, HReg** ); 770663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HInstrArray* iselSB_AMD64 ( IRSB*, 771663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexArch, 772663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexArchInfo*, 773663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexAbiInfo*, 774663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int offs_Host_EvC_Counter, 775663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int offs_Host_EvC_FailAddr, 776663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool chainingAllowed, 777663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool addProfInc, 778663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Addr64 max_ga ); 779663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 780663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* How big is an event check? This is kind of a kludge because it 781663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER, 782663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng and so assumes that they are both <= 128, and so can use the short 783663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng offset encoding. This is all checked with assertions, so in the 784663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng worst case we will merely assert at startup. */ 785663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Int evCheckSzB_AMD64 ( void ); 786663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 787663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Perform a chaining and unchaining of an XDirect jump. */ 788663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange chainXDirect_AMD64 ( void* place_to_chain, 789663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_EXPECTED, 790663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* place_to_jump_to ); 791663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 792663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain, 793663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* place_to_jump_to_EXPECTED, 794663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me ); 795663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 796663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Patch the counter location into an existing ProfInc point. */ 797663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange patchProfInc_AMD64 ( void* place_to_patch, 798663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng ULong* location_of_counter ); 799663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 800ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 801ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#endif /* ndef __VEX_HOST_AMD64_DEFS_H */ 802ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 803ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 804ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*--- end host_amd64_defs.h ---*/ 805ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 806