1ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Copyright 2013, ARM Limited 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 27ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#ifndef VIXL_A64_CONSTANTS_A64_H_ 28ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define VIXL_A64_CONSTANTS_A64_H_ 29ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 31ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 32ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst unsigned kNumberOfRegisters = 32; 33ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst unsigned kNumberOfFPRegisters = 32; 34ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Callee saved registers are x21-x30(lr). 35ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int kNumberOfCalleeSavedRegisters = 10; 36ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int kFirstCalleeSavedRegisterIndex = 21; 37ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Callee saved FP registers are d8-d15. 38ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int kNumberOfCalleeSavedFPRegisters = 8; 39ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int kFirstCalleeSavedFPRegisterIndex = 8; 40ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 41ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define REGISTER_CODE_LIST(R) \ 42ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlR(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 43ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlR(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 44ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlR(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 45ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlR(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 46ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 47578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#define INSTRUCTION_FIELDS_LIST(V_) \ 48ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Register fields */ \ 49578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Rd, 4, 0, Bits) /* Destination register. */ \ 50578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Rn, 9, 5, Bits) /* First source register. */ \ 51578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Rm, 20, 16, Bits) /* Second source register. */ \ 52578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Ra, 14, 10, Bits) /* Third source register. */ \ 53578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Rt, 4, 0, Bits) /* Load dest / store source. */ \ 54578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Rt2, 14, 10, Bits) /* Load second dest / */ \ 55ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl /* store second source. */ \ 56578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(PrefetchMode, 4, 0, Bits) \ 57ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 58ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Common bits */ \ 59578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(SixtyFourBits, 31, 31, Bits) \ 60578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(FlagsUpdate, 29, 29, Bits) \ 61ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 62ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* PC relative addressing */ \ 63578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmPCRelHi, 23, 5, SignedBits) \ 64578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmPCRelLo, 30, 29, Bits) \ 65ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 66ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Add/subtract/logical shift register */ \ 67578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ShiftDP, 23, 22, Bits) \ 68578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmDPShift, 15, 10, Bits) \ 69ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 70ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Add/subtract immediate */ \ 71578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmAddSub, 21, 10, Bits) \ 72578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ShiftAddSub, 23, 22, Bits) \ 73ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 74ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Add/substract extend */ \ 75578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmExtendShift, 12, 10, Bits) \ 76578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ExtendMode, 15, 13, Bits) \ 77ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 78ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Move wide */ \ 79578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmMoveWide, 20, 5, Bits) \ 80578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ShiftMoveWide, 22, 21, Bits) \ 81ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 82ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Logical immediate, bitfield and extract */ \ 83578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(BitN, 22, 22, Bits) \ 84578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmRotate, 21, 16, Bits) \ 85578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmSetBits, 15, 10, Bits) \ 86578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmR, 21, 16, Bits) \ 87578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmS, 15, 10, Bits) \ 88ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 89ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Test and branch immediate */ \ 90578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmTestBranch, 18, 5, SignedBits) \ 91578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmTestBranchBit40, 23, 19, Bits) \ 92578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmTestBranchBit5, 31, 31, Bits) \ 93ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 94ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Conditionals */ \ 95578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Condition, 15, 12, Bits) \ 96578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ConditionBranch, 3, 0, Bits) \ 97578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Nzcv, 3, 0, Bits) \ 98578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmCondCmp, 20, 16, Bits) \ 99578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmCondBranch, 23, 5, SignedBits) \ 100ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 101ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Floating point */ \ 102578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(FPType, 23, 22, Bits) \ 103578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmFP, 20, 13, Bits) \ 104578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(FPScale, 15, 10, Bits) \ 105ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 106ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Load Store */ \ 107578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmLS, 20, 12, SignedBits) \ 108578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmLSUnsigned, 21, 10, Bits) \ 109578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmLSPair, 21, 15, SignedBits) \ 110578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(SizeLS, 31, 30, Bits) \ 111578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmShiftLS, 12, 12, Bits) \ 112ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 113ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl/* Other immediates */ \ 114578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmUncondBranch, 25, 0, SignedBits) \ 115578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmCmpBranch, 23, 5, SignedBits) \ 116578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmLLiteral, 23, 5, SignedBits) \ 117578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmException, 20, 5, Bits) \ 118578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmHint, 11, 5, Bits) \ 119f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlV_(ImmBarrierDomain, 11, 10, Bits) \ 120f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlV_(ImmBarrierType, 9, 8, Bits) \ 121ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl \ 122578645f14e122d2b87d907e298cda7e7d0babf1farmvixl/* System (MRS, MSR) */ \ 123578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(ImmSystemRegister, 19, 5, Bits) \ 124578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(SysO0, 19, 19, Bits) \ 125578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(SysOp1, 18, 16, Bits) \ 126578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(SysOp2, 7, 5, Bits) \ 127578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(CRn, 15, 12, Bits) \ 128578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(CRm, 11, 8, Bits) \ 129578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 130578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 131578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 132578645f14e122d2b87d907e298cda7e7d0babf1farmvixl/* NZCV */ \ 133578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Flags, 31, 28, Bits) \ 134578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(N, 31, 31, Bits) \ 135578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(Z, 30, 30, Bits) \ 136578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(C, 29, 29, Bits) \ 137578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(V, 28, 28, Bits) \ 138578645f14e122d2b87d907e298cda7e7d0babf1farmvixlM_(NZCV, Flags_mask) \ 139578645f14e122d2b87d907e298cda7e7d0babf1farmvixl \ 140578645f14e122d2b87d907e298cda7e7d0babf1farmvixl/* FPCR */ \ 141578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(AHP, 26, 26, Bits) \ 142578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(DN, 25, 25, Bits) \ 143578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(FZ, 24, 24, Bits) \ 144578645f14e122d2b87d907e298cda7e7d0babf1farmvixlV_(RMode, 23, 22, Bits) \ 145578645f14e122d2b87d907e298cda7e7d0babf1farmvixlM_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 146578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 147ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 148ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Fields offsets. 149ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ 150ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int Name##_offset = LowBit; \ 151ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int Name##_width = HighBit - LowBit + 1; \ 152578645f14e122d2b87d907e298cda7e7d0babf1farmvixlconst uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 153578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#define NOTHING(A, B) 154578645f14e122d2b87d907e298cda7e7d0babf1farmvixlINSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) 155578645f14e122d2b87d907e298cda7e7d0babf1farmvixlSYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 156578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef NOTHING 157ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#undef DECLARE_FIELDS_BITS 158ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 159578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 160578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// from ImmPCRelLo and ImmPCRelHi. 161ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 162ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 163ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Condition codes. 164ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum Condition { 165ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl eq = 0, 166ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ne = 1, 167ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl hs = 2, 168ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl lo = 3, 169ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl mi = 4, 170ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl pl = 5, 171ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl vs = 6, 172ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl vc = 7, 173ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl hi = 8, 174ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ls = 9, 175ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ge = 10, 176ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl lt = 11, 177ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl gt = 12, 178ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl le = 13, 179578645f14e122d2b87d907e298cda7e7d0babf1farmvixl al = 14, 180578645f14e122d2b87d907e298cda7e7d0babf1farmvixl nv = 15 // Behaves as always/al. 181ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 182ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 183ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlinline Condition InvertCondition(Condition cond) { 184578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Conditions al and nv behave identically, as "always true". They can't be 185578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // inverted, because there is no "always false" condition. 1861123fee00a9cef7f1b448eab3c2ca333dbd426d7armvixl VIXL_ASSERT((cond != al) && (cond != nv)); 187ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return static_cast<Condition>(cond ^ 1); 188ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 189ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 190ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FlagsUpdate { 191ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SetFlags = 1, 192ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LeaveFlags = 0 193ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 194ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 195ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum StatusFlags { 196ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl NoFlag = 0, 197578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 198578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Derive the flag combinations from the system register bit descriptions. 199578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NFlag = N_mask, 200578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ZFlag = Z_mask, 201578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CFlag = C_mask, 202578645f14e122d2b87d907e298cda7e7d0babf1farmvixl VFlag = V_mask, 203578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NZFlag = NFlag | ZFlag, 204578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NCFlag = NFlag | CFlag, 205578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NVFlag = NFlag | VFlag, 206578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ZCFlag = ZFlag | CFlag, 207578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ZVFlag = ZFlag | VFlag, 208578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CVFlag = CFlag | VFlag, 209578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NZCFlag = NFlag | ZFlag | CFlag, 210578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NZVFlag = NFlag | ZFlag | VFlag, 211578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NCVFlag = NFlag | CFlag | VFlag, 212578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ZCVFlag = ZFlag | CFlag | VFlag, 213578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 214578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 215578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Floating-point comparison results. 216578645f14e122d2b87d907e298cda7e7d0babf1farmvixl FPEqualFlag = ZCFlag, 217578645f14e122d2b87d907e298cda7e7d0babf1farmvixl FPLessThanFlag = NFlag, 218578645f14e122d2b87d907e298cda7e7d0babf1farmvixl FPGreaterThanFlag = CFlag, 219578645f14e122d2b87d907e298cda7e7d0babf1farmvixl FPUnorderedFlag = CVFlag 220ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 221ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 222ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum Shift { 223ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl NO_SHIFT = -1, 224ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LSL = 0x0, 225ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LSR = 0x1, 226ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ASR = 0x2, 227ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ROR = 0x3 228ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 229ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 230ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum Extend { 231ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl NO_EXTEND = -1, 232ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UXTB = 0, 233ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UXTH = 1, 234ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UXTW = 2, 235ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UXTX = 3, 236ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SXTB = 4, 237ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SXTH = 5, 238ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SXTW = 6, 239ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SXTX = 7 240ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 241ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 242ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum SystemHint { 243ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl NOP = 0, 244ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl YIELD = 1, 245ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl WFE = 2, 246ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl WFI = 3, 247ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SEV = 4, 248ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SEVL = 5 249ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 250ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 251f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlenum BarrierDomain { 252f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl OuterShareable = 0, 253f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl NonShareable = 1, 254f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl InnerShareable = 2, 255f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FullSystem = 3 256f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl}; 257f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 258f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlenum BarrierType { 259f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl BarrierOther = 0, 260f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl BarrierReads = 1, 261f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl BarrierWrites = 2, 262f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl BarrierAll = 3 263f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl}; 264f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 265ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// System/special register names. 266ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// This information is not encoded as one field but as the concatenation of 267578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// multiple fields (Op0<0>, Op1, Crn, Crm, Op2). 268ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum SystemRegister { 269578645f14e122d2b87d907e298cda7e7d0babf1farmvixl NZCV = ((0x1 << SysO0_offset) | 270578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x3 << SysOp1_offset) | 271578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x4 << CRn_offset) | 272578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x2 << CRm_offset) | 273578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset, 274578645f14e122d2b87d907e298cda7e7d0babf1farmvixl FPCR = ((0x1 << SysO0_offset) | 275578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x3 << SysOp1_offset) | 276578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x4 << CRn_offset) | 277578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x4 << CRm_offset) | 278578645f14e122d2b87d907e298cda7e7d0babf1farmvixl (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset 279ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 280ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 281ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Instruction enumerations. 282ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 283ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// These are the masks that define a class of instructions, and the list of 284ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// instructions within each class. Each enumeration has a Fixed, FMask and 285ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Mask value. 286ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 287ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Fixed: The fixed bits in this instruction class. 288ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FMask: The mask used to extract the fixed bits in the class. 289ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Mask: The mask used to identify the instructions within a class. 290ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 291ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// The enumerations can be used like this: 292ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 2931123fee00a9cef7f1b448eab3c2ca333dbd426d7armvixl// VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 294ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// switch(instr->Mask(PCRelAddressingMask)) { 295ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 296ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 297ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// default: printf("Unknown instruction\n"); 298ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// } 299ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 300ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 301ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Generic fields. 302ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum GenericInstrField { 303ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SixtyFourBits = 0x80000000, 304ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ThirtyTwoBits = 0x00000000, 305ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FP32 = 0x00000000, 306ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FP64 = 0x00400000 307ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 308ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 309ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// PC relative addressing. 310ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum PCRelAddressingOp { 311ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PCRelAddressingFixed = 0x10000000, 312ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PCRelAddressingFMask = 0x1F000000, 313ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PCRelAddressingMask = 0x9F000000, 314ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADR = PCRelAddressingFixed | 0x00000000, 315ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADRP = PCRelAddressingFixed | 0x80000000 316ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 317ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 318ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Add/sub (immediate, shifted and extended.) 319ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int kSFOffset = 31; 320ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum AddSubOp { 321ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubOpMask = 0x60000000, 322ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubSetFlagsBit = 0x20000000, 323ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADD = 0x00000000, 324ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADDS = ADD | AddSubSetFlagsBit, 325ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SUB = 0x40000000, 326ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SUBS = SUB | AddSubSetFlagsBit 327ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 328ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 329ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define ADD_SUB_OP_LIST(V) \ 330ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ADD), \ 331ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ADDS), \ 332ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(SUB), \ 333ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(SUBS) 334ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 335ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum AddSubImmediateOp { 336ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubImmediateFixed = 0x11000000, 337ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubImmediateFMask = 0x1F000000, 338ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubImmediateMask = 0xFF000000, 339ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define ADD_SUB_IMMEDIATE(A) \ 340ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_w_imm = AddSubImmediateFixed | A, \ 341ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 342ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 343ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef ADD_SUB_IMMEDIATE 344ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 345ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 346ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum AddSubShiftedOp { 347ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubShiftedFixed = 0x0B000000, 348ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubShiftedFMask = 0x1F200000, 349ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubShiftedMask = 0xFF200000, 350ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define ADD_SUB_SHIFTED(A) \ 351ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_w_shift = AddSubShiftedFixed | A, \ 352ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 353ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 354ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef ADD_SUB_SHIFTED 355ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 356ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 357ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum AddSubExtendedOp { 358ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubExtendedFixed = 0x0B200000, 359ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubExtendedFMask = 0x1F200000, 360ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubExtendedMask = 0xFFE00000, 361ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define ADD_SUB_EXTENDED(A) \ 362ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_w_ext = AddSubExtendedFixed | A, \ 363ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 364ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 365ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef ADD_SUB_EXTENDED 366ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 367ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 368ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Add/sub with carry. 369ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum AddSubWithCarryOp { 370ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarryFixed = 0x1A000000, 371ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarryFMask = 0x1FE00000, 372ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarryMask = 0xFFE0FC00, 373ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADC_w = AddSubWithCarryFixed | ADD, 374ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 375ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADC = ADC_w, 376ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADCS_w = AddSubWithCarryFixed | ADDS, 377ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 378ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBC_w = AddSubWithCarryFixed | SUB, 379ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 380ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBC = SBC_w, 381ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBCS_w = AddSubWithCarryFixed | SUBS, 382ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 383ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 384ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 385ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 386ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Logical (immediate and shifted register). 387ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LogicalOp { 388ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalOpMask = 0x60200000, 389ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl NOT = 0x00200000, 390ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AND = 0x00000000, 391ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BIC = AND | NOT, 392ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORR = 0x20000000, 393ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORN = ORR | NOT, 394ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EOR = 0x40000000, 395ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EON = EOR | NOT, 396ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ANDS = 0x60000000, 397ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BICS = ANDS | NOT 398ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 399ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 400ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Logical immediate. 401ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LogicalImmediateOp { 402ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalImmediateFixed = 0x12000000, 403ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalImmediateFMask = 0x1F800000, 404ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalImmediateMask = 0xFF800000, 405ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AND_w_imm = LogicalImmediateFixed | AND, 406ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 407ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORR_w_imm = LogicalImmediateFixed | ORR, 408ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 409ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EOR_w_imm = LogicalImmediateFixed | EOR, 410ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 411ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ANDS_w_imm = LogicalImmediateFixed | ANDS, 412ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 413ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 414ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 415ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Logical shifted register. 416ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LogicalShiftedOp { 417ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalShiftedFixed = 0x0A000000, 418ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalShiftedFMask = 0x1F000000, 419ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalShiftedMask = 0xFF200000, 420ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AND_w = LogicalShiftedFixed | AND, 421ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 422ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AND_shift = AND_w, 423ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BIC_w = LogicalShiftedFixed | BIC, 424ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 425ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BIC_shift = BIC_w, 426ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORR_w = LogicalShiftedFixed | ORR, 427ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 428ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORR_shift = ORR_w, 429ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORN_w = LogicalShiftedFixed | ORN, 430ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 431ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ORN_shift = ORN_w, 432ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EOR_w = LogicalShiftedFixed | EOR, 433ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 434ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EOR_shift = EOR_w, 435ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EON_w = LogicalShiftedFixed | EON, 436ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 437ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EON_shift = EON_w, 438ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ANDS_w = LogicalShiftedFixed | ANDS, 439ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 440ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ANDS_shift = ANDS_w, 441ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BICS_w = LogicalShiftedFixed | BICS, 442ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 443ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BICS_shift = BICS_w 444ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 445ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 446ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Move wide immediate. 447ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum MoveWideImmediateOp { 448ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MoveWideImmediateFixed = 0x12800000, 449ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MoveWideImmediateFMask = 0x1F800000, 450ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MoveWideImmediateMask = 0xFF800000, 451ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVN = 0x00000000, 452ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVZ = 0x40000000, 453ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVK = 0x60000000, 454ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVN_w = MoveWideImmediateFixed | MOVN, 455ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 456ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVZ_w = MoveWideImmediateFixed | MOVZ, 457ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 458ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVK_w = MoveWideImmediateFixed | MOVK, 459ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 460ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 461ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 462ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Bitfield. 463ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlconst int kBitfieldNOffset = 22; 464ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum BitfieldOp { 465ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BitfieldFixed = 0x13000000, 466ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BitfieldFMask = 0x1F800000, 467ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BitfieldMask = 0xFF800000, 468ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBFM_w = BitfieldFixed | 0x00000000, 469ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBFM_x = BitfieldFixed | 0x80000000, 470ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SBFM = SBFM_w, 471ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BFM_w = BitfieldFixed | 0x20000000, 472ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BFM_x = BitfieldFixed | 0xA0000000, 473ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BFM = BFM_w, 474ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UBFM_w = BitfieldFixed | 0x40000000, 475ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UBFM_x = BitfieldFixed | 0xC0000000, 476ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UBFM = UBFM_w 477ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Bitfield N field. 478ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 479ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 480ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Extract. 481ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ExtractOp { 482ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ExtractFixed = 0x13800000, 483ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ExtractFMask = 0x1F800000, 484ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ExtractMask = 0xFFA00000, 485ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EXTR_w = ExtractFixed | 0x00000000, 486ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EXTR_x = ExtractFixed | 0x80000000, 487ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl EXTR = EXTR_w 488ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 489ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 490ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Unconditional branch. 491ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum UnconditionalBranchOp { 492ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UnconditionalBranchFixed = 0x14000000, 493ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UnconditionalBranchFMask = 0x7C000000, 494ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UnconditionalBranchMask = 0xFC000000, 495ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl B = UnconditionalBranchFixed | 0x00000000, 496ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BL = UnconditionalBranchFixed | 0x80000000 497ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 498ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 499ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Unconditional branch to register. 500ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum UnconditionalBranchToRegisterOp { 501ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UnconditionalBranchToRegisterFixed = 0xD6000000, 502ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UnconditionalBranchToRegisterFMask = 0xFE000000, 503ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UnconditionalBranchToRegisterMask = 0xFFFFFC1F, 504ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 505ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 506ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl RET = UnconditionalBranchToRegisterFixed | 0x005F0000 507ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 508ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 509ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Compare and branch. 510ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum CompareBranchOp { 511ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CompareBranchFixed = 0x34000000, 512ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CompareBranchFMask = 0x7E000000, 513ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CompareBranchMask = 0xFF000000, 514ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CBZ_w = CompareBranchFixed | 0x00000000, 515ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CBZ_x = CompareBranchFixed | 0x80000000, 516ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CBZ = CBZ_w, 517ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CBNZ_w = CompareBranchFixed | 0x01000000, 518ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CBNZ_x = CompareBranchFixed | 0x81000000, 519ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CBNZ = CBNZ_w 520ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 521ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 522ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Test and branch. 523ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum TestBranchOp { 524ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl TestBranchFixed = 0x36000000, 525ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl TestBranchFMask = 0x7E000000, 526ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl TestBranchMask = 0x7F000000, 527ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl TBZ = TestBranchFixed | 0x00000000, 528ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl TBNZ = TestBranchFixed | 0x01000000 529ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 530ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 531ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conditional branch. 532ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ConditionalBranchOp { 533ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalBranchFixed = 0x54000000, 534ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalBranchFMask = 0xFE000000, 535ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalBranchMask = 0xFF000010, 536ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl B_cond = ConditionalBranchFixed | 0x00000000 537ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 538ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 539ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// System. 540ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// System instruction encoding is complicated because some instructions use op 541ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and CR fields to encode parameters. To handle this cleanly, the system 542ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// instructions are split into more than one enum. 543ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 544ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum SystemOp { 545ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemFixed = 0xD5000000, 546ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemFMask = 0xFFC00000 547ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 548ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 549ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum SystemSysRegOp { 550ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemSysRegFixed = 0xD5100000, 551ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemSysRegFMask = 0xFFD00000, 552ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemSysRegMask = 0xFFF00000, 553ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MRS = SystemSysRegFixed | 0x00200000, 554ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MSR = SystemSysRegFixed | 0x00000000 555ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 556ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 557ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum SystemHintOp { 558ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemHintFixed = 0xD503201F, 559ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemHintFMask = 0xFFFFF01F, 560ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SystemHintMask = 0xFFFFF01F, 561ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl HINT = SystemHintFixed | 0x00000000 562ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 563ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 564ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Exception. 565ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ExceptionOp { 566ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ExceptionFixed = 0xD4000000, 567ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ExceptionFMask = 0xFF000000, 568ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ExceptionMask = 0xFFE0001F, 569ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl HLT = ExceptionFixed | 0x00400000, 570ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BRK = ExceptionFixed | 0x00200000, 571578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SVC = ExceptionFixed | 0x00000001, 572578645f14e122d2b87d907e298cda7e7d0babf1farmvixl HVC = ExceptionFixed | 0x00000002, 573578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SMC = ExceptionFixed | 0x00000003, 574578645f14e122d2b87d907e298cda7e7d0babf1farmvixl DCPS1 = ExceptionFixed | 0x00A00001, 575578645f14e122d2b87d907e298cda7e7d0babf1farmvixl DCPS2 = ExceptionFixed | 0x00A00002, 576578645f14e122d2b87d907e298cda7e7d0babf1farmvixl DCPS3 = ExceptionFixed | 0x00A00003 577ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 578ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 579f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlenum MemBarrierOp { 580f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl MemBarrierFixed = 0xD503309F, 581f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl MemBarrierFMask = 0xFFFFF09F, 582f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl MemBarrierMask = 0xFFFFF0FF, 583f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl DSB = MemBarrierFixed | 0x00000000, 584f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl DMB = MemBarrierFixed | 0x00000020, 585f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl ISB = MemBarrierFixed | 0x00000040 586f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl}; 587f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 588ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Any load or store. 589ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStoreAnyOp { 590ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreAnyFMask = 0x0a000000, 591ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreAnyFixed = 0x08000000 592ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 593ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 594ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define LOAD_STORE_PAIR_OP_LIST(V) \ 595ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(STP, w, 0x00000000), \ 596ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LDP, w, 0x00400000), \ 597ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LDPSW, x, 0x40400000), \ 598ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(STP, x, 0x80000000), \ 599ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LDP, x, 0x80400000), \ 600ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(STP, s, 0x04000000), \ 601ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LDP, s, 0x04400000), \ 602ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(STP, d, 0x44000000), \ 603ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LDP, d, 0x44400000) 604ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 605ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store pair (post, pre and offset.) 606ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePairOp { 607ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairMask = 0xC4400000, 608ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairLBit = 1 << 22, 609ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_PAIR(A, B, C) \ 610ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_##B = C 611ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 612ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_PAIR 613ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 614ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 615ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePairPostIndexOp { 616ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairPostIndexFixed = 0x28800000, 617ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairPostIndexFMask = 0x3B800000, 618ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairPostIndexMask = 0xFFC00000, 619ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 620ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 621ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 622ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_PAIR_POST_INDEX 623ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 624ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 625ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePairPreIndexOp { 626ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairPreIndexFixed = 0x29800000, 627ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairPreIndexFMask = 0x3B800000, 628ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairPreIndexMask = 0xFFC00000, 629ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 630ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 631ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 632ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_PAIR_PRE_INDEX 633ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 634ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 635ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePairOffsetOp { 636ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairOffsetFixed = 0x29000000, 637ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairOffsetFMask = 0x3B800000, 638ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairOffsetMask = 0xFFC00000, 639ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 640ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 641ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 642ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_PAIR_OFFSET 643ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 644ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 645ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePairNonTemporalOp { 646ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairNonTemporalFixed = 0x28000000, 647ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairNonTemporalFMask = 0x3B800000, 648ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePairNonTemporalMask = 0xFFC00000, 649ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl STNP_w = LoadStorePairNonTemporalFixed | STP_w, 650ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, 651ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl STNP_x = LoadStorePairNonTemporalFixed | STP_x, 652ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, 653ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl STNP_s = LoadStorePairNonTemporalFixed | STP_s, 654ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, 655ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl STNP_d = LoadStorePairNonTemporalFixed | STP_d, 656ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDNP_d = LoadStorePairNonTemporalFixed | LDP_d 657ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 658ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 659ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load literal. 660ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadLiteralOp { 661ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadLiteralFixed = 0x18000000, 662ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadLiteralFMask = 0x3B000000, 663ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadLiteralMask = 0xFF000000, 664ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDR_w_lit = LoadLiteralFixed | 0x00000000, 665ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDR_x_lit = LoadLiteralFixed | 0x40000000, 666ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 667ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PRFM_lit = LoadLiteralFixed | 0xC0000000, 668ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDR_s_lit = LoadLiteralFixed | 0x04000000, 669ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LDR_d_lit = LoadLiteralFixed | 0x44000000 670ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 671ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 672ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define LOAD_STORE_OP_LIST(V) \ 673ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ST, RB, w, 0x00000000), \ 674ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ST, RH, w, 0x40000000), \ 675ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ST, R, w, 0x80000000), \ 676ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ST, R, x, 0xC0000000), \ 677ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RB, w, 0x00400000), \ 678ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RH, w, 0x40400000), \ 679ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, R, w, 0x80400000), \ 680ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, R, x, 0xC0400000), \ 681ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RSB, x, 0x00800000), \ 682ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RSH, x, 0x40800000), \ 683ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RSW, x, 0x80800000), \ 684ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RSB, w, 0x00C00000), \ 685ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, RSH, w, 0x40C00000), \ 686ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ST, R, s, 0x84000000), \ 687ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(ST, R, d, 0xC4000000), \ 688ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, R, s, 0x84400000), \ 689ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl V(LD, R, d, 0xC4400000) 690ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 691ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 692ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store unscaled offset. 693ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStoreUnscaledOffsetOp { 694ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreUnscaledOffsetFixed = 0x38000000, 695ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreUnscaledOffsetFMask = 0x3B200C00, 696ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreUnscaledOffsetMask = 0xFFE00C00, 697ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_UNSCALED(A, B, C, D) \ 698ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 699ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 700ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_UNSCALED 701ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 702ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 703ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store (post, pre, offset and unsigned.) 704ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStoreOp { 705ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreOpMask = 0xC4C00000, 706ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE(A, B, C, D) \ 707ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##B##_##C = D 708ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_OP_LIST(LOAD_STORE), 709ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE 710ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PRFM = 0xC0800000 711ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 712ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 713ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store post index. 714ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePostIndex { 715ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePostIndexFixed = 0x38000400, 716ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePostIndexFMask = 0x3B200C00, 717ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePostIndexMask = 0xFFE00C00, 718ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 719ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##B##_##C##_post = LoadStorePostIndexFixed | D 720ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 721ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_POST_INDEX 722ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 723ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 724ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store pre index. 725ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStorePreIndex { 726ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePreIndexFixed = 0x38000C00, 727ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePreIndexFMask = 0x3B200C00, 728ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStorePreIndexMask = 0xFFE00C00, 729ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 730ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##B##_##C##_pre = LoadStorePreIndexFixed | D 731ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 732ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_PRE_INDEX 733ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 734ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 735ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store unsigned offset. 736ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStoreUnsignedOffset { 737ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreUnsignedOffsetFixed = 0x39000000, 738ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreUnsignedOffsetFMask = 0x3B000000, 739ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreUnsignedOffsetMask = 0xFFC00000, 740ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 741ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 742ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 743ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 744ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_UNSIGNED_OFFSET 745ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 746ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 747ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Load/store register offset. 748ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum LoadStoreRegisterOffset { 749ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreRegisterOffsetFixed = 0x38200800, 750ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreRegisterOffsetFMask = 0x3B200C00, 751ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreRegisterOffsetMask = 0xFFE00C00, 752ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 753ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 754ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 755ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 756ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl #undef LOAD_STORE_REGISTER_OFFSET 757ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 758ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 759ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conditional compare. 760ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ConditionalCompareOp { 761ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareMask = 0x60000000, 762ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMN = 0x20000000, 763ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMP = 0x60000000 764ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 765ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 766ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conditional compare register. 767ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ConditionalCompareRegisterOp { 768ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareRegisterFixed = 0x1A400000, 769ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareRegisterFMask = 0x1FE00800, 770ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareRegisterMask = 0xFFE00C10, 771ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMN_w = ConditionalCompareRegisterFixed | CCMN, 772ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 773ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMP_w = ConditionalCompareRegisterFixed | CCMP, 774ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 775ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 776ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 777ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conditional compare immediate. 778ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ConditionalCompareImmediateOp { 779ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareImmediateFixed = 0x1A400800, 780ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareImmediateFMask = 0x1FE00800, 781ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareImmediateMask = 0xFFE00C10, 782ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 783ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 784ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 785ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 786ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 787ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 788ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conditional select. 789ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum ConditionalSelectOp { 790ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalSelectFixed = 0x1A800000, 791ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalSelectFMask = 0x1FE00000, 792ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalSelectMask = 0xFFE00C00, 793ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSEL_w = ConditionalSelectFixed | 0x00000000, 794ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSEL_x = ConditionalSelectFixed | 0x80000000, 795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSEL = CSEL_w, 796ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSINC_w = ConditionalSelectFixed | 0x00000400, 797ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSINC_x = ConditionalSelectFixed | 0x80000400, 798ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSINC = CSINC_w, 799ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSINV_w = ConditionalSelectFixed | 0x40000000, 800ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSINV_x = ConditionalSelectFixed | 0xC0000000, 801ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSINV = CSINV_w, 802ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSNEG_w = ConditionalSelectFixed | 0x40000400, 803ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSNEG_x = ConditionalSelectFixed | 0xC0000400, 804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CSNEG = CSNEG_w 805ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 806ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 807ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Data processing 1 source. 808ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum DataProcessing1SourceOp { 809ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing1SourceFixed = 0x5AC00000, 810ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing1SourceFMask = 0x5FE00000, 811ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing1SourceMask = 0xFFFFFC00, 812ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl RBIT = DataProcessing1SourceFixed | 0x00000000, 813ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl RBIT_w = RBIT, 814ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl RBIT_x = RBIT | SixtyFourBits, 815ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV16 = DataProcessing1SourceFixed | 0x00000400, 816ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV16_w = REV16, 817ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV16_x = REV16 | SixtyFourBits, 818ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV = DataProcessing1SourceFixed | 0x00000800, 819ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV_w = REV, 820ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV32_x = REV | SixtyFourBits, 821ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 822ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CLZ = DataProcessing1SourceFixed | 0x00001000, 823ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CLZ_w = CLZ, 824ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CLZ_x = CLZ | SixtyFourBits, 825ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CLS = DataProcessing1SourceFixed | 0x00001400, 826ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CLS_w = CLS, 827ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl CLS_x = CLS | SixtyFourBits 828ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 829ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 830ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Data processing 2 source. 831ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum DataProcessing2SourceOp { 832ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing2SourceFixed = 0x1AC00000, 833ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing2SourceFMask = 0x5FE00000, 834ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing2SourceMask = 0xFFE0FC00, 835578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UDIV_w = DataProcessing2SourceFixed | 0x00000800, 836578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UDIV_x = DataProcessing2SourceFixed | 0x80000800, 837578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UDIV = UDIV_w, 838578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 839578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 840578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SDIV = SDIV_w, 841578645f14e122d2b87d907e298cda7e7d0babf1farmvixl LSLV_w = DataProcessing2SourceFixed | 0x00002000, 842578645f14e122d2b87d907e298cda7e7d0babf1farmvixl LSLV_x = DataProcessing2SourceFixed | 0x80002000, 843578645f14e122d2b87d907e298cda7e7d0babf1farmvixl LSLV = LSLV_w, 844578645f14e122d2b87d907e298cda7e7d0babf1farmvixl LSRV_w = DataProcessing2SourceFixed | 0x00002400, 845578645f14e122d2b87d907e298cda7e7d0babf1farmvixl LSRV_x = DataProcessing2SourceFixed | 0x80002400, 846578645f14e122d2b87d907e298cda7e7d0babf1farmvixl LSRV = LSRV_w, 847578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ASRV_w = DataProcessing2SourceFixed | 0x00002800, 848578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ASRV_x = DataProcessing2SourceFixed | 0x80002800, 849578645f14e122d2b87d907e298cda7e7d0babf1farmvixl ASRV = ASRV_w, 850578645f14e122d2b87d907e298cda7e7d0babf1farmvixl RORV_w = DataProcessing2SourceFixed | 0x00002C00, 851578645f14e122d2b87d907e298cda7e7d0babf1farmvixl RORV_x = DataProcessing2SourceFixed | 0x80002C00, 852578645f14e122d2b87d907e298cda7e7d0babf1farmvixl RORV = RORV_w, 853578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32B = DataProcessing2SourceFixed | 0x00004000, 854578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32H = DataProcessing2SourceFixed | 0x00004400, 855578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32W = DataProcessing2SourceFixed | 0x00004800, 856578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 857578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32CB = DataProcessing2SourceFixed | 0x00005000, 858578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32CH = DataProcessing2SourceFixed | 0x00005400, 859578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32CW = DataProcessing2SourceFixed | 0x00005800, 860578645f14e122d2b87d907e298cda7e7d0babf1farmvixl CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 861ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 862ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 863ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Data processing 3 source. 864ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum DataProcessing3SourceOp { 865ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing3SourceFixed = 0x1B000000, 866ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing3SourceFMask = 0x1F000000, 867ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl DataProcessing3SourceMask = 0xFFE08000, 868ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MADD_w = DataProcessing3SourceFixed | 0x00000000, 869ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MADD_x = DataProcessing3SourceFixed | 0x80000000, 870ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MADD = MADD_w, 871ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MSUB_w = DataProcessing3SourceFixed | 0x00008000, 872ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MSUB_x = DataProcessing3SourceFixed | 0x80008000, 873ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MSUB = MSUB_w, 874ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 875ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 876ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SMULH_x = DataProcessing3SourceFixed | 0x80400000, 877ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 878ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 879ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UMULH_x = DataProcessing3SourceFixed | 0x80C00000 880ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 881ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 882ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point compare. 883ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPCompareOp { 884ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPCompareFixed = 0x1E202000, 885ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPCompareFMask = 0x5F203C00, 886ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPCompareMask = 0xFFE0FC1F, 887ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMP_s = FPCompareFixed | 0x00000000, 888ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMP_d = FPCompareFixed | FP64 | 0x00000000, 889ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMP = FCMP_s, 890ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMP_s_zero = FPCompareFixed | 0x00000008, 891ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 892ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMP_zero = FCMP_s_zero, 893ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMPE_s = FPCompareFixed | 0x00000010, 894ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 895ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMPE_s_zero = FPCompareFixed | 0x00000018, 896ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018 897ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 898ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 899ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point conditional compare. 900ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPConditionalCompareOp { 901ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPConditionalCompareFixed = 0x1E200400, 902ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPConditionalCompareFMask = 0x5F200C00, 903ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPConditionalCompareMask = 0xFFE00C10, 904ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCCMP_s = FPConditionalCompareFixed | 0x00000000, 905ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 906ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCCMP = FCCMP_s, 907ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 908ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 909ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCCMPE = FCCMPE_s 910ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 911ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 912ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point conditional select. 913ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPConditionalSelectOp { 914ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPConditionalSelectFixed = 0x1E200C00, 915ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPConditionalSelectFMask = 0x5F200C00, 916ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPConditionalSelectMask = 0xFFE00C00, 917ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCSEL_s = FPConditionalSelectFixed | 0x00000000, 918ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 919ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCSEL = FCSEL_s 920ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 921ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 922ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point immediate. 923ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPImmediateOp { 924ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPImmediateFixed = 0x1E201000, 925ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPImmediateFMask = 0x5F201C00, 926ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPImmediateMask = 0xFFE01C00, 927ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_s_imm = FPImmediateFixed | 0x00000000, 928ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 929ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 930ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 931ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point data processing 1 source. 932ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPDataProcessing1SourceOp { 933ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing1SourceFixed = 0x1E204000, 934ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing1SourceFMask = 0x5F207C00, 935ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing1SourceMask = 0xFFFFFC00, 936ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 937ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 938ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV = FMOV_s, 939ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 940ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 941ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FABS = FABS_s, 942ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 943ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 944ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNEG = FNEG_s, 945ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 946ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 947ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FSQRT = FSQRT_s, 948ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 949ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 950ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 951ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 952ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTN = FRINTN_s, 953ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 954ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 955f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FRINTP = FRINTP_s, 956ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 957ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 958f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FRINTM = FRINTM_s, 959ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 960ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 961ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTZ = FRINTZ_s, 962ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 963ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 964f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FRINTA = FRINTA_s, 965ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 966ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 967f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FRINTX = FRINTX_s, 968ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 969f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 970f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl FRINTI = FRINTI_s 971ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 972ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 973ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point data processing 2 source. 974ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPDataProcessing2SourceOp { 975ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing2SourceFixed = 0x1E200800, 976ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing2SourceFMask = 0x5F200C00, 977ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing2SourceMask = 0xFFE0FC00, 978ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMUL = FPDataProcessing2SourceFixed | 0x00000000, 979ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMUL_s = FMUL, 980ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMUL_d = FMUL | FP64, 981ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FDIV = FPDataProcessing2SourceFixed | 0x00001000, 982ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FDIV_s = FDIV, 983ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FDIV_d = FDIV | FP64, 984ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FADD = FPDataProcessing2SourceFixed | 0x00002000, 985ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FADD_s = FADD, 986ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FADD_d = FADD | FP64, 987ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FSUB = FPDataProcessing2SourceFixed | 0x00003000, 988ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FSUB_s = FSUB, 989ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FSUB_d = FSUB | FP64, 990ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMAX = FPDataProcessing2SourceFixed | 0x00004000, 991ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMAX_s = FMAX, 992ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMAX_d = FMAX | FP64, 993ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMIN = FPDataProcessing2SourceFixed | 0x00005000, 994ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMIN_s = FMIN, 995ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMIN_d = FMIN | FP64, 996ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 997ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMAXNM_s = FMAXNM, 998ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMAXNM_d = FMAXNM | FP64, 999ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1000ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMINNM_s = FMINNM, 1001ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMINNM_d = FMINNM | FP64, 1002ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1003ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMUL_s = FNMUL, 1004ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMUL_d = FNMUL | FP64 1005ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 1006ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1007ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Floating point data processing 3 source. 1008ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPDataProcessing3SourceOp { 1009ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing3SourceFixed = 0x1F000000, 1010ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing3SourceFMask = 0x5F000000, 1011ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPDataProcessing3SourceMask = 0xFFE08000, 1012ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1013ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1014ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1015ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1016ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1017ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1018ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1019ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1020ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 1021ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1022ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conversion between floating point and integer. 1023ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPIntegerConvertOp { 1024ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPIntegerConvertFixed = 0x1E200000, 1025ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPIntegerConvertFMask = 0x5F20FC00, 1026ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPIntegerConvertMask = 0xFFFFFC00, 1027ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNS = FPIntegerConvertFixed | 0x00000000, 1028ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNS_ws = FCVTNS, 1029ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNS_xs = FCVTNS | SixtyFourBits, 1030ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNS_wd = FCVTNS | FP64, 1031ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1032ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNU = FPIntegerConvertFixed | 0x00010000, 1033ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNU_ws = FCVTNU, 1034ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNU_xs = FCVTNU | SixtyFourBits, 1035ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNU_wd = FCVTNU | FP64, 1036ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1037ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPS = FPIntegerConvertFixed | 0x00080000, 1038ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPS_ws = FCVTPS, 1039ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPS_xs = FCVTPS | SixtyFourBits, 1040ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPS_wd = FCVTPS | FP64, 1041ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1042ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPU = FPIntegerConvertFixed | 0x00090000, 1043ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPU_ws = FCVTPU, 1044ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPU_xs = FCVTPU | SixtyFourBits, 1045ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPU_wd = FCVTPU | FP64, 1046ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1047ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMS = FPIntegerConvertFixed | 0x00100000, 1048ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMS_ws = FCVTMS, 1049ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMS_xs = FCVTMS | SixtyFourBits, 1050ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMS_wd = FCVTMS | FP64, 1051ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1052ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMU = FPIntegerConvertFixed | 0x00110000, 1053ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMU_ws = FCVTMU, 1054ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMU_xs = FCVTMU | SixtyFourBits, 1055ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMU_wd = FCVTMU | FP64, 1056ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1057ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS = FPIntegerConvertFixed | 0x00180000, 1058ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_ws = FCVTZS, 1059ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_xs = FCVTZS | SixtyFourBits, 1060ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_wd = FCVTZS | FP64, 1061ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1062ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU = FPIntegerConvertFixed | 0x00190000, 1063ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_ws = FCVTZU, 1064ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_xs = FCVTZU | SixtyFourBits, 1065ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_wd = FCVTZU | FP64, 1066ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1067ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF = FPIntegerConvertFixed | 0x00020000, 1068ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_sw = SCVTF, 1069ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_sx = SCVTF | SixtyFourBits, 1070ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_dw = SCVTF | FP64, 1071ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1072ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF = FPIntegerConvertFixed | 0x00030000, 1073ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_sw = UCVTF, 1074ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_sx = UCVTF | SixtyFourBits, 1075ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_dw = UCVTF | FP64, 1076ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1077ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAS = FPIntegerConvertFixed | 0x00040000, 1078ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAS_ws = FCVTAS, 1079ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAS_xs = FCVTAS | SixtyFourBits, 1080ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAS_wd = FCVTAS | FP64, 1081ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1082ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAU = FPIntegerConvertFixed | 0x00050000, 1083ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAU_ws = FCVTAU, 1084ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAU_xs = FCVTAU | SixtyFourBits, 1085ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAU_wd = FCVTAU | FP64, 1086ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1087ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1088ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1089ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1090ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FMOV_dx = FMOV_sw | SixtyFourBits | FP64 1091ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 1092ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1093ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Conversion between fixed point and floating point. 1094ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlenum FPFixedPointConvertOp { 1095ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPFixedPointConvertFixed = 0x1E000000, 1096ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPFixedPointConvertFMask = 0x5F200000, 1097ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FPFixedPointConvertMask = 0xFFFF0000, 1098ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1099ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_ws_fixed = FCVTZS_fixed, 1100ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1101ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1102ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1103ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1104ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_ws_fixed = FCVTZU_fixed, 1105ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1106ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1107ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1108ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1109ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_sw_fixed = SCVTF_fixed, 1110ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1111ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_dw_fixed = SCVTF_fixed | FP64, 1112ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1113ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1114ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_sw_fixed = UCVTF_fixed, 1115ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1116ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_dw_fixed = UCVTF_fixed | FP64, 1117ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1118ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 1119ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1120578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// Unimplemented and unallocated instructions. These are defined to make fixed 1121578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// bit assertion easier. 1122578645f14e122d2b87d907e298cda7e7d0babf1farmvixlenum UnimplementedOp { 1123578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UnimplementedFixed = 0x00000000, 1124578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UnimplementedFMask = 0x00000000 1125ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 1126578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 1127578645f14e122d2b87d907e298cda7e7d0babf1farmvixlenum UnallocatedOp { 1128578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UnallocatedFixed = 0x00000000, 1129578645f14e122d2b87d907e298cda7e7d0babf1farmvixl UnallocatedFMask = 0x00000000 1130578645f14e122d2b87d907e298cda7e7d0babf1farmvixl}; 1131578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 1132ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 1133ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1134ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#endif // VIXL_A64_CONSTANTS_A64_H_ 1135