| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 12d3dc73dc44acd8b11cca783b826ccbd66f44da |
|
23-Aug-2013 |
Andrew Trick <atrick@apple.com> |
PrintVRegOrUnit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 997fa623fc14122153c58ddda8c90aa30f192cc8 |
|
16-May-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
|
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 108fb3202af6f500073cdbb7be32c25d7a273a2e |
|
31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e188fb7dd91c6fee15aa18c877d664d63d736000 |
|
20-Dec-2012 |
Jim Grosbach <grosbach@apple.com> |
Move isSubRegister() and isSuperRegister to MCRegisterInfo.
These were defined on TargetRegisterInfo, but they don't use any information
that's not available in MCRegisterInfo, so sink them down to be available
at the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a59ed5b156156224e97b4dbc32cfbe2101ce6e3c |
|
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
Remove two dead functions resulting from a bad rebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| eca1fcf3d2d8246c45648fea59bd21a4091f9115 |
|
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
RegisterPressure API. Add support for physical register units.
At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).
Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 83dbce2fc817fcb094a8958ca713fd3ba13758c5 |
|
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
Comment formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f71415646053e66f8a5b63a74ac06287eeab53d5 |
|
04-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.
These functions have been replaced by TRI::getRegAllocationHints() which
provides the same capabilities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 7eafc3e7be067709c6fcdae7b7fc4994c7ec2377 |
|
03-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a new hook for providing register allocator hints more flexibly.
The TargetRegisterInfo::getRegAllocationHints() function is going to
replace the existing mechanisms for providing target-dependent hints to
the register allocator: ResolveRegAllocHint() and
getRawAllocationOrder().
The new hook is more flexible because it allows the target to provide
multiple preferred candidate registers for each virtual register, and it
is easier to use because targets are not required to return a reference
to a constant array like getRawAllocationOrder().
An optional VirtRegMap argument can be used to provide target-dependent
hints that depend on the provisional assignments of other virtual
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 255f89faee13dc491cb64fbeae3c763e7e2ea4e6 |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for the include/... tree with the script.
AKA: Recompile *ALL* the source code!
This one went much better. No manual edits here. I spot-checked for
silliness and grep-checked for really broken edits and everything seemed
good. It all still compiles. Yell if you see something that looks goofy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e26e8a64ab37e98c69801ac2028b187773bc1d1f |
|
29-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MCPhysReg typedef to replace naked uint16_t.
Use this type for arrays of physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| af87dae12cab8d2e5cab033a5ab60af98e1837fe |
|
27-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Make PrintReg constructor explicit to prevent weird implicit conversions from accidentally being triggered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cf |
|
01-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Generate a table-driven version of TRI::composeSubRegIndices().
Explicitly allow composition of null sub-register indices, and handle
that common case in an inlinable stub.
Use a compressed table implementation instead of the previous nested
switches which generated pretty bad code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f4a5a613faa1a0eca6b884a6dfe83e8b1eb957b2 |
|
26-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the canCombineSubRegIndices() target hook.
The new coalescer can already do all of this, so there is no need to
duplicate the efforts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a6035773d8d29827a124e65c258adbf0dcbb1a5a |
|
11-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getSubRegIndexLaneMask().
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 59f45e4610e64b88bcee4cd46816ef64e815ff7e |
|
11-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 28897ca434892340f2e188a0331db92d5899409b |
|
02-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::hasRegUnit().
This trivial helper function tests if a register contains a register
unit. It is similar to regsOverlap(), but with asymmetric arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b7e22efa2b2a66b7d55c0297e45c217a465621ff |
|
30-Jul-2012 |
Eric Christopher <echristo@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 5ddc04caf25a649963c99be02646c3a9fc88d514 |
|
31-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a PrintRegUnit helper similar to PrintReg.
Reg-units are named after their root registers, and most units have a
single root, so they simply print as 'AL', 'XMM0', etc. The rare dual
root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ...
The printing piggybacks on the existing register name tables, so no
extra const data space is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3 |
|
30-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add MCRegisterInfo::RegListIterator.
Also add subclasses MCSubRegIterator, MCSuperRegIterator, and
MCRegAliasIterator.
These iterators provide an abstract interface to the MCRegisterInfo
register lists so the internal representation can be changed without
changing all clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 96feada378dc9769644333ca9670b265fd15a2ef |
|
30-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use MCRegUnitIterator to compute regsOverlap().
The register unit lists are typically much shorter than the register
overlap lists, and the backing table for register units has better cache
locality because it is smaller.
This makes llc about 0.5% faster. The regsOverlap() function isn't that hot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
|
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| fd87839a4888840ab5718fd116ab169ac04126af |
|
07-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getCommonSuperRegClass().
This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:
PreA
SuperRC ----------> RCA
| |
| |
PreB | | SubA
| |
| |
V V
RCB ----------> SubRC
SubB
This can be used to coalesce copies like:
%vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 7855ec62c3b6b5b7e6d3fada589511abd964fdb3 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetRegisterClass::SuperRegClasses.
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 89e38f87211f6cf34c8b2e88a06c275a70c05421 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a SuperRegClassIterator class.
This iterator class provides a more abstract interface to the (Idx,
Mask) lists of super-registers for a register class. The layout of the
tables shouldn't be exposed to clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dd63a063e2df0d0bc52b50732e3462fd58a636c0 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a shared implementation of getMatchingSuperRegClass().
TargetRegisterClass now gives access to the necessary tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1a2a19dd3ce2b163837b5f0a1ea474c72527cad6 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterClass::getSuperRegIndices().
This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1d61f283fad2e49d3e50a3585aac4cc9183a0d28 |
|
03-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix the type of SubClassMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 309076ff76c61e03ddd3a0fbbfded3042d2da2e5 |
|
03-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't override subreg functions in targets without subregisters.
Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f12f6dff9784805e8f89309787231c1ec53a8c6e |
|
03-May-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.
This ensures that targets define register classes as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
|
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d06c2decc2f5c296dfe914509ff841a639eb2a61 |
|
20-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetRegisterInfo::getRegPressureSetName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 33d9e89e5f8d7656e50353b014d5bb1b52f15e13 |
|
17-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Typo in an unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ec14cd7ddc66d47cd7927f18d8c11844c400367e |
|
11-Apr-2012 |
Andrew Trick <atrick@apple.com> |
TableGen's regpressure: emit per-registerclass weight limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2 |
|
10-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Added a TargetRegisterInfo interface for accessing register pressure sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 33ca87affb81b60c4d50214eb7458bd26d397d53 |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
MCRegisterInfo-ize getMatchingSuperReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 9ebfbf8b9fd5f982e0db9293808bd32168615ba9 |
|
05-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e4fd907e72a599eddfa7a81eac4366b5b82523e3 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b6632ba380cf624e60fe16b03d6e21b05dd07724 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 4b1212b4bfac98c688d484bf22ae158875f06ad5 |
|
01-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b3acdcc00c9dfb01663780e858e586cc5f04423f |
|
01-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.
Allows us to de-virtualize the function and provides access to it in
the instruction printer, which is useful for handling composite
physical registers (e.g., ARM register lists).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ccc8d3ba06408feff0ca6e58973c20d15010e3fc |
|
01-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.
This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.
Shrinks ARMBaseRegisterInfo.o by ~100k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2c6ae095b8a944c8355377498b9ad11bb94af2d5 |
|
09-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 50bee42b54cd9aec5f49566307df2b0cf23afcf6 |
|
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 478a8a02bc0f2e739ed8f4240152e99837e480b9 |
|
03-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| bd6dc3be1dac2d153f29927cad517af9e579b204 |
|
14-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getCallPreservedMask() hook.
The hook returns a bit-mask of call-preserved registers that will
eventually replace the current list of implicit defs on call
instructions. This will make it possible to support multiple calling
conventions without duplicating call instruction descriptors.
The call-preserved mask is slightly different from the list returned by
the getCalleeSavedRegs() hook, it includes all aliases that are
preserved by calls.
The hook takes a CallingConv::ID argument instead of a MachineFunction
pointer, so it can provide information about calls to extern functions,
and even indirect function calls.
TRI::getCalleeSavedRegs() returns information about the function
currently being compiled. TRI::getCallPreservedMask() returns
information about the functions it is calling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2d24e2a396a1d211baaeedf32148a3b657240170 |
|
20-Dec-2011 |
David Blaikie <dblaikie@gmail.com> |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 570f9a972e02830d1ca223743dd6b4cc4fdf9549 |
|
19-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d9c1fa5205cc31474f9f9a6d715af32098a1a719 |
|
06-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the TRI::getSubRegisterRegClass() hook.
This restores my karma after I added TRI::getSubClassWithSubReg().
Register constraints are applied 'backwards'. Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.
We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in? The
getSubRegisterRegClass() hook did that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 845d2c0c776abce551d16f7b1b7dc1f4d4df1a27 |
|
05-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c8e2bb68bbc4a71cc10084c8f89565b9f05e12ef |
|
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e27e1ca3c90b69e78242c98a669337f84ccded7f |
|
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move getCommonSubClass() into TRI.
It will soon need the context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c66d36028b21077aa1715331c22347b47b4da94f |
|
10-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Trim an unneeded header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 9df8567548e15c6cd91e8a5851784574c4f09528 |
|
23-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This should be faster and smaller.
Goodbye static ctors and dtors!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f496d68493acf8d178afbbe8c3146ea09bd7776b |
|
23-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Give TargetRegisterClass a pointer to the MCRegisterClass and use it to access its data.
This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 8ca9a862038e8c4e9a2ca73b3b75e1be3425155f |
|
22-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Teach tblgen to emit MCRegisterClasses.
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a50c175fe3c7a3034df18747cfacb3b153c493c8 |
|
21-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Sink parts of TargetRegisterClass into MCRegisterClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
|
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 39b5abf507b43da6b92f68b86406e0015ead18e9 |
|
18-Jul-2011 |
Frits van Bommel <fvbommel@gmail.com> |
Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 486dd90696545421c55346570b88fa03f6dd464f |
|
06-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Constify getCompactUnwindRegNum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 5cd2791513919ee7504c309151321e4e37a05a58 |
|
01-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Add target a target hook to get the register number used by the compact unwind
encoding for the registers it knows about. Return -1 if it can't handle that
register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2ca7f4d2f3782db8b9f1a264fc558a72b0fd4fa0 |
|
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename unnecessary forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 5e6b4605bd620a864055276a6d454e5a18f9fee8 |
|
25-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetRegisterDesc to MCRegisterDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f5fa52ed064098be7130aa4ec1236037907ce3fa |
|
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d |
|
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 54c47c1ce94b9e549ef768e80fd004788d13ce85 |
|
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.
The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.
It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dd5a8471526ceadf9bceb1a1221299b3db49c33a |
|
17-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.
The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 79c890f64f3b67f9b11341aa452c4302b75184aa |
|
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::getRawAllocationOrder().
This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.
Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1e56a2a85fbafce5ceee72f72d41b84a71876844 |
|
15-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b95fd2d5fd4818a601dd1df05f38863e3ca5c920 |
|
12-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Tweak hash function and compress hash tables.
Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.
Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.
Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.
This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 026dc223aeef2579d63f395007491e37d6cde3a0 |
|
12-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:
- Sub-register lists come from a pre-order traversal of the graph
defined by the SubRegs lists in the .td files.
- Super-register lists are topologically ordered so no register comes
before any of its sub-registers. When the sub-register graph is not a
tree, independent super-registers appear in numerical order.
- Lists of overlapping registers are ordered according to register
number.
This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.
The old computations are still there, but will be removed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f462e3fac7ac67503657d63dc35330d0b19359b3 |
|
03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.
TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.
The goal here is to eliminate use cases for overriding allocation_order_*
methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1f9a09c61489a83360238032b6756395bd69b620 |
|
01-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix PR10059 and future variations by handling all register subclasses.
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 6e032942cf58d1c41f88609a1cec74eb74940ecd |
|
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use the dwarf->llvm mapping to print register names in the cfi
directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 6b918b84661687f7b5fc92dabd6d58e258bf39f2 |
|
24-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a method to TargetRegisterInfo to get the register number that the Win64 EH
scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dfa178bc2a21667aab745ba9a182cd3e702fec3b |
|
24-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Work around code generation bug in Visual Studio 2010.
See http://llvm.org/pr9976 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c9e5015dece0a1a73bec358e11bc87594831279d |
|
26-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.
The hook will be used by the register allocator when recomputing register
classes after removing constraints.
Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 6bfba2e5af163442a1c6b11fe14aa9df9101cfd7 |
|
20-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.
Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.
Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee |
|
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b0519e15f70cef7ba16b712f258d4782ade17e13 |
|
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 127368 and 127371. They are exonerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 02d7c9298298f7f8fba1427f249deb2106126e9c |
|
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert 127368 and 127371 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 0f24d49acae52fc66f72136bbe4891a9a8c9cd36 |
|
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Restore the default implementation of getCrossCopyRegClass: no need for cross-regclass copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 17adafc6c179f3bad757f932a13522851ee5171f |
|
09-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
flexible.
If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
|
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 0f657b156f3d0890584bedda7294932a20b2ea16 |
|
03-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Allow a target to choose whether to prefer the scavenger emergency spill slot
be next to the frame pointer or the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 63f8659d6936077c5e8e34eecb55ff1de0db5686 |
|
02-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b79cb79a46fd4d870897f5e2fd0c50beb96dc30a |
|
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetRegisterInfo::NoRegister.
Fix the TargetRegisterInfo::NoRegister places where someone preferred
typing 'TargetRegisterInfo::NoRegister' instead of typing '0'.
Note that TableGen is already emitting xx::NoRegister in xxGenRegisterNames.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| da1f1f495066f95957fd1c19ad44d4453e47aff4 |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Change virtual register numbering to make more space for physical registers.
The numbering plan is now:
0 NoRegister.
[1;2^30) Physical registers.
[2^30;2^31) Stack slots.
[2^31;2^32) Virtual registers. (With -1u and -2u used by DenseMapInfo.)
Each segment is filled from the left, so any mistaken interpretation should
quickly cause crashes.
FirstVirtualRegister has been removed. TargetRegisterInfo provides predicates
conversion functions that should be used instead of interpreting register
numbers manually.
It is now legal to pass NoRegister to isPhysicalRegister() and
isVirtualRegister(). The result is false in both cases.
It is quite rare to represent stack slots in this way, so isPhysicalRegister()
and isVirtualRegister() require that isStackSlot() be checked first if it can
possibly return true. This allows a very fast implementation of the common
predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| be97e906e03dd9b22e14f6749157c9d5f9701dd5 |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and
physical register numbers.
This makes the hack used in LiveInterval official, and lets LiveInterval be
oblivious of stack slots.
The isPhysicalRegister() and isVirtualRegister() predicates don't know about
this, so when a variable may contain a stack slot, isStackSlot() should always
be tested first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 43a566519b85ddffa482695d6a5a3dc4a02e267f |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 4314268128be6d54c9a7f0709680e5a5b40f3ab3 |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c7d67f90d36375f1ff512a3857c887b7e4246adb |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix VirtRegMap to use TRI::index2VirtReg and TRI::virtReg2Index instead of
depending on TRI::FirstVirtualRegister.
Also use TRI::printReg instead of printing virtual registers directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b421c566f512ed0ec87851866d335e9086c3f8be |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use an IndexedMap for LiveVariables::VirtRegInfo.
Provide MRI::getNumVirtRegs() and TRI::index2VirtReg() functions to allow
iteration over virtual registers without depending on the representation of
virtual register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 976ef86689ed065361a748f81c44ca3510af2202 |
|
18-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
During local stack slot allocation, the materializeFrameBaseRegister function
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b83ff84193d44bb9aa75e1264ffaff55f468a303 |
|
15-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.
The name matches the reflexive TRI::regsOverlap(x, y) relation.
It is very common to do stuff to a register and all its aliases:
stuff(Reg)
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
stuff(*Alias);
That can now be written as the simpler:
for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
stuff(*Alias);
This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.
If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 414e5023f8f8b22486313e2867fdb39c7c4f564b |
|
14-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::printReg() to pretty-print registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 94c5ae08750f314bc3cf1bf882b686244a3927d9 |
|
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move more PEI-related hooks to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 82f58740c76b42af8370247b23677a0318f6dde8 |
|
20-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move some more hooks to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d9e3385ced2dc887e2fe8e1c071bd2611e4d3ede |
|
19-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move getInitialFrameState() to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
|
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 33464912237efaa0ed7060829e66b59055bdd48b |
|
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| cdfad36b401be6fc709ea4051f9de58e1a30bcc9 |
|
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| cc38399ea9aceb459a8d7e4bbc6deba9125ea869 |
|
10-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
add a comment explicitly calling out that allocation orders may include
reserved regs and that register allocators need to explicitly check for
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2429e2ac23cc1a5cb8154ed4fc44a16e725aa252 |
|
04-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Reapply this increase to the number of virtual registers. All of the
various breakages appear to be dealt with.
Patch by Pekka Jääskeläinen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a |
|
27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1ab3f16f06698596716593a30545799688acccd7 |
|
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up a bit. no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 3197380143cdc18837722129ac888528b9fbfc2b |
|
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a273442891ae20fd8192526132e3819ea9e5eda9 |
|
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e2f556933e1a19cddf6d4f370e2770c0f763b025 |
|
20-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Better handling of offsets on frame index references. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 638ff6d315be1df432e42f1c2068a2e6b464c4f4 |
|
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Re-re-revert this patch. It seems to be causing performance
and correctness regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e81043a7df0c7902758322a3000b7cb2048b71df |
|
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Reapply the virtual register patch from 109102. The places where we were
depending on the number of virtual registers appear to have all been handled
now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 74d803a58c7935c067397bb19afc05ec464d8159 |
|
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook for re-using virtual base registers for local stack slot access.
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.
ongoing saga of rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dc140c6e7b8350ca51aa1d408c10e25a27826e2c |
|
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add materialization of virtual base registers for frame indices allocated into
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.
Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 8708ead5a46f4ec8f2d5f832be23381924d72b8d |
|
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook to examine an instruction referencing a frame index to determine
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.
In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e6f60645c7aa208e03b3804bcf8489e08dacff0a |
|
06-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
spelling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 3012e2213bd29bd9202bf17d4053eae25311ecd7 |
|
23-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Revert r109102 for now as it's causing JIT miscompilations.
I'll try to track down why a bit later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 907cd1a569c4b3aa8451ea509f6b1018134884d3 |
|
22-Jul-2010 |
Duncan Sands <baldrick@free.fr> |
Increase the max physreg size. Patch by Pekka Jääskeläinen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 735317c0e83bd52bd3ab3e6d574a0640f722af47 |
|
20-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 72852a8cfb605056d87b644d2e36b1346051413d |
|
20-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Constify some arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 7e1b566322ecb5ff752c9a5f2feb503b6fb75262 |
|
12-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert the last use of getPhysicalRegisterRegClass and remove it.
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.
With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d6d7abaf4ebbabb850aa9c20e1617f897608fe62 |
|
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 320bdcbfe2691021702085f718db1617b1d4df49 |
|
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement X86InstrInfo::copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c2af869d629b338861e1c6f0b360a233c0c0f9c4 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Make getMinimalPhysRegClass' comment mention what makes it different
from getPhysicalRegisterRegClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d31f972bd33de85071c716f69bf5c6d735f730f2 |
|
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a606d955de3b0f777131d74162eb6f11b5f95d75 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 754f680c1fcde09a3d36bb8562e1433fdb87018e |
|
14-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 91a74da036d3a9442953ae1de3e797a50da4ccf0 |
|
02-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ce48c1de828688b34cf5c2038fde23368a0a45f4 |
|
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove uses of getCalleeSavedRegClasses from outside the
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2da53370241fdd1b5c291483311b34e609f06c73 |
|
28-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a TargetRegisterInfo::composeSubRegIndices hook with a default
implementation that is correct for most targets. Tablegen will override where
needed.
Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 76f0ad7bf5c05d6056b3bf335d0c3fb7e72de5d6 |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1fc8e759a767077726f9be35b93767e68bdf101f |
|
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Print symbolic SubRegIndex names on machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 09bc0298650c76db1a06e20ca84c1dcb34071600 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b990a2f249196ad3e0cc451d40a45fc2f9278eaf |
|
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e08b320f15b95eb3279fddba6ccb615eafbc4225 |
|
20-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Document that TargetRegisterInfo::contains does not cover virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 |
|
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 4642ad3af1cf508ac320b9afd25b065f08b36574 |
|
23-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1a2e8686f8137a1a2329952ffd1e21969ea1658c |
|
19-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| cf43e60544041c127bb875fe4cf0d0ae96cd6c78 |
|
19-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f451cb870efcf9e0302d25ed05f4cac6bb494e42 |
|
10-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 30c6b75ac2eef548c18110a38c9798ea5314caba |
|
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
constify a method argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c49a10aca1e31351c2e11b25ba636a23b93c46c8 |
|
13-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e8b0915b21026cd2314c1802bd2ccd4c91f4a83d |
|
08-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 90789 for now. It caused massive compile time regression. Post-ra scheduler slowed down dramatically with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| fb28579c568fcafaa4fb2a573b510deb6a6074e9 |
|
07-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Apply Pekka Jääskeläinen's patch to raise the first virtual register
number in order to accomodate targets with more than 1024 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| a2f20b20a8dc7f053599840557405554a0848aec |
|
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Add getFrameIndexReference() to TargetRegisterInfo, which allows targets to
tell debug info which base register to use to reference a frame index on a
per-index basis. This is useful, for example, in the presence of dynamic
stack realignment when local variables are indexed via the stack pointer and
stack-based arguments via the frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1f8f4d2db734d9881467a5706acac73660842d43 |
|
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Maintain stylistic consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89535 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 00621efb40edb7fe16bf2af6d4699c9d024a28e7 |
|
21-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Restructure code to allow renaming of multiple-register groups for anti-dep breaking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| fae3e923452b85e72b2c03dd6eacc063f59d81b1 |
|
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b9c2fd964ee7dd7823ac71db8443055e4d0f1c15 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Make the MachineFunction argument of getFrameRegister const.
This also fixes a build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d482f55af135081aee7f7ab972bb8973f189c88f |
|
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 769b7f89534caed11d7595b5c84aa47d3de30ad9 |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Add a const qualifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 65c58daa8b8985d2116216043103009815a55e77 |
|
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Re-enable register scavenging in Thumb1 by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 9f3a559dff691bc1ed85089cb0870cf30a4a2d96 |
|
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
reverting thumb1 scavenging default due to test failure while I figure out what's up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| bafa3d9f6aaf24d721476ded7b1211ad57dd46c3 |
|
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable thumb1 register scavenging by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b58f498f7502e7e1833decbbbb4df771367c7341 |
|
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 540b05d227a79443b2a7b07d5152a35cb6392abf |
|
06-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 95923d70d90e0b9901d63ec3e35bf94be260e4f0 |
|
01-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e7f3107772b1c8c2b9397ab19106b8451d31e8ab |
|
14-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetRegisterDesc::AsmName field, the asmprinters now have this table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 762ccea600158bb317dcccdff3303e942426cb71 |
|
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove all but one reference to TargetRegisterDesc::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 59bf4fcc0680e75b408579064d1205a132361196 |
|
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Public and private corrections, warned about by icc (#304).
Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 3f2f3f5341374c85955cfaffa71886724999762d |
|
03-Sep-2009 |
Lang Hames <lhames@gmail.com> |
Fixed a test that ensures the LocalRewriter does not attempt to
avoid reloads by reusing clobbered registers.
This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2cfd52c507bd5790457a171eb9bcb39019cc6860 |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 5248468473f0488a652b545ad95f7abda302b7b5 |
|
18-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable cross register class coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 910139f9ca53fc20a680d51ae61bb1e072095141 |
|
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Targets sometimes assign fixed stack object to spill certain callee-saved
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4 |
|
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 358dec51804ee52e47ea3a47c9248086e458ad7c |
|
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 90f95f88c6ce09c6744777dc9d140c3c77203b92 |
|
14-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 4d4eab219a96203f58452b39b4e94e234dfe4007 |
|
30-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| c781a243a3d17e7e763515794168d8fa6043f565 |
|
03-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.
Not yet enabled. This is part 1. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357 |
|
30-Apr-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
getCommonSubClass() - Calculate the largest common sub-class of two register
classes.
This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 8a8a0dfc3b200e193db14ea1e6f1a18bf4187866 |
|
28-Apr-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| fa4677b483b85217ac216f7e8d401c40cbe348aa |
|
28-Apr-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.
Also make the method non-asserting. It will return NULL when given an invalid subreg index.
The method is needed by an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 276944ef309ce43286120fb580eda78d6762a67e |
|
17-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Delete an unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f8c7394781f7cf27ac52ca087e289436d36844da |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.
Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.
Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ddeed50d76e2ad52d3ccb3664d21dfe1463179c6 |
|
13-Apr-2009 |
Owen Anderson <resistor@mac.com> |
Use a hashtable for TargetRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 3ca15c989ca0e09085648771db368d8c94ee1f19 |
|
10-Apr-2009 |
Owen Anderson <resistor@mac.com> |
Give register alias checking the hash table treatment too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 7d770be047059d624f37c6fb1e5b1d0f2b4961b3 |
|
09-Apr-2009 |
Owen Anderson <resistor@mac.com> |
Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 30eae3c02244e18747f9f0dca6946d86d0ccb7f5 |
|
07-Apr-2009 |
Jim Grosbach <grosbach@apple.com> |
PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 41c90738e9e7e2111fbc31944b5ce2676830f267 |
|
03-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
"This adds a getName() method to TargetRegisterClass, just like in TargetRegisterInfo.
This makes debugging register classes a bit easier."
Patch by Jakob Stoklund Olesen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 37059d52b7e51577ad2970e0ed00f230788fde18 |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
We don't really need the abort here. This unbreak x86_64 linux build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b3a021cdb3d26ddb2985e326ba0cb96761b86f69 |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change -1 => negative number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 6f8d762e6bad72b2ab9ff710cca3abb0a658fdf0 |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Document the meaning of -1 for getCopyCost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 8c08d8c77c45d4721e7d3ef746cca9e39b28e379 |
|
23-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cross register class coalescing. Not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 536ab130ec95cbb7bf30530251dafa7dfecc8471 |
|
22-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
|
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f89cfaea7a759c1a6c945852440a8d450f7e8af0 |
|
20-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
This forward declaration is unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2bbeccdee1937f6cef9f8762595246f447162a4f |
|
20-Oct-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Fix typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1ad70c09c890c3abcc147503f2e23082f683790c |
|
20-Oct-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Remove another stale comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 854255361ed5a8f009d64c4869ed2a85cf0d8fae |
|
20-Oct-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Remove an inappropriate (probably outdated) comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f522068412218cd14b2c2df74a3437717d255381 |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ffeecd65e3766ed3ace4e81a8f190dbbd7758bea |
|
11-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate some unused methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| dd595c5998214c6ee07ed46f5db551b2abbfbbb3 |
|
11-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Change getSubReg semantics. It now returns zero if the specified register doesn't have a subreg of the specified index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 605041e5a81fbb18769b0613dcd14e0cff32b5ee |
|
01-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Make the subregister hashtable output more readable by wrapping the lines,
and mark it const along with the associated changes to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 57ce0319b7eb4418aac910d9a094e57d983a64d2 |
|
01-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Implement suggestions from Chris:
- Use a more accurate heuristic for the size of the hashtable.
- Use bitwise and instead of modulo since the size is a power of two.
- Use new[] instead of malloc().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| f4f9c4f1cf4d497c63e40e6c7ef545c8c716a5ce |
|
01-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Replace the dynamically computed std::set lookup method for subregisters with a hashtable-based
version that is computed by tblgen at the time LLVM is compiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 2036835346ddf983d66b49505bd52db1d3f8b49d |
|
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate TargetRegisterDesc::ImmSubRegs. It's no longer in use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 1360b7d8f8d1969026870d18c582b4e3a7cff8b8 |
|
27-Jun-2008 |
Owen Anderson <resistor@mac.com> |
Cache subregister relationships in a set in TargetRegisterInfo to allow faster lookups.
This speeds up LiveVariables from 0.6279s to 0.6165s on kimwitu++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| b5dae003252d8e650a32bfdf33cba5aed8e41e40 |
|
26-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Fixes the last x86-64 test failure in compat.exp:
<16 x float> is 64-byte aligned (for some reason),
which gets us into the stack realignment code. The
computation changing FP-relative offsets to SP-relative
was broken, assiging a spill temp to a location
also used for parameter passing. This
fixes it by rounding up the stack frame to a multiple
of the largest alignment (I concluded it wasn't fixable
without doing this, but I'm not very sure.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 34cd4a484e532cc463fd5a4bf59b88d13c5467c1 |
|
05-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix more -Wshorten-64-to-32 warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 8102703d708e5d399926c6ba71ffa49bbd31fc8a |
|
15-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Sort sub-registers and super-registers lists according to super-sub register relations. e.g. X86::RAX sub-register list is EAX, AX, AL, AH (order of last two are not guaranteed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
|
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 676dd7c80b6f91178452535ac45ca58feb23cc42 |
|
11-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| e6d088acc90e422451e098555d383d4d65b6ce6b |
|
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Rename PrintableName to Name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 74ab84c31ef64538a1b56e1f282e49303412ad17 |
|
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 181eb737b28628adc4376b973610a02039385026 |
|
24-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Some platforms use the same name for 32-bit and 64-bit registers (like
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetRegisterInfo.h
|