History log of /external/llvm/lib/
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
50721a7a8e3c7094a828e29e7697ea52855c6542 25-Oct-2014 Stephen Hines <srhines@google.com> Merge in the following upstream patches to resolve Cortex-A57 crashes.

r214957
r215233
r216455
r216721
r217682
r217689
r217690
r217735

Change-Id: Ia53b88591471325df132caf26e1087510a65ce36
arget/AArch64/AArch64A57FPLoadBalancing.cpp
arget/AArch64/AArch64ISelLowering.cpp
22c310d78ce9630af15b0de94c18a409705b7496 10-Dec-2014 Tim Murray <timmurray@google.com> Revert "Revert "Bring in fixes for Cortex-A53 errata + build updates.""

This reverts commit c8db087b3b6d8767db4fa54057ac8fa448d812ca.
odeGen/CriticalAntiDepBreaker.cpp
odeGen/LiveRangeEdit.cpp
odeGen/MachineCSE.cpp
odeGen/MachineLICM.cpp
odeGen/MachineSink.cpp
odeGen/RegisterCoalescer.cpp
arget/AArch64/AArch64.h
arget/AArch64/AArch64A53Fix835769.cpp
arget/AArch64/AArch64A57FPLoadBalancing.cpp
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64InstrInfo.h
arget/AArch64/AArch64Subtarget.h
arget/AArch64/AArch64TargetMachine.cpp
arget/AArch64/Android.mk
arget/AArch64/CMakeLists.txt
6eeae0cf0069a272980de53836081a244ca5dffb 10-Dec-2014 Tim Murray <timmurray@google.com> Revert "Apply rL216114 from upstream LLVM."

This reverts commit 9156e80250ada6f6d39af3b464a918d4855f9a2a.
odeGen/CriticalAntiDepBreaker.cpp
9156e80250ada6f6d39af3b464a918d4855f9a2a 23-Oct-2014 Tim Murray <timmurray@google.com> Apply rL216114 from upstream LLVM.

bug 18094492

Change-Id: Ic049d4123b9240d89daf4f3c5e8d82e8276a84e7
odeGen/CriticalAntiDepBreaker.cpp
c8db087b3b6d8767db4fa54057ac8fa448d812ca 23-Oct-2014 Tim Murray <timmurray@google.com> Revert "Bring in fixes for Cortex-A53 errata + build updates."

This reverts commit 8a1773694c6d9b1277647440583811ad3d85c6a4.

bug 18094492
odeGen/CriticalAntiDepBreaker.cpp
odeGen/LiveRangeEdit.cpp
odeGen/MachineCSE.cpp
odeGen/MachineLICM.cpp
odeGen/MachineSink.cpp
odeGen/RegisterCoalescer.cpp
arget/AArch64/AArch64.h
arget/AArch64/AArch64A53Fix835769.cpp
arget/AArch64/AArch64A57FPLoadBalancing.cpp
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64InstrInfo.h
arget/AArch64/AArch64Subtarget.h
arget/AArch64/AArch64TargetMachine.cpp
arget/AArch64/Android.mk
arget/AArch64/CMakeLists.txt
8a1773694c6d9b1277647440583811ad3d85c6a4 17-Oct-2014 Stephen Hines <srhines@google.com> Bring in fixes for Cortex-A53 errata + build updates.

Bug: 18034609

(cherry picked from commit bfc2d688b591c574c0cc788348c74545ce894efa)

Change-Id: I010fb735bb84fe97ccb8e3878f9601cb533962f4
odeGen/CriticalAntiDepBreaker.cpp
odeGen/LiveRangeEdit.cpp
odeGen/MachineCSE.cpp
odeGen/MachineLICM.cpp
odeGen/MachineSink.cpp
odeGen/RegisterCoalescer.cpp
arget/AArch64/AArch64.h
arget/AArch64/AArch64A53Fix835769.cpp
arget/AArch64/AArch64A57FPLoadBalancing.cpp
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64InstrInfo.h
arget/AArch64/AArch64Subtarget.h
arget/AArch64/AArch64TargetMachine.cpp
arget/AArch64/Android.mk
arget/AArch64/CMakeLists.txt
593a05ca1e177fc584cba399bf66fbf437ba75d9 11-Aug-2014 Petar Jovanovic <petar.jovanovic@imgtec.com> Add support for scalarizing cttz_zero_undef

Follow up to r214266. Add missing case in ScalarizeVectorResult() for
cttz_zero_undef.

Differential Revision: http://reviews.llvm.org/D4813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215330 91177308-0d34-0410-b5e6-96231b3b80d8

(cherry picked from commit cddb0cfe383207ccec0cc797db401854e5f0c672)

Change-Id: I998526c9a9a77cb340c92ad6b292e7e5a9ba5767
odeGen/SelectionDAG/LegalizeVectorTypes.cpp
f06aaf11fff0e6fa12d4ee959569a263bf7bd779 30-Jul-2014 Petar Jovanovic <petar.jovanovic@imgtec.com> Add support for scalarizing ctlz_zero_undef

Fix the missing case in ScalarizeVectorResult() that was exposed with
libclcore.bc in Android.

Differential Revision: http://reviews.llvm.org/D4645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214266 91177308-0d34-0410-b5e6-96231b3b80d8

(cherry picked from commit 63045274494a5adfedbd4de7280386948f7ca9b9)

Change-Id: I38fc81e0ceefd2cfdd65d7619a62124dc4ceac6f
odeGen/SelectionDAG/LegalizeVectorTypes.cpp
aa9f408cef5714fc0bc0ec61fa4016a3ba0a8c61 12-Sep-2014 Benjamin Kramer <benny.kra@googlemail.com> Legalizer: Use the scalar bit width when promoting bit counting instrs on
vectors.

e.g. when promoting ctlz from <2 x i32> to <2 x i64> we have to fixup
the result by 32 bits, not 64. PR20917.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217671 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/LegalizeIntegerTypes.cpp
cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
nalysis/AliasAnalysis.cpp
nalysis/Analysis.cpp
nalysis/Android.mk
nalysis/BasicAliasAnalysis.cpp
nalysis/BlockFrequencyInfoImpl.cpp
nalysis/CMakeLists.txt
nalysis/ConstantFolding.cpp
nalysis/CostModel.cpp
nalysis/IPA/CallGraphSCCPass.cpp
nalysis/IPA/InlineCost.cpp
nalysis/IVUsers.cpp
nalysis/InstructionSimplify.cpp
nalysis/JumpInstrTableInfo.cpp
nalysis/LoopPass.cpp
nalysis/NoAliasAnalysis.cpp
nalysis/RegionPass.cpp
nalysis/ScalarEvolution.cpp
nalysis/ScalarEvolutionExpander.cpp
nalysis/ScalarEvolutionNormalization.cpp
nalysis/ValueTracking.cpp
smParser/LLLexer.cpp
smParser/LLLexer.h
smParser/LLParser.cpp
smParser/LLParser.h
smParser/LLToken.h
smParser/Parser.cpp
itcode/Reader/BitReader.cpp
itcode/Reader/BitcodeReader.cpp
itcode/Reader/BitcodeReader.h
itcode/Reader/BitstreamReader.cpp
itcode/Writer/BitcodeWriter.cpp
itcode/Writer/ValueEnumerator.cpp
itcode/Writer/ValueEnumerator.h
odeGen/Analysis.cpp
odeGen/Android.mk
odeGen/AsmPrinter/ARMException.cpp
odeGen/AsmPrinter/Android.mk
odeGen/AsmPrinter/AsmPrinter.cpp
odeGen/AsmPrinter/CMakeLists.txt
odeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
odeGen/AsmPrinter/DwarfCFIException.cpp
odeGen/AsmPrinter/DwarfDebug.cpp
odeGen/AsmPrinter/DwarfDebug.h
odeGen/AsmPrinter/DwarfException.cpp
odeGen/AsmPrinter/DwarfException.h
odeGen/AsmPrinter/DwarfUnit.cpp
odeGen/AsmPrinter/DwarfUnit.h
odeGen/AsmPrinter/EHStreamer.cpp
odeGen/AsmPrinter/EHStreamer.h
odeGen/AsmPrinter/Win64Exception.cpp
odeGen/AsmPrinter/WinCodeViewLineTables.cpp
odeGen/AtomicExpandLoadLinkedPass.cpp
odeGen/BasicTargetTransformInfo.cpp
odeGen/BranchFolding.cpp
odeGen/CMakeLists.txt
odeGen/CodeGenPrepare.cpp
odeGen/CriticalAntiDepBreaker.cpp
odeGen/CriticalAntiDepBreaker.h
odeGen/GlobalMerge.cpp
odeGen/JumpInstrTables.cpp
odeGen/LLVMTargetMachine.cpp
odeGen/LiveDebugVariables.cpp
odeGen/LiveDebugVariables.h
odeGen/LiveIntervalAnalysis.cpp
odeGen/MachineBasicBlock.cpp
odeGen/MachineFunction.cpp
odeGen/MachineScheduler.cpp
odeGen/Passes.cpp
odeGen/PeepholeOptimizer.cpp
odeGen/PrologEpilogInserter.cpp
odeGen/RegAllocGreedy.cpp
odeGen/RegisterPressure.cpp
odeGen/ScheduleDAGInstrs.cpp
odeGen/SelectionDAG/DAGCombiner.cpp
odeGen/SelectionDAG/FastISel.cpp
odeGen/SelectionDAG/LegalizeDAG.cpp
odeGen/SelectionDAG/LegalizeIntegerTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.h
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
odeGen/SelectionDAG/LegalizeVectorOps.cpp
odeGen/SelectionDAG/LegalizeVectorTypes.cpp
odeGen/SelectionDAG/ResourcePriorityQueue.cpp
odeGen/SelectionDAG/ScheduleDAGRRList.cpp
odeGen/SelectionDAG/ScheduleDAGVLIW.cpp
odeGen/SelectionDAG/SelectionDAG.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.h
odeGen/SelectionDAG/SelectionDAGDumper.cpp
odeGen/SelectionDAG/SelectionDAGISel.cpp
odeGen/SelectionDAG/TargetLowering.cpp
odeGen/SelectionDAG/TargetSelectionDAGInfo.cpp
odeGen/StackMapLivenessAnalysis.cpp
odeGen/TargetInstrInfo.cpp
odeGen/TargetLoweringBase.cpp
odeGen/TargetLoweringObjectFileImpl.cpp
ebugInfo/DWARFContext.cpp
ebugInfo/DWARFDebugAranges.cpp
ebugInfo/DWARFDebugAranges.h
ebugInfo/DWARFDebugInfoEntry.cpp
ebugInfo/DWARFDebugInfoEntry.h
ebugInfo/DWARFUnit.cpp
xecutionEngine/ExecutionEngine.cpp
xecutionEngine/IntelJITEvents/IntelJITEventListener.cpp
xecutionEngine/Interpreter/Interpreter.cpp
xecutionEngine/JIT/JIT.cpp
xecutionEngine/JIT/JIT.h
xecutionEngine/JIT/JITEmitter.cpp
xecutionEngine/MCJIT/MCJIT.cpp
xecutionEngine/MCJIT/SectionMemoryManager.cpp
xecutionEngine/RuntimeDyld/Android.mk
xecutionEngine/RuntimeDyld/CMakeLists.txt
xecutionEngine/RuntimeDyld/LLVMBuild.txt
xecutionEngine/RuntimeDyld/ObjectImageCommon.h
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldELF.h
xecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
xecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
R/Android.mk
R/AsmWriter.cpp
R/AsmWriter.h
R/Attributes.cpp
R/AutoUpgrade.cpp
R/CMakeLists.txt
R/Comdat.cpp
R/ConstantFold.cpp
R/Constants.cpp
R/Core.cpp
R/DIBuilder.cpp
R/DebugInfo.cpp
R/DebugLoc.cpp
R/DiagnosticInfo.cpp
R/Function.cpp
R/GCOV.cpp
R/Globals.cpp
R/Instruction.cpp
R/Instructions.cpp
R/Metadata.cpp
R/Module.cpp
R/Pass.cpp
R/PassRegistry.cpp
R/Value.cpp
R/Verifier.cpp
RReader/IRReader.cpp
TO/LLVMBuild.txt
TO/LTOCodeGenerator.cpp
TO/LTOModule.cpp
inker/LinkModules.cpp
C/Android.mk
C/CMakeLists.txt
C/ConstantPools.cpp
C/ELFObjectWriter.cpp
C/LLVMBuild.txt
C/MCAnalysis/Android.mk
C/MCAnalysis/CMakeLists.txt
C/MCAnalysis/LLVMBuild.txt
C/MCAnalysis/MCAtom.cpp
C/MCAnalysis/MCFunction.cpp
C/MCAnalysis/MCModule.cpp
C/MCAnalysis/MCModuleYAML.cpp
C/MCAnalysis/MCObjectDisassembler.cpp
C/MCAnalysis/MCObjectSymbolizer.cpp
C/MCAnalysis/Makefile
C/MCAsmInfo.cpp
C/MCAsmStreamer.cpp
C/MCAssembler.cpp
C/MCAtom.cpp
C/MCContext.cpp
C/MCDwarf.cpp
C/MCELFStreamer.cpp
C/MCFunction.cpp
C/MCMachOStreamer.cpp
C/MCModule.cpp
C/MCModuleYAML.cpp
C/MCNullStreamer.cpp
C/MCObjectDisassembler.cpp
C/MCObjectFileInfo.cpp
C/MCObjectStreamer.cpp
C/MCObjectSymbolizer.cpp
C/MCParser/AsmLexer.cpp
C/MCParser/AsmParser.cpp
C/MCParser/COFFAsmParser.cpp
C/MCParser/DarwinAsmParser.cpp
C/MCParser/ELFAsmParser.cpp
C/MCSectionCOFF.cpp
C/MCStreamer.cpp
C/MCTargetOptions.cpp
C/MCWin64EH.cpp
C/MachObjectWriter.cpp
C/Makefile
C/StringTableBuilder.cpp
C/WinCOFFObjectWriter.cpp
C/WinCOFFStreamer.cpp
C/YAML.cpp
bject/Android.mk
bject/Archive.cpp
bject/Binary.cpp
bject/CMakeLists.txt
bject/COFFObjectFile.cpp
bject/ELFObjectFile.cpp
bject/ELFYAML.cpp
bject/Error.cpp
bject/IRObjectFile.cpp
bject/LLVMBuild.txt
bject/MachOObjectFile.cpp
bject/MachOUniversal.cpp
bject/Object.cpp
bject/ObjectFile.cpp
bject/RecordStreamer.cpp
bject/RecordStreamer.h
bject/StringTableBuilder.cpp
bject/SymbolicFile.cpp
bject/YAML.cpp
ption/ArgList.cpp
rofileData/InstrProf.cpp
rofileData/InstrProfReader.cpp
rofileData/InstrProfWriter.cpp
upport/APFloat.cpp
upport/ARMWinEH.cpp
upport/Android.mk
upport/Atomic.cpp
upport/CMakeLists.txt
upport/CommandLine.cpp
upport/ConvertUTF.c
upport/CrashRecoveryContext.cpp
upport/DataExtractor.cpp
upport/DataStream.cpp
upport/DynamicLibrary.cpp
upport/ErrorHandling.cpp
upport/FileOutputBuffer.cpp
upport/FileUtilities.cpp
upport/GraphWriter.cpp
upport/Host.cpp
upport/LockFileManager.cpp
upport/Makefile
upport/ManagedStatic.cpp
upport/MemoryBuffer.cpp
upport/Path.cpp
upport/Process.cpp
upport/Program.cpp
upport/RandomNumberGenerator.cpp
upport/ScaledNumber.cpp
upport/SourceMgr.cpp
upport/SpecialCaseList.cpp
upport/StringMap.cpp
upport/StringPool.cpp
upport/TargetRegistry.cpp
upport/Threading.cpp
upport/TimeValue.cpp
upport/Timer.cpp
upport/Triple.cpp
upport/Unix/Memory.inc
upport/Unix/Path.inc
upport/Unix/Process.inc
upport/Unix/Program.inc
upport/Unix/system_error.inc
upport/Windows/DynamicLibrary.inc
upport/Windows/Memory.inc
upport/Windows/Path.inc
upport/Windows/Process.inc
upport/Windows/Program.inc
upport/Windows/WindowsSupport.h
upport/Windows/system_error.inc
upport/YAMLTraits.cpp
upport/raw_ostream.cpp
upport/regcclass.h
upport/regcname.h
upport/regex2.h
upport/regutils.h
upport/system_error.cpp
ableGen/Android.mk
ableGen/CMakeLists.txt
ableGen/Main.cpp
ableGen/Record.cpp
ableGen/SetTheory.cpp
ableGen/TGLexer.cpp
ableGen/TGLexer.h
ableGen/TGParser.cpp
ableGen/TGParser.h
arget/AArch64/AArch64.td
arget/AArch64/AArch64AddressTypePromotion.cpp
arget/AArch64/AArch64AsmPrinter.cpp
arget/AArch64/AArch64BranchRelaxation.cpp
arget/AArch64/AArch64CallingConvention.td
arget/AArch64/AArch64FastISel.cpp
arget/AArch64/AArch64FrameLowering.cpp
arget/AArch64/AArch64FrameLowering.h
arget/AArch64/AArch64ISelDAGToDAG.cpp
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64InstrInfo.h
arget/AArch64/AArch64InstrInfo.td
arget/AArch64/AArch64LoadStoreOptimizer.cpp
arget/AArch64/AArch64MCInstLower.cpp
arget/AArch64/AArch64RegisterInfo.td
arget/AArch64/AArch64SchedA53.td
arget/AArch64/AArch64SchedA57.td
arget/AArch64/AArch64SchedA57WriteRes.td
arget/AArch64/AArch64SelectionDAGInfo.cpp
arget/AArch64/AArch64SelectionDAGInfo.h
arget/AArch64/AArch64Subtarget.cpp
arget/AArch64/AArch64Subtarget.h
arget/AArch64/AArch64TargetMachine.cpp
arget/AArch64/AArch64TargetMachine.h
arget/AArch64/AArch64TargetTransformInfo.cpp
arget/AArch64/AsmParser/AArch64AsmParser.cpp
arget/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
arget/AArch64/Disassembler/CMakeLists.txt
arget/AArch64/InstPrinter/AArch64InstPrinter.cpp
arget/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
arget/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
arget/AArch64/MCTargetDesc/AArch64MCExpr.cpp
arget/AArch64/MCTargetDesc/AArch64MCExpr.h
arget/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
arget/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
arget/AArch64/MCTargetDesc/Android.mk
arget/AArch64/MCTargetDesc/CMakeLists.txt
arget/AArch64/Utils/AArch64BaseInfo.h
arget/ARM/A15SDOptimizer.cpp
arget/ARM/ARMAsmPrinter.cpp
arget/ARM/ARMBaseInstrInfo.cpp
arget/ARM/ARMBaseInstrInfo.h
arget/ARM/ARMBaseRegisterInfo.cpp
arget/ARM/ARMCodeEmitter.cpp
arget/ARM/ARMExpandPseudoInsts.cpp
arget/ARM/ARMFastISel.cpp
arget/ARM/ARMFrameLowering.cpp
arget/ARM/ARMFrameLowering.h
arget/ARM/ARMISelDAGToDAG.cpp
arget/ARM/ARMISelLowering.cpp
arget/ARM/ARMISelLowering.h
arget/ARM/ARMInstrInfo.td
arget/ARM/ARMInstrNEON.td
arget/ARM/ARMInstrThumb2.td
arget/ARM/ARMJITInfo.cpp
arget/ARM/ARMJITInfo.h
arget/ARM/ARMLoadStoreOptimizer.cpp
arget/ARM/ARMMCInstLower.cpp
arget/ARM/ARMMachineFunctionInfo.cpp
arget/ARM/ARMMachineFunctionInfo.h
arget/ARM/ARMSelectionDAGInfo.cpp
arget/ARM/ARMSelectionDAGInfo.h
arget/ARM/ARMSubtarget.cpp
arget/ARM/ARMSubtarget.h
arget/ARM/ARMTargetMachine.cpp
arget/ARM/ARMTargetMachine.h
arget/ARM/ARMTargetTransformInfo.cpp
arget/ARM/AsmParser/ARMAsmParser.cpp
arget/ARM/InstPrinter/ARMInstPrinter.cpp
arget/ARM/MCTargetDesc/ARMBaseInfo.h
arget/ARM/MCTargetDesc/ARMELFStreamer.cpp
arget/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
arget/ARM/MCTargetDesc/ARMMCExpr.cpp
arget/ARM/MCTargetDesc/ARMMCExpr.h
arget/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
arget/ARM/MCTargetDesc/ARMMCTargetDesc.h
arget/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
arget/ARM/MCTargetDesc/ARMTargetStreamer.cpp
arget/ARM/Thumb1FrameLowering.cpp
arget/ARM/Thumb1FrameLowering.h
arget/ARM/Thumb2SizeReduction.cpp
arget/CppBackend/CPPBackend.cpp
arget/Hexagon/HexagonFrameLowering.cpp
arget/Hexagon/HexagonFrameLowering.h
arget/Hexagon/HexagonISelLowering.cpp
arget/Hexagon/HexagonISelLowering.h
arget/Hexagon/HexagonInstrInfo.cpp
arget/Hexagon/HexagonMachineScheduler.cpp
arget/Hexagon/HexagonMachineScheduler.h
arget/Hexagon/HexagonSelectionDAGInfo.cpp
arget/Hexagon/HexagonSelectionDAGInfo.h
arget/Hexagon/HexagonSubtarget.cpp
arget/Hexagon/HexagonSubtarget.h
arget/Hexagon/HexagonTargetMachine.cpp
arget/Hexagon/HexagonTargetMachine.h
arget/MSP430/MSP430FrameLowering.h
arget/MSP430/MSP430ISelLowering.cpp
arget/MSP430/MSP430ISelLowering.h
arget/MSP430/MSP430InstrInfo.cpp
arget/MSP430/MSP430InstrInfo.h
arget/MSP430/MSP430RegisterInfo.cpp
arget/MSP430/MSP430RegisterInfo.h
arget/MSP430/MSP430SelectionDAGInfo.cpp
arget/MSP430/MSP430SelectionDAGInfo.h
arget/MSP430/MSP430Subtarget.cpp
arget/MSP430/MSP430Subtarget.h
arget/MSP430/MSP430TargetMachine.cpp
arget/MSP430/MSP430TargetMachine.h
arget/Mips/Android.mk
arget/Mips/AsmParser/MipsAsmParser.cpp
arget/Mips/Disassembler/MipsDisassembler.cpp
arget/Mips/MCTargetDesc/Android.mk
arget/Mips/MCTargetDesc/CMakeLists.txt
arget/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
arget/Mips/MCTargetDesc/MipsABIFlagsSection.h
arget/Mips/MCTargetDesc/MipsAsmBackend.cpp
arget/Mips/MCTargetDesc/MipsAsmBackend.h
arget/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
arget/Mips/MCTargetDesc/MipsFixupKinds.h
arget/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
arget/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
arget/Mips/MCTargetDesc/MipsMCCodeEmitter.h
arget/Mips/MCTargetDesc/MipsMCExpr.cpp
arget/Mips/MCTargetDesc/MipsMCExpr.h
arget/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
arget/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
arget/Mips/MCTargetDesc/MipsTargetStreamer.cpp
arget/Mips/MicroMipsInstrFPU.td
arget/Mips/MicroMipsInstrInfo.td
arget/Mips/Mips.td
arget/Mips/Mips16FrameLowering.cpp
arget/Mips/Mips16FrameLowering.h
arget/Mips/Mips16ISelDAGToDAG.cpp
arget/Mips/Mips16ISelLowering.cpp
arget/Mips/Mips16ISelLowering.h
arget/Mips/Mips16InstrInfo.td
arget/Mips/Mips32r6InstrFormats.td
arget/Mips/Mips32r6InstrInfo.td
arget/Mips/Mips64InstrInfo.td
arget/Mips/Mips64r6InstrInfo.td
arget/Mips/MipsAsmPrinter.cpp
arget/Mips/MipsAsmPrinter.h
arget/Mips/MipsCallingConv.td
arget/Mips/MipsCodeEmitter.cpp
arget/Mips/MipsCondMov.td
arget/Mips/MipsDSPInstrFormats.td
arget/Mips/MipsDelaySlotFiller.cpp
arget/Mips/MipsFastISel.cpp
arget/Mips/MipsFrameLowering.h
arget/Mips/MipsISelDAGToDAG.cpp
arget/Mips/MipsISelDAGToDAG.h
arget/Mips/MipsISelLowering.cpp
arget/Mips/MipsISelLowering.h
arget/Mips/MipsInstrFPU.td
arget/Mips/MipsInstrFormats.td
arget/Mips/MipsInstrInfo.td
arget/Mips/MipsLongBranch.cpp
arget/Mips/MipsMSAInstrFormats.td
arget/Mips/MipsMachineFunction.h
arget/Mips/MipsRegisterInfo.cpp
arget/Mips/MipsRegisterInfo.td
arget/Mips/MipsSEFrameLowering.cpp
arget/Mips/MipsSEFrameLowering.h
arget/Mips/MipsSEISelDAGToDAG.cpp
arget/Mips/MipsSEISelLowering.cpp
arget/Mips/MipsSEISelLowering.h
arget/Mips/MipsSEInstrInfo.cpp
arget/Mips/MipsSEInstrInfo.h
arget/Mips/MipsSelectionDAGInfo.cpp
arget/Mips/MipsSelectionDAGInfo.h
arget/Mips/MipsSubtarget.cpp
arget/Mips/MipsSubtarget.h
arget/Mips/MipsTargetMachine.cpp
arget/Mips/MipsTargetMachine.h
arget/Mips/MipsTargetStreamer.h
arget/NVPTX/NVPTX.td
arget/NVPTX/NVPTXAsmPrinter.cpp
arget/NVPTX/NVPTXFrameLowering.cpp
arget/NVPTX/NVPTXFrameLowering.h
arget/NVPTX/NVPTXGenericToNVVM.cpp
arget/NVPTX/NVPTXISelDAGToDAG.cpp
arget/NVPTX/NVPTXISelDAGToDAG.h
arget/NVPTX/NVPTXISelLowering.cpp
arget/NVPTX/NVPTXISelLowering.h
arget/NVPTX/NVPTXImageOptimizer.cpp
arget/NVPTX/NVPTXInstrInfo.cpp
arget/NVPTX/NVPTXInstrInfo.h
arget/NVPTX/NVPTXInstrInfo.td
arget/NVPTX/NVPTXIntrinsics.td
arget/NVPTX/NVPTXMCExpr.h
arget/NVPTX/NVPTXRegisterInfo.td
arget/NVPTX/NVPTXSubtarget.cpp
arget/NVPTX/NVPTXSubtarget.h
arget/NVPTX/NVPTXTargetMachine.cpp
arget/NVPTX/NVPTXTargetMachine.h
arget/NVPTX/NVVMReflect.cpp
arget/NVPTX/cl_common_defines.h
arget/PowerPC/AsmParser/PPCAsmParser.cpp
arget/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
arget/PowerPC/MCTargetDesc/PPCMCExpr.cpp
arget/PowerPC/MCTargetDesc/PPCMCExpr.h
arget/PowerPC/PPC.td
arget/PowerPC/PPCAsmPrinter.cpp
arget/PowerPC/PPCFastISel.cpp
arget/PowerPC/PPCFrameLowering.cpp
arget/PowerPC/PPCFrameLowering.h
arget/PowerPC/PPCHazardRecognizers.cpp
arget/PowerPC/PPCHazardRecognizers.h
arget/PowerPC/PPCISelDAGToDAG.cpp
arget/PowerPC/PPCISelLowering.cpp
arget/PowerPC/PPCISelLowering.h
arget/PowerPC/PPCInstr64Bit.td
arget/PowerPC/PPCInstrAltivec.td
arget/PowerPC/PPCInstrFormats.td
arget/PowerPC/PPCInstrInfo.cpp
arget/PowerPC/PPCInstrInfo.h
arget/PowerPC/PPCInstrInfo.td
arget/PowerPC/PPCJITInfo.cpp
arget/PowerPC/PPCJITInfo.h
arget/PowerPC/PPCRegisterInfo.cpp
arget/PowerPC/PPCSelectionDAGInfo.cpp
arget/PowerPC/PPCSelectionDAGInfo.h
arget/PowerPC/PPCSubtarget.cpp
arget/PowerPC/PPCSubtarget.h
arget/PowerPC/PPCTargetMachine.cpp
arget/PowerPC/PPCTargetMachine.h
arget/R600/AMDGPU.h
arget/R600/AMDGPU.td
arget/R600/AMDGPUAsmPrinter.cpp
arget/R600/AMDGPUAsmPrinter.h
arget/R600/AMDGPUConvertToISA.cpp
arget/R600/AMDGPUFrameLowering.cpp
arget/R600/AMDGPUISelDAGToDAG.cpp
arget/R600/AMDGPUISelLowering.cpp
arget/R600/AMDGPUISelLowering.h
arget/R600/AMDGPUInstrInfo.cpp
arget/R600/AMDGPUInstrInfo.h
arget/R600/AMDGPUInstrInfo.td
arget/R600/AMDGPUInstructions.td
arget/R600/AMDGPUIntrinsicInfo.cpp
arget/R600/AMDGPUIntrinsicInfo.h
arget/R600/AMDGPUIntrinsics.td
arget/R600/AMDGPUMCInstLower.cpp
arget/R600/AMDGPUMCInstLower.h
arget/R600/AMDGPUPromoteAlloca.cpp
arget/R600/AMDGPURegisterInfo.cpp
arget/R600/AMDGPURegisterInfo.h
arget/R600/AMDGPUSubtarget.cpp
arget/R600/AMDGPUSubtarget.h
arget/R600/AMDGPUTargetMachine.cpp
arget/R600/AMDGPUTargetMachine.h
arget/R600/AMDILBase.td
arget/R600/AMDILISelLowering.cpp
arget/R600/AMDILInstrInfo.td
arget/R600/AMDILIntrinsicInfo.cpp
arget/R600/AMDILIntrinsicInfo.h
arget/R600/AMDILIntrinsics.td
arget/R600/AMDILRegisterInfo.td
arget/R600/CMakeLists.txt
arget/R600/EvergreenInstructions.td
arget/R600/InstPrinter/AMDGPUInstPrinter.cpp
arget/R600/MCTargetDesc/R600MCCodeEmitter.cpp
arget/R600/R600ControlFlowFinalizer.cpp
arget/R600/R600ISelLowering.cpp
arget/R600/R600ISelLowering.h
arget/R600/R600InstrInfo.cpp
arget/R600/R600InstrInfo.h
arget/R600/R600Instructions.td
arget/R600/R600MachineScheduler.cpp
arget/R600/R600Packetizer.cpp
arget/R600/R600RegisterInfo.cpp
arget/R600/R600RegisterInfo.h
arget/R600/R600RegisterInfo.td
arget/R600/SIAnnotateControlFlow.cpp
arget/R600/SIDefines.h
arget/R600/SIFixSGPRLiveRanges.cpp
arget/R600/SIISelLowering.cpp
arget/R600/SIISelLowering.h
arget/R600/SIInsertWaits.cpp
arget/R600/SIInstrFormats.td
arget/R600/SIInstrInfo.cpp
arget/R600/SIInstrInfo.h
arget/R600/SIInstrInfo.td
arget/R600/SIInstructions.td
arget/R600/SIIntrinsics.td
arget/R600/SILowerControlFlow.cpp
arget/R600/SIMachineFunctionInfo.cpp
arget/R600/SIRegisterInfo.cpp
arget/R600/SIRegisterInfo.h
arget/R600/SIRegisterInfo.td
arget/R600/SITypeRewriter.cpp
arget/Sparc/AsmParser/SparcAsmParser.cpp
arget/Sparc/InstPrinter/SparcInstPrinter.cpp
arget/Sparc/MCTargetDesc/SparcAsmBackend.cpp
arget/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
arget/Sparc/MCTargetDesc/SparcMCExpr.cpp
arget/Sparc/MCTargetDesc/SparcMCExpr.h
arget/Sparc/SparcFrameLowering.cpp
arget/Sparc/SparcFrameLowering.h
arget/Sparc/SparcISelLowering.cpp
arget/Sparc/SparcJITInfo.cpp
arget/Sparc/SparcSelectionDAGInfo.cpp
arget/Sparc/SparcSelectionDAGInfo.h
arget/Sparc/SparcSubtarget.cpp
arget/Sparc/SparcSubtarget.h
arget/Sparc/SparcTargetMachine.cpp
arget/Sparc/SparcTargetMachine.h
arget/SystemZ/AsmParser/SystemZAsmParser.cpp
arget/SystemZ/SystemZCallingConv.td
arget/SystemZ/SystemZFrameLowering.cpp
arget/SystemZ/SystemZFrameLowering.h
arget/SystemZ/SystemZISelLowering.cpp
arget/SystemZ/SystemZISelLowering.h
arget/SystemZ/SystemZInstrFP.td
arget/SystemZ/SystemZInstrFormats.td
arget/SystemZ/SystemZInstrInfo.cpp
arget/SystemZ/SystemZInstrInfo.h
arget/SystemZ/SystemZInstrInfo.td
arget/SystemZ/SystemZOperands.td
arget/SystemZ/SystemZOperators.td
arget/SystemZ/SystemZPatterns.td
arget/SystemZ/SystemZRegisterInfo.cpp
arget/SystemZ/SystemZRegisterInfo.h
arget/SystemZ/SystemZRegisterInfo.td
arget/SystemZ/SystemZSelectionDAGInfo.cpp
arget/SystemZ/SystemZSelectionDAGInfo.h
arget/SystemZ/SystemZSubtarget.cpp
arget/SystemZ/SystemZSubtarget.h
arget/SystemZ/SystemZTargetMachine.cpp
arget/SystemZ/SystemZTargetMachine.h
arget/TargetMachine.cpp
arget/TargetSubtargetInfo.cpp
arget/X86/Android.mk
arget/X86/AsmParser/X86AsmInstrumentation.cpp
arget/X86/AsmParser/X86AsmInstrumentation.h
arget/X86/AsmParser/X86AsmParser.cpp
arget/X86/AsmParser/X86Operand.h
arget/X86/CMakeLists.txt
arget/X86/Disassembler/X86DisassemblerDecoder.cpp
arget/X86/MCTargetDesc/X86AsmBackend.cpp
arget/X86/MCTargetDesc/X86MCAsmInfo.cpp
arget/X86/MCTargetDesc/X86MCTargetDesc.cpp
arget/X86/MCTargetDesc/X86MCTargetDesc.h
arget/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
arget/X86/X86.h
arget/X86/X86.td
arget/X86/X86AtomicExpandPass.cpp
arget/X86/X86CodeEmitter.cpp
arget/X86/X86FastISel.cpp
arget/X86/X86FixupLEAs.cpp
arget/X86/X86FrameLowering.cpp
arget/X86/X86FrameLowering.h
arget/X86/X86ISelDAGToDAG.cpp
arget/X86/X86ISelLowering.cpp
arget/X86/X86ISelLowering.h
arget/X86/X86InstrAVX512.td
arget/X86/X86InstrArithmetic.td
arget/X86/X86InstrCompiler.td
arget/X86/X86InstrFragmentsSIMD.td
arget/X86/X86InstrInfo.cpp
arget/X86/X86InstrInfo.h
arget/X86/X86InstrInfo.td
arget/X86/X86InstrSSE.td
arget/X86/X86InstrSystem.td
arget/X86/X86JITInfo.cpp
arget/X86/X86JITInfo.h
arget/X86/X86MCInstLower.cpp
arget/X86/X86RegisterInfo.cpp
arget/X86/X86RegisterInfo.h
arget/X86/X86SelectionDAGInfo.cpp
arget/X86/X86SelectionDAGInfo.h
arget/X86/X86Subtarget.cpp
arget/X86/X86Subtarget.h
arget/X86/X86TargetMachine.cpp
arget/X86/X86TargetMachine.h
arget/X86/X86TargetTransformInfo.cpp
arget/XCore/XCoreFrameLowering.cpp
arget/XCore/XCoreISelLowering.cpp
arget/XCore/XCoreISelLowering.h
arget/XCore/XCoreInstrInfo.cpp
arget/XCore/XCoreSelectionDAGInfo.cpp
arget/XCore/XCoreSelectionDAGInfo.h
arget/XCore/XCoreSubtarget.cpp
arget/XCore/XCoreSubtarget.h
arget/XCore/XCoreTargetMachine.cpp
arget/XCore/XCoreTargetMachine.h
ransforms/IPO/ArgumentPromotion.cpp
ransforms/IPO/DeadArgumentElimination.cpp
ransforms/IPO/FunctionAttrs.cpp
ransforms/IPO/GlobalDCE.cpp
ransforms/IPO/GlobalOpt.cpp
ransforms/IPO/MergeFunctions.cpp
ransforms/IPO/PassManagerBuilder.cpp
ransforms/InstCombine/InstCombine.h
ransforms/InstCombine/InstCombineAddSub.cpp
ransforms/InstCombine/InstCombineAndOrXor.cpp
ransforms/InstCombine/InstCombineCalls.cpp
ransforms/InstCombine/InstCombineCasts.cpp
ransforms/InstCombine/InstCombineCompares.cpp
ransforms/InstCombine/InstCombineLoadStoreAlloca.cpp
ransforms/InstCombine/InstCombineMulDivRem.cpp
ransforms/InstCombine/InstCombineSelect.cpp
ransforms/InstCombine/InstCombineShifts.cpp
ransforms/InstCombine/InstCombineVectorOps.cpp
ransforms/InstCombine/InstructionCombining.cpp
ransforms/Instrumentation/AddressSanitizer.cpp
ransforms/Instrumentation/DataFlowSanitizer.cpp
ransforms/Instrumentation/DebugIR.cpp
ransforms/Instrumentation/GCOVProfiling.cpp
ransforms/Instrumentation/MemorySanitizer.cpp
ransforms/Instrumentation/ThreadSanitizer.cpp
ransforms/Scalar/Android.mk
ransforms/Scalar/CMakeLists.txt
ransforms/Scalar/GVN.cpp
ransforms/Scalar/GlobalMerge.cpp
ransforms/Scalar/JumpThreading.cpp
ransforms/Scalar/LICM.cpp
ransforms/Scalar/LoadCombine.cpp
ransforms/Scalar/LoopIdiomRecognize.cpp
ransforms/Scalar/LoopRerollPass.cpp
ransforms/Scalar/LoopUnrollPass.cpp
ransforms/Scalar/LowerAtomic.cpp
ransforms/Scalar/Reassociate.cpp
ransforms/Scalar/SCCP.cpp
ransforms/Scalar/SROA.cpp
ransforms/Scalar/SampleProfile.cpp
ransforms/Scalar/Scalar.cpp
ransforms/Scalar/ScalarReplAggregates.cpp
ransforms/Scalar/SeparateConstOffsetFromGEP.cpp
ransforms/Scalar/Sink.cpp
ransforms/Utils/Android.mk
ransforms/Utils/CMakeLists.txt
ransforms/Utils/CloneModule.cpp
ransforms/Utils/InlineFunction.cpp
ransforms/Utils/LoopSimplify.cpp
ransforms/Utils/LoopUnroll.cpp
ransforms/Utils/LoopUnrollRuntime.cpp
ransforms/Utils/LowerSwitch.cpp
ransforms/Utils/SimplifyCFG.cpp
ransforms/Utils/SpecialCaseList.cpp
ransforms/Vectorize/LoopVectorize.cpp
ransforms/Vectorize/SLPVectorizer.cpp
075c621d834af7ffc32d2067fadb147cc1758b99 02-Jun-2014 Chris Wailes <chriswailes@google.com> Adds the ability to run the llvm test suite in-tree.

This was accomplished by building additional tools and hand-generating
several files that are auto-generated by the configuration system when
LLVM is built out-of-tree. The LTO, Interpreter, and DebugInfo libraries
are now being compiled, and several source files were added to existing
compilation targets.

To run these tests you must first run build/envsetup.sh and have used
lunch to select a target. You can then launch the test script by running:

cd $ANDROID_BUILD_TOP/external/llvm && ./android_test.sh

Bug: 15433215

Change-Id: I43d87de0a4620cdd46c8d0f825dd4428e8409702
nalysis/Android.mk
ebugInfo/Android.mk
xecutionEngine/Interpreter/Android.mk
R/Android.mk
TO/Android.mk
C/Android.mk
bject/Android.mk
rofileData/Android.mk
upport/Android.mk
7cfe7b81886cb23fc41ff32b5f2bc5941dc3f682 05-Jun-2014 Chris Wailes <chriswailes@google.com> Updated the makefiles to use AArch64 name.

The makefiles had previously used the name Arm64 for the AArch64
libraries. This patch changes all of makefiles to use the correct
name for the backend.

Change-Id: Ida062b1173b719b6d2519618827c3a67ede8b479
arget/AArch64/Android.mk
arget/AArch64/AsmParser/Android.mk
arget/AArch64/Disassembler/Android.mk
arget/AArch64/InstPrinter/Android.mk
arget/AArch64/MCTargetDesc/Android.mk
arget/AArch64/TargetInfo/Android.mk
arget/AArch64/Utils/Android.mk
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
nalysis/AliasAnalysis.cpp
nalysis/AliasAnalysisCounter.cpp
nalysis/AliasSetTracker.cpp
nalysis/Analysis.cpp
nalysis/Android.mk
nalysis/BasicAliasAnalysis.cpp
nalysis/BlockFrequencyInfo.cpp
nalysis/BlockFrequencyInfoImpl.cpp
nalysis/BranchProbabilityInfo.cpp
nalysis/CFG.cpp
nalysis/CFGPrinter.cpp
nalysis/CGSCCPassManager.cpp
nalysis/CMakeLists.txt
nalysis/ConstantFolding.cpp
nalysis/CostModel.cpp
nalysis/Delinearization.cpp
nalysis/DependenceAnalysis.cpp
nalysis/DominanceFrontier.cpp
nalysis/IPA/CallGraph.cpp
nalysis/IPA/CallGraphSCCPass.cpp
nalysis/IPA/GlobalsModRef.cpp
nalysis/IPA/InlineCost.cpp
nalysis/IVUsers.cpp
nalysis/InstCount.cpp
nalysis/InstructionSimplify.cpp
nalysis/IntervalPartition.cpp
nalysis/LazyCallGraph.cpp
nalysis/LazyValueInfo.cpp
nalysis/LibCallAliasAnalysis.cpp
nalysis/LibCallSemantics.cpp
nalysis/Lint.cpp
nalysis/Loads.cpp
nalysis/LoopInfo.cpp
nalysis/LoopPass.cpp
nalysis/MemDepPrinter.cpp
nalysis/MemoryBuiltins.cpp
nalysis/MemoryDependenceAnalysis.cpp
nalysis/NoAliasAnalysis.cpp
nalysis/PHITransAddr.cpp
nalysis/PostDominators.cpp
nalysis/RegionInfo.cpp
nalysis/RegionPass.cpp
nalysis/RegionPrinter.cpp
nalysis/ScalarEvolution.cpp
nalysis/ScalarEvolutionAliasAnalysis.cpp
nalysis/ScalarEvolutionExpander.cpp
nalysis/ScalarEvolutionNormalization.cpp
nalysis/SparsePropagation.cpp
nalysis/TargetTransformInfo.cpp
nalysis/TypeBasedAliasAnalysis.cpp
nalysis/ValueTracking.cpp
smParser/LLLexer.cpp
smParser/LLLexer.h
smParser/LLParser.cpp
smParser/LLParser.h
smParser/LLToken.h
smParser/Parser.cpp
smParser/module.modulemap
itcode/Reader/BitReader.cpp
itcode/Reader/BitcodeReader.cpp
itcode/Reader/BitcodeReader.h
itcode/Reader/BitstreamReader.cpp
itcode/Writer/BitWriter.cpp
itcode/Writer/BitcodeWriter.cpp
itcode/module.modulemap
odeGen/AggressiveAntiDepBreaker.cpp
odeGen/AggressiveAntiDepBreaker.h
odeGen/AllocationOrder.cpp
odeGen/Analysis.cpp
odeGen/Android.mk
odeGen/AsmPrinter/ARMException.cpp
odeGen/AsmPrinter/AddressPool.cpp
odeGen/AsmPrinter/AddressPool.h
odeGen/AsmPrinter/Android.mk
odeGen/AsmPrinter/AsmPrinter.cpp
odeGen/AsmPrinter/AsmPrinterDwarf.cpp
odeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
odeGen/AsmPrinter/CMakeLists.txt
odeGen/AsmPrinter/DIE.cpp
odeGen/AsmPrinter/DIE.h
odeGen/AsmPrinter/DIEHash.cpp
odeGen/AsmPrinter/DIEHash.h
odeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
odeGen/AsmPrinter/DbgValueHistoryCalculator.h
odeGen/AsmPrinter/DebugLocEntry.h
odeGen/AsmPrinter/DwarfAccelTable.cpp
odeGen/AsmPrinter/DwarfAccelTable.h
odeGen/AsmPrinter/DwarfDebug.cpp
odeGen/AsmPrinter/DwarfDebug.h
odeGen/AsmPrinter/DwarfException.cpp
odeGen/AsmPrinter/DwarfFile.cpp
odeGen/AsmPrinter/DwarfFile.h
odeGen/AsmPrinter/DwarfStringPool.cpp
odeGen/AsmPrinter/DwarfStringPool.h
odeGen/AsmPrinter/DwarfUnit.cpp
odeGen/AsmPrinter/DwarfUnit.h
odeGen/AsmPrinter/WinCodeViewLineTables.cpp
odeGen/AsmPrinter/WinCodeViewLineTables.h
odeGen/AtomicExpandLoadLinkedPass.cpp
odeGen/BasicTargetTransformInfo.cpp
odeGen/BranchFolding.cpp
odeGen/CMakeLists.txt
odeGen/CalcSpillWeights.cpp
odeGen/CallingConvLower.cpp
odeGen/CodeGen.cpp
odeGen/CodeGenPrepare.cpp
odeGen/CriticalAntiDepBreaker.cpp
odeGen/DFAPacketizer.cpp
odeGen/DeadMachineInstructionElim.cpp
odeGen/DwarfEHPrepare.cpp
odeGen/EarlyIfConversion.cpp
odeGen/EdgeBundles.cpp
odeGen/ExecutionDepsFix.cpp
odeGen/ExpandISelPseudos.cpp
odeGen/ExpandPostRAPseudos.cpp
odeGen/GCMetadata.cpp
odeGen/GCStrategy.cpp
odeGen/IfConversion.cpp
odeGen/InlineSpiller.cpp
odeGen/InterferenceCache.cpp
odeGen/InterferenceCache.h
odeGen/IntrinsicLowering.cpp
odeGen/LLVMTargetMachine.cpp
odeGen/LatencyPriorityQueue.cpp
odeGen/LexicalScopes.cpp
odeGen/LiveDebugVariables.cpp
odeGen/LiveInterval.cpp
odeGen/LiveIntervalAnalysis.cpp
odeGen/LiveIntervalUnion.cpp
odeGen/LiveRangeCalc.cpp
odeGen/LiveRangeCalc.h
odeGen/LiveRangeEdit.cpp
odeGen/LiveRegMatrix.cpp
odeGen/LiveStackAnalysis.cpp
odeGen/LiveVariables.cpp
odeGen/LocalStackSlotAllocation.cpp
odeGen/MachineBasicBlock.cpp
odeGen/MachineBlockFrequencyInfo.cpp
odeGen/MachineBlockPlacement.cpp
odeGen/MachineBranchProbabilityInfo.cpp
odeGen/MachineCSE.cpp
odeGen/MachineCopyPropagation.cpp
odeGen/MachineFunction.cpp
odeGen/MachineFunctionAnalysis.cpp
odeGen/MachineInstr.cpp
odeGen/MachineLICM.cpp
odeGen/MachineModuleInfo.cpp
odeGen/MachinePassRegistry.cpp
odeGen/MachineRegisterInfo.cpp
odeGen/MachineSSAUpdater.cpp
odeGen/MachineScheduler.cpp
odeGen/MachineSink.cpp
odeGen/MachineTraceMetrics.cpp
odeGen/MachineVerifier.cpp
odeGen/OptimizePHIs.cpp
odeGen/PHIElimination.cpp
odeGen/Passes.cpp
odeGen/PeepholeOptimizer.cpp
odeGen/PostRASchedulerList.cpp
odeGen/ProcessImplicitDefs.cpp
odeGen/PrologEpilogInserter.cpp
odeGen/PseudoSourceValue.cpp
odeGen/RegAllocBase.cpp
odeGen/RegAllocBase.h
odeGen/RegAllocBasic.cpp
odeGen/RegAllocFast.cpp
odeGen/RegAllocGreedy.cpp
odeGen/RegAllocPBQP.cpp
odeGen/RegisterClassInfo.cpp
odeGen/RegisterCoalescer.cpp
odeGen/RegisterCoalescer.h
odeGen/RegisterPressure.cpp
odeGen/RegisterScavenging.cpp
odeGen/ScheduleDAG.cpp
odeGen/ScheduleDAGInstrs.cpp
odeGen/ScoreboardHazardRecognizer.cpp
odeGen/SelectionDAG/DAGCombiner.cpp
odeGen/SelectionDAG/FastISel.cpp
odeGen/SelectionDAG/FunctionLoweringInfo.cpp
odeGen/SelectionDAG/InstrEmitter.cpp
odeGen/SelectionDAG/LegalizeDAG.cpp
odeGen/SelectionDAG/LegalizeFloatTypes.cpp
odeGen/SelectionDAG/LegalizeIntegerTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.h
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
odeGen/SelectionDAG/LegalizeVectorOps.cpp
odeGen/SelectionDAG/LegalizeVectorTypes.cpp
odeGen/SelectionDAG/ResourcePriorityQueue.cpp
odeGen/SelectionDAG/SDNodeDbgValue.h
odeGen/SelectionDAG/ScheduleDAGFast.cpp
odeGen/SelectionDAG/ScheduleDAGRRList.cpp
odeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
odeGen/SelectionDAG/ScheduleDAGSDNodes.h
odeGen/SelectionDAG/ScheduleDAGVLIW.cpp
odeGen/SelectionDAG/SelectionDAG.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.h
odeGen/SelectionDAG/SelectionDAGDumper.cpp
odeGen/SelectionDAG/SelectionDAGISel.cpp
odeGen/SelectionDAG/SelectionDAGPrinter.cpp
odeGen/SelectionDAG/TargetLowering.cpp
odeGen/ShadowStackGC.cpp
odeGen/SjLjEHPrepare.cpp
odeGen/SlotIndexes.cpp
odeGen/SpillPlacement.cpp
odeGen/SpillPlacement.h
odeGen/Spiller.cpp
odeGen/SplitKit.cpp
odeGen/SplitKit.h
odeGen/StackColoring.cpp
odeGen/StackMapLivenessAnalysis.cpp
odeGen/StackMaps.cpp
odeGen/StackProtector.cpp
odeGen/StackSlotColoring.cpp
odeGen/TailDuplication.cpp
odeGen/TargetInstrInfo.cpp
odeGen/TargetLoweringBase.cpp
odeGen/TargetLoweringObjectFileImpl.cpp
odeGen/TargetRegisterInfo.cpp
odeGen/TwoAddressInstructionPass.cpp
odeGen/VirtRegMap.cpp
odeGen/module.modulemap
ebugInfo/DWARFCompileUnit.h
ebugInfo/DWARFContext.cpp
ebugInfo/DWARFContext.h
ebugInfo/DWARFDebugAbbrev.cpp
ebugInfo/DWARFDebugAbbrev.h
ebugInfo/DWARFDebugArangeSet.h
ebugInfo/DWARFDebugAranges.cpp
ebugInfo/DWARFDebugAranges.h
ebugInfo/DWARFDebugFrame.cpp
ebugInfo/DWARFDebugFrame.h
ebugInfo/DWARFDebugInfoEntry.cpp
ebugInfo/DWARFDebugInfoEntry.h
ebugInfo/DWARFDebugLine.cpp
ebugInfo/DWARFDebugLine.h
ebugInfo/DWARFDebugRangeList.cpp
ebugInfo/DWARFDebugRangeList.h
ebugInfo/DWARFFormValue.cpp
ebugInfo/DWARFTypeUnit.h
ebugInfo/DWARFUnit.cpp
ebugInfo/DWARFUnit.h
ebugInfo/module.modulemap
xecutionEngine/ExecutionEngine.cpp
xecutionEngine/ExecutionEngineBindings.cpp
xecutionEngine/IntelJITEvents/IntelJITEventListener.cpp
xecutionEngine/Interpreter/Execution.cpp
xecutionEngine/Interpreter/ExternalFunctions.cpp
xecutionEngine/Interpreter/Interpreter.cpp
xecutionEngine/Interpreter/Interpreter.h
xecutionEngine/JIT/JIT.cpp
xecutionEngine/JIT/JIT.h
xecutionEngine/JIT/JITEmitter.cpp
xecutionEngine/JIT/JITMemoryManager.cpp
xecutionEngine/MCJIT/LLVMBuild.txt
xecutionEngine/MCJIT/MCJIT.cpp
xecutionEngine/MCJIT/MCJIT.h
xecutionEngine/MCJIT/SectionMemoryManager.cpp
xecutionEngine/OProfileJIT/OProfileJITEventListener.cpp
xecutionEngine/OProfileJIT/OProfileWrapper.cpp
xecutionEngine/RuntimeDyld/GDBRegistrar.cpp
xecutionEngine/RuntimeDyld/ObjectImageCommon.h
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldELF.h
xecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
xecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
xecutionEngine/TargetSelect.cpp
R/Android.mk
R/AsmWriter.cpp
R/Attributes.cpp
R/AutoUpgrade.cpp
R/BasicBlock.cpp
R/CMakeLists.txt
R/ConstantFold.cpp
R/Constants.cpp
R/ConstantsContext.h
R/Core.cpp
R/DIBuilder.cpp
R/DataLayout.cpp
R/DebugInfo.cpp
R/DebugLoc.cpp
R/DiagnosticInfo.cpp
R/Function.cpp
R/GCOV.cpp
R/Globals.cpp
R/IRPrintingPasses.cpp
R/InlineAsm.cpp
R/Instruction.cpp
R/Instructions.cpp
R/IntrinsicInst.cpp
R/LLVMContext.cpp
R/LLVMContextImpl.cpp
R/LLVMContextImpl.h
R/LeaksContext.h
R/LegacyPassManager.cpp
R/MDBuilder.cpp
R/Mangler.cpp
R/Metadata.cpp
R/Module.cpp
R/Pass.cpp
R/PassManager.cpp
R/PassRegistry.cpp
R/SymbolTableListTraitsImpl.h
R/Type.cpp
R/Use.cpp
R/Value.cpp
R/ValueSymbolTable.cpp
R/Verifier.cpp
R/module.modulemap
RReader/IRReader.cpp
TO/LTOCodeGenerator.cpp
TO/LTOModule.cpp
inker/LinkModules.cpp
C/Android.mk
C/CMakeLists.txt
C/ELFObjectWriter.cpp
C/MCAsmInfo.cpp
C/MCAsmStreamer.cpp
C/MCAssembler.cpp
C/MCContext.cpp
C/MCDisassembler.cpp
C/MCDisassembler/Disassembler.cpp
C/MCDwarf.cpp
C/MCELFStreamer.cpp
C/MCExpr.cpp
C/MCExternalSymbolizer.cpp
C/MCFixup.cpp
C/MCFunction.cpp
C/MCInst.cpp
C/MCMachOStreamer.cpp
C/MCModule.cpp
C/MCModuleYAML.cpp
C/MCNullStreamer.cpp
C/MCObjectDisassembler.cpp
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C/MCObjectSymbolizer.cpp
C/MCParser/AsmLexer.cpp
C/MCParser/AsmParser.cpp
C/MCParser/COFFAsmParser.cpp
C/MCParser/DarwinAsmParser.cpp
C/MCParser/ELFAsmParser.cpp
C/MCParser/MCAsmLexer.cpp
C/MCParser/MCAsmParser.cpp
C/MCRelocationInfo.cpp
C/MCSectionCOFF.cpp
C/MCSectionMachO.cpp
C/MCStreamer.cpp
C/MCSubtargetInfo.cpp
C/MCTargetOptions.cpp
C/MCValue.cpp
C/MachObjectWriter.cpp
C/SubtargetFeature.cpp
C/WinCOFFObjectWriter.cpp
C/WinCOFFStreamer.cpp
bject/Android.mk
bject/Archive.cpp
bject/CMakeLists.txt
bject/COFFObjectFile.cpp
bject/COFFYAML.cpp
bject/ELF.cpp
bject/ELFYAML.cpp
bject/LLVMBuild.txt
bject/MachOObjectFile.cpp
bject/MachOUniversal.cpp
bject/Object.cpp
bject/StringTableBuilder.cpp
ption/ArgList.cpp
ption/OptTable.cpp
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rofileData/InstrProfReader.cpp
rofileData/InstrProfWriter.cpp
upport/APFloat.cpp
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upport/Mutex.cpp
upport/Path.cpp
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upport/RWMutex.cpp
upport/Regex.cpp
upport/SearchForAddressOfSpecialSymbol.cpp
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upport/Unix/TimeValue.inc
upport/Windows/DynamicLibrary.inc
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upport/YAMLParser.cpp
upport/YAMLTraits.cpp
upport/raw_ostream.cpp
upport/regengine.inc
ableGen/Main.cpp
ableGen/Record.cpp
ableGen/TGLexer.cpp
ableGen/TGLexer.h
ableGen/TGParser.cpp
ableGen/TGParser.h
ableGen/module.modulemap
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arget/NVPTX/NVPTXISelDAGToDAG.h
arget/NVPTX/NVPTXISelLowering.cpp
arget/NVPTX/NVPTXISelLowering.h
arget/NVPTX/NVPTXImageOptimizer.cpp
arget/NVPTX/NVPTXInstrInfo.cpp
arget/NVPTX/NVPTXInstrInfo.h
arget/NVPTX/NVPTXIntrinsics.td
arget/NVPTX/NVPTXLowerAggrCopies.h
arget/NVPTX/NVPTXMCExpr.cpp
arget/NVPTX/NVPTXMCExpr.h
arget/NVPTX/NVPTXMachineFunctionInfo.h
arget/NVPTX/NVPTXPrologEpilogPass.cpp
arget/NVPTX/NVPTXRegisterInfo.cpp
arget/NVPTX/NVPTXRegisterInfo.h
arget/NVPTX/NVPTXReplaceImageHandles.cpp
arget/NVPTX/NVPTXSection.h
arget/NVPTX/NVPTXSubtarget.cpp
arget/NVPTX/NVPTXSubtarget.h
arget/NVPTX/NVPTXTargetMachine.cpp
arget/NVPTX/NVPTXTargetMachine.h
arget/NVPTX/NVPTXTargetObjectFile.h
arget/NVPTX/NVPTXUtilities.cpp
arget/NVPTX/NVPTXUtilities.h
arget/NVPTX/NVVMReflect.cpp
arget/PowerPC/AsmParser/LLVMBuild.txt
arget/PowerPC/AsmParser/PPCAsmParser.cpp
arget/PowerPC/Disassembler/LLVMBuild.txt
arget/PowerPC/Disassembler/PPCDisassembler.cpp
arget/PowerPC/InstPrinter/PPCInstPrinter.cpp
arget/PowerPC/InstPrinter/PPCInstPrinter.h
arget/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
arget/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
arget/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
arget/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
arget/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
arget/PowerPC/MCTargetDesc/PPCMCExpr.cpp
arget/PowerPC/MCTargetDesc/PPCMCExpr.h
arget/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
arget/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
arget/PowerPC/PPCAsmPrinter.cpp
arget/PowerPC/PPCBranchSelector.cpp
arget/PowerPC/PPCCTRLoops.cpp
arget/PowerPC/PPCCodeEmitter.cpp
arget/PowerPC/PPCFastISel.cpp
arget/PowerPC/PPCFrameLowering.cpp
arget/PowerPC/PPCFrameLowering.h
arget/PowerPC/PPCHazardRecognizers.cpp
arget/PowerPC/PPCHazardRecognizers.h
arget/PowerPC/PPCISelDAGToDAG.cpp
arget/PowerPC/PPCISelLowering.cpp
arget/PowerPC/PPCISelLowering.h
arget/PowerPC/PPCInstrAltivec.td
arget/PowerPC/PPCInstrInfo.cpp
arget/PowerPC/PPCInstrInfo.h
arget/PowerPC/PPCInstrInfo.td
arget/PowerPC/PPCInstrVSX.td
arget/PowerPC/PPCJITInfo.cpp
arget/PowerPC/PPCJITInfo.h
arget/PowerPC/PPCMCInstLower.cpp
arget/PowerPC/PPCRegisterInfo.cpp
arget/PowerPC/PPCRegisterInfo.h
arget/PowerPC/PPCRegisterInfo.td
arget/PowerPC/PPCSelectionDAGInfo.cpp
arget/PowerPC/PPCSubtarget.cpp
arget/PowerPC/PPCSubtarget.h
arget/PowerPC/PPCTargetMachine.cpp
arget/PowerPC/PPCTargetMachine.h
arget/PowerPC/PPCTargetTransformInfo.cpp
arget/R600/AMDGPU.h
arget/R600/AMDGPU.td
arget/R600/AMDGPUAsmPrinter.cpp
arget/R600/AMDGPUAsmPrinter.h
arget/R600/AMDGPUCallingConv.td
arget/R600/AMDGPUConvertToISA.cpp
arget/R600/AMDGPUFrameLowering.cpp
arget/R600/AMDGPUFrameLowering.h
arget/R600/AMDGPUISelDAGToDAG.cpp
arget/R600/AMDGPUISelLowering.cpp
arget/R600/AMDGPUISelLowering.h
arget/R600/AMDGPUInstrInfo.cpp
arget/R600/AMDGPUInstrInfo.h
arget/R600/AMDGPUInstrInfo.td
arget/R600/AMDGPUInstructions.td
arget/R600/AMDGPUIntrinsics.td
arget/R600/AMDGPUMCInstLower.cpp
arget/R600/AMDGPUMCInstLower.h
arget/R600/AMDGPURegisterInfo.cpp
arget/R600/AMDGPURegisterInfo.h
arget/R600/AMDGPUSubtarget.cpp
arget/R600/AMDGPUSubtarget.h
arget/R600/AMDGPUTargetMachine.cpp
arget/R600/AMDGPUTargetMachine.h
arget/R600/AMDGPUTargetTransformInfo.cpp
arget/R600/AMDILCFGStructurizer.cpp
arget/R600/AMDILISelLowering.cpp
arget/R600/AMDILIntrinsicInfo.cpp
arget/R600/AMDILIntrinsicInfo.h
arget/R600/AMDILIntrinsics.td
arget/R600/CMakeLists.txt
arget/R600/CaymanInstructions.td
arget/R600/EvergreenInstructions.td
arget/R600/InstPrinter/AMDGPUInstPrinter.cpp
arget/R600/InstPrinter/AMDGPUInstPrinter.h
arget/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
arget/R600/MCTargetDesc/AMDGPUMCAsmInfo.cpp
arget/R600/MCTargetDesc/AMDGPUMCAsmInfo.h
arget/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
arget/R600/MCTargetDesc/LLVMBuild.txt
arget/R600/MCTargetDesc/R600MCCodeEmitter.cpp
arget/R600/MCTargetDesc/SIMCCodeEmitter.cpp
arget/R600/Processors.td
arget/R600/R600ClauseMergePass.cpp
arget/R600/R600ControlFlowFinalizer.cpp
arget/R600/R600EmitClauseMarkers.cpp
arget/R600/R600ExpandSpecialInstrs.cpp
arget/R600/R600ISelLowering.cpp
arget/R600/R600ISelLowering.h
arget/R600/R600InstrInfo.cpp
arget/R600/R600InstrInfo.h
arget/R600/R600Instructions.td
arget/R600/R600MachineFunctionInfo.h
arget/R600/R600MachineScheduler.cpp
arget/R600/R600MachineScheduler.h
arget/R600/R600OptimizeVectorRegisters.cpp
arget/R600/R600Packetizer.cpp
arget/R600/R600RegisterInfo.h
arget/R600/R600TextureIntrinsicsReplacer.cpp
arget/R600/SIAnnotateControlFlow.cpp
arget/R600/SIFixSGPRCopies.cpp
arget/R600/SIISelLowering.cpp
arget/R600/SIISelLowering.h
arget/R600/SIInsertWaits.cpp
arget/R600/SIInstrFormats.td
arget/R600/SIInstrInfo.cpp
arget/R600/SIInstrInfo.h
arget/R600/SIInstrInfo.td
arget/R600/SIInstructions.td
arget/R600/SILowerControlFlow.cpp
arget/R600/SILowerI1Copies.cpp
arget/R600/SIMachineFunctionInfo.cpp
arget/R600/SIMachineFunctionInfo.h
arget/R600/SIRegisterInfo.cpp
arget/R600/SIRegisterInfo.h
arget/R600/SIRegisterInfo.td
arget/R600/SITypeRewriter.cpp
arget/Sparc/AsmParser/LLVMBuild.txt
arget/Sparc/AsmParser/SparcAsmParser.cpp
arget/Sparc/DelaySlotFiller.cpp
arget/Sparc/Disassembler/LLVMBuild.txt
arget/Sparc/Disassembler/SparcDisassembler.cpp
arget/Sparc/InstPrinter/SparcInstPrinter.cpp
arget/Sparc/InstPrinter/SparcInstPrinter.h
arget/Sparc/MCTargetDesc/SparcAsmBackend.cpp
arget/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
arget/Sparc/MCTargetDesc/SparcMCAsmInfo.h
arget/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
arget/Sparc/MCTargetDesc/SparcMCExpr.cpp
arget/Sparc/MCTargetDesc/SparcMCExpr.h
arget/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
arget/Sparc/SparcAsmPrinter.cpp
arget/Sparc/SparcCodeEmitter.cpp
arget/Sparc/SparcFrameLowering.cpp
arget/Sparc/SparcFrameLowering.h
arget/Sparc/SparcISelDAGToDAG.cpp
arget/Sparc/SparcISelLowering.cpp
arget/Sparc/SparcISelLowering.h
arget/Sparc/SparcInstr64Bit.td
arget/Sparc/SparcInstrAliases.td
arget/Sparc/SparcInstrInfo.cpp
arget/Sparc/SparcInstrInfo.h
arget/Sparc/SparcJITInfo.cpp
arget/Sparc/SparcJITInfo.h
arget/Sparc/SparcMCInstLower.cpp
arget/Sparc/SparcRegisterInfo.cpp
arget/Sparc/SparcRegisterInfo.h
arget/Sparc/SparcSelectionDAGInfo.cpp
arget/Sparc/SparcSubtarget.cpp
arget/Sparc/SparcTargetMachine.cpp
arget/Sparc/SparcTargetMachine.h
arget/Sparc/SparcTargetObjectFile.cpp
arget/Sparc/SparcTargetStreamer.h
arget/SystemZ/AsmParser/LLVMBuild.txt
arget/SystemZ/AsmParser/SystemZAsmParser.cpp
arget/SystemZ/Disassembler/SystemZDisassembler.cpp
arget/SystemZ/InstPrinter/SystemZInstPrinter.cpp
arget/SystemZ/MCTargetDesc/LLVMBuild.txt
arget/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
arget/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
arget/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
arget/SystemZ/SystemZElimCompare.cpp
arget/SystemZ/SystemZFrameLowering.cpp
arget/SystemZ/SystemZISelDAGToDAG.cpp
arget/SystemZ/SystemZISelLowering.cpp
arget/SystemZ/SystemZInstrFormats.td
arget/SystemZ/SystemZInstrInfo.cpp
arget/SystemZ/SystemZInstrInfo.h
arget/SystemZ/SystemZLongBranch.cpp
arget/SystemZ/SystemZRegisterInfo.cpp
arget/SystemZ/SystemZRegisterInfo.h
arget/SystemZ/SystemZSelectionDAGInfo.cpp
arget/SystemZ/SystemZShortenInst.cpp
arget/SystemZ/SystemZSubtarget.cpp
arget/Target.cpp
arget/TargetLoweringObjectFile.cpp
arget/TargetMachine.cpp
arget/TargetMachineC.cpp
arget/TargetSubtargetInfo.cpp
arget/X86/Android.mk
arget/X86/AsmParser/X86AsmInstrumentation.cpp
arget/X86/AsmParser/X86AsmInstrumentation.h
arget/X86/AsmParser/X86AsmParser.cpp
arget/X86/AsmParser/X86Operand.h
arget/X86/CMakeLists.txt
arget/X86/Disassembler/Android.mk
arget/X86/Disassembler/CMakeLists.txt
arget/X86/Disassembler/Makefile
arget/X86/Disassembler/X86Disassembler.cpp
arget/X86/Disassembler/X86Disassembler.h
arget/X86/Disassembler/X86DisassemblerDecoder.c
arget/X86/Disassembler/X86DisassemblerDecoder.cpp
arget/X86/Disassembler/X86DisassemblerDecoder.h
arget/X86/Disassembler/X86DisassemblerDecoderCommon.h
arget/X86/InstPrinter/X86ATTInstPrinter.cpp
arget/X86/InstPrinter/X86ATTInstPrinter.h
arget/X86/InstPrinter/X86InstComments.cpp
arget/X86/InstPrinter/X86IntelInstPrinter.cpp
arget/X86/MCTargetDesc/Android.mk
arget/X86/MCTargetDesc/CMakeLists.txt
arget/X86/MCTargetDesc/LLVMBuild.txt
arget/X86/MCTargetDesc/X86AsmBackend.cpp
arget/X86/MCTargetDesc/X86BaseInfo.h
arget/X86/MCTargetDesc/X86ELFObjectWriter.cpp
arget/X86/MCTargetDesc/X86ELFRelocationInfo.cpp
arget/X86/MCTargetDesc/X86FixupKinds.h
arget/X86/MCTargetDesc/X86MCAsmInfo.cpp
arget/X86/MCTargetDesc/X86MCCodeEmitter.cpp
arget/X86/MCTargetDesc/X86MCTargetDesc.cpp
arget/X86/MCTargetDesc/X86MCTargetDesc.h
arget/X86/MCTargetDesc/X86MachORelocationInfo.cpp
arget/X86/MCTargetDesc/X86MachObjectWriter.cpp
arget/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
arget/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
arget/X86/X86.h
arget/X86/X86.td
arget/X86/X86AsmPrinter.cpp
arget/X86/X86AsmPrinter.h
arget/X86/X86COFFMachineModuleInfo.cpp
arget/X86/X86COFFMachineModuleInfo.h
arget/X86/X86CallingConv.h
arget/X86/X86CallingConv.td
arget/X86/X86CodeEmitter.cpp
arget/X86/X86FastISel.cpp
arget/X86/X86FixupLEAs.cpp
arget/X86/X86FloatingPoint.cpp
arget/X86/X86FrameLowering.cpp
arget/X86/X86FrameLowering.h
arget/X86/X86ISelDAGToDAG.cpp
arget/X86/X86ISelLowering.cpp
arget/X86/X86ISelLowering.h
arget/X86/X86InstrAVX512.td
arget/X86/X86InstrBuilder.h
arget/X86/X86InstrCompiler.td
arget/X86/X86InstrFMA.td
arget/X86/X86InstrFragmentsSIMD.td
arget/X86/X86InstrInfo.cpp
arget/X86/X86InstrInfo.h
arget/X86/X86InstrInfo.td
arget/X86/X86InstrMMX.td
arget/X86/X86InstrSSE.td
arget/X86/X86InstrSystem.td
arget/X86/X86JITInfo.cpp
arget/X86/X86MCInstLower.cpp
arget/X86/X86PadShortFunction.cpp
arget/X86/X86RegisterInfo.cpp
arget/X86/X86RegisterInfo.h
arget/X86/X86SchedHaswell.td
arget/X86/X86SchedSandyBridge.td
arget/X86/X86ScheduleAtom.td
arget/X86/X86ScheduleSLM.td
arget/X86/X86SelectionDAGInfo.cpp
arget/X86/X86Subtarget.cpp
arget/X86/X86Subtarget.h
arget/X86/X86TargetMachine.cpp
arget/X86/X86TargetObjectFile.cpp
arget/X86/X86TargetTransformInfo.cpp
arget/X86/X86VZeroUpper.cpp
arget/XCore/Disassembler/XCoreDisassembler.cpp
arget/XCore/InstPrinter/XCoreInstPrinter.cpp
arget/XCore/InstPrinter/XCoreInstPrinter.h
arget/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp
arget/XCore/MCTargetDesc/XCoreMCAsmInfo.h
arget/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
arget/XCore/XCoreAsmPrinter.cpp
arget/XCore/XCoreFrameLowering.cpp
arget/XCore/XCoreFrameLowering.h
arget/XCore/XCoreFrameToArgsOffsetElim.cpp
arget/XCore/XCoreISelDAGToDAG.cpp
arget/XCore/XCoreISelLowering.cpp
arget/XCore/XCoreISelLowering.h
arget/XCore/XCoreInstrInfo.cpp
arget/XCore/XCoreInstrInfo.h
arget/XCore/XCoreLowerThreadLocal.cpp
arget/XCore/XCoreRegisterInfo.cpp
arget/XCore/XCoreRegisterInfo.h
arget/XCore/XCoreSelectionDAGInfo.cpp
arget/XCore/XCoreSelectionDAGInfo.h
arget/XCore/XCoreSubtarget.cpp
arget/XCore/XCoreTargetMachine.cpp
arget/XCore/XCoreTargetMachine.h
arget/XCore/XCoreTargetObjectFile.h
arget/XCore/XCoreTargetTransformInfo.cpp
ransforms/Hello/Hello.cpp
ransforms/IPO/ArgumentPromotion.cpp
ransforms/IPO/ConstantMerge.cpp
ransforms/IPO/DeadArgumentElimination.cpp
ransforms/IPO/ExtractGV.cpp
ransforms/IPO/FunctionAttrs.cpp
ransforms/IPO/GlobalDCE.cpp
ransforms/IPO/GlobalOpt.cpp
ransforms/IPO/IPConstantPropagation.cpp
ransforms/IPO/InlineAlways.cpp
ransforms/IPO/InlineSimple.cpp
ransforms/IPO/Inliner.cpp
ransforms/IPO/Internalize.cpp
ransforms/IPO/LoopExtractor.cpp
ransforms/IPO/MergeFunctions.cpp
ransforms/IPO/PartialInlining.cpp
ransforms/IPO/PassManagerBuilder.cpp
ransforms/IPO/PruneEH.cpp
ransforms/IPO/StripDeadPrototypes.cpp
ransforms/IPO/StripSymbols.cpp
ransforms/InstCombine/InstCombine.h
ransforms/InstCombine/InstCombineAddSub.cpp
ransforms/InstCombine/InstCombineAndOrXor.cpp
ransforms/InstCombine/InstCombineCalls.cpp
ransforms/InstCombine/InstCombineCasts.cpp
ransforms/InstCombine/InstCombineCompares.cpp
ransforms/InstCombine/InstCombineLoadStoreAlloca.cpp
ransforms/InstCombine/InstCombineMulDivRem.cpp
ransforms/InstCombine/InstCombinePHI.cpp
ransforms/InstCombine/InstCombineSelect.cpp
ransforms/InstCombine/InstCombineShifts.cpp
ransforms/InstCombine/InstCombineSimplifyDemanded.cpp
ransforms/InstCombine/InstCombineVectorOps.cpp
ransforms/InstCombine/InstCombineWorklist.h
ransforms/InstCombine/InstructionCombining.cpp
ransforms/Instrumentation/AddressSanitizer.cpp
ransforms/Instrumentation/BoundsChecking.cpp
ransforms/Instrumentation/DataFlowSanitizer.cpp
ransforms/Instrumentation/DebugIR.cpp
ransforms/Instrumentation/DebugIR.h
ransforms/Instrumentation/GCOVProfiling.cpp
ransforms/Instrumentation/MemorySanitizer.cpp
ransforms/Instrumentation/ThreadSanitizer.cpp
ransforms/ObjCARC/ARCRuntimeEntryPoints.h
ransforms/ObjCARC/DependencyAnalysis.cpp
ransforms/ObjCARC/ObjCARCAPElim.cpp
ransforms/ObjCARC/ObjCARCAliasAnalysis.cpp
ransforms/ObjCARC/ObjCARCContract.cpp
ransforms/ObjCARC/ObjCARCExpand.cpp
ransforms/ObjCARC/ObjCARCOpts.cpp
ransforms/Scalar/ADCE.cpp
ransforms/Scalar/Android.mk
ransforms/Scalar/CMakeLists.txt
ransforms/Scalar/ConstantHoisting.cpp
ransforms/Scalar/ConstantProp.cpp
ransforms/Scalar/CorrelatedValuePropagation.cpp
ransforms/Scalar/DCE.cpp
ransforms/Scalar/DeadStoreElimination.cpp
ransforms/Scalar/EarlyCSE.cpp
ransforms/Scalar/FlattenCFGPass.cpp
ransforms/Scalar/GVN.cpp
ransforms/Scalar/GlobalMerge.cpp
ransforms/Scalar/IndVarSimplify.cpp
ransforms/Scalar/JumpThreading.cpp
ransforms/Scalar/LICM.cpp
ransforms/Scalar/LoopDeletion.cpp
ransforms/Scalar/LoopIdiomRecognize.cpp
ransforms/Scalar/LoopInstSimplify.cpp
ransforms/Scalar/LoopRerollPass.cpp
ransforms/Scalar/LoopRotation.cpp
ransforms/Scalar/LoopStrengthReduce.cpp
ransforms/Scalar/LoopUnrollPass.cpp
ransforms/Scalar/LoopUnswitch.cpp
ransforms/Scalar/LowerAtomic.cpp
ransforms/Scalar/MemCpyOptimizer.cpp
ransforms/Scalar/PartiallyInlineLibCalls.cpp
ransforms/Scalar/Reassociate.cpp
ransforms/Scalar/Reg2Mem.cpp
ransforms/Scalar/SCCP.cpp
ransforms/Scalar/SROA.cpp
ransforms/Scalar/SampleProfile.cpp
ransforms/Scalar/Scalar.cpp
ransforms/Scalar/ScalarReplAggregates.cpp
ransforms/Scalar/Scalarizer.cpp
ransforms/Scalar/SeparateConstOffsetFromGEP.cpp
ransforms/Scalar/SimplifyCFGPass.cpp
ransforms/Scalar/Sink.cpp
ransforms/Scalar/StructurizeCFG.cpp
ransforms/Scalar/TailRecursionElimination.cpp
ransforms/Utils/AddDiscriminators.cpp
ransforms/Utils/Android.mk
ransforms/Utils/BasicBlockUtils.cpp
ransforms/Utils/BreakCriticalEdges.cpp
ransforms/Utils/BuildLibCalls.cpp
ransforms/Utils/BypassSlowDivision.cpp
ransforms/Utils/CMakeLists.txt
ransforms/Utils/CloneFunction.cpp
ransforms/Utils/CloneModule.cpp
ransforms/Utils/CmpInstAnalysis.cpp
ransforms/Utils/CodeExtractor.cpp
ransforms/Utils/CtorUtils.cpp
ransforms/Utils/DemoteRegToStack.cpp
ransforms/Utils/FlattenCFG.cpp
ransforms/Utils/GlobalStatus.cpp
ransforms/Utils/InlineFunction.cpp
ransforms/Utils/IntegerDivision.cpp
ransforms/Utils/LCSSA.cpp
ransforms/Utils/Local.cpp
ransforms/Utils/LoopSimplify.cpp
ransforms/Utils/LoopUnroll.cpp
ransforms/Utils/LoopUnrollRuntime.cpp
ransforms/Utils/LowerExpectIntrinsic.cpp
ransforms/Utils/LowerInvoke.cpp
ransforms/Utils/LowerSwitch.cpp
ransforms/Utils/Mem2Reg.cpp
ransforms/Utils/ModuleUtils.cpp
ransforms/Utils/PromoteMemoryToRegister.cpp
ransforms/Utils/SSAUpdater.cpp
ransforms/Utils/SimplifyCFG.cpp
ransforms/Utils/SimplifyIndVar.cpp
ransforms/Utils/SimplifyInstructions.cpp
ransforms/Utils/SimplifyLibCalls.cpp
ransforms/Utils/SpecialCaseList.cpp
ransforms/Utils/UnifyFunctionExitNodes.cpp
ransforms/Utils/ValueMapper.cpp
ransforms/Vectorize/BBVectorize.cpp
ransforms/Vectorize/LoopVectorize.cpp
ransforms/Vectorize/SLPVectorizer.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
nalysis/AliasAnalysis.cpp
nalysis/AliasAnalysisCounter.cpp
nalysis/AliasAnalysisEvaluator.cpp
nalysis/AliasDebugger.cpp
nalysis/AliasSetTracker.cpp
nalysis/Analysis.cpp
nalysis/Android.mk
nalysis/BasicAliasAnalysis.cpp
nalysis/BlockFrequencyInfo.cpp
nalysis/BranchProbabilityInfo.cpp
nalysis/CFG.cpp
nalysis/CFGPrinter.cpp
nalysis/CMakeLists.txt
nalysis/CaptureTracking.cpp
nalysis/CodeMetrics.cpp
nalysis/ConstantFolding.cpp
nalysis/CostModel.cpp
nalysis/Delinearization.cpp
nalysis/DependenceAnalysis.cpp
nalysis/DomPrinter.cpp
nalysis/DominanceFrontier.cpp
nalysis/IPA/Android.mk
nalysis/IPA/CallGraph.cpp
nalysis/IPA/CallGraphSCCPass.cpp
nalysis/IPA/CallPrinter.cpp
nalysis/IPA/FindUsedTypes.cpp
nalysis/IPA/GlobalsModRef.cpp
nalysis/IPA/IPA.cpp
nalysis/IPA/InlineCost.cpp
nalysis/IVUsers.cpp
nalysis/InstCount.cpp
nalysis/InstructionSimplify.cpp
nalysis/Interval.cpp
nalysis/LazyCallGraph.cpp
nalysis/LazyValueInfo.cpp
nalysis/Lint.cpp
nalysis/LoopInfo.cpp
nalysis/LoopPass.cpp
nalysis/MemDepPrinter.cpp
nalysis/MemoryBuiltins.cpp
nalysis/MemoryDependenceAnalysis.cpp
nalysis/ModuleDebugInfoPrinter.cpp
nalysis/NOTICE
nalysis/NoAliasAnalysis.cpp
nalysis/PHITransAddr.cpp
nalysis/PostDominators.cpp
nalysis/PtrUseVisitor.cpp
nalysis/RegionInfo.cpp
nalysis/RegionPass.cpp
nalysis/RegionPrinter.cpp
nalysis/ScalarEvolution.cpp
nalysis/ScalarEvolutionAliasAnalysis.cpp
nalysis/ScalarEvolutionExpander.cpp
nalysis/ScalarEvolutionNormalization.cpp
nalysis/SparsePropagation.cpp
nalysis/TargetTransformInfo.cpp
nalysis/Trace.cpp
nalysis/TypeBasedAliasAnalysis.cpp
nalysis/ValueTracking.cpp
smParser/Android.mk
smParser/LLLexer.cpp
smParser/LLParser.cpp
smParser/LLParser.h
smParser/LLToken.h
smParser/Parser.cpp
itcode/Reader/Android.mk
itcode/Reader/BitReader.cpp
itcode/Reader/BitcodeReader.cpp
itcode/Reader/BitcodeReader.h
itcode/Writer/Android.mk
itcode/Writer/BitWriter.cpp
itcode/Writer/BitcodeWriter.cpp
itcode/Writer/BitcodeWriterPass.cpp
itcode/Writer/ValueEnumerator.cpp
MakeLists.txt
odeGen/AggressiveAntiDepBreaker.cpp
odeGen/AggressiveAntiDepBreaker.h
odeGen/AllocationOrder.h
odeGen/Analysis.cpp
odeGen/Android.mk
odeGen/AsmPrinter/ARMException.cpp
odeGen/AsmPrinter/Android.mk
odeGen/AsmPrinter/AsmPrinter.cpp
odeGen/AsmPrinter/AsmPrinterDwarf.cpp
odeGen/AsmPrinter/AsmPrinterHandler.h
odeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
odeGen/AsmPrinter/ByteStreamer.h
odeGen/AsmPrinter/CMakeLists.txt
odeGen/AsmPrinter/DIE.cpp
odeGen/AsmPrinter/DIE.h
odeGen/AsmPrinter/DIEHash.cpp
odeGen/AsmPrinter/DIEHash.h
odeGen/AsmPrinter/DebugLocEntry.h
odeGen/AsmPrinter/DebugLocList.h
odeGen/AsmPrinter/DwarfAccelTable.cpp
odeGen/AsmPrinter/DwarfAccelTable.h
odeGen/AsmPrinter/DwarfCFIException.cpp
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfCompileUnit.h
odeGen/AsmPrinter/DwarfDebug.cpp
odeGen/AsmPrinter/DwarfDebug.h
odeGen/AsmPrinter/DwarfException.cpp
odeGen/AsmPrinter/DwarfException.h
odeGen/AsmPrinter/DwarfUnit.cpp
odeGen/AsmPrinter/DwarfUnit.h
odeGen/AsmPrinter/ErlangGCPrinter.cpp
odeGen/AsmPrinter/LLVMBuild.txt
odeGen/AsmPrinter/OcamlGCPrinter.cpp
odeGen/AsmPrinter/Win64Exception.cpp
odeGen/AsmPrinter/WinCodeViewLineTables.cpp
odeGen/AsmPrinter/WinCodeViewLineTables.h
odeGen/BasicTargetTransformInfo.cpp
odeGen/BranchFolding.cpp
odeGen/CMakeLists.txt
odeGen/CalcSpillWeights.cpp
odeGen/CodeGen.cpp
odeGen/CodeGenPrepare.cpp
odeGen/CriticalAntiDepBreaker.cpp
odeGen/CriticalAntiDepBreaker.h
odeGen/DFAPacketizer.cpp
odeGen/DeadMachineInstructionElim.cpp
odeGen/DwarfEHPrepare.cpp
odeGen/EarlyIfConversion.cpp
odeGen/ErlangGC.cpp
odeGen/ExecutionDepsFix.cpp
odeGen/ExpandISelPseudos.cpp
odeGen/ExpandPostRAPseudos.cpp
odeGen/GCMetadata.cpp
odeGen/GCStrategy.cpp
odeGen/IfConversion.cpp
odeGen/InlineSpiller.cpp
odeGen/InterferenceCache.cpp
odeGen/InterferenceCache.h
odeGen/IntrinsicLowering.cpp
odeGen/LLVMBuild.txt
odeGen/LLVMTargetMachine.cpp
odeGen/LatencyPriorityQueue.cpp
odeGen/LexicalScopes.cpp
odeGen/LiveDebugVariables.cpp
odeGen/LiveDebugVariables.h
odeGen/LiveInterval.cpp
odeGen/LiveIntervalAnalysis.cpp
odeGen/LivePhysRegs.cpp
odeGen/LiveRangeCalc.cpp
odeGen/LiveRangeEdit.cpp
odeGen/LiveRegMatrix.cpp
odeGen/LiveRegUnits.cpp
odeGen/LocalStackSlotAllocation.cpp
odeGen/MachineBasicBlock.cpp
odeGen/MachineBlockFrequencyInfo.cpp
odeGen/MachineBlockPlacement.cpp
odeGen/MachineBranchProbabilityInfo.cpp
odeGen/MachineCSE.cpp
odeGen/MachineCopyPropagation.cpp
odeGen/MachineFunction.cpp
odeGen/MachineFunctionPass.cpp
odeGen/MachineFunctionPrinterPass.cpp
odeGen/MachineInstr.cpp
odeGen/MachineInstrBundle.cpp
odeGen/MachineLICM.cpp
odeGen/MachineLoopInfo.cpp
odeGen/MachineModuleInfo.cpp
odeGen/MachineRegisterInfo.cpp
odeGen/MachineSSAUpdater.cpp
odeGen/MachineScheduler.cpp
odeGen/MachineSink.cpp
odeGen/MachineTraceMetrics.cpp
odeGen/MachineVerifier.cpp
odeGen/OptimizePHIs.cpp
odeGen/PHIElimination.cpp
odeGen/PHIEliminationUtils.cpp
odeGen/Passes.cpp
odeGen/PeepholeOptimizer.cpp
odeGen/PostRASchedulerList.cpp
odeGen/ProcessImplicitDefs.cpp
odeGen/PrologEpilogInserter.cpp
odeGen/PrologEpilogInserter.h
odeGen/RegAllocBase.cpp
odeGen/RegAllocBase.h
odeGen/RegAllocBasic.cpp
odeGen/RegAllocFast.cpp
odeGen/RegAllocGreedy.cpp
odeGen/RegAllocPBQP.cpp
odeGen/RegisterClassInfo.cpp
odeGen/RegisterCoalescer.cpp
odeGen/RegisterPressure.cpp
odeGen/RegisterScavenging.cpp
odeGen/ScheduleDAG.cpp
odeGen/ScheduleDAGInstrs.cpp
odeGen/ScheduleDAGPrinter.cpp
odeGen/SelectionDAG/Android.mk
odeGen/SelectionDAG/DAGCombiner.cpp
odeGen/SelectionDAG/FastISel.cpp
odeGen/SelectionDAG/FunctionLoweringInfo.cpp
odeGen/SelectionDAG/InstrEmitter.cpp
odeGen/SelectionDAG/LegalizeDAG.cpp
odeGen/SelectionDAG/LegalizeIntegerTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.h
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
odeGen/SelectionDAG/LegalizeVectorOps.cpp
odeGen/SelectionDAG/LegalizeVectorTypes.cpp
odeGen/SelectionDAG/ResourcePriorityQueue.cpp
odeGen/SelectionDAG/SDNodeDbgValue.h
odeGen/SelectionDAG/ScheduleDAGFast.cpp
odeGen/SelectionDAG/ScheduleDAGRRList.cpp
odeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
odeGen/SelectionDAG/ScheduleDAGSDNodes.h
odeGen/SelectionDAG/ScheduleDAGVLIW.cpp
odeGen/SelectionDAG/SelectionDAG.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.h
odeGen/SelectionDAG/SelectionDAGDumper.cpp
odeGen/SelectionDAG/SelectionDAGISel.cpp
odeGen/SelectionDAG/SelectionDAGPrinter.cpp
odeGen/SelectionDAG/TargetLowering.cpp
odeGen/SelectionDAG/TargetSelectionDAGInfo.cpp
odeGen/ShadowStackGC.cpp
odeGen/SjLjEHPrepare.cpp
odeGen/SlotIndexes.cpp
odeGen/SpillPlacement.cpp
odeGen/SpillPlacement.h
odeGen/Spiller.cpp
odeGen/SplitKit.cpp
odeGen/StackColoring.cpp
odeGen/StackMapLivenessAnalysis.cpp
odeGen/StackMaps.cpp
odeGen/StackProtector.cpp
odeGen/StackSlotColoring.cpp
odeGen/TailDuplication.cpp
odeGen/TargetInstrInfo.cpp
odeGen/TargetLoweringBase.cpp
odeGen/TargetLoweringObjectFileImpl.cpp
odeGen/TargetOptionsImpl.cpp
odeGen/TwoAddressInstructionPass.cpp
odeGen/UnreachableBlockElim.cpp
odeGen/VirtRegMap.cpp
ebugInfo/DWARFAbbreviationDeclaration.cpp
ebugInfo/DWARFAbbreviationDeclaration.h
ebugInfo/DWARFCompileUnit.h
ebugInfo/DWARFContext.cpp
ebugInfo/DWARFContext.h
ebugInfo/DWARFDebugAbbrev.cpp
ebugInfo/DWARFDebugArangeSet.cpp
ebugInfo/DWARFDebugArangeSet.h
ebugInfo/DWARFDebugAranges.cpp
ebugInfo/DWARFDebugFrame.cpp
ebugInfo/DWARFDebugFrame.h
ebugInfo/DWARFDebugInfoEntry.cpp
ebugInfo/DWARFDebugInfoEntry.h
ebugInfo/DWARFDebugLine.cpp
ebugInfo/DWARFDebugLine.h
ebugInfo/DWARFDebugLoc.cpp
ebugInfo/DWARFDebugLoc.h
ebugInfo/DWARFDebugRangeList.cpp
ebugInfo/DWARFTypeUnit.h
ebugInfo/DWARFUnit.cpp
ebugInfo/DWARFUnit.h
xecutionEngine/EventListenerCommon.h
xecutionEngine/ExecutionEngine.cpp
xecutionEngine/ExecutionEngineBindings.cpp
xecutionEngine/IntelJITEvents/IntelJITEventListener.cpp
xecutionEngine/IntelJITEvents/jitprofiling.h
xecutionEngine/Interpreter/Execution.cpp
xecutionEngine/Interpreter/Interpreter.cpp
xecutionEngine/Interpreter/Interpreter.h
xecutionEngine/Interpreter/LLVMBuild.txt
xecutionEngine/JIT/JIT.cpp
xecutionEngine/JIT/JIT.h
xecutionEngine/JIT/JITEmitter.cpp
xecutionEngine/JIT/JITMemoryManager.cpp
xecutionEngine/JIT/LLVMBuild.txt
xecutionEngine/LLVMBuild.txt
xecutionEngine/MCJIT/LLVMBuild.txt
xecutionEngine/MCJIT/MCJIT.cpp
xecutionEngine/MCJIT/MCJIT.h
xecutionEngine/MCJIT/SectionMemoryManager.cpp
xecutionEngine/OProfileJIT/OProfileJITEventListener.cpp
xecutionEngine/OProfileJIT/OProfileWrapper.cpp
xecutionEngine/RTDyldMemoryManager.cpp
xecutionEngine/RuntimeDyld/GDBRegistrar.cpp
xecutionEngine/RuntimeDyld/ObjectImageCommon.h
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldELF.h
xecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
xecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
xecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
R/Android.mk
R/AsmWriter.cpp
R/AsmWriter.h
R/AttributeImpl.h
R/Attributes.cpp
R/AutoUpgrade.cpp
R/BasicBlock.cpp
R/CMakeLists.txt
R/ConstantFold.cpp
R/ConstantRange.cpp
R/Constants.cpp
R/ConstantsContext.h
R/Core.cpp
R/DIBuilder.cpp
R/DataLayout.cpp
R/DebugInfo.cpp
R/DebugLoc.cpp
R/DiagnosticInfo.cpp
R/DiagnosticPrinter.cpp
R/Dominators.cpp
R/Function.cpp
R/GCOV.cpp
R/GVMaterializer.cpp
R/Globals.cpp
R/IRPrintingPasses.cpp
R/InlineAsm.cpp
R/Instruction.cpp
R/Instructions.cpp
R/IntrinsicInst.cpp
R/LLVMContext.cpp
R/LLVMContextImpl.cpp
R/LLVMContextImpl.h
R/LeakDetector.cpp
R/LegacyPassManager.cpp
R/Mangler.cpp
R/Metadata.cpp
R/Module.cpp
R/Pass.cpp
R/PassManager.cpp
R/PassRegistry.cpp
R/PrintModulePass.cpp
R/Type.cpp
R/Use.cpp
R/Value.cpp
R/Verifier.cpp
RReader/Android.mk
RReader/IRReader.cpp
LVMBuild.txt
TO/LLVMBuild.txt
TO/LTOCodeGenerator.cpp
TO/LTOModule.cpp
ineEditor/CMakeLists.txt
ineEditor/LLVMBuild.txt
ineEditor/LineEditor.cpp
ineEditor/Makefile
inker/Android.mk
inker/LinkModules.cpp
C/Android.mk
C/CMakeLists.txt
C/ELFObjectWriter.cpp
C/MCAsmBackend.cpp
C/MCAsmInfo.cpp
C/MCAsmInfoCOFF.cpp
C/MCAsmInfoDarwin.cpp
C/MCAsmInfoELF.cpp
C/MCAsmStreamer.cpp
C/MCAssembler.cpp
C/MCContext.cpp
C/MCDisassembler.cpp
C/MCDisassembler/Disassembler.cpp
C/MCDisassembler/Disassembler.h
C/MCDisassembler/LLVMBuild.txt
C/MCDwarf.cpp
C/MCELF.cpp
C/MCELFObjectTargetWriter.cpp
C/MCELFStreamer.cpp
C/MCExpr.cpp
C/MCExternalSymbolizer.cpp
C/MCFixup.cpp
C/MCLinkerOptimizationHint.cpp
C/MCMachOStreamer.cpp
C/MCModuleYAML.cpp
C/MCNullStreamer.cpp
C/MCObjectDisassembler.cpp
C/MCObjectFileInfo.cpp
C/MCObjectStreamer.cpp
C/MCObjectSymbolizer.cpp
C/MCParser/Android.mk
C/MCParser/AsmLexer.cpp
C/MCParser/AsmParser.cpp
C/MCParser/COFFAsmParser.cpp
C/MCParser/DarwinAsmParser.cpp
C/MCParser/ELFAsmParser.cpp
C/MCPureStreamer.cpp
C/MCRelocationInfo.cpp
C/MCSectionCOFF.cpp
C/MCSectionMachO.cpp
C/MCStreamer.cpp
C/MCSymbolizer.cpp
C/MCValue.cpp
C/MachObjectWriter.cpp
C/WinCOFFObjectWriter.cpp
C/WinCOFFStreamer.cpp
akefile
bject/Android.mk
bject/Archive.cpp
bject/Binary.cpp
bject/CMakeLists.txt
bject/COFFObjectFile.cpp
bject/COFFYAML.cpp
bject/ELF.cpp
bject/ELFObjectFile.cpp
bject/ELFYAML.cpp
bject/Error.cpp
bject/IRObjectFile.cpp
bject/LLVMBuild.txt
bject/MachOObjectFile.cpp
bject/MachOUniversal.cpp
bject/Object.cpp
bject/ObjectFile.cpp
bject/SymbolicFile.cpp
bject/YAML.cpp
ption/Android.mk
ption/ArgList.cpp
rofileData/CMakeLists.txt
rofileData/InstrProf.cpp
rofileData/InstrProfReader.cpp
rofileData/InstrProfWriter.cpp
rofileData/LLVMBuild.txt
rofileData/Makefile
upport/APFloat.cpp
upport/APInt.cpp
upport/ARMBuildAttrs.cpp
upport/Allocator.cpp
upport/Android.mk
upport/Atomic.cpp
upport/BlockFrequency.cpp
upport/CMakeLists.txt
upport/CommandLine.cpp
upport/Compression.cpp
upport/ConstantRange.cpp
upport/CrashRecoveryContext.cpp
upport/DAGDeltaAlgorithm.cpp
upport/DataStream.cpp
upport/Dwarf.cpp
upport/DynamicLibrary.cpp
upport/ErrorHandling.cpp
upport/FileOutputBuffer.cpp
upport/FileUtilities.cpp
upport/GraphWriter.cpp
upport/Host.cpp
upport/LEB128.cpp
upport/LineIterator.cpp
upport/LockFileManager.cpp
upport/MemoryBuffer.cpp
upport/Mutex.cpp
upport/Path.cpp
upport/PrettyStackTrace.cpp
upport/Process.cpp
upport/Regex.cpp
upport/SmallPtrSet.cpp
upport/SourceMgr.cpp
upport/Statistic.cpp
upport/StreamableMemoryObject.cpp
upport/StringRef.cpp
upport/TargetRegistry.cpp
upport/ThreadLocal.cpp
upport/Threading.cpp
upport/Timer.cpp
upport/ToolOutputFile.cpp
upport/Triple.cpp
upport/Twine.cpp
upport/Unix/Host.inc
upport/Unix/Memory.inc
upport/Unix/Path.inc
upport/Unix/Process.inc
upport/Unix/Program.inc
upport/Unix/RWMutex.inc
upport/Unix/Signals.inc
upport/Valgrind.cpp
upport/Windows/DynamicLibrary.inc
upport/Windows/Host.inc
upport/Windows/Memory.inc
upport/Windows/Mutex.inc
upport/Windows/Path.inc
upport/Windows/Process.inc
upport/Windows/Program.inc
upport/Windows/RWMutex.inc
upport/Windows/Signals.inc
upport/Windows/ThreadLocal.inc
upport/Windows/TimeValue.inc
upport/Windows/Windows.h
upport/Windows/WindowsSupport.h
upport/YAMLParser.cpp
upport/YAMLTraits.cpp
upport/raw_ostream.cpp
upport/regcomp.c
upport/system_error.cpp
ableGen/Android.mk
ableGen/Error.cpp
ableGen/Main.cpp
ableGen/Record.cpp
ableGen/TGParser.cpp
ableGen/TGParser.h
arget/AArch64/AArch64.h
arget/AArch64/AArch64.td
arget/AArch64/AArch64AsmPrinter.cpp
arget/AArch64/AArch64BranchFixupPass.cpp
arget/AArch64/AArch64CallingConv.td
arget/AArch64/AArch64FrameLowering.cpp
arget/AArch64/AArch64ISelDAGToDAG.cpp
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrInfo.cpp
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arget/AArch64/AArch64InstrInfo.td
arget/AArch64/AArch64InstrNEON.td
arget/AArch64/AArch64MCInstLower.cpp
arget/AArch64/AArch64RegisterInfo.cpp
arget/AArch64/AArch64RegisterInfo.td
arget/AArch64/AArch64Schedule.td
arget/AArch64/AArch64ScheduleA53.td
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arget/AArch64/AArch64Subtarget.h
arget/AArch64/AArch64TargetMachine.cpp
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arget/AArch64/Android.mk
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arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
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arget/ARM/A15SDOptimizer.cpp
arget/ARM/ARM.h
arget/ARM/ARM.td
arget/ARM/ARMAsmPrinter.cpp
arget/ARM/ARMAsmPrinter.h
arget/ARM/ARMAtomicExpandPass.cpp
arget/ARM/ARMBaseInstrInfo.cpp
arget/ARM/ARMBaseInstrInfo.h
arget/ARM/ARMBaseRegisterInfo.cpp
arget/ARM/ARMBaseRegisterInfo.h
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arget/ARM/ARMCallingConv.td
arget/ARM/ARMCodeEmitter.cpp
arget/ARM/ARMConstantIslandPass.cpp
arget/ARM/ARMConstantPoolValue.h
arget/ARM/ARMExpandPseudoInsts.cpp
arget/ARM/ARMFPUName.def
arget/ARM/ARMFastISel.cpp
arget/ARM/ARMFeatures.h
arget/ARM/ARMFrameLowering.cpp
arget/ARM/ARMFrameLowering.h
arget/ARM/ARMHazardRecognizer.cpp
arget/ARM/ARMHazardRecognizer.h
arget/ARM/ARMISelDAGToDAG.cpp
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arget/ARM/AsmParser/ARMAsmParser.cpp
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arget/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
arget/ARM/MCTargetDesc/ARMELFStreamer.cpp
arget/ARM/MCTargetDesc/ARMFixupKinds.h
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arget/ARM/MCTargetDesc/ARMMCAsmInfo.h
arget/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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arget/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp
arget/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
arget/ARM/MCTargetDesc/ARMTargetStreamer.cpp
arget/ARM/MCTargetDesc/ARMUnwindOp.h
arget/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
arget/ARM/MCTargetDesc/ARMUnwindOpAsm.h
arget/ARM/MCTargetDesc/Android.mk
arget/ARM/MCTargetDesc/CMakeLists.txt
arget/ARM/MLxExpansionPass.cpp
arget/ARM/TargetInfo/ARMTargetInfo.cpp
arget/ARM/TargetInfo/Android.mk
arget/ARM/TargetInfo/CMakeLists.txt
arget/ARM/TargetInfo/LLVMBuild.txt
arget/ARM/Thumb1FrameLowering.cpp
arget/ARM/Thumb1FrameLowering.h
arget/ARM/Thumb1InstrInfo.cpp
arget/ARM/Thumb1InstrInfo.h
arget/ARM/Thumb1RegisterInfo.cpp
arget/ARM/Thumb1RegisterInfo.h
arget/ARM/Thumb2ITBlockPass.cpp
arget/ARM/Thumb2InstrInfo.cpp
arget/ARM/Thumb2InstrInfo.h
arget/ARM/Thumb2RegisterInfo.cpp
arget/ARM/Thumb2RegisterInfo.h
arget/ARM/Thumb2SizeReduction.cpp
arget/ARM64/ARM64.h
arget/ARM64/ARM64.td
arget/ARM64/ARM64AddressTypePromotion.cpp
arget/ARM64/ARM64AdvSIMDScalarPass.cpp
arget/ARM64/ARM64AsmPrinter.cpp
arget/ARM64/ARM64BranchRelaxation.cpp
arget/ARM64/ARM64CallingConv.h
arget/ARM64/ARM64CallingConvention.td
arget/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp
arget/ARM64/ARM64CollectLOH.cpp
arget/ARM64/ARM64ConditionalCompares.cpp
arget/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
arget/ARM64/ARM64ExpandPseudoInsts.cpp
arget/ARM64/ARM64FastISel.cpp
arget/ARM64/ARM64FrameLowering.cpp
arget/ARM64/ARM64FrameLowering.h
arget/ARM64/ARM64ISelDAGToDAG.cpp
arget/ARM64/ARM64ISelLowering.cpp
arget/ARM64/ARM64ISelLowering.h
arget/ARM64/ARM64InstrAtomics.td
arget/ARM64/ARM64InstrFormats.td
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arget/ARM64/ARM64InstrInfo.h
arget/ARM64/ARM64InstrInfo.td
arget/ARM64/ARM64LoadStoreOptimizer.cpp
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arget/ARM64/ARM64PerfectShuffle.h
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arget/ARM64/ARM64RegisterInfo.td
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arget/ARM64/ARM64Schedule.td
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arget/ARM64/ARM64SelectionDAGInfo.h
arget/ARM64/ARM64StorePairSuppress.cpp
arget/ARM64/ARM64Subtarget.cpp
arget/ARM64/ARM64Subtarget.h
arget/ARM64/ARM64TargetMachine.cpp
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arget/ARM64/ARM64TargetObjectFile.cpp
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arget/X86/X86Subtarget.cpp
arget/X86/X86Subtarget.h
arget/X86/X86TargetMachine.cpp
arget/X86/X86TargetMachine.h
arget/X86/X86TargetObjectFile.cpp
arget/X86/X86TargetObjectFile.h
arget/X86/X86TargetTransformInfo.cpp
arget/X86/X86VZeroUpper.cpp
arget/XCore/CMakeLists.txt
arget/XCore/Disassembler/CMakeLists.txt
arget/XCore/InstPrinter/CMakeLists.txt
arget/XCore/LLVMBuild.txt
arget/XCore/MCTargetDesc/CMakeLists.txt
arget/XCore/MCTargetDesc/LLVMBuild.txt
arget/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp
arget/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
arget/XCore/TargetInfo/CMakeLists.txt
arget/XCore/TargetInfo/LLVMBuild.txt
arget/XCore/XCore.h
arget/XCore/XCore.td
arget/XCore/XCoreAsmPrinter.cpp
arget/XCore/XCoreCallingConv.td
arget/XCore/XCoreFrameLowering.cpp
arget/XCore/XCoreFrameLowering.h
arget/XCore/XCoreFrameToArgsOffsetElim.cpp
arget/XCore/XCoreISelDAGToDAG.cpp
arget/XCore/XCoreISelLowering.cpp
arget/XCore/XCoreISelLowering.h
arget/XCore/XCoreInstrInfo.cpp
arget/XCore/XCoreInstrInfo.h
arget/XCore/XCoreInstrInfo.td
arget/XCore/XCoreLowerThreadLocal.cpp
arget/XCore/XCoreMCInstLower.cpp
arget/XCore/XCoreMachineFunctionInfo.cpp
arget/XCore/XCoreMachineFunctionInfo.h
arget/XCore/XCoreRegisterInfo.cpp
arget/XCore/XCoreRegisterInfo.h
arget/XCore/XCoreSelectionDAGInfo.cpp
arget/XCore/XCoreSelectionDAGInfo.h
arget/XCore/XCoreTargetMachine.cpp
arget/XCore/XCoreTargetObjectFile.cpp
arget/XCore/XCoreTargetObjectFile.h
arget/XCore/XCoreTargetStreamer.h
arget/XCore/XCoreTargetTransformInfo.cpp
ransforms/Hello/CMakeLists.txt
ransforms/Hello/Hello.cpp
ransforms/IPO/Android.mk
ransforms/IPO/ArgumentPromotion.cpp
ransforms/IPO/BarrierNoopPass.cpp
ransforms/IPO/ConstantMerge.cpp
ransforms/IPO/DeadArgumentElimination.cpp
ransforms/IPO/ExtractGV.cpp
ransforms/IPO/FunctionAttrs.cpp
ransforms/IPO/GlobalDCE.cpp
ransforms/IPO/GlobalOpt.cpp
ransforms/IPO/IPConstantPropagation.cpp
ransforms/IPO/IPO.cpp
ransforms/IPO/InlineAlways.cpp
ransforms/IPO/InlineSimple.cpp
ransforms/IPO/Inliner.cpp
ransforms/IPO/Internalize.cpp
ransforms/IPO/LLVMBuild.txt
ransforms/IPO/LoopExtractor.cpp
ransforms/IPO/MergeFunctions.cpp
ransforms/IPO/PartialInlining.cpp
ransforms/IPO/PassManagerBuilder.cpp
ransforms/IPO/PruneEH.cpp
ransforms/IPO/StripDeadPrototypes.cpp
ransforms/IPO/StripSymbols.cpp
ransforms/InstCombine/Android.mk
ransforms/InstCombine/InstCombine.h
ransforms/InstCombine/InstCombineAddSub.cpp
ransforms/InstCombine/InstCombineAndOrXor.cpp
ransforms/InstCombine/InstCombineCalls.cpp
ransforms/InstCombine/InstCombineCasts.cpp
ransforms/InstCombine/InstCombineCompares.cpp
ransforms/InstCombine/InstCombineLoadStoreAlloca.cpp
ransforms/InstCombine/InstCombineMulDivRem.cpp
ransforms/InstCombine/InstCombinePHI.cpp
ransforms/InstCombine/InstCombineSelect.cpp
ransforms/InstCombine/InstCombineShifts.cpp
ransforms/InstCombine/InstCombineSimplifyDemanded.cpp
ransforms/InstCombine/InstCombineVectorOps.cpp
ransforms/InstCombine/InstCombineWorklist.h
ransforms/InstCombine/InstructionCombining.cpp
ransforms/Instrumentation/AddressSanitizer.cpp
ransforms/Instrumentation/Android.mk
ransforms/Instrumentation/BoundsChecking.cpp
ransforms/Instrumentation/DataFlowSanitizer.cpp
ransforms/Instrumentation/DebugIR.cpp
ransforms/Instrumentation/DebugIR.h
ransforms/Instrumentation/GCOVProfiling.cpp
ransforms/Instrumentation/Instrumentation.cpp
ransforms/Instrumentation/LLVMBuild.txt
ransforms/Instrumentation/MemorySanitizer.cpp
ransforms/Instrumentation/ThreadSanitizer.cpp
ransforms/ObjCARC/Android.mk
ransforms/ObjCARC/DependencyAnalysis.cpp
ransforms/ObjCARC/ObjCARC.h
ransforms/ObjCARC/ObjCARCAPElim.cpp
ransforms/ObjCARC/ObjCARCAliasAnalysis.h
ransforms/ObjCARC/ObjCARCContract.cpp
ransforms/ObjCARC/ObjCARCExpand.cpp
ransforms/ObjCARC/ObjCARCOpts.cpp
ransforms/ObjCARC/ProvenanceAnalysis.cpp
ransforms/Scalar/ADCE.cpp
ransforms/Scalar/Android.mk
ransforms/Scalar/CMakeLists.txt
ransforms/Scalar/CodeGenPrepare.cpp
ransforms/Scalar/ConstantHoisting.cpp
ransforms/Scalar/ConstantProp.cpp
ransforms/Scalar/CorrelatedValuePropagation.cpp
ransforms/Scalar/DCE.cpp
ransforms/Scalar/DeadStoreElimination.cpp
ransforms/Scalar/EarlyCSE.cpp
ransforms/Scalar/FlattenCFGPass.cpp
ransforms/Scalar/GVN.cpp
ransforms/Scalar/GlobalMerge.cpp
ransforms/Scalar/IndVarSimplify.cpp
ransforms/Scalar/JumpThreading.cpp
ransforms/Scalar/LICM.cpp
ransforms/Scalar/LLVMBuild.txt
ransforms/Scalar/LoopDeletion.cpp
ransforms/Scalar/LoopIdiomRecognize.cpp
ransforms/Scalar/LoopInstSimplify.cpp
ransforms/Scalar/LoopRerollPass.cpp
ransforms/Scalar/LoopRotation.cpp
ransforms/Scalar/LoopStrengthReduce.cpp
ransforms/Scalar/LoopUnrollPass.cpp
ransforms/Scalar/LoopUnswitch.cpp
ransforms/Scalar/LowerAtomic.cpp
ransforms/Scalar/MemCpyOptimizer.cpp
ransforms/Scalar/PartiallyInlineLibCalls.cpp
ransforms/Scalar/Reassociate.cpp
ransforms/Scalar/Reg2Mem.cpp
ransforms/Scalar/SCCP.cpp
ransforms/Scalar/SROA.cpp
ransforms/Scalar/SampleProfile.cpp
ransforms/Scalar/Scalar.cpp
ransforms/Scalar/ScalarReplAggregates.cpp
ransforms/Scalar/Scalarizer.cpp
ransforms/Scalar/SimplifyCFGPass.cpp
ransforms/Scalar/Sink.cpp
ransforms/Scalar/StructurizeCFG.cpp
ransforms/Scalar/TailRecursionElimination.cpp
ransforms/Utils/ASanStackFrameLayout.cpp
ransforms/Utils/AddDiscriminators.cpp
ransforms/Utils/Android.mk
ransforms/Utils/BasicBlockUtils.cpp
ransforms/Utils/BreakCriticalEdges.cpp
ransforms/Utils/BuildLibCalls.cpp
ransforms/Utils/CMakeLists.txt
ransforms/Utils/CloneFunction.cpp
ransforms/Utils/CodeExtractor.cpp
ransforms/Utils/DemoteRegToStack.cpp
ransforms/Utils/FlattenCFG.cpp
ransforms/Utils/GlobalStatus.cpp
ransforms/Utils/InlineFunction.cpp
ransforms/Utils/InstructionNamer.cpp
ransforms/Utils/IntegerDivision.cpp
ransforms/Utils/LCSSA.cpp
ransforms/Utils/Local.cpp
ransforms/Utils/LoopSimplify.cpp
ransforms/Utils/LoopUnroll.cpp
ransforms/Utils/LowerExpectIntrinsic.cpp
ransforms/Utils/LowerInvoke.cpp
ransforms/Utils/LowerSwitch.cpp
ransforms/Utils/Mem2Reg.cpp
ransforms/Utils/MetaRenamer.cpp
ransforms/Utils/PromoteMemoryToRegister.cpp
ransforms/Utils/SSAUpdater.cpp
ransforms/Utils/SimplifyCFG.cpp
ransforms/Utils/SimplifyIndVar.cpp
ransforms/Utils/SimplifyInstructions.cpp
ransforms/Utils/SimplifyLibCalls.cpp
ransforms/Utils/SpecialCaseList.cpp
ransforms/Utils/Utils.cpp
ransforms/Vectorize/Android.mk
ransforms/Vectorize/BBVectorize.cpp
ransforms/Vectorize/LLVMBuild.txt
ransforms/Vectorize/LoopVectorize.cpp
ransforms/Vectorize/SLPVectorizer.cpp
ransforms/Vectorize/Vectorize.cpp
97b218ea4ffb9c0883025b8a35a1fb06be7e7a62 17-Apr-2014 Stephen Hines <srhines@google.com> Remove the -O1 WAR for SROA.cpp compilation.

Bug: 8047767
Change-Id: I036af8d0578f723d3f5cb07f1d26b3c6895d8690
ransforms/Scalar/Android.mk
8aa5ce8cbaa58d14493eb694f06c8a0fde23c509 07-Mar-2014 Tim Murray <timmurray@google.com> Make LLVM build on AArch64.

bug 13343378

Change-Id: I4152d2437a144645fa0b5a425b7bfdcb3a2a5594
arget/AArch64/AArch64InstrNEON.td
arget/AArch64/Android.mk
arget/AArch64/AsmParser/Android.mk
arget/AArch64/Disassembler/Android.mk
arget/AArch64/InstPrinter/Android.mk
arget/AArch64/MCTargetDesc/Android.mk
arget/AArch64/TargetInfo/Android.mk
arget/AArch64/Utils/Android.mk
bd3e4ce9cfa61bcc0176ac17a06f0904cb854a9a 19-Feb-2014 Colin Cross <ccross@android.com> am b7485134: am 449fc261: Merge "llvm: convert makefiles to support multilib build"

* commit 'b7485134a2cbecc47904988b4cfde24019ac4fa1':
llvm: convert makefiles to support multilib build
373aa5c665fe6df6b9c5586d397dc3617f25aab5 07-Feb-2014 Stephen Hines <srhines@google.com> Update LLVM for merge to 3.4.

Update config.h files.

Add RS SubtargetFeature for +long64 on ARM devices.

Adjust Android.mk for added/removed files:

+ Delinearization.cpp
- PathNumbering.cpp
- PathProfileInfo.cpp
- PathProfileVerifier.cpp
- ProfileDataLoader.cpp
- ProfileDataLoaderPass.cpp
- ProfileEstimatorPass.cpp
- ProfileInfo.cpp
- ProfileInfoLoader.cpp
- ProfileInfoLoaderPass.cpp
- ProfileVerifierPass.cpp

+ LiveRegUnits.cpp
- ShrinkWrapping.cpp
+ StackMaps.cpp
- StrongPHIElimination.cpp

+ DIEHash.cpp

+ LegacyPassManager.cpp

+ ELF.cpp

+ Unicode.cpp

- MipsOptimizeMathLibCalls.cpp

- MipsELFStreamer.cpp
+ MipsTargetStreamer.cpp

- EdgeProfiling.cpp
+ DataFlowSanitizer.cpp
+ DebugIR.cpp
- OptimalEdgeProfiling.cpp
- PathProfiling.cpp
- ProfilingUtils.cpp

- BasicBlockPlacement.cpp
+ LoopRerollPass.cpp
+ PartiallyInlineLibCalls.cpp
+ SampleProfile.cpp

+ GlobalStatus.cpp

Change-Id: I17dcf0bf53a1720acd8226ae3e30d84993562a91
nalysis/Android.mk
odeGen/Android.mk
odeGen/AsmPrinter/Android.mk
R/Android.mk
C/Android.mk
bject/Android.mk
upport/Android.mk
arget/ARM/ARM.td
arget/ARM/ARMSubtarget.cpp
arget/ARM/ARMSubtarget.h
arget/Mips/Android.mk
arget/Mips/MCTargetDesc/Android.mk
ransforms/Instrumentation/Android.mk
ransforms/Scalar/Android.mk
ransforms/Utils/Android.mk
ce9904c6ea8fd669978a8eefb854b330eb9828ff 12-Feb-2014 Stephen Hines <srhines@google.com> Merge remote-tracking branch 'upstream/release_34' into merge-20140211

Conflicts:
lib/Linker/LinkModules.cpp
lib/Support/Unix/Signals.inc

Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
b7325c318ecf01d4c82391c1f0a63090c8de0144 05-Feb-2014 Colin Cross <ccross@android.com> llvm: convert makefiles to support multilib build

Convert makefiles to allow for building two architectures at the
same time. This will also cause make checkbuild to build the target
libraries for all supported architectures.

Change-Id: Ia5e6fe5b1186a67753faafd3532ed4cb280a8b10
arget/ARM/Android.mk
arget/ARM/Disassembler/Android.mk
arget/ARM/MCTargetDesc/Android.mk
arget/ARM/TargetInfo/Android.mk
arget/Mips/Android.mk
arget/Mips/Disassembler/Android.mk
arget/Mips/MCTargetDesc/Android.mk
arget/Mips/TargetInfo/Android.mk
arget/X86/Android.mk
arget/X86/Disassembler/Android.mk
arget/X86/InstPrinter/Android.mk
arget/X86/MCTargetDesc/Android.mk
arget/X86/TargetInfo/Android.mk
ransforms/Scalar/Android.mk
dbb832b83351cec97b025b61c26536ef50c3181c 24-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197483:
------------------------------------------------------------------------
r197483 | yrnkrn | 2013-12-17 00:40:11 -0800 (Tue, 17 Dec 2013) | 8 lines

There are no __register_frame and __deregister_frame functions
when using structured exception handling (SEH) on Windows 64.

http://llvm-reviews.chandlerc.com/D2378

Patch by Jonathan Liu!


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197944 91177308-0d34-0410-b5e6-96231b3b80d8
xecutionEngine/RTDyldMemoryManager.cpp
2ca55e9ced49ee958be65020998e95c6019e42ab 20-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197492:
------------------------------------------------------------------------
r197492 | dyatkovskiy | 2013-12-17 04:07:33 -0800 (Tue, 17 Dec 2013) | 26 lines

Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045

Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:

$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
[ID=58]
0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
0x41dcb10: i32 = undef [ID=2]

The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.

The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal.

P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197779 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86ISelLowering.cpp
b95f36183ccbb26154accc99fd304f6e04075682 20-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197718:
------------------------------------------------------------------------
r197718 | hans | 2013-12-19 12:32:44 -0800 (Thu, 19 Dec 2013) | 10 lines

Make sys::ThreadLocal<> zero-initialized on non-thread builds (PR18205)

According to the docs, ThreadLocal<>::get() should return NULL
if no object has been set. This patch makes that the case also for non-thread
builds and adds a very basic unit test to check it.

(This was causing PR18205 because PrettyStackTraceHead didn't get zero-
initialized and we'd crash trying to read past the end of that list. We didn't
notice this so much on Linux since we'd crash after printing all the entries,
but on Mac we print into a SmallString, and would crash before printing that.)
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197778 91177308-0d34-0410-b5e6-96231b3b80d8
upport/ThreadLocal.cpp
upport/Unix/ThreadLocal.inc
e39b15195a3607ee708be9d105b5fc591b4665dd 17-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197449:
------------------------------------------------------------------------
r197449 | arnolds | 2013-12-16 17:11:01 -0800 (Mon, 16 Dec 2013) | 7 lines

LoopVectorizer: Don't if-convert constant expressions that can trap

A phi node operand or an instruction operand could be a constant expression that
can trap (division). Check that we don't vectorize such cases.

PR16729
radar://15653590
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197453 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/LoopVectorize.cpp
77e30195a006a022b1554933bc766b604692b9d1 15-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197047:
------------------------------------------------------------------------
r197047 | d0k | 2013-12-11 08:36:09 -0800 (Wed, 11 Dec 2013) | 3 lines

SelectionDAG: Fix a typo.

Found by "cppcheck". PR18208.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197355 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
b525888b1f988f6a993054285a3a43a24c26fbca 15-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197216:
------------------------------------------------------------------------
r197216 | chandlerc | 2013-12-13 00:00:01 -0800 (Fri, 13 Dec 2013) | 9 lines

[inliner] Fix PR18206 by preventing inlining functions that call setjmp
through an invoke instruction.

The original patch for this was written by Mark Seaborn, but I've
reworked his test case into the existing returns_twice test case and
implemented the fix by the prior refactoring to actually run the cost
analysis over invoke instructions, and then here fixing our detection of
the returns_twice attribute to work for both calls and invokes. We never
noticed because we never saw an invoke. =[
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197352 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/IPA/InlineCost.cpp
e6725194d1045eeb5a9371316120b9b027f3d289 15-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197215:
------------------------------------------------------------------------
r197215 | chandlerc | 2013-12-12 23:59:56 -0800 (Thu, 12 Dec 2013) | 24 lines

[inliner] Completely change (and fix) how the inline cost analysis
handles terminator instructions.

The inline cost analysis inheritted some pretty rough handling of
terminator insts from the original cost analysis, and then made it much,
much worse by factoring all of the important analyses into a separate
instruction visitor. That instruction visitor never visited the
terminator.

This works fine for things like conditional branches, but for many other
things we simply computed The Wrong Value. First example are
unconditional branches, which should be free but were counted as full
cost. This is most significant for conditional branches where the
condition simplifies and folds during inlining. We paid a 1 instruction
tax on every branch in a straight line specialized path. =[

Oh, we also claimed that the unreachable instruction had cost.

But it gets worse. Let's consider invoke. We never applied the call
penalty. We never accounted for the cost of the arguments. Nope. Worse
still, we didn't handle the *correctness* constraints of not inlining
recursive invokes, or exception throwing returns_twice functions. Oops.
See PR18206. Sadly, PR18206 requires yet another fix, but this
refactoring is at least a huge step in that direction.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197351 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/IPA/InlineCost.cpp
dd36ddfaec578968b163fc4bbb7148921084aa6e 14-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197178:
------------------------------------------------------------------------
r197178 | hfinkel | 2013-12-12 12:45:24 -0800 (Thu, 12 Dec 2013) | 9 lines

Fix a use-after-free error in GlobalOpt CleanupConstantGlobalUsers

GlobalOpt's CleanupConstantGlobalUsers function uses a worklist array to manage
constant users to be visited. The pointers in this array need to be weak
handles because when we delete a constant array, we may also be holding a
pointer to one of its elements (or an element of one of its elements if we're
dealing with an array of arrays) in the worklist.

Fixes PR17347.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197322 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/IPO/GlobalOpt.cpp
e09cd8d42b7621050d2dcdccc37ee341a1b553d5 14-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197228:
------------------------------------------------------------------------
r197228 | d0k | 2013-12-13 05:40:24 -0800 (Fri, 13 Dec 2013) | 8 lines

X86: When lowering shl_parts, don't emit shift amounts larger than the bit width.

While it's safe for the X86-specific shift nodes, dag combining will
kill generic nodes. Insert an AND to make it safe, isel will nuke it
as x86's shift instructions have an implicit AND.

Fixes PR16108, which contains a contraption to hit this case in between
constant folders.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197321 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86ISelLowering.cpp
593c23caad07bd8b4d042db897b7d9fed7b4f213 12-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r-197100:
------------------------------------------------------------------------
r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line

Remove unused multiclass from PPCInstrInfo.td
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197131 91177308-0d34-0410-b5e6-96231b3b80d8
arget/PowerPC/PPCInstrInfo.td
02d8bf1f24c25a0db1f43789958c28975903ccb7 12-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197100:
------------------------------------------------------------------------
r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line

Remove unused multiclass from PPCInstrInfo.td
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197130 91177308-0d34-0410-b5e6-96231b3b80d8
arget/PowerPC/PPCInstrInfo.td
b29de8ba0044548f0259b5eca180e07bdba992bc 12-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197089:
------------------------------------------------------------------------
r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines

Fix the PPC subsumes-predicate check

For one predicate to subsume another, they must both check the same condition
register. Failure to check this prerequisite was causing miscompiles.

Fixes PR18003.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8
arget/PowerPC/PPCInstrInfo.cpp
b1eb9dd018475d45d9a8f705441f8f6c86a8f986 10-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196858:
------------------------------------------------------------------------
r196858 | nadav | 2013-12-09 17:13:59 -0800 (Mon, 09 Dec 2013) | 1 line

Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196886 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
31985c7d2a8e8c4d14e29904d072e1936dd0b6bb 10-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196806:
------------------------------------------------------------------------
r196806 | apazos | 2013-12-09 11:29:14 -0800 (Mon, 09 Dec 2013) | 11 lines


Fix pattern match for movi with 0D result

Patch by Jiangning Liu.

With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196872 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
51fce2c886e4ca33272975cc80bc1cc5abfcdffd 09-Dec-2013 Manman Ren <manman.ren@gmail.com> Merging r196172:
------------------------------------------------------------------------
r196172 | mren | 2013-12-02 16:12:14 -0800 (Mon, 02 Dec 2013) | 4 lines

Debug Info: rename getDebugInfoVersionFromModule to getDebugMetadataVersionFromModule.

Suggested by Eric.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196823 91177308-0d34-0410-b5e6-96231b3b80d8
R/AutoUpgrade.cpp
R/DebugInfo.cpp
27457ac42f7a9267ab7e0190424a95fecf0ea201 09-Dec-2013 Manman Ren <manman.ren@gmail.com> Merging r196158:
------------------------------------------------------------------------
r196158 | mren | 2013-12-02 13:29:56 -0800 (Mon, 02 Dec 2013) | 12 lines

Debug Info: drop debug info via upgrading path if version number does not match.

Add a helper function getDebugInfoVersionFromModule to return the debug info
version number for a module.

"Verifier/module-flags-1.ll" checks for verification errors.
It will seg fault when calling getDebugInfoVersionFromModule because of the
incorrect format for module flags in the testing case. We make
getModuleFlagsMetadata more robust by checking for error conditions.

PR17982

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196822 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/LLParser.cpp
itcode/Reader/BitcodeReader.cpp
R/AutoUpgrade.cpp
R/DebugInfo.cpp
R/Module.cpp
c877b10446669bf107c19cab78b920ce9cffb989 09-Dec-2013 Manman Ren <manman.ren@gmail.com> Merging r195505:
------------------------------------------------------------------------
r195505 | mren | 2013-11-22 14:06:31 -0800 (Fri, 22 Nov 2013) | 8 lines

Debug Info: move StripDebugInfo from StripSymbols.cpp to DebugInfo.cpp.

We can share the implementation between StripSymbols and dropping debug info
for metadata versions that do not match.

Also update the comments to match the implementation. A follow-on patch will
drop the "Debug Info Version" module flag in StripDebugInfo.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196816 91177308-0d34-0410-b5e6-96231b3b80d8
R/DebugInfo.cpp
ransforms/IPO/StripSymbols.cpp
863c7b48a6672f7074b2e69683fe4259c8c31bd7 09-Dec-2013 Tim Northover <tnorthover@apple.com> Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. This
should fix the issue.
------------------------------------------------------------------------
r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines

[AArch64]Add missing floating point convert, round and misc intrinsics.
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196772 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
54ed08e250a76b570c2162d49633e11b8ebb2d98 09-Dec-2013 Tim Northover <tnorthover@apple.com> Merge r196725 (conflicts on same API as before):
------------------------------------------------------------------------
r196725 | tnorthover | 2013-12-08 15:56:50 +0000 (Sun, 08 Dec 2013) |
19 lines

ARM: fix folding of stack-adjustment (yet again).

When trying to eliminate an "sub sp, sp, #N" instruction by folding
it into an existing push/pop using dummy registers, we need to account
for the fact that this might affect precisely how "fp" gets set in the
prologue.

We were attempting this, but assuming that *whenever* we performed a
fold it would make a difference. This is false, for example, in:
push {r4, r7, lr}
add fp, sp, #4
vpush {d8}
sub sp, sp, #8

we can fold the "sub" into the "vpush", forming "vpush {d7, d8}".
However, in that case the "add fp" instruction mustn't change, which
we were getting wrong before.

Should fix PR18160.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196769 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMFrameLowering.cpp
7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3 09-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196751:
------------------------------------------------------------------------
r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines

[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.


------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196766 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/SparcISelLowering.cpp
arget/Sparc/SparcISelLowering.h
571a02f291b051b22d804f90257e2623cbacd7ec 09-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196755:
------------------------------------------------------------------------
r196755 | venkatra | 2013-12-08 21:13:25 -0800 (Sun, 08 Dec 2013) | 2 lines

[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196764 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/SparcISelLowering.cpp
f9a98aeb5b5129c9eeb95978c7cf925e4a88e224 09-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196735:
------------------------------------------------------------------------
r196735 | venkatra | 2013-12-08 14:06:07 -0800 (Sun, 08 Dec 2013) | 3 lines

[SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.
This fixes PR18150.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196744 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/SparcISelLowering.cpp
e8098892f517c492193f8f8ebdcbb861d7a7b54a 08-Dec-2013 Tim Northover <tnorthover@apple.com> Merging r196493. Simple conflict due to change API of updated
function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196717 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMFrameLowering.cpp
209178dacacb5c254926a9d8c72933f23feced9f 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196638:
------------------------------------------------------------------------
r196638 | arsenm | 2013-12-06 18:58:45 -0800 (Fri, 06 Dec 2013) | 1 line

Fix assert with copy from global through addrspacecast
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196709 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineLoadStoreAlloca.cpp
cf5f97edf1355be0d7847c73559f8f2b73b54074 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196637:
------------------------------------------------------------------------
r196637 | arsenm | 2013-12-06 18:58:41 -0800 (Fri, 06 Dec 2013) | 1 line

Add getBitCastOrAddrSpaceCast
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196707 91177308-0d34-0410-b5e6-96231b3b80d8
R/Constants.cpp
b7e206eab9de36cefa28ca79b560772d69cfa607 08-Dec-2013 Bill Wendling <isanbard@gmail.com> --- Reverse-merging r196668 into '.':
U lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
U test/Transforms/InstCombine/addrspacecast.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196705 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineLoadStoreAlloca.cpp
2bdc0dd2db145591eb3fdc01fa0b2a3d831f334b 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196588:
------------------------------------------------------------------------
r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines

Bug 18149: [AArch32] VSel instructions has no ARMCC field

The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196704 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMBaseInstrInfo.cpp
b376b061da8305e7031cecbde73d78c43b98efba 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196533:
------------------------------------------------------------------------
r196533 | apazos | 2013-12-05 13:07:49 -0800 (Thu, 05 Dec 2013) | 3 lines

Implemented vget/vset_lane_f16 intrinsics


------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196701 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
f04a4d74b86733b853b7445ab6d5a3bde025a30d 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196456:
------------------------------------------------------------------------
r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines

For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
488aab6df3723d49e256042b99e5ef2f5a9cf46b 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196362:
------------------------------------------------------------------------
r196362 | kevinqin | 2013-12-04 00:02:34 -0800 (Wed, 04 Dec 2013) | 1 line

[AArch64 Neon] Add ACLE intrinsic vceqz_f64.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196699 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
4d919e4ec419bb2f2a175c28dacc0e7e367262fb 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196360:
------------------------------------------------------------------------
r196360 | kevinqin | 2013-12-03 23:53:28 -0800 (Tue, 03 Dec 2013) | 1 line

[AArch64 NEON] Add missing compare intrinsics.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196697 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
3e87fe769011563bda76ef9848e991cb2aa533cc 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196208:
------------------------------------------------------------------------
r196208 | haoliu | 2013-12-02 21:58:30 -0800 (Mon, 02 Dec 2013) | 3 lines

AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196693 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
180eb0418294b890122b8e9ec1586ea4fe404a7b 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196198:
------------------------------------------------------------------------
r196198 | haoliu | 2013-12-02 19:39:47 -0800 (Mon, 02 Dec 2013) | 3 lines

AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196691 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
a72b30d8e8f4e5debd79d920141b2781b2a4de54 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196192:
------------------------------------------------------------------------
r196192 | jiangning | 2013-12-02 17:33:52 -0800 (Mon, 02 Dec 2013) | 2 lines

Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196690 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
9584d3222fa54f7419d008c41d49b4b44331c51c 08-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196190:
------------------------------------------------------------------------
r196190 | jiangning | 2013-12-02 17:29:32 -0800 (Mon, 02 Dec 2013) | 2 lines

Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196688 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64InstrNEON.td
fccbdd27bcd604e232dfa8c77105dcb625da305e 07-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196638:
------------------------------------------------------------------------
r196638 | arsenm | 2013-12-06 18:58:45 -0800 (Fri, 06 Dec 2013) | 1 line

Fix assert with copy from global through addrspacecast
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196668 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineLoadStoreAlloca.cpp
d51d36e3f1c83eb183625af2e3988a08bb984cb7 07-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196391:
------------------------------------------------------------------------
r196391 | hliao | 2013-12-04 09:44:22 -0800 (Wed, 04 Dec 2013) | 5 lines

[X86] Check YMM31/ZMM31 as well

- No test case as there's no calling convention preserve YMM31/ZMM31 only


------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196653 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86VZeroUpper.cpp
2990853ea8bf4888b179ac6c493836b83769e87b 07-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196261:
------------------------------------------------------------------------
r196261 | hliao | 2013-12-03 01:17:32 -0800 (Tue, 03 Dec 2013) | 13 lines

Enhance the fix of PR17631

- The fix to PR17631 fixes part of the cases where 'vzeroupper' should
not be issued before 'call' insn. There're other cases where helper
calls will be inserted not limited to epilog. These helper calls do
not follow the standard calling convention and won't clobber any YMM
registers. (So far, all call conventions will clobber any or part of
YMM registers.)
This patch enhances the previous fix to cover more cases 'vzerosupper' should
not be inserted by checking if that function call won't clobber any YMM
registers and skipping it if so.


------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196652 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86VZeroUpper.cpp
31928dfc03d92322f9f2fb1c4a7878024d3cc9d1 07-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196269:
------------------------------------------------------------------------
r196269 | jamesm | 2013-12-03 03:23:11 -0800 (Tue, 03 Dec 2013) | 5 lines

Addrspacecasts are no-ops on ARM.

Testcase added.


------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196651 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMISelLowering.h
7b7037563b12589e675c655e5d1e4f737f50fa9d 06-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196611:
------------------------------------------------------------------------
r196611 | dexonsmith | 2013-12-06 13:48:36 -0800 (Fri, 06 Dec 2013) | 5 lines

Don't use isNullValue to evaluate ConstantExpr

ConstantExpr can evaluate to false even when isNullValue gives false.

Fixes PR18143.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196614 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstructionCombining.cpp
7f6926930f48234484167e9ecce90f627a030702 06-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196508:
------------------------------------------------------------------------
r196508 | arnolds | 2013-12-05 07:14:40 -0800 (Thu, 05 Dec 2013) | 12 lines

SLPVectorizer: An in-tree vectorized entry cannot also be a scalar external use

We were creating external uses for scalar values in MustGather entries that also
had a ScalarToTreeEntry (they also are present in a vectorized tuple). This
meant we would keep a value 'alive' as a scalar and vectorized causing havoc.
This is not necessary because when we create a MustGather vector we explicitly
create external uses entries for the insertelement instructions of the
MustGather vector elements.

Fixes PR18129.

radar://15582184
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196571 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/SLPVectorizer.cpp
aee5c3e1052b2e144fdc6461bd602cdc502a93cc 05-Dec-2013 Bill Wendling <isanbard@gmail.com> Revert r191049 and r191059. They were causing failures. See PR17975.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196521 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
2a2a323488a31fbdb3524f7f288b8e5c3fc3b7c3 03-Dec-2013 Richard Sandiford <rsandifo@linux.vnet.ibm.com> Merging r196267:
------------------------------------------------------------------------
r196267 | rsandifo | 2013-12-03 11:01:54 +0000 (Tue, 03 Dec 2013) | 12 lines

[SystemZ] Fix choice of known-zero mask in insertion optimization

The backend converts 64-bit ORs into subreg moves if the upper 32 bits
of one operand and the low 32 bits of the other are known to be zero.
It then tries to peel away redundant ANDs from the upper 32 bits.

Since AND masks are canonicalized to exclude known-zero bits,
the test ORs the mask and the known-zero bits together before
checking for redundancy. The problem was that it was using the
wrong node when checking for known-zero bits, so could drop ANDs
that were still needed.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196268 91177308-0d34-0410-b5e6-96231b3b80d8
arget/SystemZ/SystemZISelLowering.cpp
38348240d179131d9292c28c7540ced97b29ed8b 03-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196151:
------------------------------------------------------------------------
r196151 | mcrosier | 2013-12-02 13:05:16 -0800 (Mon, 02 Dec 2013) | 2 lines

[AArch64] Implemented vcopy_lane patterns using scalar DUP instruction.
Patch by Ana Pazos!
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196230 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
cdf67d5791d044a5f217114e18eb8d6242222b98 02-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196104:
------------------------------------------------------------------------
r196104 | rafael | 2013-12-02 06:59:34 -0800 (Mon, 02 Dec 2013) | 1 line

Output .eh_frames on COFF too now that the integrated as is used on mingw.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196137 91177308-0d34-0410-b5e6-96231b3b80d8
C/WinCOFFStreamer.cpp
21f315bc883057c75cedbd31b11f9924af064c2d 02-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196129:
------------------------------------------------------------------------
r196129 | kkhoo | 2013-12-02 10:43:59 -0800 (Mon, 02 Dec 2013) | 1 line

Conservative fix for PR17827 - don't optimize a shift + and + compare sequence where the shift is logical unless the comparison is unsigned
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196132 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineCompares.cpp
1b26fdbf1f01e90b803cc035b6b932cd95c76830 02-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196046:
------------------------------------------------------------------------
r196046 | tnorthover | 2013-12-01 06:16:24 -0800 (Sun, 01 Dec 2013) | 8 lines

ARM: fix bug in -Oz stack adjustment folding

Previously, we clobbered callee-saved registers when folding an "add
sp, #N" into a "pop {rD, ...}" instruction. This change checks whether
a register we're going to add to the "pop" could actually be live
outside the function before doing so and should fix the issue.

This should fix PR18081.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196074 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMBaseInstrInfo.cpp
arget/ARM/ARMBaseRegisterInfo.h
arget/ARM/ARMFrameLowering.cpp
arget/ARM/Thumb1FrameLowering.cpp
3d238de4d54eb0b16afd96a57f49f92b2f7748e0 02-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195401:
------------------------------------------------------------------------
r195401 | lhames | 2013-11-21 16:46:32 -0800 (Thu, 21 Nov 2013) | 8 lines

Fix a typo where we were creating <def,kill> operands instead of
<def,dead> ones.

Add an assertion to make sure we catch this in the future.

Fixes <rdar://problem/15464559>.


------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196073 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMBaseInstrInfo.cpp
247f6b1909347883e6bd132e8e0ef086ced89362 02-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196044:
------------------------------------------------------------------------
r196044 | d0k | 2013-12-01 03:47:42 -0800 (Sun, 01 Dec 2013) | 6 lines

Revamp error checking in the ms inline asm parser.

- Actually abort when an error occurred.
- Check that the frontend lookup worked when parsing length/size/type operators.

Tested by a clang test. PR18096.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196070 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/AsmParser/X86AsmParser.cpp
102f231863034e18863333bf850f8037b46e6947 01-Dec-2013 Daniel Sanders <daniel.sanders@imgtec.com> Merged r195973:
------------------------------------------------------------------------
r195973 | dsanders | 2013-11-30 13:47:57 +0000 (Sat, 30 Nov 2013) | 5 lines

[mips][msa] MSA loads and stores have a 10-bit offset. Account for this when lowering FrameIndex.

This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s
when the stack frame is between 512 and 32,768 bytes in size.

------------------------------------------------------------------------

Review of this commit by Matheus Almeida revealed that it is still possible to
emit invalid code (when the offset is not a multiple of the element size).
However, we agreed that this commit still represents an improvement since it
fixes many cases that previously emitted invalid code, and does not cause any
cases that previously emitted valid code to emit invalid code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196049 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsSERegisterInfo.cpp
ff4b604f961aa9b9ec2f05a5c31885b19fa636e4 01-Dec-2013 Daniel Sanders <daniel.sanders@imgtec.com> Merged r195972:
------------------------------------------------------------------------
r195972 | dsanders | 2013-11-30 13:15:21 +0000 (Sat, 30 Nov 2013) | 5 lines

[mips][msa] A small refactor to reduce patch noise in my next commit

No functional change. An if-statement has been split into two nested if-statements.

------------------------------------------------------------------------



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196047 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsSERegisterInfo.cpp
88fc0183be1b1fc94375421c48f8e0ef6fa9139e 01-Dec-2013 Daniel Sanders <daniel.sanders@imgtec.com> Merged from r195975 and r195976.
------------------------------------------------------------------------
r195975 | zjovanovic | 2013-11-30 19:12:28 +0000 (Sat, 30 Nov 2013) | 1 line

Fixed issue with microMIPS long branch.
------------------------------------------------------------------------
r195976 | zjovanovic | 2013-11-30 19:13:15 +0000 (Sat, 30 Nov 2013) | 1 line

Test case for issue with microMIPS long branch.
------------------------------------------------------------------------

To expand on those commit messages:
The immediate in a MIPS branch is multiplied by the instruction size before use
as an offset. For many MIPS ISA's this is 4 bytes, but for microMIPS it is 2
bytes. This commit corrects the scale factor used for microMIPS so that attempts
to use large offsets result in a valid sequence of instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196043 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsLongBranch.cpp
d0cf77ad590633c0e10336e4c59b509140328042 01-Dec-2013 Bill Wendling <isanbard@gmail.com> --- Reverse-merging r195823 into '.':
U lib/MC/MCSectionCOFF.cpp
U lib/CodeGen/TargetLoweringObjectFileImpl.cpp
U test/MC/COFF/weak-symbol.ll
U test/MC/COFF/tricky-names.ll
G .
--- Recording mergeinfo for reverse merge of r195823 into '.':
G .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196036 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/TargetLoweringObjectFileImpl.cpp
C/MCSectionCOFF.cpp
243896adcf7c22bb54ce136b0e89fa1fa8c4925f 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195941:
------------------------------------------------------------------------
r195941 | haoliu | 2013-11-28 18:11:22 -0800 (Thu, 28 Nov 2013) | 4 lines

AArch64: The pattern match should check the range of the immediate value.
Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196033 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
64762d9538c2edb20009eb947d19103cde754d93 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195938:
------------------------------------------------------------------------
r195938 | jiangning | 2013-11-28 17:37:15 -0800 (Thu, 28 Nov 2013) | 3 lines

Add missing pattern for supporting intrinsic function vbsl_f64 with
argument double floating point.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196030 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
ffafab019600347714602ff8a5ed38ce7d740ee4 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195936:
------------------------------------------------------------------------
r195936 | kevinqin | 2013-11-28 17:29:16 -0800 (Thu, 28 Nov 2013) | 1 line

[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196028 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
arget/AArch64/Disassembler/AArch64Disassembler.cpp
f4b097829a14829bb0e538123326c7537f122a5f 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195932:
------------------------------------------------------------------------
r195932 | d0k | 2013-11-28 11:58:56 -0800 (Thu, 28 Nov 2013) | 3 lines

Silence sign-compare warning and reduce nesting.

No functionality change.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196027 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
508d25f26bf636d5e2c78ce720c7c67bb87d43d2 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195905:
------------------------------------------------------------------------
r195905 | jiangning | 2013-11-27 17:34:55 -0800 (Wed, 27 Nov 2013) | 3 lines

Remove the variable only used by assert to avoid the build failure
caused by build options [-Werror,-Wunused-variable].

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196026 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
ae38e1a9b485dcbeddac0ac9530c195e387cafe3 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195903:
------------------------------------------------------------------------
r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines

AArch64: Fix a bug about disassembling post-index load single element to 4 vectors

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196025 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/Disassembler/AArch64Disassembler.cpp
b50063e0ce18983513d6241c3bd638b074a98e31 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196004:
------------------------------------------------------------------------
r196004 | void | 2013-11-30 19:36:07 -0800 (Sat, 30 Nov 2013) | 3 lines

Use 'unsigned char' to get this past gcc error message:

error: invalid conversion from 'unsigned char' to '{anonymous}::Sequence'
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196005 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/ObjCARC/ObjCARCOpts.cpp
f914aab181e9deb5852dcc5b99fd70e0f5d9db98 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195590:
------------------------------------------------------------------------
r195590 | chapuni | 2013-11-24 16:52:46 -0800 (Sun, 24 Nov 2013) | 1 line

SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable]
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196003 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/SparcFrameLowering.cpp
06866a72b0117e15463b0706d994270b3e20948d 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195677:
------------------------------------------------------------------------
r195677 | dpeixott | 2013-11-25 11:11:13 -0800 (Mon, 25 Nov 2013) | 41 lines

ARM integrated assembler generates incorrect nop opcode

This patch fixes a bug in the assembler that was causing bad code to
be emitted. When switching modes in an assembly file (e.g. arm to
thumb mode) we would always emit the opcode from the original mode.

Consider this small example:

$ cat align.s
.code 16
foo:
add r0, r0
.align 3
add r0, r0

$ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o
$ llvm-objdump -triple thumbv7 -d t.o
Disassembly of section .text:
foo:
0: 00 44 add r0, r0
2: 00 f0 20 e3 blx #4195904
6: 00 00 movs r0, r0
8: 00 44 add r0, r0

This shows that we have actually emitted an arm nop (e320f000)
instead of a thumb nop. Unfortunately, this encodes to a thumb
branch which causes bad things to happen when compiling assembly
code with align directives.

The fix is to notify the ARMAsmBackend when we switch mode. The
MCMachOStreamer was already doing this correctly. This patch makes
the same change for the MCElfStreamer.

There is still a bug in the way nops are emitted for alignment
because the MCAlignment fragment does not store the correct mode.
The ARMAsmBackend will emit nops for the last mode it knew about. In
the example above, we still generate an arm nop if we add a `.code
32` to the end of the file.

PR18019

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196001 91177308-0d34-0410-b5e6-96231b3b80d8
C/MCELFStreamer.cpp
ef39d3e9d0f82338406eb391ce67076eb2611565 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195881:
------------------------------------------------------------------------
r195881 | tstellar | 2013-11-27 13:23:39 -0800 (Wed, 27 Nov 2013) | 3 lines

R600: Expand vector FABS

NOTE: This is a candidate for the 3.4 branch.
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arget/R600/AMDGPUISelLowering.cpp
08885c6758a8ee88a360e30d2be457f759498e10 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195879:
------------------------------------------------------------------------
r195879 | tstellar | 2013-11-27 13:23:29 -0800 (Wed, 27 Nov 2013) | 6 lines

R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs

Writing to the M0 register from an SMRD instruction hangs the GPU, so
we need to use the SGPR_32 register class, which does not include M0.

NOTE: This is a candidate for the 3.4 branch.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195999 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstructions.td
1afaeb1c39125115260b7a06b1dfc8f651d3ac2f 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195878:
------------------------------------------------------------------------
r195878 | tstellar | 2013-11-27 13:23:20 -0800 (Wed, 27 Nov 2013) | 3 lines

R600: Add support for ISD::FROUND

NOTE: This is a candidate for the 3.4 branch.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195998 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPUISelLowering.cpp
arget/R600/AMDGPUInstrInfo.td
arget/R600/R600Instructions.td
d85ed0caa1f780cbd13af1891d2a30fdfbad547a 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195843:
------------------------------------------------------------------------
r195843 | jiangning | 2013-11-27 06:02:25 -0800 (Wed, 27 Nov 2013) | 2 lines

Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195997 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64InstrNEON.td
5f1f4773d95560b68a9c75856563e45e3a4d57e3 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195803:
------------------------------------------------------------------------
r195803 | mcrosier | 2013-11-26 17:45:58 -0800 (Tue, 26 Nov 2013) | 1 line

[AArch64] Add support for NEON scalar floating-point absolute difference.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195994 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
2527bdac885f5822bb2b9a805fc9d80b35dd8f8b 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195788:
------------------------------------------------------------------------
r195788 | mcrosier | 2013-11-26 14:17:37 -0800 (Tue, 26 Nov 2013) | 2 lines

[AArch64] Add support for NEON scalar floating-point to integer convert
instructions.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195993 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
3f297541c5440c4758b34214fdbbf9ae5414c0f1 01-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r195787:
------------------------------------------------------------------------
r195787 | arnolds | 2013-11-26 14:11:23 -0800 (Tue, 26 Nov 2013) | 8 lines

LoopVectorizer: Truncate i64 trip counts of i32 phis if necessary

In signed arithmetic we could end up with an i64 trip count for an i32 phi.
Because it is signed arithmetic we know that this is only defined if the i32
does not wrap. It is therefore safe to truncate the i64 trip count to a i32
value.

Fixes PR18049.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195991 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/LoopVectorize.cpp
3a1e76d62706f2773c23a684446b4c549c151669 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195576:
------------------------------------------------------------------------
r195576 | venkatra | 2013-11-24 12:23:25 -0800 (Sun, 24 Nov 2013) | 2 lines

[Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195870 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/Sparc.h
arget/Sparc/SparcFrameLowering.cpp
arget/Sparc/SparcFrameLowering.h
arget/Sparc/SparcRegisterInfo.cpp
1cefde83ffcfe869e86ef1976667f47856087dd3 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195575:
------------------------------------------------------------------------
r195575 | venkatra | 2013-11-24 12:07:35 -0800 (Sun, 24 Nov 2013) | 2 lines

[Sparc]: Implement LEA pattern for sparcv9.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195869 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/SparcInstr64Bit.td
arget/Sparc/SparcInstrInfo.td
8bb91f77cb1488c19cb4bdb17b4af5f093d233fd 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195574:
------------------------------------------------------------------------
r195574 | venkatra | 2013-11-24 10:41:49 -0800 (Sun, 24 Nov 2013) | 2 lines

[SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself.

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arget/Sparc/SparcAsmPrinter.cpp
f63e418d2c299a540ac27ddfed69b2c4698bb3c3 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195573:
------------------------------------------------------------------------
r195573 | venkatra | 2013-11-24 09:41:41 -0800 (Sun, 24 Nov 2013) | 2 lines

[SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.

------------------------------------------------------------------------


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arget/Sparc/SparcISelLowering.cpp
38af06736e6d46ef3d417e40b9843ca1658fc8e7 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195798:
------------------------------------------------------------------------
r195798 | rafael | 2013-11-26 17:18:37 -0800 (Tue, 26 Nov 2013) | 9 lines

Use simple section names for COMDAT sections on COFF.

With this patch we use simple names for COMDAT sections (like .text or .bss).
This matches the MSVC behavior.

When merging it is the COMDAT symbol that is used to decide if two sections
should be merged, so there is no point in building a fancy name.

This survived a bootstrap on mingw32.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195823 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/TargetLoweringObjectFileImpl.cpp
C/MCSectionCOFF.cpp
0ae07098f7d2ad5a1868d448d0b1b4eef2a3b091 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195148:
------------------------------------------------------------------------
r195148 | rafael | 2013-11-19 11:52:52 -0800 (Tue, 19 Nov 2013) | 15 lines

Support multiple COFF sections with the same name but different COMDAT.

This is the first step to fix pr17918.

It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given

.section foo
.linkonce....

.section foo
.linkonce

we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195822 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/TargetLoweringObjectFileImpl.cpp
C/MCContext.cpp
C/MCParser/COFFAsmParser.cpp
C/WinCOFFStreamer.cpp
b1df5b013a38ab7381630af8b3142c56f604d85b 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195779:
------------------------------------------------------------------------
r195779 | hliao | 2013-11-26 12:31:31 -0800 (Tue, 26 Nov 2013) | 7 lines

Fix PR18054

- Fix bug in (vsext (vzext x)) -> (vsext x) in SIGN_EXTEND_IN_REG
lowering where we need to check whether x is a vector type (in-reg
type) of i8, i16 or i32; otherwise, that optimization is not valid.


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arget/X86/X86ISelLowering.cpp
a0d44fe4cd92c11466b82af4f5089af845a2eeb5 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195791:
------------------------------------------------------------------------
r195791 | nadav | 2013-11-26 14:24:25 -0800 (Tue, 26 Nov 2013) | 4 lines

PR1860 - We can't save a list of ExtractElement instructions to CSE because some of these instructions
may be removed and optimized in future iterations. Instead we save a list of basic blocks that we need to CSE.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195818 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/SLPVectorizer.cpp
3209153cc9728358211b7305305b83cdd0ad1435 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195773:
------------------------------------------------------------------------
r195773 | nadav | 2013-11-26 09:29:19 -0800 (Tue, 26 Nov 2013) | 6 lines

PR18060 - When we RAUW values with ExtractElement instructions in some cases
we generate PHI nodes with multiple entries from the same basic block but
with different values. Enabling CSE on ExtractElement instructions make sure
that all of the RAUWed instructions are the same.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195817 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/SLPVectorizer.cpp
fcb80cc5656e4672702e3150bfe425f4a58b7a65 27-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195769:
------------------------------------------------------------------------
r195769 | dyatkovskiy | 2013-11-26 08:11:03 -0800 (Tue, 26 Nov 2013) | 27 lines

PR17925 bugfix.

Short description.

This issue is about case of treating pointers as integers.
We treat pointers as different if they references different address space.
At the same time, we treat pointers equal to integers (with machine address
width). It was a point of false-positive. Consider next case on 32bit machine:

void foo0(i32 addrespace(1)* %p)
void foo1(i32 addrespace(2)* %p)
void foo2(i32 %p)

foo0 != foo1, while
foo1 == foo2 and foo0 == foo2.

As you can see it breaks transitivity. That means that result depends on order
of how functions are presented in module. Next order causes merging of foo0
and foo1: foo2, foo0, foo1
First foo0 will be merged with foo2, foo0 will be erased. Second foo1 will be
merged with foo2.
Depending on order, things could be merged we don't expect to.

The fix:
Forbid to treat any pointer as integer, except for those, who belong to address space 0.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195810 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/IPO/MergeFunctions.cpp
f38d6740c6532c452983731521b8323d75fc4745 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195424:
------------------------------------------------------------------------
r195424 | haoliu | 2013-11-22 00:47:22 -0800 (Fri, 22 Nov 2013) | 4 lines

Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected.
"%tmp = bitcast i64 %in to <2 x i32>" can't be selected.

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arget/AArch64/AArch64InstrNEON.td
c23b3b05499f4518c64a953eea0a2496739e6d24 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195408:
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r195408 | jiangning | 2013-11-21 18:45:13 -0800 (Thu, 21 Nov 2013) | 2 lines

For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG.

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arget/AArch64/AArch64InstrNEON.td
e40ef6a9fc96c74f7df5681a070246ea990499eb 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195713:
------------------------------------------------------------------------
r195713 | kevinqin | 2013-11-25 18:33:42 -0800 (Mon, 25 Nov 2013) | 1 line

[AArch64]Implement 128 bit register copy with NEON.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195758 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrInfo.cpp
5943d4e3eea9ad5ef55618c075262337463aafa9 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195684:
------------------------------------------------------------------------
r195684 | rafael | 2013-11-25 12:50:03 -0800 (Mon, 25 Nov 2013) | 3 lines

Do the string comparison in the constructor instead of once per nop.

Thanks to Roman Divacky for the suggestion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195746 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/MCTargetDesc/X86AsmBackend.cpp
9f71b97c0cd7ff930164fafe8d6d5b5a9b871c86 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195456:
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r195456 | dsanders | 2013-11-22 05:22:52 -0800 (Fri, 22 Nov 2013) | 4 lines

Fix typo in a comment added in r195455.

Credit to Matheus Almeida for spotting it.

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arget/Mips/MipsSEISelLowering.cpp
876f8f123e9a52bf8e970f9e04b93700380b5dbf 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195444:
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r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines

[mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.

Fixes an instruction selection failure detected by llvm-stress.

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arget/Mips/MipsSEISelLowering.cpp
1184bebd31edac189a2c129ba93795b66cf4876d 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195364:
------------------------------------------------------------------------
r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines

[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.

Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.

In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.


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arget/Mips/MipsSEISelLowering.cpp
9148c5d5495a25e8479f6a58e57f7058da1b4871 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195343:
------------------------------------------------------------------------
r195343 | dsanders | 2013-11-21 03:40:14 -0800 (Thu, 21 Nov 2013) | 5 lines

[mips][msa/dsp] Only do DSP combines if DSP is enabled.

Fixes a crash (null pointer dereferenced) when MSA is enabled.


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arget/Mips/MipsSEISelLowering.cpp
fb5e6804f3aca40c78d88d6810ad22853816ae06 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195632:
------------------------------------------------------------------------
r195632 | tnorthover | 2013-11-25 01:52:59 -0800 (Mon, 25 Nov 2013) | 3 lines

X86: enable AVX2 under Haswell native compilation

Patch by Adam Strzelecki
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upport/Host.cpp
arget/X86/X86Subtarget.cpp
86a735396ab4804a06e76d1b4ce49dbd44c35827 26-Nov-2013 Richard Sandiford <rsandifo@linux.vnet.ibm.com> Merging r195731:
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r195731 | rsandifo | 2013-11-26 10:53:16 +0000 (Tue, 26 Nov 2013) | 7 lines

[SystemZ] Fix incorrect use of RISBG for a zero-extended right shift

We would wrongly transform the testcase into the equivalent of an AND with 1.
The problem was that, when testing whether the shifted-in bits of the right
shift were significant, we used the width of the final zero-extended result
rather than the width of the shifted value.

------------------------------------------------------------------------


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arget/SystemZ/SystemZISelDAGToDAG.cpp
8a0ff1f236e77214878c9d493e786b30656ad2a1 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195716:
------------------------------------------------------------------------
r195716 | kevinqin | 2013-11-25 19:26:47 -0800 (Mon, 25 Nov 2013) | 3 lines

Refactored the implementation of AArch64 NEON instruction ZIP, UZP
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().
------------------------------------------------------------------------


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arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
arget/AArch64/AArch64InstrNEON.td
9ed81d16f71b60c246a7b8e9ed4fdd58a48ce4b9 26-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195679:
------------------------------------------------------------------------
r195679 | rafael | 2013-11-25 12:15:14 -0800 (Mon, 25 Nov 2013) | 12 lines

Don't use nopl in cpus that don't support it.

Patch by Mikulas Patocka. I added the test. I checked that for cpu names that
gas knows about, it also doesn't generate nopl.

The modified cpus:
i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta
Crusoe, Microsoft VirtualBox - see
https://bbs.archlinux.org/viewtopic.php?pid=775414
k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs
via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that
Via c3 and c3-Nehemiah don't have nopl
------------------------------------------------------------------------


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arget/X86/MCTargetDesc/X86AsmBackend.cpp
1349899ba424eb4655c890bdfecb514682627a8d 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195670:
------------------------------------------------------------------------
r195670 | void | 2013-11-25 10:05:22 -0800 (Mon, 25 Nov 2013) | 5 lines

Unrevert r195599 with testcase fix.

I'm not sure how it was checking for the wrong values...
PR18023.

------------------------------------------------------------------------


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odeGen/SelectionDAG/DAGCombiner.cpp
ddc3c964657cc0be4994ddfaf056d5ec6bb11e5b 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195636:
------------------------------------------------------------------------
r195636 | aemerson | 2013-11-25 03:24:18 -0800 (Mon, 25 Nov 2013) | 2 lines

Revert r195599 as it broke the builds.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195671 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
975e958dbc12ba412385b721100fc1c830b0e3ab 25-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> Merging r195635:
------------------------------------------------------------------------
r195635 | dsanders | 2013-11-25 11:14:43 +0000 (Mon, 25 Nov 2013) | 19 lines

Fixed tryFoldToZero() for vector types that need expansion.

Summary:
Moved the requirement for SelectionDAG::getConstant() to return legally
typed nodes slightly earlier. There were two optional DAGCombine passes
that were missed out and were required to produce type-legal DAGs.

Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant().
This provides support for both promoted and expanded vector types whereas the
previous code only supported promoted vector types.

Fixes a "Type for zero vector elements is not legal" assertion detected by
an llvm-stress generated test.

Reviewers: resistor

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2251
------------------------------------------------------------------------



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195651 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
odeGen/SelectionDAG/SelectionDAGISel.cpp
c844be242228e2966851658a784a367ff5e249ca 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195591:
------------------------------------------------------------------------
r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines

Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

------------------------------------------------------------------------


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arget/AArch64/Disassembler/AArch64Disassembler.cpp
e8bb6e26b83e08631ad336bb0d8076787b858c34 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195330:
------------------------------------------------------------------------
r195330 | apazos | 2013-11-21 00:16:15 -0800 (Thu, 21 Nov 2013) | 5 lines

Implemented Neon scalar vdup_lane intrinsics.

Fixed scalar dup alias and added test case.


------------------------------------------------------------------------


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arget/AArch64/AArch64InstrNEON.td
83a5c7898e26166199ef8a55527d176b5dc4cb04 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195327:
------------------------------------------------------------------------
r195327 | apazos | 2013-11-20 23:37:04 -0800 (Wed, 20 Nov 2013) | 6 lines

Implemented Neon scalar by element intrinsics.

Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.


------------------------------------------------------------------------


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arget/AArch64/AArch64InstrNEON.td
fd76325f8afd780f3b5863a32d4a7f1bc88fec07 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195514:
------------------------------------------------------------------------
r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines

R600/SI: Fixing handling of condition codes

We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195609 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPUInstructions.td
arget/R600/R600Instructions.td
arget/R600/SIISelLowering.cpp
arget/R600/SIInstructions.td
fc1f9531d3f9bf14b4b20b80f158317795d3d1d8 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195528:
------------------------------------------------------------------------
r195528 | chandlerc | 2013-11-22 16:48:34 -0800 (Fri, 22 Nov 2013) | 7 lines

Migrate metadata information from scalar to vector instructions during
SLP vectorization. Based on the code in BBVectorizer.

Fixes PR17741.

Patch by Raul Silvera, reviewed by Hal and Nadav. Reformatted by my
driving of clang-format. =]
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ransforms/Vectorize/SLPVectorizer.cpp
e96466ecc0b2bdee0bed2156e12dc16f4adb2d50 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195493:
------------------------------------------------------------------------
r195493 | arsenm | 2013-11-22 11:24:39 -0800 (Fri, 22 Nov 2013) | 6 lines

StructurizeCFG: Fix verification failure with some loops.

If the beginning of the loop was also the entry block
of the function, branches were inserted to the entry block
which isn't allowed. If this occurs, create a new dummy
function entry block that branches to the start of the loop.
------------------------------------------------------------------------


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ransforms/Scalar/StructurizeCFG.cpp
215aad562cbff81f5b1ce5b570076b88a87998f8 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195492:
------------------------------------------------------------------------
r195492 | arsenm | 2013-11-22 11:24:37 -0800 (Fri, 22 Nov 2013) | 1 line

StructurizeCFG: Fix inverting a branch on an argument
------------------------------------------------------------------------


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ransforms/Scalar/StructurizeCFG.cpp
f02a188899769cde2315c964f0fbed1d024b7514 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195491:
------------------------------------------------------------------------
r195491 | probinson | 2013-11-22 11:11:24 -0800 (Fri, 22 Nov 2013) | 11 lines

Teach ISel not to optimize 'optnone' functions (revised).

Improvements over r195317:
- Set/restore EnableFastISel flag instead of just running FastISel within
SelectAllBasicBlocks; the flag is checked in various places, and
FastISel won't run properly if those places don't do the right thing.
- Test looks for normal ISel versus FastISel behavior, and not
something more subtle that doesn't work everywhere.

Based on work by Andrea Di Biagio.

------------------------------------------------------------------------


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odeGen/SelectionDAG/SelectionDAGISel.cpp
arget/TargetMachine.cpp
3343ddf466b414f811048dc9f3be2d55ffbb9658 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195477:
------------------------------------------------------------------------
r195477 | rafael | 2013-11-22 09:58:12 -0800 (Fri, 22 Nov 2013) | 13 lines

Add a fixed version of r195470 back.

The fix is simply to use CurI instead of I when handling aliases to
avoid accessing a invalid iterator.

original message:

Convert linkonce* to weak* instead of strong.

Also refactor the logic into a helper function. This is an important improve
on mingw where the linker complains about mixed weak and strong symbols.
Converting to weak ensures that the symbol is not dropped, but keeps in a
comdat, making the linker happy.
------------------------------------------------------------------------


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ransforms/IPO/ExtractGV.cpp
16f81f783207fa359f3afc589e2135d4805c9b98 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195476:
------------------------------------------------------------------------
r195476 | hliao | 2013-11-22 09:56:57 -0800 (Fri, 22 Nov 2013) | 6 lines

Fix PR18014

- When simplifying the mask generation for BLEND, check whether that mask is
also consumed by other non-BLEND insns. If true, skip that simplification.


------------------------------------------------------------------------


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arget/X86/X86ISelLowering.cpp
9add5c2d4b282f7cae583ece5cea3f83d33c488b 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195432:
------------------------------------------------------------------------
r195432 | haoliu | 2013-11-22 01:24:41 -0800 (Fri, 22 Nov 2013) | 3 lines

Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros.
This patch only renames variables, no functional change.

------------------------------------------------------------------------


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arget/AArch64/AArch64RegisterInfo.td
arget/AArch64/AsmParser/AArch64AsmParser.cpp
arget/AArch64/InstPrinter/AArch64InstPrinter.cpp
arget/AArch64/Utils/AArch64BaseInfo.h
e1679735d6df98bd71808f3c34a32599de0f40a1 25-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195599:
------------------------------------------------------------------------
r195599 | void | 2013-11-24 21:01:21 -0800 (Sun, 24 Nov 2013) | 4 lines

Don't look past volatile loads.

A volatile load should block us from trying to coalesce stores.
PR18023
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195600 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
0162226db8b99306d598d7b790be7cc938bb689e 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195439:
------------------------------------------------------------------------
r195439 | kcc | 2013-11-22 02:30:39 -0800 (Fri, 22 Nov 2013) | 3 lines

Revert r195318 as it causes miscompilation (PR18029)


------------------------------------------------------------------------


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arget/X86/X86ISelLowering.cpp
fff1ff91915a613c0c23a5bbf7acb4694654d694 22-Nov-2013 Richard Sandiford <rsandifo@linux.vnet.ibm.com> Merging r195473:
------------------------------------------------------------------------
r195473 | rsandifo | 2013-11-22 17:28:28 +0000 (Fri, 22 Nov 2013) | 10 lines

[SystemZ] Fix TMHH and TMHL usage for z10 with -O0

I've no idea why I decided to handle TMxx differently from all the other
high/low logic operations, but it was a stupid thing to do. The high
registers aren't available as separate 32-bit registers on z10,
so subreg_h32 can't be used on a GR64 there.

I've normally been testing with z196 and with -O3 and so hadn't noticed
this until now.

------------------------------------------------------------------------


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arget/SystemZ/SystemZAsmPrinter.cpp
arget/SystemZ/SystemZInstrFormats.td
arget/SystemZ/SystemZInstrInfo.td
arget/SystemZ/SystemZPatterns.td
151dfc7d7ff6406a471058fcd142018a10b0c479 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195423:
------------------------------------------------------------------------
r195423 | haoliu | 2013-11-22 00:34:54 -0800 (Fri, 22 Nov 2013) | 2 lines

Revert last change by haoliu because of buildbot failure.

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arget/AArch64/AArch64RegisterInfo.td
arget/AArch64/AsmParser/AArch64AsmParser.cpp
arget/AArch64/InstPrinter/AArch64InstPrinter.cpp
arget/AArch64/Utils/AArch64BaseInfo.h
81a22ba0e7e6aa455cc0ee73c8b43171bff237b6 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195421:
------------------------------------------------------------------------
r195421 | haoliu | 2013-11-22 00:17:16 -0800 (Fri, 22 Nov 2013) | 5 lines

Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros.
This solution only renames variables, no functional change.

NOTE: This is a candidate for the 3.4 branch.

------------------------------------------------------------------------


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arget/AArch64/AArch64RegisterInfo.td
arget/AArch64/AsmParser/AArch64AsmParser.cpp
arget/AArch64/InstPrinter/AArch64InstPrinter.cpp
arget/AArch64/Utils/AArch64BaseInfo.h
9e78ba4ddcf80e2e292220b4a07a9baba21cfa15 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195399:
------------------------------------------------------------------------
r195399 | tstellar | 2013-11-21 16:41:08 -0800 (Thu, 21 Nov 2013) | 10 lines

R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()

Splitting a basic block will create a new ALU clause, so we need to make
sure we aren't moving uses of registers that are local to their
current clause into a new one.

I had a test case for this, but unfortunately unrelated schedule changes
invalidated it, and I wasn't been able to come up with another one.

NOTE: This is a candidate for the 3.4 branch.
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arget/R600/R600InstrInfo.cpp
arget/R600/R600InstrInfo.h
f0061998dd1256df1ba933e80fdad2f594ea3f50 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195398:
------------------------------------------------------------------------
r195398 | tstellar | 2013-11-21 16:41:05 -0800 (Thu, 21 Nov 2013) | 7 lines

SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type

The legalizer can now do this type of expansion for more
type combinations without loading and storing to and
from the stack.

NOTE: This is a candidate for the 3.4 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195414 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/LegalizeTypes.h
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
f62b274a93d4014d56fa3a656f4fac6e7d827358 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195397:
------------------------------------------------------------------------
r195397 | tstellar | 2013-11-21 16:39:23 -0800 (Thu, 21 Nov 2013) | 11 lines

Split SETCC if VSELECT requires splitting too.

This patch is a rewrite of the original patch commited in r194542. Instead of
relying on the type legalizer to do the splitting for us, we now peform the
splitting ourselves in the DAG combiner. This is necessary for the case where
the vector mask is a legal type after promotion and still wouldn't require
splitting.

Patch by: Juergen Ributzka

NOTE: This is a candidate for the 3.4 branch.
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odeGen/SelectionDAG/DAGCombiner.cpp
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
ee287ca22abcce9f769618c107ff3f46aa2d0cba 22-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195156:
------------------------------------------------------------------------
r195156 | ributzka | 2013-11-19 13:20:17 -0800 (Tue, 19 Nov 2013) | 3 lines

[DAG] Refactor vector splitting code in SelectionDAG. No functional change intended.

Reviewed by Tom
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odeGen/SelectionDAG/LegalizeTypes.cpp
odeGen/SelectionDAG/LegalizeTypes.h
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
odeGen/SelectionDAG/LegalizeVectorTypes.cpp
odeGen/SelectionDAG/SelectionDAG.cpp
odeGen/SelectionDAG/SelectionDAGISel.cpp
54075bbea7e70fea6cdb9e5e89b066118c1d314b 21-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195339:
------------------------------------------------------------------------
r195339 | chapuni | 2013-11-21 02:55:15 -0800 (Thu, 21 Nov 2013) | 5 lines

Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."

It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown".

FYI, it didn't appear to add either "-O0" or "-fast-isel".
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odeGen/SelectionDAG/SelectionDAGISel.cpp
arget/TargetMachine.cpp
4e2d2f091e88dd83d1685173d2c0692d8ae155e6 21-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> Merging r195355:
------------------------------------------------------------------------
r195355 | dsanders | 2013-11-21 13:24:49 +0000 (Thu, 21 Nov 2013) | 20 lines

Add support for legalizing SETNE/SETEQ by inverting the condition code and the result of the comparison.

Summary:
LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse
condition and requesting that the caller invert the result of the condition.

The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do
so as follows:
SETCC, BR_CC:
Invert the result of the SETCC with SelectionDAG::getNOT()
SELECT_CC:
Swap the true/false operands.

This is necessary for MSA which lacks an integer SETNE instruction.

Reviewers: resistor

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2229
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odeGen/SelectionDAG/LegalizeDAG.cpp
0a0da619eb7a072836cf2c5debee1c5c7c8f5496 21-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195317:
------------------------------------------------------------------------
r195317 | probinson | 2013-11-20 22:33:32 -0800 (Wed, 20 Nov 2013) | 4 lines

Teach ISel not to optimize 'optnone' functions.

Based on work by Andrea Di Biagio.

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odeGen/SelectionDAG/SelectionDAGISel.cpp
arget/TargetMachine.cpp
ade90c9f1d01f3401a5db183a33b5a6380476a35 21-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195272:
------------------------------------------------------------------------
r195272 | hfinkel | 2013-11-20 12:54:55 -0800 (Wed, 20 Nov 2013) | 4 lines

PPC popcnt[dw] do not have record forms

The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.
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arget/PowerPC/PPCInstr64Bit.td
8ae03404a3a38e34474d29f20bf5cd6b7088ada8 21-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195318:
------------------------------------------------------------------------
r195318 | void | 2013-11-20 23:04:30 -0800 (Wed, 20 Nov 2013) | 29 lines

The basic problem is that some mainstream programs cannot deal with the way
clang optimizes tail calls, as in this example:

int foo(void);
int bar(void) {
return foo();
}

where the call is transformed to:

calll .L0$pb
.L0$pb:
popl %eax
.Ltmp0:
addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
movl foo@GOT(%eax), %eax
popl %ebp
jmpl *%eax # TAILCALL

However, the GOT references must all be resolved at dlopen() time, and so this
approach cannot be used with lazy dynamic linking (e.g. using RTLD_LAZY), which
usually populates the PLT with stubs that perform the actual resolving.

This patch changes X86TargetLowering::LowerCall() to skip tail call
optimization, if the called function is a global or external symbol.

Patch by Dimitry Andric!

PR15086
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arget/X86/X86ISelLowering.cpp
0ff917e85472b98aec8f9d48647cde6941a5ea27 21-Nov-2013 Petar Jovanovic <petar.jovanovic@imgtec.com> Merging r195157:
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r195157 | petarj | 2013-11-19 22:56:00 +0100 (Tue, 19 Nov 2013) | 8 lines

[mips] Resolve relocation for the stubs in MCJIT when load address is known

Instead of processing relocation for branch to stubs right away, emit a
modified relocation and add it to queue to be resolved later when final load
address is known.
This resolves seven MIPS MCJIT issues that were caused by missing relocation
fixups at the end.

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xecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
dd9c5e98c87a33eae1fe0ec9e03bc41f6f3a731d 20-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195162:
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r195162 | arnolds | 2013-11-19 14:20:20 -0800 (Tue, 19 Nov 2013) | 12 lines

SLPVectorizer: Fix stale for Value pointer array

We are slicing an array of Value pointers and process those slices in a loop.
The problem is that we might invalidate a later slice by vectorizing a former
slice.

Use a WeakVH to track the pointer. If the pointer is deleted or RAUW'ed we can
tell.

The test case will only fail when running with libgmalloc.

radar://15498655
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195222 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/SLPVectorizer.cpp
8e5b91849a39173b1ce1c15e0e279b94562204b5 20-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195161:
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r195161 | arnolds | 2013-11-19 14:20:18 -0800 (Tue, 19 Nov 2013) | 1 line

SLPVectorizer: Fix whitespace errors
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195221 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/SLPVectorizer.cpp
a87a147ee7bb9adb4caea631ff0ba7e66bb9b0b5 20-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195152:
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r195152 | jacksprat | 2013-11-19 12:53:28 -0800 (Tue, 19 Nov 2013) | 1 line

reverts 195057 per request
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195220 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/AsmParser/MipsAsmParser.cpp
arget/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
arget/Mips/MCTargetDesc/MipsTargetStreamer.cpp
arget/Mips/MipsAsmPrinter.cpp
arget/Mips/MipsTargetStreamer.h
3773bef110790fbeeb386b083bdf8ad16bbceb91 20-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195138:
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r195138 | atrick | 2013-11-19 10:29:45 -0800 (Tue, 19 Nov 2013) | 3 lines

Obvious pasto survived a couple rounds of cleanup.

Caught by Aaron Ballman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195219 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/StackMaps.cpp
2af1d85c5deef2abca4e16d695f15a6bc8dec58a 20-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195129:
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r195129 | mcinally | 2013-11-19 06:36:00 -0800 (Tue, 19 Nov 2013) | 2 lines

Fix assembly operands for the SSE2 cvtsd2ss instruction.

------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195218 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86InstrSSE.td
43f41cc550e74346f927dc45cb82c57ddcf07117 20-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195118:
------------------------------------------------------------------------
r195118 | chandlerc | 2013-11-19 01:03:18 -0800 (Tue, 19 Nov 2013) | 22 lines

Fix an issue where SROA computed different results based on the relative
order of slices of the alloca which have exactly the same size and other
properties. This was found by a perniciously unstable sort
implementation used to flush out buggy uses of the algorithm.

The fundamental idea is that findCommonType should return the best
common type it can find across all of the slices in the range. There
were two bugs here previously:

1) We would accept an integer type smaller than a byte-width multiple,
and if there were different bit-width integer types, we would accept
the first one. This caused an actual failure in the testcase updated
here when the sort order changed.
2) If we found a bad combination of types or a non-load, non-store use
before an integer typed load or store we would bail, but if we found
the integere typed load or store, we would use it. The correct
behavior is to always use an integer typed operation which covers the
partition if one exists.

While a clever debugging sort algorithm found problem #1 in our existing
test cases, I have no useful test case ideas for #2. I spotted in by
inspection when looking at this code.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195217 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Scalar/SROA.cpp
c00090b16b2b35f2d042d965945c4246d13321b5 19-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195103:
------------------------------------------------------------------------
r195103 | atrick | 2013-11-18 21:05:43 -0800 (Mon, 18 Nov 2013) | 1 line

Fix patchpoint comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195115 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/InstrEmitter.cpp
1070c0a33692cb38ba23efd11ff3116f2fc33834 19-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195094:
------------------------------------------------------------------------
r195094 | atrick | 2013-11-18 19:29:59 -0800 (Mon, 18 Nov 2013) | 3 lines

Use symbolic operands in the patchpoint folding routine and fix a spilling bug.

Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195113 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86InstrInfo.cpp
72ef53ad21cf2df7cdf6f2a0470b4eaa98d9e7ed 19-Nov-2013 Bill Wendling <isanbard@gmail.com> Merging r195093:
------------------------------------------------------------------------
r195093 | atrick | 2013-11-18 19:29:56 -0800 (Mon, 18 Nov 2013) | 4 lines

Add an abstraction to handle patchpoint operands.

Hard-coded operand indices were scattered throughout lowering stages
and layers. It was super bug prone.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195112 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/StackMaps.cpp
arget/X86/X86MCInstLower.cpp
36c7806f4eacd676932ba630246f88e0e37b1cd4 19-Nov-2013 Hao Liu <Hao.Liu@arm.com> Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelDAGToDAG.cpp
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrNEON.td
arget/AArch64/AsmParser/AArch64AsmParser.cpp
arget/AArch64/Disassembler/AArch64Disassembler.cpp
arget/AArch64/InstPrinter/AArch64InstPrinter.cpp
arget/AArch64/Utils/AArch64BaseInfo.h
e40e68add7f17f6ad5cd5e85ea44b149f6935147 19-Nov-2013 Eric Christopher <echristo@gmail.com> Remove unused special member functions and reformat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195077 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MCTargetDesc/MipsTargetStreamer.cpp
arget/Mips/MipsTargetStreamer.h
15602d786beee8308af765ade2e6debde2b81ad2 19-Nov-2013 Eric Christopher <echristo@gmail.com> Fix previous commit and fully remove variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195076 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
arget/Mips/MCTargetDesc/MipsTargetStreamer.cpp
arget/Mips/MipsTargetStreamer.h
2a4888b347ec1e7f69dcf2dcad0d7fd7baef50c5 19-Nov-2013 Eric Christopher <echristo@gmail.com> Remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195075 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsTargetStreamer.h
f11b55c5cc85193170194c9d289ab15b2ad58b6d 19-Nov-2013 Jiangning Liu <jiangning.liu@arm.com> Implement AArch64 SISD intrinsics for vget_high and vget_low.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
282a979dddff8d06a744c1b686fb3b7a7619d0f4 19-Nov-2013 Kevin Qin <Kevin.Qin@arm.com> implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
arget/AArch64/AsmParser/AArch64AsmParser.cpp
01dd5728cc897777da95a7f4672b5a2540d52564 19-Nov-2013 Jiangning Liu <jiangning.liu@arm.com> Add predicate for AArch64 crypto instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
e53969b4758274ee833ce3acef37134bcf6554ea 19-Nov-2013 Jack Carter <jack.carter@imgtec.com> [Mips] Support for MicroMips STO refactoring.

No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/AsmParser/MipsAsmParser.cpp
arget/Mips/MCTargetDesc/MipsTargetStreamer.cpp
arget/Mips/MipsAsmPrinter.cpp
arget/Mips/MipsTargetStreamer.h
354362524a72b3fa43a6c09380b7ae3b2380cbba 19-Nov-2013 Juergen Ributzka <juergen@apple.com> [weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/MachineRegisterInfo.cpp
odeGen/MachineScheduler.cpp
odeGen/RegAllocBase.cpp
odeGen/RegAllocBase.h
xecutionEngine/ExecutionEngine.cpp
xecutionEngine/RuntimeDyld/JITRegistrar.h
xecutionEngine/RuntimeDyld/ObjectImageCommon.h
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
R/AttributeImpl.h
R/Attributes.cpp
R/Metadata.cpp
R/Value.cpp
C/MCAtom.cpp
C/MCStreamer.cpp
C/WinCOFFObjectWriter.cpp
upport/CommandLine.cpp
upport/YAMLParser.cpp
upport/YAMLTraits.cpp
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64Subtarget.cpp
arget/AArch64/AArch64Subtarget.h
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
arget/ARM/ARMBaseInstrInfo.cpp
arget/Hexagon/CMakeLists.txt
arget/Hexagon/HexagonInstrInfo.cpp
arget/Hexagon/HexagonInstrInfo.h
arget/Hexagon/HexagonMachineFunctionInfo.cpp
arget/Hexagon/HexagonMachineFunctionInfo.h
arget/Hexagon/HexagonSubtarget.cpp
arget/Hexagon/HexagonSubtarget.h
arget/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
arget/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
arget/MSP430/MSP430InstrInfo.cpp
arget/MSP430/MSP430InstrInfo.h
arget/Mips/MipsInstrInfo.cpp
arget/Mips/MipsInstrInfo.h
arget/Mips/MipsTargetStreamer.h
arget/NVPTX/NVPTXISelLowering.cpp
arget/NVPTX/NVPTXInstrInfo.cpp
arget/NVPTX/NVPTXInstrInfo.h
arget/NVPTX/NVPTXSection.h
arget/NVPTX/NVPTXSubtarget.cpp
arget/NVPTX/NVPTXSubtarget.h
arget/NVPTX/NVPTXTargetObjectFile.h
arget/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
arget/PowerPC/PPCInstrInfo.cpp
arget/PowerPC/PPCInstrInfo.h
arget/PowerPC/PPCTargetStreamer.h
arget/R600/AMDGPUInstrInfo.cpp
arget/R600/AMDGPUInstrInfo.h
arget/R600/AMDGPUMachineFunction.cpp
arget/R600/AMDGPUMachineFunction.h
arget/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
arget/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h
arget/R600/MCTargetDesc/CMakeLists.txt
arget/R600/R600InstrInfo.cpp
arget/R600/R600MachineFunctionInfo.cpp
arget/R600/R600MachineFunctionInfo.h
arget/R600/SIMachineFunctionInfo.cpp
arget/R600/SIMachineFunctionInfo.h
arget/Sparc/SparcInstrInfo.cpp
arget/Sparc/SparcInstrInfo.h
arget/SystemZ/CMakeLists.txt
arget/SystemZ/SystemZInstrInfo.cpp
arget/SystemZ/SystemZInstrInfo.h
arget/SystemZ/SystemZMachineFunctionInfo.cpp
arget/SystemZ/SystemZMachineFunctionInfo.h
arget/SystemZ/SystemZSubtarget.cpp
arget/SystemZ/SystemZSubtarget.h
arget/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
arget/X86/X86InstrInfo.cpp
arget/X86/X86InstrInfo.h
arget/XCore/XCoreInstrInfo.cpp
arget/XCore/XCoreInstrInfo.h
8da7540802d67336892deeac3385442e0400333c 19-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfDebug: Move trailing else to the same line as prior closing brace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195060 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfDebug.cpp
d6dffb40cb05909dd6289e6dc37c25359ab14b52 19-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfDebug: Remove some more redundant explicit constructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195059 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfDebug.cpp
4c1625b3cb23745dba38e205b20e7b63954d8067 19-Nov-2013 Jack Carter <jack.carter@imgtec.com> [Mips] MipsTargetStreamer refactoring.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195057 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MCTargetDesc/CMakeLists.txt
arget/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
arget/Mips/MCTargetDesc/MipsTargetStreamer.cpp
arget/Mips/MipsTargetStreamer.h
4adba52570723c2e1654b1c01feddf759893f096 19-Nov-2013 David Blaikie <dblaikie@gmail.com> DebugInfo: Simplify a few more explicit constructions, underconstrained types, and make DIType(MDNode*) explicit like all the other DI* node ctors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195055 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
R/DIBuilder.cpp
a7b7a7d629c3101f6f6c87e6848e865734e0238c 19-Nov-2013 Reid Kleckner <reid@kleckner.net> Revert "COFF: Emit all MCSymbols rather than filtering out some of them"

This reverts commit r190888, to fix PR17967. The original change wasn't
the right way to get @feat.00 into the object file. The right fix is to
make @feat.00 be a global symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
C/WinCOFFObjectWriter.cpp
arget/X86/X86AsmPrinter.cpp
940267e7f208751fdc48dbb7d6b5d86b6310ce7c 19-Nov-2013 Adrian Prantl <aprantl@apple.com> Debug info: Let LowerDbgDeclare perfom the dbg.declare -> dbg.value
lowering only for load/stores to scalar allocas. The resulting values
confuse the backend and don't add anything because we can describe
array-allocas with a dbg.declare intrinsic just fine.

rdar://problem/15464571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195052 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Utils/Local.cpp
fe45fd084db872f9c7106c26e52c1cc8c9cba3a5 18-Nov-2013 Paul Robinson <paul_robinson@playstation.sony.com> The 'optnone' attribute means don't inline anything into this function
(except functions marked always_inline).
Functions with 'optnone' must also have 'noinline' so they don't get
inlined into any other function.

Based on work by Andrea Di Biagio.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195046 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/IPA/InlineCost.cpp
R/Verifier.cpp
3560dd2dcd67d42eeb8e59975581d598d71669df 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Fix moveToVALU when the first operand is VSrc.

Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
arget/R600/SIRegisterInfo.cpp
9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Fix multiple SGPR reads when using VCC.

No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
e64a2896094be370f5ca3d755f62c762fb94b37a 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Implement add i64, but do not yet enable.

Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIISelLowering.cpp
arget/R600/SIISelLowering.h
15703e0a71e7583b107499045374c364976452e2 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Specify SSrc operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195039 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstructions.td
f38be91a829ad5a0391b6f139f0bd8cef341e689 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: addc / adde i32 are legal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195038 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIISelLowering.cpp
b2254e603d12be6673d58f098cd384203f964e55 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Match addc to S_ADD_U32.

The carry always goes to SCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195037 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstructions.td
62f35fb9267d4c58d5359c43358ab42c25708df4 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195036 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstructions.td
f53b7841a1f173cb06a42e59e549b2759063bb97 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Specify S_ADD/S_SUB set SCC and add is commutable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195035 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstructions.td
3e38856f04a01651819c6bc16fac4434a5d2b4c6 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Move patterns to match add / sub to scalar instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
arget/R600/SIInstructions.td
836c5133c66edecedeaa79448964b4c103f99271 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Fix extra defs of VCC / SCC.

When replacing scalar operations with vector,
the wrong implicit output register was used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
b570599c8f048c2eda78edb9304bd8e283fb6908 18-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Enable the IR structurizer by default

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPU.td
arget/R600/AMDGPUSubtarget.cpp
arget/R600/AMDGPUTargetMachine.cpp
44248e0f631beec23db16fa62ddfd799492ea3ff 18-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix a crash in the AMDILCFGStrucurizer

The ifPatternMatch() function was not correctly reporting the number
of matches in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDILCFGStructurizer.cpp
ef37e453c407675ab5934d2f6bcec706b7810878 18-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add a SubtargetFeatture for disabling the ifcvt pass.

This is useful when writing test cases for the AMDIL structurizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPU.td
arget/R600/AMDGPUSubtarget.cpp
arget/R600/AMDGPUSubtarget.h
arget/R600/AMDGPUTargetMachine.cpp
b4c3516b0f7d879e332adf6f4dba3f4763c74086 18-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Use lower-case for EnableIRStructurizer feature

llc converts all values passed to -mattr= to lowercase, so this
enables us to toggle this feature when using llc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195028 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPU.td
204c953cd59415d7ed50b81c64906bf5a0c97455 18-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Fix illegal VGPR->SGPR copy inside of loop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
bf9ddd5e8ff207e9b9a1cd484242e8d460f3834e 18-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Fix another case of illegal VGPR->SGPR copy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
7c5498ee55e241dea91cca022bd9a5831a1ba4b1 18-Nov-2013 Aaron Ballman <aaron@aaronballman.com> Checking for a return value with FormatMessage; if the call fails, there's no guarantee that the buffer will be non-null.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195019 91177308-0d34-0410-b5e6-96231b3b80d8
upport/Windows/Windows.h
eae6e546ec5339179b4c7401416fbf2d641a9e90 18-Nov-2013 Aaron Ballman <aaron@aaronballman.com> Fixing a possible memory leak from a failing realloc() call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195018 91177308-0d34-0410-b5e6-96231b3b80d8
upport/SmallPtrSet.cpp
6919bec07f9c4ee57a0e99f263b63546b386f22b 18-Nov-2013 Alexander Kornienko <alexfh@google.com> Recover gracefully when deserializing invalid YAML input.
Fixes http://llvm.org/PR16221, http://llvm.org/PR15927
Phabricator: http://llvm-reviews.chandlerc.com/D1236

Patch by Andrew Tulloch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195016 91177308-0d34-0410-b5e6-96231b3b80d8
upport/YAMLTraits.cpp
64409ad8e3b360b84349042f14b57f87a5c0ca18 18-Nov-2013 Alexey Samsonov <samsonov@google.com> [ASan] Fix PR17867 - make sure ASan doesn't crash if use-after-scope and use-after-return are combined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195014 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Instrumentation/AddressSanitizer.cpp
07a3c481c656c9cc1e0ace3d599eef1fa81e3cc6 18-Nov-2013 Arnold Schwaighofer <aschwaighofer@apple.com> LoopVectorizer: Extend the induction variable to a larger type

In some case the loop exit count computation can overflow. Extend the type to
prevent most of those cases.

The problem is loops like:
int main ()
{
int a = 1;
char b = 0;
lbl:
a &= 4;
b--;
if (b) goto lbl;
return a;
}

The backedge count is 255. The induction variable type is i8. If we add one to
255 to get the exit count we overflow to zero.

To work around this issue we extend the type of the induction variable to i32 in
the case of i8 and i16.

PR17532

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195008 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/LoopVectorize.cpp
23427207ea575f57b571cf5aad1effb1f97e7ee1 18-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)

Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsSEISelDAGToDAG.cpp
arget/Mips/MipsSEInstrInfo.cpp
26651c7a6602626cf13ff3cda13f3ec2401bf790 18-Nov-2013 Matheus Almeida <matheus.almeida@imgtec.com> [mips][msa] Update encoding of bnz.v (typo).

Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsMSAInstrInfo.td
95adf91f29980e374bf094e15bc3f2764ef9baf4 18-Nov-2013 Matheus Almeida <matheus.almeida@imgtec.com> [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.

The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/AsmParser/MipsAsmParser.cpp
arget/Mips/Disassembler/MipsDisassembler.cpp
arget/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
arget/Mips/MipsCodeEmitter.cpp
arget/Mips/MipsMSAInstrInfo.td
b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 18-Nov-2013 Alexey Samsonov <samsonov@google.com> Revert r194865 and r194874.

This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/MachineRegisterInfo.cpp
odeGen/MachineScheduler.cpp
odeGen/RegAllocBase.cpp
odeGen/RegAllocBase.h
xecutionEngine/ExecutionEngine.cpp
xecutionEngine/RuntimeDyld/JITRegistrar.h
xecutionEngine/RuntimeDyld/ObjectImageCommon.h
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
R/AttributeImpl.h
R/Attributes.cpp
R/Metadata.cpp
R/Value.cpp
C/MCAtom.cpp
C/MCStreamer.cpp
C/WinCOFFObjectWriter.cpp
upport/CommandLine.cpp
upport/ErrorHandling.cpp
upport/YAMLParser.cpp
upport/YAMLTraits.cpp
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64Subtarget.cpp
arget/AArch64/AArch64Subtarget.h
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
arget/ARM/ARMBaseInstrInfo.cpp
arget/Hexagon/CMakeLists.txt
arget/Hexagon/HexagonInstrInfo.cpp
arget/Hexagon/HexagonInstrInfo.h
arget/Hexagon/HexagonMachineFunctionInfo.cpp
arget/Hexagon/HexagonMachineFunctionInfo.h
arget/Hexagon/HexagonSubtarget.cpp
arget/Hexagon/HexagonSubtarget.h
arget/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
arget/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
arget/MSP430/MSP430InstrInfo.cpp
arget/MSP430/MSP430InstrInfo.h
arget/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
arget/Mips/MipsInstrInfo.cpp
arget/Mips/MipsInstrInfo.h
arget/Mips/MipsTargetStreamer.h
arget/NVPTX/NVPTXISelLowering.cpp
arget/NVPTX/NVPTXInstrInfo.cpp
arget/NVPTX/NVPTXInstrInfo.h
arget/NVPTX/NVPTXSection.h
arget/NVPTX/NVPTXSubtarget.cpp
arget/NVPTX/NVPTXSubtarget.h
arget/NVPTX/NVPTXTargetObjectFile.h
arget/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
arget/PowerPC/PPCInstrInfo.cpp
arget/PowerPC/PPCInstrInfo.h
arget/PowerPC/PPCTargetStreamer.h
arget/R600/AMDGPUInstrInfo.cpp
arget/R600/AMDGPUInstrInfo.h
arget/R600/AMDGPUMachineFunction.cpp
arget/R600/AMDGPUMachineFunction.h
arget/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
arget/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h
arget/R600/MCTargetDesc/CMakeLists.txt
arget/R600/R600InstrInfo.cpp
arget/R600/R600MachineFunctionInfo.cpp
arget/R600/R600MachineFunctionInfo.h
arget/R600/SIMachineFunctionInfo.cpp
arget/R600/SIMachineFunctionInfo.h
arget/Sparc/SparcInstrInfo.cpp
arget/Sparc/SparcInstrInfo.h
arget/SystemZ/CMakeLists.txt
arget/SystemZ/SystemZInstrInfo.cpp
arget/SystemZ/SystemZInstrInfo.h
arget/SystemZ/SystemZMachineFunctionInfo.cpp
arget/SystemZ/SystemZMachineFunctionInfo.h
arget/SystemZ/SystemZSubtarget.cpp
arget/SystemZ/SystemZSubtarget.h
arget/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
arget/X86/X86InstrInfo.cpp
arget/X86/X86InstrInfo.h
arget/XCore/XCoreInstrInfo.cpp
arget/XCore/XCoreInstrInfo.h
69b2447b6a3fcc303e03cba8c7c50d745b0284d2 18-Nov-2013 Kevin Qin <Kevin.Qin@arm.com> [AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
97577757c6dc84233ad10cd432664257e593e76d 18-Nov-2013 Hao Liu <Hao.Liu@arm.com> Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelDAGToDAG.cpp
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
arget/AArch64/AArch64InstrNEON.td
65c102e7fb68f78117be665dd9d4a73ef7e9f795 18-Nov-2013 Manman Ren <manman.ren@gmail.com> Debug Info Verifier: disable it by default.

Debug info verifier is part of the verifier which is a Function Pass.
Tot currently tries to pull all reachable debug info MDNodes in each function,
which is too time-consuming. The correct fix seems to be separating debug info
verification to its own module pass.

I will disable the debug info verifier until a correct fix is found.

For Bill's testing case, enabling debug info verifier increase compile
time from 11s to 11m.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194986 91177308-0d34-0410-b5e6-96231b3b80d8
R/Verifier.cpp
1572ba716bad4944a83040adef76c186c4841e95 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Fix spacing, forward declare order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194985 91177308-0d34-0410-b5e6-96231b3b80d8
itcode/Reader/BitcodeReader.cpp
itcode/Writer/BitcodeWriter.cpp
17a88a7e8b8ad2f0766c4099d09cd29229296352 17-Nov-2013 David Blaikie <dblaikie@gmail.com> Remove unnecessary temporary construction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194981 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
fbf70b383d170e00d5104b22f1bda604214d6c30 17-Nov-2013 David Blaikie <dblaikie@gmail.com> Remove redundant explicit default initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194980 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
08e51e1d97e4dd2e5a0b4539da186869916ae5c3 17-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Add type safety to createGlobalVariableDIE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194979 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfCompileUnit.h
odeGen/AsmPrinter/DwarfDebug.cpp
6950be28511caf355abdf405404b5f37cc136bc5 17-Nov-2013 Manman Ren <manman.ren@gmail.com> Debug Info: fix typo in function name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194975 91177308-0d34-0410-b5e6-96231b3b80d8
R/DebugInfo.cpp
9564d643d7b5ec2ea4068d7dadae88f285ae928e 17-Nov-2013 Manman Ren <manman.ren@gmail.com> Debug Info Verifier: fix when to find debug info nodes and when to verify them.

We used to collect debug info MDNodes in doInitialization and verify them in
doFinalization. That is incorrect since MDNodes can be modified by passes run
between doInitialization and doFinalization.

To fix the problem, we handle debug info MDNodes that can be reached from a
function in runOnFunction (i.e we collect those nodes by calling processDeclare,
processValue and processLocation, and then verify them in runOnFunction).

We handle debug info MDNodes that can be reached from named metadata in
doFinalization. This is in line with how Verifier handles module-level data
(they are verified in doFinalization).

rdar://15472296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194974 91177308-0d34-0410-b5e6-96231b3b80d8
R/Verifier.cpp
2b31b8227fb5507c26a8c4724574fc87fb90f482 17-Nov-2013 Manman Ren <manman.ren@gmail.com> Debug Info Verifier: enable public functions of Finder to update the type map.

We used to depend on running processModule before the other public functions
such as processDeclare, processValue and processLocation. We are now relaxing
the constraint by adding a module argument to the three functions and
letting the three functions to initialize the type map. This will be used in
a follow-on patch that collects nodes reachable from a Function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194973 91177308-0d34-0410-b5e6-96231b3b80d8
R/DebugInfo.cpp
R/Verifier.cpp
80ccd9ea59b8911f12836da98aceedce4ebc6a6f 17-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> Utils/LoopUnroll.cpp: Tweak (StringRef)OldName to be valid until it is used, since r194601.

eraseFromParent() invalidates OldName.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194970 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Utils/LoopUnroll.cpp
c8dc96be28fd1a3d6ddebbb48b8d55b61e4bd89b 17-Nov-2013 Hal Finkel <hfinkel@anl.gov> Add a loop rerolling flag to the PassManagerBuilder

This adds a boolean member variable to the PassManagerBuilder to control loop
rerolling (just like we have for unrolling and the various vectorization
options). This is necessary for control by the frontend. Loop rerolling remains
disabled by default at all optimization levels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194966 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/IPO/PassManagerBuilder.cpp
fe128c6ac8a6ae6aa85f0168f99d9c28de010fd8 17-Nov-2013 Bill Wendling <isanbard@gmail.com> Revert "Micro-optimization"

This reverts commit f1d9fe9d04ce93f6d5dcebbd2cb6a07414d7a029.

This was causing PR17964. We need to use thread data before regular data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194960 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/TargetLoweringObjectFileImpl.cpp
d5ae5b018644345ba0fc48a47030ef1105e1abfd 17-Nov-2013 Benjamin Kramer <benny.kra@googlemail.com> DAGCombiner: Partially revert r192795, getNOT was fixed not to create illegal constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194959 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
e7a1e3ee8279f12d0f2b49fb198d577949795c88 17-Nov-2013 Michael Gottesman <mgottesman@apple.com> [block-freq] Add BlockFrequency::scale that returns a remainder from the division and make the private scale in BlockFrequency more performant.

This change is the first in a series of changes improving LLVM's Block
Frequency propogation implementation to not lose probability mass in
branchy code when propogating block frequency information from a basic
block to its successors. This patch is a simple infrastructure
improvement that does not actually modify the block frequency
algorithm. The specific changes are:

1. Changes the division algorithm used when scaling block frequencies by
branch probabilities to a short division algorithm. This gives us the
remainder for free as well as provides a nice speed boost. When I
benched the old routine and the new routine on a Sandy Bridge iMac with
disabled turbo mode performing 8192 iterations on an array of length
32768, I saw ~600% increase in speed in mean/median performance.

2. Exposes a scale method that returns a remainder. This is important so
we can ensure that when we scale a block frequency by some branch
probability BP = N/D, the remainder from the division by D can be
retrieved and propagated to other children to ensure no probability mass
is lost (more to come on this).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194950 91177308-0d34-0410-b5e6-96231b3b80d8
upport/BlockFrequency.cpp
ca1b7799aaeeeb0c6af80fa31fb8f74e79ab2967 17-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Use more getZExtOrTruncs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194945 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/LegalizeDAG.cpp
odeGen/SelectionDAG/LegalizeTypes.cpp
91053d585abf6b20b770532d007a8b7648d0621f 17-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Use getZExtOrTrunc instead of repeating the same logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194944 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/LegalizeDAG.cpp
390564206f67b742ad7cbee1cf17ae52efa77cb6 17-Nov-2013 Hal Finkel <hfinkel@anl.gov> Add the cold attribute to error-reporting call sites

Generally speaking, control flow paths with error reporting calls are cold.
So far, error reporting calls are calls to perror and calls to fprintf,
fwrite, etc. with stderr as the stream. This can be extended in the future.

The primary motivation is to improve block placement (the cold attribute
affects the static branch prediction heuristics).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194943 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Utils/SimplifyLibCalls.cpp
bb756ca24401e190e3b704e5d92759c7a79cc6b7 17-Nov-2013 Andrew Trick <atrick@apple.com> Added a size field to the stack map record to handle subregister spills.

Implementing this on bigendian platforms could get strange. I added a
target hook, getStackSlotRange, per Jakob's recommendation to make
this as explicit as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/InlineSpiller.cpp
odeGen/StackMaps.cpp
odeGen/TargetInstrInfo.cpp
arget/X86/X86AsmPrinter.h
arget/X86/X86InstrInfo.cpp
arget/X86/X86MCInstLower.cpp
b7dabccbce5fc6fcf7b36669eb04abcb001e7f9e 17-Nov-2013 Hal Finkel <hfinkel@anl.gov> Fix ndebug-build unused variable in loop rerolling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194941 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Scalar/LoopRerollPass.cpp
94437c9691d538cc5d3862660c79fce2a32e2279 17-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Use right address space pointer size

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194940 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/SelectionDAG.cpp
bebe48dbfe00078329341945bfb11f778ace6d12 17-Nov-2013 Hal Finkel <hfinkel@anl.gov> Add a loop rerolling pass

This adds a loop rerolling pass: the opposite of (partial) loop unrolling. The
transformation aims to take loops like this:

for (int i = 0; i < 3200; i += 5) {
a[i] += alpha * b[i];
a[i + 1] += alpha * b[i + 1];
a[i + 2] += alpha * b[i + 2];
a[i + 3] += alpha * b[i + 3];
a[i + 4] += alpha * b[i + 4];
}

and turn them into this:

for (int i = 0; i < 3200; ++i) {
a[i] += alpha * b[i];
}

and loops like this:

for (int i = 0; i < 500; ++i) {
x[3*i] = foo(0);
x[3*i+1] = foo(0);
x[3*i+2] = foo(0);
}

and turn them into this:

for (int i = 0; i < 1500; ++i) {
x[i] = foo(0);
}

There are two motivations for this transformation:

1. Code-size reduction (especially relevant, obviously, when compiling for
code size).

2. Providing greater choice to the loop vectorizer (and generic unroller) to
choose the unrolling factor (and a better ability to vectorize). The loop
vectorizer can take vector lengths and register pressure into account when
choosing an unrolling factor, for example, and a pre-unrolled loop limits that
choice. This is especially problematic if the manual unrolling was optimized
for a machine different from the current target.

The current implementation is limited to single basic-block loops only. The
rerolling recognition should work regardless of how the loop iterations are
intermixed within the loop body (subject to dependency and side-effect
constraints), but the significant restriction is that the order of the
instructions in each iteration must be identical. This seems sufficient to
capture all current use cases.

This pass is not currently enabled by default at any optimization level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194939 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/IPO/PassManagerBuilder.cpp
ransforms/Scalar/CMakeLists.txt
ransforms/Scalar/LoopRerollPass.cpp
ransforms/Scalar/Scalar.cpp
0ccb37a7339883e1fd090beadc2deb1ce40ea7d4 16-Nov-2013 Juergen Ributzka <juergen@apple.com> The WebKit_JS CC preserves the same registers as the C CC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194936 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86RegisterInfo.cpp
64fa501b1081b5d5c25e5e9639075abb0cb724d9 16-Nov-2013 Hal Finkel <hfinkel@anl.gov> Apply the InstCombine fptrunc sqrt optimization to llvm.sqrt

InstCombine, in visitFPTrunc, applies the following optimization to sqrt calls:

(fptrunc (sqrt (fpext x))) -> (sqrtf x)

but does not apply the same optimization to llvm.sqrt. This is a problem
because, to enable vectorization, Clang generates llvm.sqrt instead of sqrt in
fast-math mode, and because this optimization is being applied to sqrt and not
applied to llvm.sqrt, sometimes the fast-math code is slower.

This change makes InstCombine apply this optimization to llvm.sqrt as well.

This fixes the specific problem in PR17758, although the same underlying issue
(optimizations applied to libcalls are not applied to intrinsics) exists for
other optimizations in SimplifyLibCalls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194935 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineCasts.cpp
e6e811277f045ee3d61cd62622d71005c47eb48d 16-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Fix assert on unaligned access to global with different address space size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194934 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/SelectionDAG.cpp
4fe5b640ee935f983db9445dc9fdb4009d4fa639 16-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Fix codegen for null different sized pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194932 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
b69143c6a9bfc969e7c95bbd48b83bb962086070 16-Nov-2013 Benjamin Kramer <benny.kra@googlemail.com> Annotate APInt methods where it's not clear whether they are in place with warn_unused_result.

Fix ScalarEvolution bugs uncovered by this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194928 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/ScalarEvolution.cpp
411079785388290738049dd099bff8755e6a2c8d 16-Nov-2013 Vincent Lejeune <vljn@ovi.com> R600: Make dot_4 instructions predicable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194927 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/R600InstrInfo.cpp
0fb32eb56aabb24950bbfecc927596a3fffabcb1 16-Nov-2013 Duncan P. N. Exon Smith <dexonsmith@apple.com> Use array_pod_sort instead of std::sort

Per Rafael's review of r194514.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194926 91177308-0d34-0410-b5e6-96231b3b80d8
TO/LTOCodeGenerator.cpp
e9cdbf68e542bbb79597d6233dd2a339c89862a2 16-Nov-2013 Benjamin Kramer <benny.kra@googlemail.com> InstCombine: fold (A >> C) == (B >> C) --> (A^B) < (1 << C) for constant Cs.

This is common in bitfield code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194925 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineCompares.cpp
3d429d80e4c062d0371fb105a87cc5260652c9b2 16-Nov-2013 Manman Ren <manman.ren@gmail.com> Debug Info Verifier: remove un-used argument in verifyDebugInfo.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194917 91177308-0d34-0410-b5e6-96231b3b80d8
R/Verifier.cpp
35de9946d5fc01d2fed970bdcc7966bad92bdbc4 16-Nov-2013 Jim Grosbach <grosbach@apple.com> X86: Encode the 'h' cpu subtype in the MachO header for x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194906 91177308-0d34-0410-b5e6-96231b3b80d8
upport/Triple.cpp
arget/X86/MCTargetDesc/X86AsmBackend.cpp
74c996cbd12aa39e75990e3e694549bb1be90e4d 16-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Use correct size for address space in BasicAA.

The tests just hit this with a different sized
address space since I haven't figured out how
to use this to break it.

I thought I committed this a long time ago,
and I'm not sure why missing this hasn't caused
any problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194903 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/BasicAliasAnalysis.cpp
1dc27239969889661115f40b293c83ab9ff3efd5 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Push type safety of DIDescriptor through CompileUnit::createAndAddDIE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194902 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfCompileUnit.h
21c9708c0909a4373d04f0910ab0cb05b94f25ef 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Remove unnecessary OwningPtr<T>::get() call

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194901 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
87fd14d9b52079828c5db4e1e4878046a7488f81 16-Nov-2013 Eric Christopher <echristo@gmail.com> For dwarf4 use the correct form for referencing debug_loc locations,
and update test cases accordingly.

This doesn't affect the output dumped using llvm-dwarfdump, but
readelf does now dump the debug_loc section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194898 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfDebug.cpp
7b8677109452dc3f106f931edab2d1ccaf1d06b1 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Add type safety to CompileUnit::getNode by returning DICompileUnit instead of a raw MDNode*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194895 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.h
odeGen/AsmPrinter/DwarfDebug.cpp
942431fa710f186f11538eebdf3dc4a6b824a6ba 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Add type safety by using DICompileUnit rather than raw MDNode* for the CU metadata node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194893 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfCompileUnit.h
odeGen/AsmPrinter/DwarfDebug.cpp
odeGen/AsmPrinter/DwarfDebug.h
aedaa723c26c33d4f9497a79d9d74a3c197fa262 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Simplify getLanguage() calls to use existing member function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194892 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
a53bf06f7a998f9ea9e13ba844efc2460a2185dd 16-Nov-2013 Ana Pazos <apazos@codeaurora.org> Implemented aarch64 Neon scalar vmulx_lane intrinsics
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
6bc810a49983e12006ba7a0dba61f7b2534b8f26 16-Nov-2013 Adrian Prantl <aprantl@apple.com> Replace the dangling context hotfix with an assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194883 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
445fd04f530e9f8467f8f8f8b8e5b8c8bdaa353c 16-Nov-2013 Lang Hames <lhames@gmail.com> Remove unused arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194882 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86MCInstLower.cpp
8c66df2c7a0e6309eb26d83741f3e121fd3b8550 16-Nov-2013 Lang Hames <lhames@gmail.com> During folding for patchpoint/stackmap instructions, defer creation of new MIs
until we know that folding will be successful.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194880 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86InstrInfo.cpp
14f41e7e1811b0c504c82865bd6828acfee82527 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfDebug: Push DISubprogram through updateSubprogramScopeDIE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194879 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfDebug.cpp
odeGen/AsmPrinter/DwarfDebug.h
4634338655449a6e76b6a948c91fbe5bc736d24b 16-Nov-2013 Arnold Schwaighofer <aschwaighofer@apple.com> LoopVectorizer: Use abi alignment for accesses with no alignment

When we vectorize a scalar access with no alignment specified, we have to set
the target's abi alignment of the scalar access on the vectorized access.
Using the same alignment of zero would be wrong because most targets will have a
bigger abi alignment for vector types.

This probably fixes PR17878.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194876 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Vectorize/LoopVectorize.cpp
cbc85a270d2546c49fc09f700687de2ecd46bd87 16-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Push DIDescriptors through a getDIE/insertDIE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194875 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfCompileUnit.h
odeGen/AsmPrinter/DwarfDebug.cpp
86a33487376848a606fdc629ffce2a581ae45653 15-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit: Push DIDescriptor usage out from isShareableAcrossCUs

This is the first of a few similar patches. We'll see how far it
goes/makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194871 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 15-Nov-2013 Juergen Ributzka <juergen@apple.com> [weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/MachineRegisterInfo.cpp
odeGen/MachineScheduler.cpp
odeGen/RegAllocBase.cpp
odeGen/RegAllocBase.h
xecutionEngine/ExecutionEngine.cpp
xecutionEngine/RuntimeDyld/JITRegistrar.h
xecutionEngine/RuntimeDyld/ObjectImageCommon.h
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
R/AttributeImpl.h
R/Attributes.cpp
R/Metadata.cpp
R/Value.cpp
C/MCAtom.cpp
C/MCStreamer.cpp
C/WinCOFFObjectWriter.cpp
upport/CommandLine.cpp
upport/ErrorHandling.cpp
upport/YAMLParser.cpp
upport/YAMLTraits.cpp
arget/AArch64/AArch64InstrInfo.cpp
arget/AArch64/AArch64Subtarget.cpp
arget/AArch64/AArch64Subtarget.h
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
arget/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
arget/ARM/ARMBaseInstrInfo.cpp
arget/Hexagon/CMakeLists.txt
arget/Hexagon/HexagonInstrInfo.cpp
arget/Hexagon/HexagonInstrInfo.h
arget/Hexagon/HexagonMachineFunctionInfo.cpp
arget/Hexagon/HexagonMachineFunctionInfo.h
arget/Hexagon/HexagonSubtarget.cpp
arget/Hexagon/HexagonSubtarget.h
arget/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
arget/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
arget/MSP430/MSP430InstrInfo.cpp
arget/MSP430/MSP430InstrInfo.h
arget/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
arget/Mips/MipsInstrInfo.cpp
arget/Mips/MipsInstrInfo.h
arget/Mips/MipsTargetStreamer.h
arget/NVPTX/NVPTXISelLowering.cpp
arget/NVPTX/NVPTXInstrInfo.cpp
arget/NVPTX/NVPTXInstrInfo.h
arget/NVPTX/NVPTXSection.h
arget/NVPTX/NVPTXSubtarget.cpp
arget/NVPTX/NVPTXSubtarget.h
arget/NVPTX/NVPTXTargetObjectFile.h
arget/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
arget/PowerPC/PPCInstrInfo.cpp
arget/PowerPC/PPCInstrInfo.h
arget/PowerPC/PPCTargetStreamer.h
arget/R600/AMDGPUInstrInfo.cpp
arget/R600/AMDGPUInstrInfo.h
arget/R600/AMDGPUMachineFunction.cpp
arget/R600/AMDGPUMachineFunction.h
arget/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
arget/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h
arget/R600/MCTargetDesc/CMakeLists.txt
arget/R600/R600InstrInfo.cpp
arget/R600/R600MachineFunctionInfo.cpp
arget/R600/R600MachineFunctionInfo.h
arget/R600/SIMachineFunctionInfo.cpp
arget/R600/SIMachineFunctionInfo.h
arget/Sparc/SparcInstrInfo.cpp
arget/Sparc/SparcInstrInfo.h
arget/SystemZ/CMakeLists.txt
arget/SystemZ/SystemZInstrInfo.cpp
arget/SystemZ/SystemZInstrInfo.h
arget/SystemZ/SystemZMachineFunctionInfo.cpp
arget/SystemZ/SystemZMachineFunctionInfo.h
arget/SystemZ/SystemZSubtarget.cpp
arget/SystemZ/SystemZSubtarget.h
arget/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
arget/X86/X86InstrInfo.cpp
arget/X86/X86InstrInfo.h
arget/XCore/XCoreInstrInfo.cpp
arget/XCore/XCoreInstrInfo.h
17d4ac8c461fb3c32483cf7a37bc52937caeb650 15-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Fix confusing machine verifier error.

The error reported the number of explicit operands,
but that isn't what is checked. In my case, this
resulted in the confusing errors

"Too few operands." followed shortly by
"8 operands expected, but 8 given."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194862 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/MachineVerifier.cpp
59bbf5a759a4891ea90ac67f13485f67ef42234c 15-Nov-2013 Andrew Kaylor <andrew.kaylor@intel.com> Fix a problem in MCJIT identifying the module containing a global variable.

Patch by Keno Fischer!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194859 91177308-0d34-0410-b5e6-96231b3b80d8
xecutionEngine/MCJIT/MCJIT.cpp
c3ec7e2273a26d8ae3b8d98160e13f8f44299ad2 15-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Make method static

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194858 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
arget/R600/SIInstrInfo.h
4303b091d0b0c4982efde6f575f4dfd72ff14c42 15-Nov-2013 Chandler Carruth <chandlerc@gmail.com> [PM] Fix an iterator problem spotted by the MSVC debug iterators and
AaronBallman. Thanks for the excellent review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194857 91177308-0d34-0410-b5e6-96231b3b80d8
R/PassManager.cpp
d515e98ebf711d7e80589e4029f27c206573b400 15-Nov-2013 Chandler Carruth <chandlerc@gmail.com> [PM] Run clang-format on a few lines that I missed in my first pass,
pulling them under 80-columns. No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194856 91177308-0d34-0410-b5e6-96231b3b80d8
R/PassManager.cpp
5758c3c832daf4c0b37042684f822fa1896966ac 15-Nov-2013 Chad Rosier <mcrosier@codeaurora.org> [AArch64] Fix the scalar NEON ACLE functions so that they return float/double
rather than the vector equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
8a631b2cbe2f8621eb3679a4898205da577453b7 15-Nov-2013 Rui Ueyama <ruiu@google.com> Path: Recognize COFF import library file magic.

Summary: Make identify_magic to recognize COFF import file.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194852 91177308-0d34-0410-b5e6-96231b3b80d8
xecutionEngine/RuntimeDyld/RuntimeDyld.cpp
bject/Binary.cpp
bject/ObjectFile.cpp
upport/Path.cpp
0cbdb81de76274c3f1731d92dc09864d2277d690 15-Nov-2013 Adrian Prantl <aprantl@apple.com> Reimplement r194843 in a slightly less broken way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194848 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
c160efc28b815dbea73f0243f0729c1f0e1fabdb 15-Nov-2013 Manman Ren <manman.ren@gmail.com> ArgumentPromotion: correctly transfer TBAA tags and alignments.

We used to use std::map<IndicesVector, LoadInst*> for OriginalLoads, and when we
try to promote two arguments, they will both write to OriginalLoads causing
created loads for the two arguments to have the same original load. And the same
tbaa tag and alignment will be put to the created loads for the two arguments.

The fix is to use std::map<std::pair<Argument*, IndicesVector>, LoadInst*>
for OriginalLoads, so each Argument will write to different parts of the map.

PR17906


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194846 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/IPO/ArgumentPromotion.cpp
3a226015a0ca52936763a079da582656164c2908 15-Nov-2013 Rui Ueyama <ruiu@google.com> Readobj: If NumbersOfSections is 0xffff, it's an COFF import library.

0xffff does not mean that there are 65535 sections in a COFF file but
indicates that it's a COFF import library. This patch fixes SEGV error
when an import library file is passed to llvm-readobj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194844 91177308-0d34-0410-b5e6-96231b3b80d8
bject/COFFObjectFile.cpp
7d5f2bd5f9615c0f20d3a1f75ec01452d813283b 15-Nov-2013 Adrian Prantl <aprantl@apple.com> Restore the behaviour from before r194728.
If getDIE() fails, getOrCreateContextDIE() should also return the CUDie.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194843 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
cc7052343e5e955d4e2f48885c06360f9003390a 15-Nov-2013 Bob Wilson <bob.wilson@apple.com> Avoid illegal integer promotion in fastisel

Stop folding constant adds into GEP when the type size doesn't match.
Otherwise, the adds' operands are effectively being promoted, changing the
conditions of an overflow. Results are different when:

sext(a) + sext(b) != sext(a + b)

Problem originally found on x86-64, but also fixed issues with ARM and PPC,
which used similar code.

<rdar://problem/15292280>

Patch by Duncan Exon Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194840 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/FastISel.cpp
arget/ARM/ARMFastISel.cpp
arget/PowerPC/PPCFastISel.cpp
arget/X86/X86FastISel.cpp
5cddda6d13ab66c462ccbd61255ad6e6f95e9f6f 15-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()

This fixes a crash with GNOME settings manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIRegisterInfo.cpp
1ab6084c9e785415da3a48083d53b25a38f0fb48 15-Nov-2013 Andrew Kaylor <andrew.kaylor@intel.com> Resolve JIT runtime linking problems on Android.

Patch by James Lyon!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194832 91177308-0d34-0410-b5e6-96231b3b80d8
xecutionEngine/JIT/JITMemoryManager.cpp
xecutionEngine/RTDyldMemoryManager.cpp
48079e0fef9301442eb787d2234ea99ba3f06fa8 15-Nov-2013 Andrew Kaylor <andrew.kaylor@intel.com> Don't try to initialize memory for a global if the allocation failed in ExecutionEngine.

Patch by Dale Martin!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194831 91177308-0d34-0410-b5e6-96231b3b80d8
xecutionEngine/ExecutionEngine.cpp
28e12e9f02cf1c5029994b4a6d7e2988512e1310 15-Nov-2013 Cameron McInally <cameron.mcinally@nyu.edu> Add AVX512 unmasked FMA intrinsics and support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194824 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86ISelLowering.cpp
cb85ded9980644fc6a3ff7d8e4dc56351adcc114 15-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of using a long-winded equivalent.

Now that getConstant(-1, MVT::v2i64) works correctly on MIPS32 we can use
SelectionDAG::getNOT() to produce the bitmask.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194819 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsSEISelLowering.cpp
421556176882360e6854c77fc658bc4e8de75b58 15-Nov-2013 Alexey Samsonov <samsonov@google.com> Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan bootstrap bot

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194818 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AsmParser/AArch64AsmParser.cpp
ea28aafa83fc2b6dd632041278c9a18e5a2b2b41 15-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 type

Summary:
When getConstant() is called for an expanded vector type, it is split into
multiple scalar constants which are then combined using appropriate build_vector
and bitcast operations.

In addition to the usual big/little endian differences, the case where the
element-order of the vector does not have the same endianness as the elements
themselves is also accounted for. For example, for v4i32 on big-endian MIPS,
the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is
<0123,4567,89AB,CDEF>.
Handling this case turns out to be a nop since getConstant() returns a splatted
vector (so reversing the element order doesn't change the value)

This fixes a number of cases in MIPS MSA where calling getConstant() during
operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF
into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger
differences between illegal and legal types such as legalizing v2i64 into v8i16.

lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling
getConstant() so this function has been updated in the same patch.

For the sake of transparency, the steps I've taken since the review are:
* Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed
that the MIPS tests were falsely passing because a polymorphic function was
not actually polymorphic in the reviewed patch.
* Fixed the tests that were now failing. This involved deleting the code to
handle the MIPS MSA element-order (which was previously doing an byte-order
swap instead of an element-order swap). This left
isVectorEltOrderLittleEndian() unused and it was deleted.
* Fixed build failures caused by rebasing beyond r194467-r194472. These build
failures involved the bset, bneg, and bclr instructions added in these commits
using lowerMSASplatImm() in a way that was no longer valid after this patch.
Some of these were fixed by calling SelectionDAG::getConstant() instead,
others were fixed by a new function getBuildVectorSplat() that provided the
removed functionality of lowerMSASplatImm() in a more sensible way.

Reviewers: bkramer

Reviewed By: bkramer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/SelectionDAG.cpp
odeGen/SelectionDAG/SelectionDAGISel.cpp
arget/Mips/MipsSEISelLowering.cpp
4d748eb0e4b55262619305c96a89c55c30bffe6c 15-Nov-2013 Justin Holewinski <jholewinski@nvidia.com> [NVPTX] Fix handling of indirect calls

Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
arget/NVPTX/InstPrinter/NVPTXInstPrinter.cpp
arget/NVPTX/InstPrinter/NVPTXInstPrinter.h
arget/NVPTX/NVPTXAsmPrinter.cpp
arget/NVPTX/NVPTXISelLowering.cpp
arget/NVPTX/NVPTXISelLowering.h
arget/NVPTX/NVPTXInstrInfo.td
0dd0d1af2bec2b11dd28f513c1b740d9f6d822fa 15-Nov-2013 Yaron Keren <yaron.keren@gmail.com> Correct spelling.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194808 91177308-0d34-0410-b5e6-96231b3b80d8
xecutionEngine/IntelJITEvents/IntelJITEventsWrapper.h
8f15c6822251bbe7eb21732c46aa6d9f30ba8836 15-Nov-2013 Kostya Serebryany <kcc@google.com> [asan] use GlobalValue::PrivateLinkage for coverage guard to save quite a bit of code size

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194800 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Instrumentation/AddressSanitizer.cpp
d881c1bdd1f63bbbdb8eec5f6ae7fd765103972f 15-Nov-2013 Benjamin Kramer <benny.kra@googlemail.com> llvm-cov: Clean up memory leaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194799 91177308-0d34-0410-b5e6-96231b3b80d8
R/GCOV.cpp
42cb3abaddfcff16ab18b114c3de034839c85e05 15-Nov-2013 Zoran Jovanovic <zoran.jovanovic@imgtec.com> Use instr mapping for microMIPS in llvm-mc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MicroMipsInstrFormats.td
arget/Mips/MipsInstrInfo.td
4b8991424a8967dfdafc1768a9748f67e6c8b36f 15-Nov-2013 Bob Wilson <bob.wilson@apple.com> Reapply "[asan] Poor man's coverage that works with ASan"

I was able to successfully run a bootstrapped LTO build of clang with
r194701, so this change does not seem to be the cause of our failing
buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194789 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Instrumentation/AddressSanitizer.cpp
6dd44d3b7f33c9984dfb40461630d50c4fed1234 15-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Add instcombine visitor for addrspacecast

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194786 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombine.h
ransforms/InstCombine/InstCombineCasts.cpp
509a492442b7e889d615d3b451629c81a810aef1 15-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Add target hook to prevent folding some bitcasted loads.

This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)

On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.

Patch by Micah Villmow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
arget/R600/AMDGPUISelLowering.cpp
arget/R600/AMDGPUISelLowering.h
2475da80edafcf3a45bddbc937e60312dba435ad 15-Nov-2013 Bob Wilson <bob.wilson@apple.com> Revert "[asan] Poor man's coverage that works with ASan"

This reverts commit 194701. Apple's bootstrapped LTO builds have been failing,
and this change (along with compiler-rt 194702-194704) is the only thing on
the blamelist. I will either reappy these changes or help debug the problem,
depending on whether this fixes the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194780 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Instrumentation/AddressSanitizer.cpp
e016a163e97d29a4c343189e678633066a3365ab 15-Nov-2013 Peter Zotov <whitequark@whitequark.org> [llvm-c] Make LLVMGetTargetFromName actually work

LLVMGetTargetFromName used to compare two char* strings directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194771 91177308-0d34-0410-b5e6-96231b3b80d8
arget/TargetMachineC.cpp
fa74752298602e0b74fb60ce3f0e76d0c461d3d8 15-Nov-2013 Peter Zotov <whitequark@whitequark.org> [llvm-c] Add missing const qualifiers to LLVMCreateTargetMachine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194770 91177308-0d34-0410-b5e6-96231b3b80d8
arget/TargetMachineC.cpp
5ea0c20ce7a161d23a9bf8f1beea0ffb6a02898c 15-Nov-2013 Peter Zotov <whitequark@whitequark.org> [llvm-c] Simplify signature of LLVMGetTargetFromName

LLVMGetTargetFromName was not yet present in an LLVM release,
so this does not break compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194769 91177308-0d34-0410-b5e6-96231b3b80d8
arget/TargetMachineC.cpp
1703a714954f9ef0c32415423e2a1e15b152e711 15-Nov-2013 Reed Kotler <rkotler@mips.com> Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range.
Since there is not direct object emitter at this time, it does not
have any material affect because the assembler sorts this out. But we
need to know for the actual constant island work. We track the difference
by putting # 16 inst in the comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/Mips16ISelLowering.cpp
arget/Mips/Mips16InstrInfo.cpp
arget/Mips/Mips16InstrInfo.td
7b641815290f34f0212e4cb7b26ed1708270cb97 15-Nov-2013 Eric Christopher <echristo@gmail.com> Use a reference rather than a pointer as we don't expect a NULL
DbgVariable.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194761 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
odeGen/AsmPrinter/DwarfCompileUnit.h
odeGen/AsmPrinter/DwarfDebug.cpp
59d3ae6cdc4316ad338cd848251f33a236ccb36c 15-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Add addrspacecast instruction.

Patch by Michele Scandale!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/ConstantFolding.cpp
smParser/LLLexer.cpp
smParser/LLParser.cpp
smParser/LLToken.h
itcode/Reader/BitcodeReader.cpp
itcode/Writer/BitcodeWriter.cpp
odeGen/SelectionDAG/SelectionDAG.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
odeGen/SelectionDAG/SelectionDAGBuilder.h
odeGen/SelectionDAG/SelectionDAGDumper.cpp
odeGen/TargetLoweringBase.cpp
R/AutoUpgrade.cpp
R/ConstantFold.cpp
R/Constants.cpp
R/Core.cpp
R/Instruction.cpp
R/Instructions.cpp
R/Value.cpp
R/Verifier.cpp
arget/NVPTX/NVPTXGenericToNVVM.cpp
arget/X86/X86ISelLowering.cpp
arget/X86/X86ISelLowering.h
19a99df130f5747da950faf4ca5170d71f05594c 15-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix scheduling of instructions that use the LDS output queue

The LDS output queue is accessed via the OQAP register. The OQAP
register cannot be live across clauses, so if value is written to the
output queue, it must be retrieved before the end of the clause.
With the machine scheduler, we cannot statisfy this constraint, because
it lacks proper alias analysis and it will mark some LDS accesses as
having a chain dependency on vertex fetches. Since vertex fetches
require a new clauses, the dependency may end up spiltting OQAP uses and
defs so the end up in different clauses. See the lds-output-queue.ll
test for a more detailed explanation.

To work around this issue, we now combine the LDS read and the OQAP
copy into one instruction and expand it after register allocation.

This patch also adds some checks to the EmitClauseMarker pass, so that
it doesn't end a clause with a value still in the output queue and
removes AR.X and OQAP handling from the scheduler (AR.X uses and defs
were already being expanded post-RA, so the scheduler will never see
them).

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/R600EmitClauseMarkers.cpp
arget/R600/R600ExpandSpecialInstrs.cpp
arget/R600/R600ISelLowering.cpp
arget/R600/R600InstrInfo.cpp
arget/R600/R600InstrInfo.h
arget/R600/R600MachineScheduler.cpp
arget/R600/R600MachineScheduler.h
arget/R600/R600RegisterInfo.cpp
arget/R600/R600RegisterInfo.h
bdbcffa4af01cda413690276d8e81b3ab5cea9b6 15-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add processor type for Hawaii

Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194752 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/Processors.td
849596ced42f2760c5b63f7676e16829b808b5c9 15-Nov-2013 Andrew Trick <atrick@apple.com> When folding memory operands, preserve existing MachineMemOperands.

This comes into play with patchpoint, which can fold multiple
operands. Since the patchpoint is already treated as a call, the
machine mem operands won't affect anything, and there's nothing to
test. But we still want to do the right thing here to be sure that our
MIs obey the rules.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194750 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/TargetInstrInfo.cpp
25116f50965b237155e5d9221c36e9ffa6bff2d2 15-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Remove redundant legalizeOperands call

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194749 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
ba0e1ee0303d31138c9d94ee5fc52a1c8572876b 15-Nov-2013 Hans Wennborg <hans@hanshq.net> Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cpp

This was casuing my release+asserts build on Windows to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194747 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
5f59fe577485312a86debc48c7f310ea9265c201 14-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Specify S_ADDK/S_MULK set SCC and are commutable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194738 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstructions.td
41e1a18885b8ef29219b7102ad25cd480c4a3f55 14-Nov-2013 David Blaikie <dblaikie@gmail.com> DebugInfo: Simplify/narrow null-check for getOrCreateType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194737 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
b850a05f2c914fef74dbafbf61470512a976c632 14-Nov-2013 Rui Ueyama <ruiu@google.com> Recognize 0x0000 as a COFF file magic.

Summary:
Some machine-type-neutral object files containing only undefined symbols
actually do exist in the Windows standard library. Need to recognize them
as COFF files.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2164

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194734 91177308-0d34-0410-b5e6-96231b3b80d8
upport/Path.cpp
6a1a5e94e2b094aead41f171ee060d91ad25777c 14-Nov-2013 Chad Rosier <mcrosier@codeaurora.org> [AArch64] Remove redundant Neon_immAllOnes/Neon_immAllZeros leaf patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194733 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
8c0fecc39fe7f0928a7592104b4419022ad4b54e 14-Nov-2013 David Blaikie <dblaikie@gmail.com> DwarfCompileUnit::getOrCreateContext: Return the compile unit DIE rather than null.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194728 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
f4837be7c1d8f2a9e90100e849b148eb86a2d27e 14-Nov-2013 David Blaikie <dblaikie@gmail.com> Remove unnecessary 'else' after return.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194724 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DwarfCompileUnit.cpp
bf7329d9a0169abbd6ec837dc8b682b2f2fd98cd 14-Nov-2013 Tim Northover <tnorthover@apple.com> ARM: produce friendly error for invalid inline asm

We used to perform an invalid operation on an MVT and crash, which wasn't much
fun.

Patch by Oliver Stannard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194714 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMISelLowering.cpp
3d47402f2e8701c7ed340884720cc99727bd7f85 14-Nov-2013 Rafael Espindola <rafael.espindola@gmail.com> Error if we see an alias to a declaration.

In ELF and COFF an alias is just another offset in a section. There is no way
to represent an alias to something in another file.

In MachO, the spec has the N_INDR type which should allow for exactly that, but
is not currently implemented. Given that it is specified but not implemented,
we error in codegen to avoid miscompiling but don't reject aliases to
declarations in the verifier to leave the option open of implementing it.

In the past we have used alias to declarations as a way of implementing
weakref, which is why it exists in some old tests which this patch updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194705 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/AsmPrinter.cpp
8cc5f7cd59c69250ab3b6a68e38405dcdb6a4b25 14-Nov-2013 Kostya Serebryany <kcc@google.com> [asan] Poor man's coverage that works with ASan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194701 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Instrumentation/AddressSanitizer.cpp
34432aeb6d42fbe3e327d1d339ea4156c99aa133 14-Nov-2013 Evgeniy Stepanov <eugeni.stepanov@gmail.com> [msan] Fast path optimization for wrap-indirect-calls feature of MemorySanitizer.

Indirect call wrapping helps MSanDR (dynamic instrumentation companion tool
for MSan) to catch all cases where execution leaves a compiler-instrumented
module by allowing the tool to rewrite targets of indirect calls.

This change is an optimization that skips wrapping for calls when target is
inside the current module. This relies on the linker providing symbols at the
begin and end of the module code (or code + data, does not really matter).
Gold linker provides such symbols by default. GNU (BFD) linker needs a link
flag: -Wl,--defsym=__executable_start=0.

More info:
https://code.google.com/p/memory-sanitizer/wiki/MSanDR#Native_exec


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194697 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Instrumentation/MemorySanitizer.cpp
bdc23320c10f58f9579a397bd36584dcbd702fae 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> IR/GCOV.cpp: Use PRIu64 as format string with uint64_t.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194693 91177308-0d34-0410-b5e6-96231b3b80d8
R/GCOV.cpp
12e90cb69a0a39d0db208de98162e39a2e3d6d1e 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194692 91177308-0d34-0410-b5e6-96231b3b80d8
R/GCOV.cpp
f58e4144054b85e855c57c86eb058a6bb1907552 14-Nov-2013 Elena Demikhovsky <elena.demikhovsky@intel.com> AVX-512: Handled extractelement from mask vector;
Added VMOSHDUP/VMOVSLDUP shuffle instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86ISelLowering.cpp
arget/X86/X86InstrAVX512.td
arget/X86/X86InstrInfo.cpp
29a651af8a4b522daf1f9102c93e4c8ecc2ef3c2 14-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Indentation fixes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194688 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPUAsmPrinter.cpp
arget/R600/SIInstrInfo.cpp
54f009f5a427c640266d223826eed851a8a340c3 14-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Add a comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194684 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
a837ac357cf1354eba301665f643d7e95e26cd51 14-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Fix trailing whitespace in debug printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194683 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
2b8d813851c19596c6591c54721082217f0ab5ef 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> yaml::Input::mapTag(): Don't use StringRef to hold return type of std::string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194681 91177308-0d34-0410-b5e6-96231b3b80d8
upport/YAMLTraits.cpp
163568698c3bf439fe89833842cf9de7331dfacd 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194680 91177308-0d34-0410-b5e6-96231b3b80d8
upport/YAMLTraits.cpp
f116f8a63fb26feb0f8c59ba4d69d7954393d7d1 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> AArch64DAGToDAGISel::SelectVTBL(): Fix a warning. [-Wunused-variable]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194679 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelDAGToDAG.cpp
72cf01cc7c8f668a17e7fdfe6aaed50e164cac1b 14-Nov-2013 Andrew Trick <atrick@apple.com> Minor extension to llvm.experimental.patchpoint: don't require a call.

If a null call target is provided, don't emit a dummy call. This
allows the runtime to reserve as little nop space as it needs without
the requirement of emitting a call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194676 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/SelectionDAGBuilder.cpp
arget/X86/X86MCInstLower.cpp
732cf2d598b4c9ca47e9c32fbd2e7732d971bda6 14-Nov-2013 Rafael Espindola <rafael.espindola@gmail.com> Don't mangle \n and "

There is nothing special about quotes and newlines from the object
file point of view, only the assembler has to worry about expanding
the \n and \".

This patch then removes the special handling from the Mangler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194667 91177308-0d34-0410-b5e6-96231b3b80d8
C/MCSymbol.cpp
arget/Mangler.cpp
e59daaa2b83ddb7b6c563e69ef9ae5d67d3a8e07 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> R600/SIFixSGPRCopies.cpp: Fix \param to \return. [-Wdocumentation]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194662 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
b502e097427e853122d899362ae0a6df3a44e682 14-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194661 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIFixSGPRCopies.cpp
0710afb9af81cff9846ceda7b56d03cf177dd6ef 14-Nov-2013 Kevin Qin <Kevin.Qin@arm.com> [AArch64 neon] support poly64 and relevant intrinsic functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194659 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
a08063a000cfc7499f08a472d85f14e7a5e90f8d 14-Nov-2013 Kevin Qin <Kevin.Qin@arm.com> Implement aarch64 neon instruction class SIMD misc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelLowering.cpp
arget/AArch64/AArch64ISelLowering.h
arget/AArch64/AArch64InstrNEON.td
04fca67d6f4b314ba618714698b58dbfba3af005 14-Nov-2013 Nick Kledzik <kledzik@apple.com> Add dyn_cast<> support to YAML I/O's IO class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194655 91177308-0d34-0410-b5e6-96231b3b80d8
upport/YAMLTraits.cpp
e2058ff5bd4fa0397b57f6bdd84e5a5aa2343433 14-Nov-2013 Michael Gottesman <mgottesman@apple.com> Added BlockFrequencyInfo::view for displaying the block frequency propagation graph via graphviz.

This is useful for debugging issues in the BlockFrequency implementation since
one can easily visualize where probability mass and other errors occur in the
propagation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194654 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/BlockFrequencyInfo.cpp
082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17 14-Nov-2013 Jiangning Liu <jiangning.liu@arm.com> Implement AArch64 NEON instruction set AdvSIMD (table).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64ISelDAGToDAG.cpp
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrNEON.td
2999b2f2ccc3a48c834dffe19bb39c67641a3afd 14-Nov-2013 Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> Fixing a heisenbug where the memory dependence analysis behaves differently
with and without -g.

Adding a test case to make sure that the threshold used in the memory
dependence analysis is respected. The test case also checks that debug
intrinsics are not counted towards this threshold.

Differential Revision: http://llvm-reviews.chandlerc.com/D2141



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194646 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/MemoryDependenceAnalysis.cpp
4e7c22a90b28828e4a28751b65ae24091f7df4ec 14-Nov-2013 Nick Kledzik <kledzik@apple.com> Add simple support for tags in YAML I/O

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194644 91177308-0d34-0410-b5e6-96231b3b80d8
upport/YAMLTraits.cpp
4bd0224887a8de1434186cad2f618c18dea06c0b 14-Nov-2013 Yuchen Wu <yuchenericwu@hotmail.com> llvm-cov: Slightly improved error checking.

- readInt() should check all 4 bytes can be read, not just 1.
- In the event of false data in the gcno file, it was possible to index
into a non-existent index of SmallVector, causing assertion error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194639 91177308-0d34-0410-b5e6-96231b3b80d8
R/GCOV.cpp
131a764e0e7abc90b322fd568e042d3c5a0633af 14-Nov-2013 Yuchen Wu <yuchenericwu@hotmail.com> llvm-cov: Removed StringMap holding GCOVLines.

According to the hazy gcov documentation, it appeared to be technically
possible for lines within a block to belong to different source files.
However, upon further investigation, gcov does not actually support
multiple source files for a single block.

This change removes a level of separation between blocks and lines by
replacing the StringMap of GCOVLines with a SmallVector of ints
representing line numbers. This also means that the GCOVLines class is
no longer needed.

This paves the way for supporting the "-a" option, which will output
block information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194637 91177308-0d34-0410-b5e6-96231b3b80d8
R/GCOV.cpp
dbb51ff01fd08df39e5040c1cd9edacdc3e4308a 14-Nov-2013 Yuchen Wu <yuchenericwu@hotmail.com> llvm-cov: Replaced asserts with proper error handling.

Unified the interface for read functions. They all return a boolean
indicating if the read from file succeeded. Functions that previously
returned the read value now store it into a variable that is passed in
by reference instead. Callers will need to check the return value to
detect if an error occurred.

Also added a new test which ensures that no assertions occur when file
contains invalid data. llvm-cov should return with error code 1 upon
failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194635 91177308-0d34-0410-b5e6-96231b3b80d8
R/GCOV.cpp
006806267a4f85a5abf32573348c81098f2696d2 14-Nov-2013 Michael Gottesman <mgottesman@apple.com> Fixed 80+ violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194634 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/BlockFrequencyInfo.cpp
7c94599d1b34fbe3a3857edf41946dc62f9cfba2 14-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix uninitialized variable usage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194632 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIInstrInfo.cpp
5aeb5e530e11a1473ecddb126b72cd4e37fada81 14-Nov-2013 Reed Kotler <rkotler@mips.com> Take care of long short branch immediate instructions for mips16 in
constant islands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194630 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsConstantIslandPass.cpp
a2b4eb6d15a13de257319ac6231b5ab622cd02b1 14-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add support for private address space load/store

Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/AMDGPUISelDAGToDAG.cpp
arget/R600/AMDGPUISelLowering.cpp
arget/R600/AMDGPUISelLowering.h
arget/R600/AMDGPUInstrInfo.cpp
arget/R600/AMDGPUInstrInfo.h
arget/R600/AMDGPUInstructions.td
arget/R600/AMDGPURegisterInfo.h
arget/R600/R600ISelLowering.cpp
arget/R600/R600ISelLowering.h
arget/R600/R600InstrInfo.cpp
arget/R600/R600InstrInfo.h
arget/R600/R600Instructions.td
arget/R600/R600RegisterInfo.cpp
arget/R600/R600RegisterInfo.h
arget/R600/SIISelLowering.cpp
arget/R600/SIISelLowering.h
arget/R600/SIInsertWaits.cpp
arget/R600/SIInstrInfo.cpp
arget/R600/SIInstrInfo.h
arget/R600/SIInstrInfo.td
arget/R600/SIInstructions.td
arget/R600/SILowerControlFlow.cpp
arget/R600/SIRegisterInfo.cpp
arget/R600/SIRegisterInfo.h
b52bf6a3b31596a309f4b12884522e9b4a344654 14-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Prefer SALU instructions for bit shift operations

All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/SIDefines.h
arget/R600/SIFixSGPRCopies.cpp
arget/R600/SIInstrFormats.td
arget/R600/SIInstrInfo.cpp
arget/R600/SIInstrInfo.h
arget/R600/SIInstrInfo.td
arget/R600/SIInstructions.td
arget/R600/SIRegisterInfo.cpp
arget/R600/SIRegisterInfo.h
f44941d81dc30cfd357c12292059721c9644a27f 13-Nov-2013 Sebastian Pop <spop@codeaurora.org> add more comments around the delinearization of arrays

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194612 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/Delinearization.cpp
nalysis/DependenceAnalysis.cpp
nalysis/ScalarEvolution.cpp
dc9a217d05eb5b65b51ad1f806166ae6430308b1 13-Nov-2013 Jakub Staszak <kubastaszak@gmail.com> Simplify code. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194602 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/LoopInfo.cpp
a305ffb65becc1031abbf85e70aec8fb3c337986 13-Nov-2013 Jakub Staszak <kubastaszak@gmail.com> Use StringRef instead of std::string

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194601 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Utils/LoopUnroll.cpp
11966d7c984c3e32b102ecd26083c6f274973d96 13-Nov-2013 Chad Rosier <mcrosier@codeaurora.org> [AArch64] Add support for legacy AArch32 NEON scalar shift by immediate
instructions. This patch does not include the shift right and accumulate
instructions. A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194598 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrNEON.td
929bdb23794b615dc6b0cc59db21f0450c3ce33b 13-Nov-2013 Weiming Zhao <weimingz@codeaurora.org> Enable generating legacy IT block for AArch32

By default, the behavior of IT block generation will be determinated
dynamically base on the arch (armv8 vs armv7). This patch adds backend
options: -arm-restrict-it and -arm-no-restrict-it. The former one
restricts the generation of IT blocks (the same behavior as thumbv8) for
both arches. The later one allows the generation of legacy IT block (the
same behavior as ARMv7 Thumb2) for both arches.

Clang will support -mrestrict-it and -mno-restrict-it, which is
compatible with GCC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/ARMBaseInstrInfo.cpp
arget/ARM/ARMSubtarget.cpp
arget/ARM/ARMSubtarget.h
arget/ARM/ARMTargetMachine.cpp
arget/ARM/Thumb2ITBlockPass.cpp
a9a8f0f432966438800ffabb1b740a4cc8cd2599 13-Nov-2013 David Blaikie <dblaikie@gmail.com> DIEHash: Move header include to be first in the implementation file to flush out header inclusion ordering issues

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194588 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/AsmPrinter/DIEHash.cpp
odeGen/AsmPrinter/DIEHash.h
541c5de2fb57b2f459f0ec49f33a0ecce3532acd 13-Nov-2013 Richard Sandiford <rsandifo@linux.vnet.ibm.com> [SystemZ] Add the general form of BCR

At the moment this is just the MC support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
arget/SystemZ/Disassembler/SystemZDisassembler.cpp
arget/SystemZ/SystemZInstrInfo.td
1a362619f8f74267776a93f101ef32b69b53f5b3 13-Nov-2013 Benjamin Kramer <benny.kra@googlemail.com> Move Delinearization pass into an anonymous namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194582 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/Delinearization.cpp
43a0f3959e00ad8ab455d1e32a54a45c39a7ee8a 13-Nov-2013 Benjamin Kramer <benny.kra@googlemail.com> Make sure LLVMLoadLibraryPermanently gets an extern "C" symbol.

Otherwise it's impossible to use it. Also don't include C++ headers in
a C header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194581 91177308-0d34-0410-b5e6-96231b3b80d8
upport/DynamicLibrary.cpp
de9a1a2055851a0f0a88e459cd23a246a90efd45 13-Nov-2013 Rafael Espindola <rafael.espindola@gmail.com> Remove AllowQuotesInName and friends from MCAsmInfo.

Accepting quotes is a property of an assembler, not of an object file. For
example, ELF can support any names for sections and symbols, but the gnu
assembler only accepts quotes in some contexts and llvm-mc in a few more.

LLVM should not produce different symbols based on a guess about which assembler
will be reading the code it is printing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194575 91177308-0d34-0410-b5e6-96231b3b80d8
C/MCAsmInfo.cpp
C/MCAsmInfoCOFF.cpp
C/MCAsmInfoDarwin.cpp
C/MCSectionELF.cpp
arget/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
arget/Mangler.cpp
arget/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
arget/R600/MCTargetDesc/AMDGPUMCAsmInfo.cpp
7af43e0ad01a5f85f9066b69faba990a72f89536 13-Nov-2013 Rafael Espindola <rafael.espindola@gmail.com> Don't call doFinalization from verifyFunction.

verifyFunction needs to call doInitialization to collect metadata and avoid
crashing when verifying debug info in a function.

But it should not call doFinalization since that is where the verifier will
check declarations, variables and aliases, which is not desirable when one
only wants to verify a function.

A possible cleanup would be to split the class into a ModuleVerifier and
FunctionVerifier.

Issue reported by Ilia Filippov. Patch by Michael Kruse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194574 91177308-0d34-0410-b5e6-96231b3b80d8
R/Verifier.cpp
c0fad4d9fdb1aebe029bcb54311fad7059b1a9e5 13-Nov-2013 Vladimir Medic <Vladimir.Medic@imgtec.com> Fix bug in .gpword directive parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/AsmParser/MipsAsmParser.cpp
1206f1968b0886ab41739aebe113dd4813f3fc46 13-Nov-2013 Zoran Jovanovic <zoran.jovanovic@imgtec.com> Support for microMIPS trap instruction with immediate operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MicroMipsInstrFormats.td
arget/Mips/MicroMipsInstrInfo.td
arget/Mips/MipsInstrFormats.td
arget/Mips/MipsInstrInfo.td
4223b9601058369536caa1d15c9c19bc7c5a3706 13-Nov-2013 Alexey Samsonov <samsonov@google.com> Fix -Wdelete-non-virtual-dtor warnings by making SampleProfile methods non-virtual

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194568 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Scalar/SampleProfile.cpp
563b29f8db68275407ffcd2a9a5f0ba77ee5e899 13-Nov-2013 Diego Novillo <dnovillo@google.com> SampleProfileLoader pass. Initial setup.

This adds a new scalar pass that reads a file with samples generated
by 'perf' during runtime. The samples read from the profile are
incorporated and emmited as IR metadata reflecting that profile.

The profile file is assumed to have been generated by an external
profile source. The profile information is converted into IR metadata,
which is later used by the analysis routines to estimate block
frequencies, edge weights and other related data.

External profile information files have no fixed format, each profiler
is free to define its own. This includes both the on-disk representation
of the profile and the kind of profile information stored in the file.
A common kind of profile is based on sampling (e.g., perf), which
essentially counts how many times each line of the program has been
executed during the run.

The SampleProfileLoader pass is organized as a scalar transformation.
On startup, it reads the file given in -sample-profile-file to
determine what kind of profile it contains. This file is assumed to
contain profile information for the whole application. The profile
data in the file is read and incorporated into the internal state of
the corresponding profiler.

To facilitate testing, I've organized the profilers to support two file
formats: text and native. The native format is whatever on-disk
representation the profiler wants to support, I think this will mostly
be bitcode files, but it could be anything the profiler wants to
support. To do this, every profiler must implement the
SampleProfile::loadNative() function.

The text format is mostly meant for debugging. Records are separated by
newlines, but each profiler is free to interpret records as it sees fit.
Profilers must implement the SampleProfile::loadText() function.

Finally, the pass will call SampleProfile::emitAnnotations() for each
function in the current translation unit. This function needs to
translate the loaded profile into IR metadata, which the analyzer will
later be able to use.

This patch implements the first steps towards the above design. I've
implemented a sample-based flat profiler. The format of the profile is
fairly simplistic. Each sampled function contains a list of relative
line locations (from the start of the function) together with a count
representing how many samples were collected at that line during
execution. I generate this profile using perf and a separate converter
tool.

Currently, I have only implemented a text format for these profiles. I
am interested in initial feedback to the whole approach before I send
the other parts of the implementation for review.

This patch implements:

- The SampleProfileLoader pass.
- The base ExternalProfile class with the core interface.
- A SampleProfile sub-class using the above interface. The profiler
generates branch weight metadata on every branch instructions that
matches the profiles.
- A text loader class to assist the implementation of
SampleProfile::loadText().
- Basic unit tests for the pass.

Additionally, the patch uses profile information to compute branch
weights based on instruction samples.

This patch converts instruction samples into branch weights. It
does a fairly simplistic conversion:

Given a multi-way branch instruction, it calculates the weight of
each branch based on the maximum sample count gathered from each
target basic block.

Note that this assignment of branch weights is somewhat lossy and can be
misleading. If a basic block has more than one incoming branch, all the
incoming branches will get the same weight. In reality, it may be that
only one of them is the most heavily taken branch.

I will adjust this assignment in subsequent patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194566 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Scalar/CMakeLists.txt
ransforms/Scalar/SampleProfile.cpp
ransforms/Scalar/Scalar.cpp
8b99622b9b0902c709a33a07efb3461bc7830852 13-Nov-2013 Robert Lytton <robert@xmos.com> XCore target: implement exception handling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194564 91177308-0d34-0410-b5e6-96231b3b80d8
arget/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp
arget/XCore/XCoreFrameLowering.cpp
arget/XCore/XCoreISelLowering.cpp
c7ebe502765fecc2af047ced115845936e8ed58e 13-Nov-2013 Vladimir Medic <Vladimir.Medic@imgtec.com> This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/AsmParser/MipsAsmParser.cpp
6c242d385b44d063a8a9d4690e5a9d8fdd72ef35 13-Nov-2013 NAKAMURA Takumi <geek4civic@gmail.com> Mips16InstrInfo.cpp: Use <cctype> instead of <ctype.h>

Also, prune <stdlib.h>, seems stray.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194557 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/Mips16InstrInfo.cpp
4df21b14675954ba951ad118d1dc4a4021650078 13-Nov-2013 Reed Kotler <rkotler@mips.com> Allow the code which returns the length for inline assembler to know
specifically about the .space directive. This allows us to force large
blocks of code to appear in test cases for things like constant islands
without having to make giant test cases to force things like long
branches to take effect.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194555 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/Mips16InstrInfo.cpp
arget/Mips/Mips16InstrInfo.h
arget/Mips/MipsConstantIslandPass.cpp
29f1788de96cbf88ab87e3da130cf626b2e8e029 13-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600: Fix selection failure on EXTLOAD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194547 91177308-0d34-0410-b5e6-96231b3b80d8
arget/R600/R600ISelLowering.cpp
c7e77f91fecd662b198939a9a8ee0a0cc3828fc4 13-Nov-2013 Juergen Ributzka <juergen@apple.com> SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.

This patch reapplies r193676 with an additional fix for the Hexagon backend. The
SystemZ backend has already been fixed by r194148.

The Type Legalizer recognizes that VSELECT needs to be split, because the type
is to wide for the given target. The same does not always apply to SETCC,
because less space is required to encode the result of a comparison. As a result
VSELECT is split and SETCC is unrolled into scalar comparisons.

This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG
Combiner. If a matching pattern is found, then the result mask of SETCC is
promoted to the expected vector mask type for the given target. Now the type
legalizer will split both VSELECT and SETCC.

This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.

Reviewed by Nadav

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194542 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/SelectionDAG/DAGCombiner.cpp
odeGen/SelectionDAG/LegalizeTypesGeneric.cpp
arget/Hexagon/HexagonISelLowering.h
arget/X86/X86ISelLowering.cpp
f348c9782c5c31309dfd2d04e3dbee21fefe07ff 13-Nov-2013 Chandler Carruth <chandlerc@gmail.com> Introduce an AnalysisManager which is like a pass manager but with a lot
more smarts in it. This is where most of the interesting logic that used
to live in the implicit-scheduling-hackery of the old pass manager will
live.

Like the previous commits, note that this is a very early prototype!
I expect substantial changes before this is ready to use.

The core of the design is the following:

- We have an AnalysisManager which can be used across a series of
passes over a module.
- The code setting up a pass pipeline registers the analyses available
with the manager.
- Individual transform passes can check than an analysis manager
provides the analyses they require in order to fail-fast.
- There is *no* implicit registration or scheduling.
- Analysis passes are different from other passes: they produce an
analysis result that is cached and made available via the analysis
manager.
- Cached results are invalidated automatically by the pass managers.
- When a transform pass requests an analysis result, either the analysis
is run to produce the result or a cached result is provided.

There are a few aspects of this design that I *know* will change in
subsequent commits:
- Currently there is no "preservation" system, that needs to be added.
- All of the analysis management should move up to the analysis library.
- The analysis management needs to support at least SCC passes. Maybe
loop passes. Living in the analysis library will facilitate this.
- Need support for analyses which are *both* module and function passes.
- Need support for pro-actively running module analyses to have cached
results within a function pass manager.
- Need a clear design for "immutable" passes.
- Need support for requesting cached results when available and not
re-running the pass even if that would be necessary.
- Need more thorough testing of all of this infrastructure.

There are other aspects that I view as open questions I'm hoping to
resolve as I iterate a bit on the infrastructure, and especially as
I start writing actual passes against this.
- Should we have separate management layers for function, module, and
SCC analyses? I think "yes", but I'm not yet ready to switch the code.
Adding SCC support will likely resolve this definitively.
- How should the 'require' functionality work? Should *that* be the only
way to request results to ensure that passes always require things?
- How should preservation work?
- Probably some other things I'm forgetting. =]

Look forward to more patches in shorter order now that this is in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194538 91177308-0d34-0410-b5e6-96231b3b80d8
R/CMakeLists.txt
R/PassManager.cpp
0d833348c2dea181e08d3ece8da18079653f96ee 13-Nov-2013 Nadav Rotem <nrotem@apple.com> Update the docs to match the function name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194537 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineAndOrXor.cpp
eb3602472026dc029beb45ccbe09bc84162ba949 13-Nov-2013 Aaron Ballman <aaron@aaronballman.com> Replacing HUGE_VALF with llvm::huge_valf in order to work around a warning triggered in MSVC 12.

Patch reviewed by Reid Kleckner and Jim Grosbach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194533 91177308-0d34-0410-b5e6-96231b3b80d8
odeGen/LiveIntervalAnalysis.cpp
odeGen/RegAllocGreedy.cpp
odeGen/Spiller.cpp
328066513d18acd4e44ad57172c73f1a2a026022 13-Nov-2013 Rafael Espindola <rafael.espindola@gmail.com> Remove always true flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194530 91177308-0d34-0410-b5e6-96231b3b80d8
C/MCAsmInfo.cpp
arget/Mangler.cpp
7107aded170612748f46380f21ec6b71dfaf4910 12-Nov-2013 Andrew Trick <atrick@apple.com> Cleanup the stackmap operand folding code and fix a corner case.

I still don't know how to refer to the fixed operands symbolically. I
plan to look into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194529 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86InstrInfo.cpp
5230ad61fd35d3006e7764c3152d28e2e68c288f 12-Nov-2013 Sebastian Pop <spop@codeaurora.org> delinearization of arrays

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194527 91177308-0d34-0410-b5e6-96231b3b80d8
nalysis/Analysis.cpp
nalysis/CMakeLists.txt
nalysis/Delinearization.cpp
nalysis/DependenceAnalysis.cpp
nalysis/ScalarEvolution.cpp
6c84f7ad2dbba5d1afa26a4929c3b032ae9e7e10 12-Nov-2013 Nadav Rotem <nrotem@apple.com> Fold (iszero(A&K1) | iszero(A&K2)) -> (A&(K1|K2)) != (K1|K2) if we know that K1 and K2 are 'one-hot' (only one bit is on).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194525 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/InstCombine/InstCombineAndOrXor.cpp
f3bd3ea3fe1abf414d3a38a684f3df7382a1a8d5 12-Nov-2013 Nadav Rotem <nrotem@apple.com> FoldBranchToCommonDest merges branches into a single branch with or/and of the condition. It has a heuristics for estimating when some of the dependencies are processed by out-of-order processors. This patch adds another rule to the heuristics that says that if the "BonusInstruction" that we speculatively execute is used by the condition of the second branch then it is okay to hoist it. This change exposes more opportunities for other passes to transform the code. It does not matter that much that we if-convert the code because the selectiondag builder splits or/and branches into multiple branches when profitable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194524 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/Utils/SimplifyCFG.cpp
714e04b84ac5c2342f468aa55953694e4cdf3834 12-Nov-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix a bug in function CC_MipsO32_FP64. The second double precision
argument was not being passed in $f14.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsISelLowering.cpp
2a499a73131e06162a1a6cfa813adc077251781b 12-Nov-2013 Eric Christopher <echristo@gmail.com> Add a FIXME for 32-bit q modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194515 91177308-0d34-0410-b5e6-96231b3b80d8
arget/X86/X86AsmPrinter.cpp
dc6b4b4fc2665eea17684d29e4dae219b258b5ef 12-Nov-2013 Justin Bogner <mail@justinbogner.com> Protect user-supplied runtime library functions in LTO

Add user-supplied C runtime and compiler-rt library functions to
llvm.compiler.used to protect them from premature optimization by
passes like -globalopt and -ipsccp. Calls to (seemingly unused)
runtime library functions can be added by -instcombine and instruction
lowering.

Patch by Duncan Exon Smith, thanks!

Fixes <rdar://problem/14740087>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194514 91177308-0d34-0410-b5e6-96231b3b80d8
TO/LTOCodeGenerator.cpp
59e648e3c8966e0678902a2994558f25c8573ce4 12-Nov-2013 Tim Northover <tnorthover@apple.com> ARM: diagnose invalid system LDM/STM

The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
arget/ARM/AsmParser/ARMAsmParser.cpp
d4765aa047c43dc0ce2c4a6a3ccdb91b8fa73c51 12-Nov-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Revert part of r194510 that was accidentally committed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194511 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsISelLowering.cpp
0a227ad4d5e12ca90fd937bf2b05d8bca291a1ad 12-Nov-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix and re-enable a test case that has been disabled for a long time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Mips/MipsISelLowering.cpp
46456f6a2ff5b81a3ea60bdcf9a0813c9fa4257f 12-Nov-2013 Rafael Espindola <rafael.espindola@gmail.com> Corruptly merge constants with explicit and implicit alignments.

Constant merge can merge a constant with implicit alignment with one that has
explicit alignment. Before this change it was assuming that the explicit
alignment was higher than the implicit one, causing the result to be under
aligned in some cases.

Fixes pr17815.

Patch by Chris Smowton!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194506 91177308-0d34-0410-b5e6-96231b3b80d8
ransforms/IPO/ConstantMerge.cpp
13c83a2a09a0842ff57ec020fe3f534de766ccd1 12-Nov-2013 Chad Rosier <mcrosier@codeaurora.org> [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
arget/AArch64/AArch64InstrFormats.td
arget/AArch64/AArch64InstrInfo.td
arget/AArch64/AArch64InstrNEON.td
arget/AArch64/Disassembler/AArch64Disassembler.cpp
3e94418e857d5e17b5d16dbc5abc8b5a8b4efac6 12-Nov-2013 Roman Divacky <rdivacky@freebsd.org> Expand rotate instructions on sparcv9 as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194500 91177308-0d34-0410-b5e6-96231b3b80d8
arget/Sparc/SparcISelLowering.cpp
0085d5e5ae45e74254c2aa682e18574cd79f3455 12-Nov-2013 Andrew Trick <atrick@apple.com> Simplify operand folding when rematerializing a load.

We already know how to fold a reload from a frameindex without
analyzing the load instruction. Generalize this to handle any
frameindex load. This streamlines the logic for rematerializing loads
from stack arguments. As a side effect, it allows stackmaps to record
a stack argument location without spilling it.

Verified no effect on codegen for llvm test-suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@