dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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258115258f8fe15e9d74b5fb524f90b75bb917d1 |
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06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Bitwise Extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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6a5a667517160ca1b557002a29d08868ae029451 |
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10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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812ddcc50f8bc3ec6ce115863ff2263815906aaf |
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10-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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d622bef31d11a5a6429fe7fad557c9b111e96f69 |
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10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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e54360be01d1eaccd5ef27f510634927aaa887a4 |
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17-Sep-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement 3 AArch64 neon instructions : umov smov ins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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630c5e06d633fad142af4b145ee684e90754700e |
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13-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: use RegisterOperand for NEON registers. Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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87773c318fcee853fb34a80a10c4347d523bdafb |
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01-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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dfe076af9879eb68a7b8331f9c02eecf563d85be |
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05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Fix formatting in AArch64 backend. This should fix three purely whitespace issues: + 80 column violations. + Tab characters. + TableGen brace placement. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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19254c49a8752fe8c6fa648a6eb29f20a1f62c8b |
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05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove cyclic dependency in AArch64 libraries This moves the bit twiddling and string fiddling functions required by other parts of the backend into a separate library. Previously they resided in AArch64Desc, which created a circular dependency between various components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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72062f5744557e270a38192554c3126ea5f97434 |
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31-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 as an experimental target. This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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