| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
15SDOptimizer.cpp
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMFrameLowering.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb2.td
RMJITInfo.cpp
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMCInstLower.cpp
RMMachineFunctionInfo.cpp
RMMachineFunctionInfo.h
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
RMTargetTransformInfo.cpp
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMBaseInfo.h
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCExpr.cpp
CTargetDesc/ARMMCExpr.h
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/ARMMachObjectWriter.cpp
CTargetDesc/ARMTargetStreamer.cpp
humb1FrameLowering.cpp
humb1FrameLowering.h
humb2SizeReduction.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
15SDOptimizer.cpp
RM.h
RMAsmPrinter.cpp
RMAsmPrinter.h
RMAtomicExpandPass.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCallingConv.h
RMCallingConv.td
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMFeatures.h
RMFrameLowering.cpp
RMFrameLowering.h
RMHazardRecognizer.cpp
RMHazardRecognizer.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMOptimizeBarriersPass.cpp
RMRegisterInfo.td
RMScheduleV6.td
RMSelectionDAGInfo.cpp
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
RMTargetObjectFile.cpp
RMTargetObjectFile.h
RMTargetTransformInfo.cpp
ndroid.mk
smParser/ARMAsmParser.cpp
MakeLists.txt
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMMCAsmInfo.cpp
CTargetDesc/ARMMCAsmInfo.h
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCExpr.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/ARMMachObjectWriter.cpp
CTargetDesc/ARMTargetStreamer.cpp
CTargetDesc/ARMWinCOFFObjectWriter.cpp
CTargetDesc/ARMWinCOFFStreamer.cpp
CTargetDesc/Android.mk
CTargetDesc/CMakeLists.txt
LxExpansionPass.cpp
EADME-Thumb.txt
humb1FrameLowering.cpp
humb1RegisterInfo.h
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
15SDOptimizer.cpp
RM.h
RM.td
RMAsmPrinter.cpp
RMAsmPrinter.h
RMAtomicExpandPass.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMBuildAttrs.h
RMCallingConv.td
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.h
RMExpandPseudoInsts.cpp
RMFPUName.def
RMFastISel.cpp
RMFeatures.h
RMFrameLowering.cpp
RMFrameLowering.h
RMHazardRecognizer.cpp
RMHazardRecognizer.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.cpp
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMCInstLower.cpp
RMMachineFunctionInfo.h
RMOptimizeBarriersPass.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMRelocations.h
RMScheduleA9.td
RMScheduleSwift.td
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
RMTargetObjectFile.cpp
RMTargetObjectFile.h
RMTargetTransformInfo.cpp
ndroid.mk
smParser/ARMAsmParser.cpp
smParser/Android.mk
smParser/CMakeLists.txt
MakeLists.txt
isassembler/ARMDisassembler.cpp
isassembler/Android.mk
isassembler/CMakeLists.txt
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
nstPrinter/Android.mk
nstPrinter/CMakeLists.txt
LVMBuild.txt
CTargetDesc/ARMArchName.def
CTargetDesc/ARMArchName.h
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMBaseInfo.h
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMFixupKinds.h
CTargetDesc/ARMMCAsmInfo.cpp
CTargetDesc/ARMMCAsmInfo.h
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCExpr.h
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/ARMMachORelocationInfo.cpp
CTargetDesc/ARMMachObjectWriter.cpp
CTargetDesc/ARMTargetStreamer.cpp
CTargetDesc/ARMUnwindOp.h
CTargetDesc/ARMUnwindOpAsm.cpp
CTargetDesc/ARMUnwindOpAsm.h
CTargetDesc/Android.mk
CTargetDesc/CMakeLists.txt
LxExpansionPass.cpp
argetInfo/ARMTargetInfo.cpp
argetInfo/Android.mk
argetInfo/CMakeLists.txt
argetInfo/LLVMBuild.txt
humb1FrameLowering.cpp
humb1FrameLowering.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
humb2SizeReduction.cpp
|
| bd3e4ce9cfa61bcc0176ac17a06f0904cb854a9a |
19-Feb-2014 |
Colin Cross <ccross@android.com> |
am b7485134: am 449fc261: Merge "llvm: convert makefiles to support multilib build"
* commit 'b7485134a2cbecc47904988b4cfde24019ac4fa1':
llvm: convert makefiles to support multilib build
|
| 373aa5c665fe6df6b9c5586d397dc3617f25aab5 |
07-Feb-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to 3.4.
Update config.h files.
Add RS SubtargetFeature for +long64 on ARM devices.
Adjust Android.mk for added/removed files:
+ Delinearization.cpp
- PathNumbering.cpp
- PathProfileInfo.cpp
- PathProfileVerifier.cpp
- ProfileDataLoader.cpp
- ProfileDataLoaderPass.cpp
- ProfileEstimatorPass.cpp
- ProfileInfo.cpp
- ProfileInfoLoader.cpp
- ProfileInfoLoaderPass.cpp
- ProfileVerifierPass.cpp
+ LiveRegUnits.cpp
- ShrinkWrapping.cpp
+ StackMaps.cpp
- StrongPHIElimination.cpp
+ DIEHash.cpp
+ LegacyPassManager.cpp
+ ELF.cpp
+ Unicode.cpp
- MipsOptimizeMathLibCalls.cpp
- MipsELFStreamer.cpp
+ MipsTargetStreamer.cpp
- EdgeProfiling.cpp
+ DataFlowSanitizer.cpp
+ DebugIR.cpp
- OptimalEdgeProfiling.cpp
- PathProfiling.cpp
- ProfilingUtils.cpp
- BasicBlockPlacement.cpp
+ LoopRerollPass.cpp
+ PartiallyInlineLibCalls.cpp
+ SampleProfile.cpp
+ GlobalStatus.cpp
Change-Id: I17dcf0bf53a1720acd8226ae3e30d84993562a91
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| ce9904c6ea8fd669978a8eefb854b330eb9828ff |
12-Feb-2014 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/release_34' into merge-20140211
Conflicts:
lib/Linker/LinkModules.cpp
lib/Support/Unix/Signals.inc
Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
|
| b7325c318ecf01d4c82391c1f0a63090c8de0144 |
05-Feb-2014 |
Colin Cross <ccross@android.com> |
llvm: convert makefiles to support multilib build
Convert makefiles to allow for building two architectures at the
same time. This will also cause make checkbuild to build the target
libraries for all supported architectures.
Change-Id: Ia5e6fe5b1186a67753faafd3532ed4cb280a8b10
ndroid.mk
isassembler/Android.mk
CTargetDesc/Android.mk
argetInfo/Android.mk
|
| 54ed08e250a76b570c2162d49633e11b8ebb2d98 |
09-Dec-2013 |
Tim Northover <tnorthover@apple.com> |
Merge r196725 (conflicts on same API as before):
------------------------------------------------------------------------
r196725 | tnorthover | 2013-12-08 15:56:50 +0000 (Sun, 08 Dec 2013) |
19 lines
ARM: fix folding of stack-adjustment (yet again).
When trying to eliminate an "sub sp, sp, #N" instruction by folding
it into an existing push/pop using dummy registers, we need to account
for the fact that this might affect precisely how "fp" gets set in the
prologue.
We were attempting this, but assuming that *whenever* we performed a
fold it would make a difference. This is false, for example, in:
push {r4, r7, lr}
add fp, sp, #4
vpush {d8}
sub sp, sp, #8
we can fold the "sub" into the "vpush", forming "vpush {d7, d8}".
However, in that case the "add fp" instruction mustn't change, which
we were getting wrong before.
Should fix PR18160.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196769 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| e8098892f517c492193f8f8ebdcbb861d7a7b54a |
08-Dec-2013 |
Tim Northover <tnorthover@apple.com> |
Merging r196493. Simple conflict due to change API of updated
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196717 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 2bdc0dd2db145591eb3fdc01fa0b2a3d831f334b |
08-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196588:
------------------------------------------------------------------------
r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines
Bug 18149: [AArch32] VSel instructions has no ARMCC field
The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196704 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 31928dfc03d92322f9f2fb1c4a7878024d3cc9d1 |
07-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196269:
------------------------------------------------------------------------
r196269 | jamesm | 2013-12-03 03:23:11 -0800 (Tue, 03 Dec 2013) | 5 lines
Addrspacecasts are no-ops on ARM.
Testcase added.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196651 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 1b26fdbf1f01e90b803cc035b6b932cd95c76830 |
02-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196046:
------------------------------------------------------------------------
r196046 | tnorthover | 2013-12-01 06:16:24 -0800 (Sun, 01 Dec 2013) | 8 lines
ARM: fix bug in -Oz stack adjustment folding
Previously, we clobbered callee-saved registers when folding an "add
sp, #N" into a "pop {rD, ...}" instruction. This change checks whether
a register we're going to add to the "pop" could actually be live
outside the function before doing so and should fix the issue.
This should fix PR18081.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196074 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.h
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 3d238de4d54eb0b16afd96a57f49f92b2f7748e0 |
02-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195401:
------------------------------------------------------------------------
r195401 | lhames | 2013-11-21 16:46:32 -0800 (Thu, 21 Nov 2013) | 8 lines
Fix a typo where we were creating <def,kill> operands instead of
<def,dead> ones.
Add an assertion to make sure we catch this in the future.
Fixes <rdar://problem/15464559>.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196073 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 354362524a72b3fa43a6c09380b7ae3b2380cbba |
19-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 |
18-Nov-2013 |
Alexey Samsonov <samsonov@google.com> |
Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 |
15-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cc7052343e5e955d4e2f48885c06360f9003390a |
15-Nov-2013 |
Bob Wilson <bob.wilson@apple.com> |
Avoid illegal integer promotion in fastisel
Stop folding constant adds into GEP when the type size doesn't match.
Otherwise, the adds' operands are effectively being promoted, changing the
conditions of an overflow. Results are different when:
sext(a) + sext(b) != sext(a + b)
Problem originally found on x86-64, but also fixed issues with ARM and PPC,
which used similar code.
<rdar://problem/15292280>
Patch by Duncan Exon Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194840 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bf7329d9a0169abbd6ec837dc8b682b2f2fd98cd |
14-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: produce friendly error for invalid inline asm
We used to perform an invalid operation on an MVT and crash, which wasn't much
fun.
Patch by Oliver Stannard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194714 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 929bdb23794b615dc6b0cc59db21f0450c3ce33b |
13-Nov-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Enable generating legacy IT block for AArch32
By default, the behavior of IT block generation will be determinated
dynamically base on the arch (armv8 vs armv7). This patch adds backend
options: -arm-restrict-it and -arm-no-restrict-it. The former one
restricts the generation of IT blocks (the same behavior as thumbv8) for
both arches. The later one allows the generation of legacy IT block (the
same behavior as ARMv7 Thumb2) for both arches.
Clang will support -mrestrict-it and -mno-restrict-it, which is
compatible with GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
humb2ITBlockPass.cpp
|
| 59e648e3c8966e0678902a2994558f25c8573ce4 |
12-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).
(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2ca352d027da26194deaa77ebc486df159e51c28 |
12-Nov-2013 |
Bradley Smith <bradley.smith@arm.com> |
[ARM] Add support for FP_HP_extension build attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194470 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| ef572e31e210a03c0669e3ed2ed7cf2d789f8599 |
11-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMRegisterInfo.td
|
| 1343fbcb7e00b12b63ae90b8c211c2d42416a74f |
09-Nov-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove some unnecessary temporary strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194335 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f008d3465ea57849801cc6c71e64625f4a6d4bc4 |
09-Nov-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
[arm] Refine ARMBuildAttrs.h.
This commit cleans up some comments in ARMBuildAttrs.h.
Besides, this commit fixes an error related to AllowWMMXv1
and AllowWMMXv2 (although they are not used currently.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194327 91177308-0d34-0410-b5e6-96231b3b80d8
RMBuildAttrs.h
|
| 323ac85d6ad7ba5d9593d8e151d879bd91d82e08 |
08-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fold prologue/epilogue sp updates into push/pop for code size
ARM prologues usually look like:
push {r7, lr}
sub sp, sp, #4
If code size is extremely important, this can be optimised to the single
instruction:
push {r6, r7, lr}
where we don't actually care about the contents of r6, but pushing it subtracts
4 from sp as a side effect.
This should implement such a conversion, predicated on the "minsize" function
attribute (-Oz) since I've yet to find any code it actually makes faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194264 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 2b01682aa7b9509e9fa1865ebed3d0a7928f5b7a |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fa840ba402806d978c18401c6bea1c808607d944 |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 1b91231347c00bf1be46bdd5b27ae8c45fdc0d0c |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f635ab8eabb06a41fa791d897ebf32eb338688a0 |
05-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e53abc20724ddde4e91467671328b531361a734f |
05-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove unnecessary state-tracking during frame lowering.
ResolveFrameIndex had what appeared to be a very nasty hack for when the
frame-index referred to a callee-saved register. In this case it "adjusted" the
offset so that the address was correct if (and only if) the MachineInstr
immediately followed the respective push.
This "worked" for all forms of GPR & DPR but was only ever used to set the
frame pointer itself, and once this was put in a more sensible location the
entire state-tracking machinery it relied on became redundant. So I stripped
it.
The only wrinkle is that "add r7, sp, #0" might theoretically be slower (need
an actual ALU slot) compared to "mov r7, sp" so I added a micro-optimisation
that also makes emitARMRegUpdate and emitT2RegUpdate also work when NumBytes ==
0.
No test changes since there shouldn't be any functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194025 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMFrameLowering.cpp
RMMachineFunctionInfo.h
humb1FrameLowering.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| cb01efb7988d119d6e2aedab1740695aa6a9cc0c |
03-Nov-2013 |
Bob Wilson <bob.wilson@apple.com> |
Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.
rdar://12856873
Patch by Evan Cheng, with a fix for rdar://13209539 by Tilmann Scheller
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193942 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.cpp
RMSubtarget.h
|
| 6186de5c54b580414b2d162e0f335b62b3d9812c |
01-Nov-2013 |
Bradley Smith <bradley.smith@arm.com> |
[ARM] Add Virtualization subtarget feature and more build attributes in this area
Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.
Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMBuildAttrs.h
RMSubtarget.cpp
RMSubtarget.h
|
| 479a2de32a994b1902869b88e56253936d943531 |
01-Nov-2013 |
Bradley Smith <bradley.smith@arm.com> |
[ARM] Fix Tag_ABI_HardFP_use build attribute
Fix Tag_ABI_HardFP_use build attribute to handle single precision FP,
replace deprecated Tag_ABI_HardFP_use value of 3 with 0 and also add
some tests for Tag_ABI_VFP_args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193856 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 0e536ee4cae5f7359e8a8db99edadc39a5c12132 |
31-Oct-2013 |
Jim Grosbach <grosbach@apple.com> |
Legalize: Improve legalization of long vector extends.
When an extend more than doubles the size of the elements (e.g., a zext
from v16i8 to v16i32), the normal legalization method of splitting the
vectors will run into problems as by the time the destination vector is
legal, the source vector is illegal. The end result is the operation
often becoming scalarized, with the typical horrible performance. For
example, on x86_64, the simple input of:
define void @bar(<16 x i8> %a, <16 x i32>* %p) nounwind {
%tmp = zext <16 x i8> %a to <16 x i32>
store <16 x i32> %tmp, <16 x i32>*%p
ret void
}
Generates:
.section __TEXT,__text,regular,pure_instructions
.section __TEXT,__const
.align 5
LCPI0_0:
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.section __TEXT,__text,regular,pure_instructions
.globl _bar
.align 4, 0x90
_bar:
vpunpckhbw %xmm0, %xmm0, %xmm1
vpunpckhwd %xmm0, %xmm1, %xmm2
vpmovzxwd %xmm1, %xmm1
vinsertf128 $1, %xmm2, %ymm1, %ymm1
vmovaps LCPI0_0(%rip), %ymm2
vandps %ymm2, %ymm1, %ymm1
vpmovzxbw %xmm0, %xmm3
vpunpckhwd %xmm0, %xmm3, %xmm3
vpmovzxbd %xmm0, %xmm0
vinsertf128 $1, %xmm3, %ymm0, %ymm0
vandps %ymm2, %ymm0, %ymm0
vmovaps %ymm0, (%rdi)
vmovaps %ymm1, 32(%rdi)
vzeroupper
ret
So instead we can check if there are legal types that enable us to split
more cleverly when the input vector is already legal such that we don't
turn it into an illegal type. If the extend is such that it's more than
doubling the size of the input we check if
- the number of vector elements is even,
- the source type is legal,
- the type of a split source is illegal,
- the type of an extended (by doubling element size) source is legal, and
- the type of that extended source when split is legal.
If the conditions are met, instead of just splitting both the
destination and the source types, we create an extend that only goes up
one "step" (doubling the element width), and the continue legalizing the
rest of the operation normally. The result is that this operates as a
new, more effecient, termination condition for the loop of "split the
operation until the destination type is legal."
With this change, the above example now compiles to:
_bar:
vpxor %xmm1, %xmm1, %xmm1
vpunpcklbw %xmm1, %xmm0, %xmm2
vpunpckhwd %xmm1, %xmm2, %xmm3
vpunpcklwd %xmm1, %xmm2, %xmm2
vinsertf128 $1, %xmm3, %ymm2, %ymm2
vpunpckhbw %xmm1, %xmm0, %xmm0
vpunpckhwd %xmm1, %xmm0, %xmm3
vpunpcklwd %xmm1, %xmm0, %xmm0
vinsertf128 $1, %xmm3, %ymm0, %ymm0
vmovaps %ymm0, 32(%rdi)
vmovaps %ymm2, (%rdi)
vzeroupper
ret
This generalizes a custom lowering that was added a while back to the
ARM backend. That lowering is no longer necessary, and is removed. The
testcases for it, however, provide excellent ARM tests for this change
and so remain.
rdar://14735100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193727 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3f04b5068619ca0411521c9871f4bfc6b04f951f |
30-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] NEON instructions were erroneously decoded from certain invalid encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| d1ea5928ddbd38e99507f7f18df8ec8a865c7799 |
29-Oct-2013 |
Manman Ren <manman.ren@gmail.com> |
Struct byval cleanup: add helper functions to reduce code duplication.
Helper functions are added:
emitPostLd: emit a post-increment load operation with given size.
emitPostSt: emit a post-increment store operation with given size.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193656 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 93cf0939f95b3d580d9c05375a7c84164e1ba72e |
29-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move getSymbol to TargetLoweringObjectFile.
This allows constructing a Mangler with just a TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193630 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
|
| ffc7dca885151ed42642c2d6733e8db75d276621 |
29-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a helper getSymbol to AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMCInstLower.cpp
|
| 57bca7b26ec916ca1b74b1408608a6c69a1aa422 |
29-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Make sure HasCRC is initialized to false in Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193624 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 47c6d17b1cce85ba30471b2270419e35ba3d5653 |
29-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.
Differential Revision: http://llvm-reviews.chandlerc.com/D2036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| c04d241d13820b33224b5cbd89a427fc08e5d1d9 |
29-Oct-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Unaligned vectorized double stores are expensive
Updated a test case that assumed that <2 x double> would vectorize to use
<4 x float>.
radar://15338229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193574 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 7e8cebf22d170769b0bf0c2a69309faa0e36ac4c |
29-Oct-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Account for zero cost scalar SROA instructions
By vectorizing a series of srl, or, ... instructions we have obfuscated the
intention so much that the backend does not know how to fold this code away.
radar://15336950
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193573 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 3d478aee8e2480661cb0d98b10da8ad2ebf59fcf |
28-Oct-2013 |
Lang Hames <lhames@gmail.com> |
Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.
When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.
Fixes <rdar://problem/15155975>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 23125d02d929758e1b0dbb30b13f1deff7a5ea4b |
28-Oct-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMBuildAttrs.h
RMFPUName.def
RMFPUName.h
smParser/ARMAsmParser.cpp
CTargetDesc/ARMELFStreamer.cpp
|
| c8f4e5db29270fc7ed164af973ece7ba5921539b |
25-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow .thumb_func to be separated from symbol definition
When assembling, a .thumb_func directive is supposed to be applicable to the
next symbol definition, even if there are intervening directives. We were
racing ahead to try and find it, and this commit should fix the issue.
Patch by Gabor Ballabas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193403 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 214c37d1816b62a25525282817f7088a1e2ed1dc |
25-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: don't expand atomicrmw inline on Cortex-M0
There's a barrier instruction so that should still be used, but most actual
atomic operations are going to need a platform decision on the correct
behaviour (either nop if single-threaded or OS-support otherwise).
rdar://problem/15287210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193399 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.h
|
| 3115047182dfa0e4692901e897a58e5be3329423 |
25-Oct-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tweak usage of '*vfp' compiler_rt functions.
Only use them if the subtarget has ARM mode, as these routines are implemented
as ARM code.
rdar://15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e8d84d8936dc8fb4fc260b0601b37e93679de421 |
24-Oct-2013 |
David Peixotto <dpeixott@codeaurora.org> |
Remove class abstraction from ARM struct byval lowering
This commit changes the struct byval lowering for arm to use inline
checks for the subtarget instead of a class abstraction to represent
the differences. The class abstraction was judged to be too much
code for this task.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193357 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 44edc227c743052bd58e73a5e1402fa68ed728f0 |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.
No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.
rdar://problem/15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrVFP.td
|
| e2dee623e0eeb12c6e22add0e55139693ffb2dca |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193342 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| eac623a18b1e7ad9e5a7da76a323039450b7d7ce |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.
This tidies up the obvious VFP and NEON cases I found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| 6c0138e5fca970b126a76ee9252af462760c99c0 |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Use non-VFP softcalls on embedded Darwinish targets
The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1
code to make use of VFP instructions by switching back to ARM mode, they make
no sense for M-class processors which don't even have an ARM mode.
Given that justification, in practice this is a platform ABI decision so the
actual check is based on that rather than CPU features.
rdar://problem/15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cdd776d13f799da1aff4b2c9c58a236bee74ea2e |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.
With some vigorous hand-waving in the error message both problems can be
fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193322 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b161955ffbda5ccb5293e0c76ef982acb6ec6661 |
23-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
Make ARM hint ranges consistent, and add tests for these ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 01b0e94bb731310e72f66977e4b57cd3f3280ba4 |
22-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.
For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 5b46ad4faf3216b4faaf30fa3a32f0af06f1ae36 |
22-Oct-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb2 copy for GPRPair needs to use thumb instructions.
Use tMOVr instead of plain MOVr.
rdar://15193017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193139 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 6c28682963e96699e7e0ab15282319c152bd6373 |
22-Oct-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Clean up copyPhysReg() a bit.
No functional change, just cleaning things up for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193138 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 22cfec4c01516481090f22117ff555e166734661 |
18-Oct-2013 |
Richard Barton <richard.barton@arm.com> |
Pure refactoring change.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192977 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 485333df7157d6e8681d910d85b271b0bc96b48e |
18-Oct-2013 |
Richard Barton <richard.barton@arm.com> |
Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
humb2InstrInfo.cpp
|
| b1c480900bdc6486624a476b6ae25cb02a3b6276 |
18-Oct-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192963 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
|
| 7014d274e4adb51cbb20201ab002057395b7dcaa |
17-Oct-2013 |
David Peixotto <dpeixott@codeaurora.org> |
17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets
This commit implements the correct lowering of the
COPY_STRUCT_BYVAL_I32 pseudo-instruction for thumb1 targets.
Previously, the lowering of COPY_STRUCT_BYVAL_I32 generated the
post-increment forms of ldr/ldrh/ldrb instructions. Thumb1 does not
have the post-increment form of these instructions so the generated
assembly contained invalid instructions.
Passing the generated assembly to gcc caused it to complain with an
error like this:
Error: cannot honor width suffix -- `ldrb r3,[r0],#1'
and the integrated assembler would generate an object file with an
invalid instruction encoding.
This commit contains a small test case that demonstrates the problem
with thumb1 targets as well as an expanded test case that more
throughly tests the lowering of byval struct passing for arm,
thumb1, and thumb2 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192916 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6483751a362948bb83940e55f63226c27c472bc0 |
17-Oct-2013 |
David Peixotto <dpeixott@codeaurora.org> |
Refactor lowering for COPY_STRUCT_BYVAL_I32
This commit refactors the lowering of the COPY_STRUCT_BYVAL_I32
pseudo-instruction in the ARM backend. We introduce a new helper
class that encapsulates all of the operations needed during the
lowering. The operations are implemented for each subtarget in
different subclasses. Currently only arm and thumb2 subtargets are
supported.
This refactoring was done to easily implement support for thumb1
subtargets. This initial patch does not add support for thumb1, but
is only a refactoring. A follow on patch will implement the support
for thumb1 subtargets.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192915 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 06957f43f6051901590b318c10b1a0a5c7f898d4 |
16-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCAsmInfoELF class and factor some code into it.
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCAsmInfo.cpp
CTargetDesc/ARMMCAsmInfo.h
|
| 05ac87f864a34bff0e6f2a029d48eab3e4cb464a |
15-Oct-2013 |
Manman Ren <manman.ren@gmail.com> |
Struct byval: fix a copy-paste error for thumb2.
PR17309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192730 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0d1e2aebe641fc26bba5d895bbcadcac6f23aaec |
14-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Add Cortex-A57 support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 7220572e74844aa37b1b492ef67a8c1b403a254f |
14-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| fc3dc102e0bef8ecb7cd13ceab77dc130175f792 |
11-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Fix FP ABI attributes with no VFP enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8ccf2b3c9e0f70220c88f3328ddebebd7866f92c |
10-Oct-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192350 91177308-0d34-0410-b5e6-96231b3b80d8
RMFeatures.h
|
| acd79ce0ada50c7a437757d188f410d67030fbb9 |
10-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: correct liveness flags during ARMLoadStoreOpt
When we had a sequence like:
s1 = VLDRS [r0, 1], Q0<imp-def>
s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.
This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.
rdar://problem/15124449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3353c592de08c4a7b7b282714b8044d7cfc4c6ad |
09-Oct-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Flip the ownership of MCStreamer and MCTargetStreamer.
MCStreamer now owns the target streamer. This prevents leaking the target
streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192303 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 320296a4cfe414ce59f406b8a5ce15272f563103 |
08-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.
The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.
I will send an email to llvmdev with instructions on how to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmParser.cpp
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| fb92f4645968724d2095ef95a7034d7e20d39b3f |
07-Oct-2013 |
Manman Ren <manman.ren@gmail.com> |
Struct byval: use the correct alignment for loads generated to load
from struct byval to registers.
We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.
The fix is to pass the alignment of the struct byval.
rdar://problem/15144402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192126 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ca7b2d08d7b918e5e8e921a837623af962b27d00 |
07-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Improve build attributes emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMBuildAttrs.h
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| ef8c4ca252f1289ca8d0a1e6cfd96ca17fe3c5a8 |
07-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove getEHExceptionRegister and getEHHandlerRegister.
They haven't been used for a long time. Patch by MathOnNapkins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 |
07-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.
rdar://problem/15144406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb.td
RMSubtarget.h
smParser/ARMAsmParser.cpp
|
| 5e195a4c8d8cd4498ab7e0aa16a3b6f273daf457 |
05-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.
The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.
It was never the intention that targets would keep doing things like
if (hasRawTextSupport())
Set flags in one way.
else
Set flags in another way.
When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.
This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.
The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.
I will also try to implement a target streamer interface, so that we can
move this out of the common code.
In summary, for any new work, two rules of the thumb are
* Don't use "llc -filetype=obj" in tests.
* Don't add calls to hasRawTextSupport.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmParser.cpp
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMELFStreamer.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| d1bd8d904c5adbe14f700be02f1e6479b5a6d04b |
04-Oct-2013 |
Matthias Braun <matze@braunis.de> |
ARM: optimizeSelect has to consider the previous register class
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191963 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 4e54f41d6ce6b5a502d2f8496f1e8360ed953b7d |
04-Oct-2013 |
Matthias Braun <matze@braunis.de> |
ARM: do not add a regmask for TAILJUMPs
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e1bde51d63f888e0011dfd3b9cfd78b1736d0b5d |
04-Oct-2013 |
Matthias Braun <matze@braunis.de> |
ARM: preserve undef flag in pseudo instruction expanders
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 6eef361b73b457896b310d411251aedd5e72476a |
03-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMFeatures.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| bba9390fc6c0d536172c6bb4a9c93db557c1aff4 |
01-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/14207019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCallingConv.td
RMExpandPseudoInsts.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 441aeddd56d000ff77460586961a523e41edd205 |
01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Remove an unused function from the disassembler.
Pointed out by Joerg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191749 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| d1311ac171f9cb90cab4906a6c0e091b6b65b862 |
01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| a64fa348df0f5d80109ae244b03142b3c4f9a981 |
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Clean up ARMAsmParser::validateInstruction().
Fix some LLVM Coding Standards violations.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191686 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9724873c317d2b170cfea87cdf2a402fcd7c6c7d |
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
See ARM ARM A8.8.72.
Violating this constraint results in unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7373265e1a2042032dfa48f1d0accca4e5b68fe1 |
30-Sep-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Swift model: Fix uop description on some writes
Those writes really need two/three uops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191677 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| d42730dc712026cbfb1322a979e0ac72cd31a19e |
30-Sep-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
IfConverter: Use TargetSchedule for instruction latencies
For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).
Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.
ATTENTION: Out of tree targets!
(I will also send out an email later to LLVMDev)
This means, if your target implements
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost);
and returns a value for "PredCost", you now also need to implement
unsigned getPredictationCost(const MachineInstr *MI);
(if your target uses the IfConversion.cpp pass)
radar://15077010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 3f4f420ab7acb10221ba971543a7eed5489fb626 |
28-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
humb1RegisterInfo.cpp
|
| cca114611945332852094fcadfaa4ffbd012bfb3 |
27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f1e7cba627ded914a3d40c52ad7d85ac6bf3a837 |
27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191505 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6b968eccd79409b0986f394fa597101cf79433d8 |
27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!
As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.
If this constraint is not met the result of executing the instruction will be unpredictable.
Fixes rdar://14479780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 82f36241c2484a72ba11b7ae5af3f485504a7b6e |
26-Sep-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191441 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 268c743a3ba44ada364938bc5ff9b1be219df54f |
26-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
CTargetDesc/ARMMCTargetDesc.cpp
|
| 541681c8485c18b564970c80180a798b2c1663e8 |
26-Sep-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Fix PR 17368: disable vector mul distribution for square of add/sub for ARM
Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
x = a + b (add)
y = a * x (mul)
z = y + b * y (mla)
Without distribution:
x = a + b (add)
z = x * x (mul)
This patch checks if a mul is a square of add/sub. If yes, skip
distribution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dfca6eec3171802d6fcb091da01604ef4420fb3b |
25-Sep-2013 |
Andrew Trick <atrick@apple.com> |
CriticalAntiDepBreaker is no longer needed for armv7 scheduling.
This is being disabled because it is no longer needed for
performance. It is only used by postRAscheduler which is also planned
for removal, and it is implemented with an out-dated view of register
liveness. It consideres aliases instead of register units, assumes
valid kill flags, and assumes implicit uses on partial register
defs. Kill flags and implicit operands are error prone and impossible
to verify. We should gradually eliminate dependence on them in the
postRA phases.
Targets that still benefit from this should move to the MI
scheduler. If that doesn't solve the problem, then we should add a
hook to regalloc to optimize reload placement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 0f22c134be40a337b30e30bdafb9e8b6880dea1e |
23-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Split A/R class into separate subtarget features.
Patch by Bradley Smith.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5cc319a42a914b24b164a94d9a563c728a7a4026 |
20-Sep-2013 |
Richard Mitton <richard@codersnotes.com> |
Added support for generate DWARF .debug_aranges sections automatically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191052 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 5df37dab763ce377095389c4ea1cff88db369954 |
19-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMSubtarget.cpp
RMSubtarget.h
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| a4d46d7fc6431ec3576839f11cb61862b784cb3e |
18-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CRC instructions.
Patch by Bradley Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| dc0de80f24a83336cb26dcb9ed1fa030142a504d |
17-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
CTargetDesc/ARMMCTargetDesc.cpp
|
| 9bc7603750926c15648dae0d31a5451861a0d11e |
16-Sep-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Deduplicate ConstantPoolValues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190779 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 94ee55d4b39d6506cf4e0f4e4b1c0b7fbbfeaed5 |
16-Sep-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace some unnecessary vector copies with references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| d9d6e6d59159160299a51fe5010a940db27ae89b |
14-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Fix spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190749 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2a9af9f18eac90b0de739b6ceddf6c2209086303 |
13-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMBuildAttrs.h
RMISelLowering.cpp
RMInstrInfo.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 8312905790f2250d7c807b4c153be7d64ab22572 |
13-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Emit the proper .fpu directive.
Patch by Bradley Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190683 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 715d98d657491b3fb8ea0e14643e9801b2f9628c |
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 1039e106d095979b3707bb27cfa765cd2c0f3b54 |
10-Sep-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Use the PICADD opcode calculated.
We were figuring out whether to use tPICADD or PICADD, then just using
tPICADD unconditionally anyway. Oops.
A testcase from someone familiar enough with ELF to produce one would
be appreciated. The existing PIC testcase correctly verifies the .s
generated, but that doesn't catch this bug, which only showed up in
direct-to-object mode.
http://llvm.org/bugs/show_bug.cgi?id=17180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190417 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 28823ec4088e216f455278ba42f99f79d0d71969 |
10-Sep-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Remove unused private member in ARMAsmPrinter.cpp.
This commit removes the unused "AttributeItem" from
ObjectAttributeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190412 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b57d99694b87326a2eea26d76becf67bf5784b49 |
09-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.
IT blocks can only be one instruction lonf, and can only contain a subset of
the 16 instructions.
Patch by Artyom Skrobov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190309 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMFastISel.cpp
RMTargetMachine.cpp
humb2ITBlockPass.cpp
|
| c3cee57f7d20f69a84fd88464ed8cf050e63c7ad |
09-Sep-2013 |
Bill Wendling <isanbard@gmail.com> |
Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.
Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.
<rdar://problem/13623355>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| 4897151df698197f0eb5c4085545312dbb20c94d |
05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMBaseInfo.h
|
| b5523ce1bb50e86942ad5273e3a89872c4d26b73 |
05-Sep-2013 |
Richard Barton <richard.barton@arm.com> |
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 8f3d54d057007552d0abc37c87a50ef34a7ab9ef |
05-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMRegisterInfo.td
humb2InstrInfo.cpp
|
| 10b5086e6e945b830ff909821240eff5c4a42bfc |
05-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.
Patch by Daniel Stewart!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMRegisterInfo.td
humb2InstrInfo.cpp
|
| 1bfa80359edc004bc8a91999de7c8e16708d2206 |
04-Sep-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.
I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).
PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189972 91177308-0d34-0410-b5e6-96231b3b80d8
15SDOptimizer.cpp
|
| 3d476a80e9da0136681f69247abfbd6de986c137 |
04-Sep-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Swift: Only build vldm/vstm with q register aligned register lists
Unaligned vldm/vstm need more uops and therefore are slower in general on swift.
radar://14522102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189961 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 87b120690b64f41c5b2367653e542ae2cfaa27ba |
04-Sep-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189958 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| b81d7a89129ff1621fa609144b400df3500542d6 |
03-Sep-2013 |
Jim Grosbach <grosbach@apple.com> |
Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
This reverts commit r189648.
Fixes for the previously failing clang-side arm_neon_intrinsics test
cases will be checked in separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189841 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 195dd8a1ce38970e3463ee1425647280373b60a7 |
02-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.
Test cases adjusted accordingly.
This fixes rdar://14871821.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189766 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 5bed440eb13b4104b64fa9c557954f335aac2aab |
02-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Revert 189756 for now, it doesn't match what rdar://14871821 really wants.
What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189763 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 024e76b69bc46a20e96eba22f2655d249c495d00 |
02-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Default to Swift when compiling for iOS 6 or later.
Test cases adjusted accordingly.
This fixes rdar://14871821.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189756 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 5510728d28bb1ee04abc32da3d21b7df12948053 |
01-Sep-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| 5de35bc7303ac36714e9e8ad42987c86cabf9c74 |
30-Aug-2013 |
Michael Gottesman <mgottesman@apple.com> |
Revert "ARM: Improve pattern for isel mul of vector by scalar."
This reverts commit r189619.
The commit was breaking the arm_neon_intrinsic test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189648 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 88acef0b8e93d065aa4de164422ce4c546a7cd5f |
30-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Improve pattern for isel mul of vector by scalar.
In addition to recognizing when the multiply's second argument is
coming from an explicit VDUPLANE, also look for a plain scalar
f32 reference and reference it via the corresponding vector
lane.
rdar://14870054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189619 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 441c557708b5dbe91f1799baf790ad418c23ea70 |
29-Aug-2013 |
Cameron Esfahani <dirty@apple.com> |
Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| b2e5453821ef27306036a9961818cf530a3ca8cb |
28-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8]
Fix a few things in one swoop.
# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 22266c1d4817fc30355a90bb264ede08482bba3a |
28-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Use "dmb sy" for barriers on M-class CPUs
The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189483 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bafb5f8d9f415340d9035ee9430f9480da9a50fb |
28-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add a missing IsThumb to t2LDAEXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189482 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d3128a4a5a8531a256a224422d7da178d18459eb |
28-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.
Clang is now generating cleaner IR, so this removes the old variants which
should be completely unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189481 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c85bb78714e8e05fb3022148320ea685d7f98d60 |
28-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add patterns for vqdmlal with separate vqdmull and vqadds
The vqdmlal and vqdmlls instructions are really just a fused pair consisting of
a vqdmull.sN and a vqadd.sN. This adds patterns to LLVM so that we can switch
Clang's CodeGen over to generating these instead of the special vqdmlal
intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189480 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0b90c6223d9c49b5e0dc4bf4e53796b0714d7b80 |
27-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add MC support for the new load/store acquire/release instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| dcfa0f7a408e54f15f0237daf2336df852053c6b |
27-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| c59efb626a7a11ec661981e96ba09bba0497b731 |
27-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add natural patterns for vaddhl and vsubhl.
These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189335 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f69a29b23a116a3520f185054290c445abf9aa62 |
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."
This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189321 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| 9c3dd1b0d1e96ef408b68da3b06c6ebd6c943601 |
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189315 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| 383a810b129aa5120d6a7f6e88e141ec4a45f61b |
26-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e3dad19e0de5c639886055c09da1f4faaa8556f9 |
26-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: FastISel verifier error cleanup.
Constant pool and global value reference instructions need more
restricted register classes than plain GPR.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189270 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bb4066123d91c0347cb6333caca527d1a979e703 |
26-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fix ELF global base reg intialization.
The create machine code wasn't properly in SSA, which the machine verifier
properly complains about. Now that fast-isel is closer to verifier clean,
errors like this show up more clearly.
Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb
mode functions, which is obviously wrong. Fix that along the way.
Test case is part of the following commit which will finish making an
additional fast-isel test verifier clean an enable it for the
regression test suite. This commit is separate since its not just
a verifier cleanup, but an actual correctness issue.
rdar://12594152 (for the fast-isel verifier aspects)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189269 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 6cbb39e556c94ef47a8e02e3a4bb87eb91df5aa3 |
23-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Fix another ARM FastISel -verify-machineinstrs issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189109 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a0b2d332c114571716746ba90c815cfb6f68d4ab |
23-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CodeGen for VMAXNM/VMINNM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrVFP.td
|
| 287c84a0b45cc826b1200f4cf4be3547d2fcd69c |
23-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: make sure ARM-mode pseudo-inst requires IsARM
I'd forgotten that "Requires" blocks override rather than add to the
constraints, so my pseudo-instruction was being selected in Thumb mode leading
to nonsense instructions.
rdar://problem/14817358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 35eab1db2f21aee9678fe946a5d983a67285e7e4 |
22-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CodeGen support for VSEL.
This uses the ARMcmov pattern that Tim cleaned up in r188995.
Thanks to Simon Tatham for his floating point help!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrVFP.td
|
| 5f268555b967fccbfab6e7b69305d74006116927 |
22-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix ARM vcvt encoding when the number of fractional bits is zero.
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions.
This patch adds the necessary instruction aliases to achieve this behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| bad8d4ca599024de8fdc6255a4b73bb294f49239 |
22-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7ddda4704cdb24163591857e8d08614463cec335 |
22-Aug-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix ARM FastISel PIC function call.
The function call to external function should come with PLT relocation
type if the PIC relocation model is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189002 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 |
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.
TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| bccc6f89b7a15abda5593a30c101ae85d1dc3b77 |
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: respect tied 64-bit inlineasm operands when printing
The code for 'Q' and 'R' operand modifiers needs to look through tied
operands to discover the register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188990 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| e2a48fbd9d1ec8bebb5b10cf8770d716f8bdda28 |
22-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: R9 is not safe to use for tcGPR.
Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.
rdar://14793425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188967 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 1a9f21abac47dcea0c62341b0ee4fd35481350b8 |
21-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 8b262e5ab8cbeb8f6f61d92b20d886675966fe34 |
20-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.
rdar://14779513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 32c2bfda77d54ca6ad8e08d2de03daa7ae432305 |
20-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188773 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 756e89c8c2a3c30ce3a73ed13724aad1b41a5608 |
19-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction.
All the patch does is adjust a register constraint on an instruction alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 57cf3500a3dec411500737b91e1a3970be488337 |
18-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: make sure we keep inline asm operands tied.
When patching inlineasm nodes to use GPRPair for 64-bit values, we
were dropping the information that two operands were tied, which
effectively broke the live-interval of vregs affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188643 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 62c7749437a74a4e0cf28edff865bd82f2b9aecc |
17-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Properly constrain comparison fastisel register classes.
Ongoing 'make the verifier happy' improvements to ARM fast-isel.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188595 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 785bd598529fa12d0a0f577c4d63c4ab371bc559 |
17-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fast-isel register class constrain for extends.
Properly constrain the operand register class for instructions used
in [sz]ext expansion. Update more tests to use the verifier now that
we're getting the register classes correct.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188594 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b49860ef030cb2dba0386278ee8737eecc4e7272 |
17-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fix more fast-isel verifier failures.
Teach the generic instruction selection helper functions to constrain
the register classes of their input operands. For non-physical register
references, the generic code needs to be careful not to mess that up
when replacing references to result registers. As the comment indicates
for MachineRegisterInfo::replaceRegWith(), it's important to call
constrainRegClass() first.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188593 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0673379712100110c213a0e7610b73b6c706e83d |
17-Aug-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Clean up fast-isel machine verifier errors.
Lots of machine verifier errors result from using a plain GPR regclass
for incoming argument copies. A more restrictive rGPR class is more
appropriate since it more accurately represents what's happening, plus
it lines up better with isel later on so the verifier is happier.
Reduces the number of ARM fast-isel tests not running with the verifier
enabled by over half.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188592 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 671aea08f8dfb09a0191e7b9e266c2884efd3252 |
16-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
When initializing the PIC global base register on ARM/ELF add pc to fix the address.
This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches
what GCC and SDag do for PIC but may not cover all of the many flavors of PIC
that exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188551 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| e97fc44045732de9fc4715241013f9238ec007dc |
16-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for
negative zero. This fixes parsing and encoding so that #-0
is correctly processed. The parser represents #-0 as INT32_MIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 8b36f9e4314ac4d786d2d4fd5fa9e7858487ee9e |
16-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix Thumb2 aliasing complementary instructions taking modified immediates
There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.
For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented.
The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the
complementary immediate is encodable.
The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand
rather than the ARM one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 14c41370e36068ae25c871d5bd8f99f92bbb7d45 |
15-Aug-2013 |
Renato Golin <renato.golin@linaro.org> |
make arm-use-movt available for all ARM
Before this patch this flag is IOS specific, but is also
useful for bare project like bootloaders / kernels etc,
since movw / movt prevents simple relocation. Therefore
make this flag more commonly available.
note: this patch depends on a similiar rename in clang
Patch by Jeroen Hofstee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188487 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 24adc8f60f0a39e45363eef5392fe1a7e27bd12f |
15-Aug-2013 |
Renato Golin <renato.golin@linaro.org> |
make arm-reserve-r9 available for all ARM
r9 is defined as a platform-specific register in the ARM EABI.
It can be reserved for a special purpose or be used as a general
purpose register. Add support for reserving r9 for all ARM, while
leaving the IOS usage unchanged.
Patch by Jeroen Hofstee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188485 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 428715d4e120e6ef6fc898665607a92f3dd02709 |
15-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 5a0910b34959fa8e0b5a49908f51a15bc3a48069 |
15-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188441 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dd34dc99fdf66edc52b5fc2ddf8132ebaa134aee |
14-Aug-2013 |
Renato Golin <renato.golin@linaro.org> |
Let t2LDRBi8 and t2LDRBi12 have same Base Pointer
When determining if two different loads are from the same base address,
this patch allows one load to use a t2LDRi8 address mode and another to
use a t2LDRi12 address mode. The current implementation is very
conservative and this allows the case of differing Thumb2 byte loads to
be considered. Allowing these differing modes instead of forcing the exact
same opcode is useful for situations where one opcodes loads from a base
address+1 and a second opcode loads for a base address-1.
Patch by Daniel Stewart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188385 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 3f87f2510c0d84fe092ac311a0e25a5e2f7aa3ac |
13-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
ARMv8: SWP and SWPB are obsoleted on ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ea8ddd86b1e364a799e57fc0ac468a9c4a8f8bcf |
13-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix signed overflow in when computing encodings for ADR instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| fc6434a73d053c3e1d9c79034a267ae1434483ad |
09-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a overload to CostTable which allows it to infer the size of the table.
Use it to avoid repeating ourselves too often. Also store MVT::SimpleValueType
in the TTI tables so they can be statically initialized, MVT's constructors
create bloated initialization code otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188095 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 04b03fac11f10c92cf7ce63ba2f548a42ee2c448 |
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}
Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}
Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e921f323533ee751b3fa34bd00d10fa72096ffd3 |
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.
Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.
Due to this, for any mnemonic there are really 4 encodings to choose for.
The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that
order is governed by the lexicographical ordering of the names of operand
classes...
To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| cee35382331d792ed9354bb7fe0f3e10b09f46a3 |
08-Aug-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Remove the now redundant FeatureFP16 from the Cortex-A15 feature list. It was made redundant when FeatureVFP4 was added which implies FP16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187985 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 868bed99674cf19e5cb475945f3067f0f4cc421e |
08-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
The name "tCDP" isn't used anywhere else in the source code, so renaming it for consistency doesn't cause any problems.
This is the only Thumb2 instruction defined with "t" prefix; all other Thumb2 instructions have "t2" prefix (e.g. "t2CDP2" which is defined immediately afterwards).
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187973 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fab2daa4a1127ecb217abe2b07c1769122b6fee1 |
08-Aug-2013 |
Stephen Hines <srhines@google.com> |
Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807
Conflicts:
lib/Archive/ArchiveReader.cpp
lib/Support/Unix/PathV2.inc
Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
|
| 4f7092176c3d3eaae0ea7af26aec2d77b3e4035f |
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| 4a378b95aa0f24ba461e512608b8aaeaa803996f |
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMRegisterInfo.td
|
| 8775a51d94b277ca6ebe12a1d20bfc2bc5a53960 |
06-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement allowTruncateForTailCall
Now that it's in place, it seems silly not to let ARM make use of the extra
tail call opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187795 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 8e1d64666f493e4994b26a390bec1290a5d94b96 |
06-Aug-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 527692a59442345afc662488c68d4f9d9e468da9 |
04-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARMAsmParser: Plug a leak.
Using an object to do the cleanup may look like overkill, but it's safer and nicer than putting deletes everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187696 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e7bc73b8d127e0e17ba6ac7ceb7462134c730f68 |
02-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a missing 'return' statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187671 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 787fdb86a71c5108c231b3bbbb7d3fea3ce4bb8c |
02-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187666 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 38ffffeebc22ca8ea67456193672109a3adc11b6 |
02-Aug-2013 |
Renato Golin <renato.golin@linaro.org> |
Fixes ARM LNT bot from SLP change in O3
This patch fixes the multiple breakages on ARM test-suite after the SLP
vectorizer was introduced by default on O3. The problem was an illegal
vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple.
The guard protects this code from breaking (cause of the problems) but
doesn't fix the issue that is generating the odd vector in the first
place, which also needs to be investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187658 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 61fc8d670f1e991804c2ab753e567981e60962cb |
01-Aug-2013 |
Bill Wendling <isanbard@gmail.com> |
Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e38070fc32818a6e412dafbb8b3807b413d0819e |
31-Jul-2013 |
Kevin Enderby <enderby@apple.com> |
Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match. Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.
rdar://14214063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| f7f22a64df583df9da6bdd74e2f928568276f837 |
30-Jul-2013 |
Saleem Abdulrasool <compnerd@compnerd.org> |
[ARM] check bitwidth in PerformORCombine
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.
Split the check of the value of the second operands to the ands. Move the cast
and variable declaration slightly higher to make it slightly easier to follow.
Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fd79485dfa4fee67467299720efac2d0c21d846c |
29-Jul-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187349 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMTargetMachine.cpp
|
| 214de30d9d3739bb384188720aa6c389edcf89dc |
27-Jul-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Create a constant pool symbol for the GOT in the ARMCGBR the same way we
do in the SDag when lowering references to the GOT: use
ARMConstantPoolSymbol rather than creating a dummy global variable. The
computation of the alignment still feels weird (it uses IR types and
datalayout) but it preserves the exact previous behavior. This change
fixes the memory leak of the global variable detected on the valgrind
leak checking bot.
Thanks to Benjamin Kramer for pointing me at ARMConstantPoolSymbol to
handle this use case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187303 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 6c54b3dfb4ac80418a9e9ee11e5cc1702e9694e6 |
27-Jul-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Fix yet another memory leak found by the vg-leak bot. Folks (including
me) should start watching this bot more as its catching lots of bugs.
The fix here is to not construct the global if we aren't going to need
it. That's cheaper anyways, and globals have highly predictable types in
practice. I've added an assert to catch skew between our manual testing
of the type and the actual type just for paranoia's sake.
Note that this pattern is actually fine in most globals because when you
build a global with a module it automatically is moved to be owned by
that module. But here, we're in isel and don't really want to do that.
The solution of not creating a global is simpler anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187302 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 17f99a991f2e270a34c53854ce80acc30754537b |
24-Jul-2013 |
Quentin Colombet <qcolombet@apple.com> |
[ARM][ISel] Improve the lowering of vector loads.
When vectors are built from a single value, the ARM lowering issues a
scalar_to_vector node.
This node is then always morphed into a move from the general purpose unit to
the vector unit.
When the value comes from a load, this can be simplified into a vector load to
the right lane.
This patch changes the lowering of insert_vector_elt to expose a vector
friendly pattern in this situation.
This is a step toward fixing <rdar://problem/14170854>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186999 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 02265382929b0275d7b7b334eab5e2fd34e1b9fe |
22-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:
1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMAsmBackend.cpp
|
| 1c6e6ce10c61f8db656a04af36e2b374c0fe9566 |
22-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove now unneeded custom Asm converters
After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186810 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 7b61a701932d850d2777fafda1fea5ec841d893b |
20-Jul-2013 |
Lang Hames <lhames@gmail.com> |
Refactor AnalyzeBranch on ARM. The previous version did not always analyze
indirect branches correctly. Under some circumstances, this led to the deletion
of basic blocks that were the destination of indirect branches. In that case it
left indirect branches to nowhere in the code.
This patch replaces, and is more general than either of the previous fixes for
indirect-branch-analysis issues, r181161 and r186461.
For other branches (not indirect) this refactor should have *almost* identical
behavior to the previous version. There are some corner cases where this
refactor is able to analyze blocks that the previous version could not (e.g.
this necessitated the update to thumb2-ifcvt2.ll).
<rdar://problem/14464830>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186735 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 55dcefbc4006204c0d2816d5a7c921517c53383c |
19-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a line that got missed off somehow. Sorry about that!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186692 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6fec715a1a662ce3b560f85c710875cfeeb1fb98 |
19-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| cae5d5ea658e05091e66b742b5834f1896ff2f5d |
19-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.
Related to <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| bbcea55b68fad8116c29b3e831c5df398d558569 |
19-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Make sure the instruction alias for PLI uses the right subtarget features.
PLI requires both the Thumb2 and the ARMv7 feature.
Related to <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186620 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4e377d9306f471025415beb7639e0a3e776efa27 |
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Change 'n' to 'N' to keep consistent with other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186576 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 59b3300664d062bf04159eacaeb44d6c729e6a8c |
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add NEON instructions VCVT{A, N, P, M}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 6a3d933e1645d34984f4c7c9e2e4e46d0d15e1b3 |
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add Thumb tests for the ARMv8 FP instructions that I recently added.
Also, fix the namespace for two instructions that I missed previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186572 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| d46bb05e1ae484c491ea85527e45da86e78be658 |
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Remove the extra leading 0 from VMAXNMND.
The N3VDIntnp pattern takes bits<5> and I gave it 6 bits.
Thanks to Jiangning Liu for spotting it!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186568 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 19c14abf1c4ccebfa7d07bdd6ea8462a15c0b749 |
17-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add support for the NEON instructions vmaxnm/vminnm.
This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| d055c595443fefe64b33d28d0b2556ace04084ad |
17-Jul-2013 |
JF Bastien <jfb@google.com> |
Fix ARMFastISel::ARMEmitIntExt shift emission
My patch 'r183551 - ARM FastISel integer sext/zext improvements' was incorrect when emitting ARM register-immediate ASR, LSL, LSR instructions: they are pseudo-instructions in ARMInstrInfo.td and I should have used MOVsi instead.
This is not an issue when code is generated through a .s file, but is an issue when generated straight to a .o (-filetype=obj).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186489 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 82d4215f64dc941f21bbae7ec781367d343387b8 |
17-Jul-2013 |
Lang Hames <lhames@gmail.com> |
Related to r181161 - Indirect branches may not be the last branch in a basic
block. Blocks that have an indirect branch terminator, even if it's not the
last terminator, should still be treated as unanalyzable.
<rdar://problem/14437274>
Reducing a useful regression test case is proving difficult - I hope to have
one soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186461 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 898788c6bcc2abfe0e1c7b21c14394352963acd6 |
16-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add support for the Thumb2 PLI alternate literal form.
This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]
See A8.8.129 in the ARM ARM (DDI 0406C.b).
Fixes <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ad9a0d27d36f18dff2b2d37dd13b11ed2d07688b |
16-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow printing of ARM atomic DAG nodes.
We'd forgotten to provide string representations for the special ARMISD atomic
nodes; this adds them in. No effect on CodeGen, just makes the output of
"-view-whatever-dags" slightly more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186406 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2f438131f115a3860ee344a827a091790d6dc13d |
16-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement ldrex, strex and clrex intrinsics
Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 103ba845f09252d90a05109af7174f54bf412daf |
16-Jul-2013 |
Renato Golin <renato.golin@linaro.org> |
ARM EABI divmod support
This patch enables calls to __aeabi_idivmod when in EABI mode,
by using the remainder value returned on registers (R1),
enabled by the ARM triple "none-eabi". Note that Darwin and
GNUEABI triples will continue lowering on GNU style, that is,
using the stack for the remainder.
Still need to add SREM/UREM support fix for 64-bit lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186390 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.h
|
| b9df53a40b22c74ce3f3a7b4a7c0676a38cf5e73 |
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186301 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMLoadStoreOptimizer.cpp
|
| 1b6f5a29ab62fd3e763983f31200b4cc69fa752b |
13-Jul-2013 |
JF Bastien <jfb@google.com> |
Fix ARM paired GPR COPY lowering
ARM paired GPR COPY was being lowered to two MOVr without CC. This
patch puts the CC back.
My test is a reduction of the case where I encountered the issue,
64-bit atomics use paired GPRs.
The issue only occurs with selectionDAG, FastISel doesn't encounter it
so I didn't bother calling it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186226 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| adde9da01c78dd837a4e32217c9445c2c1aadb27 |
13-Jul-2013 |
Eric Christopher <echristo@gmail.com> |
Remove extraneous braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186212 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4a1c764264a8908aa041acf12f68cd8bcc2037b1 |
12-Jul-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Add cost for gather/scather
Fixes a 35% degradation compared to unvectorized code in
MiBench/automotive-susan and an equally serious regression on a private
image processing benchmark.
radar://14351991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186188 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| c0a11edba6ea46c782672ab3fb4e4ab3dc267a22 |
12-Jul-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
TargetTransformInfo: address calculation parameter for gather/scather
Address calculation for gather/scather in vectorized code can incur a
significant cost making vectorization unbeneficial. Add infrastructure to add
cost.
Tests and cost model for targets will be in follow-up commits.
radar://14351991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186187 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 4d6d0d0d821489e866c4709126e5fa97e12735d6 |
11-Jul-2013 |
Stephen Hines <srhines@google.com> |
Allow global-merge option to be accessed externally.
Change-Id: I39d1c5e05b5f1bbbf76f7491f7dc8cfa70a83611
RMTargetMachine.cpp
|
| 5fa2ba2769d31815f54ebf1af42f868f1486e4d0 |
10-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186013 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ea870a53a5a0c644e5b15af5ae59d8a4378a4d2a |
10-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185995 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 9ddfe5ea6f46448cf01e114c971e6bd7ac6ad06c |
10-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Explicitly define ARMISelLowering::isFMAFasterThanFMulAndFAdd. No functionality change.
Currently ARM is the only backend that supports FMA instructions (for at least some subtargets) but does not implement this virtual, so FMAs are never generated except from explicit fma intrinsic calls. Apparently this is due to the fact that it supports both fused (one rounding step) and unfused (two rounding step) multiply + add instructions. This patch clarifies that this the case without changing behavior by implementing the virtual function to simply return false, as the default TargetLoweringBase version does.
It is possible that some cpus perform the fused version faster than the unfused version and vice-versa, so the function implementation should be revisited if hard data is found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185994 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 97c37bb4d4ae5e505350091e520a1354069941e0 |
10-Jul-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fix incorrect pack pattern for thumb2
Propagate the fix from r185712 to Thumb2 codegen as well. Original
commit message applies here as well:
A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and
packs them in the bottom half of "x". An arithmetic and logic shift are
only equivalent in this context if the shift amount is 16. We would be
shifting in ones into the bottom 16bits instead of zeros if "y" is
negative.
rdar://14338767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185982 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 12f45c3782c0d01bcf9973bbc23dba2b17ce54cb |
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 8dc741d29f9c9beff8a9f26ff23b307b9df4f8fd |
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185926 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 9fb5a6588becc92be1d7cf503d2947b170be3c31 |
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185922 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 881b0b5c77ec3f6849e32b7763b6c75057b81501 |
08-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a comment to this change, requested by Eric Christopher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185853 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| dc2d418dd29ad9396aea06f2b72c9a7d29b30940 |
08-Jul-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Improve codegen for generic vselect.
Fall back to by-element insert rather than building it up on the stack.
rdar://14351991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185846 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2a9683289b78a2533b261e1b341f9ea9724465a0 |
06-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC support for the v8fp instructions: vmaxnm and vminnm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| fe3b2995aa38b25bada9fa2e850590b3988668b5 |
05-Jul-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM: Add a pack pattern for matching arithmetic shift right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185714 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ffd3bb8f0d875f4aae3097660f973b1e7512ee05 |
05-Jul-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM: Fix incorrect pack pattern
A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them
in the bottom half of "x". An arithmetic and logic shift are only equivalent in
this context if the shift amount is 16. We would be shifting in ones into the
bottom 16bits instead of zeros if "y" is negative.
radar://14338767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 00d9fe2de7f0b8f9d1ea19ae30cc78b1a1e1fb92 |
05-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.
In the SelectionDAG immediate operands to inline asm are constructed as
two separate operands. The first is a constant of value InlineAsm::Kind_Imm
and the second is a constant with the value of the immediate.
In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we
should skip over the next operand too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185688 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1e9ddc229f3d837a79eed1d7ac43743db148f8d1 |
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185651 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 4ea250524f77a67102118747dad6ee69f9f3b3aa |
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 929d9ef111cc0053e245d04464c5ba9fba7727b2 |
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| 6227d5c690504c7ada5780c00a635b282c46e275 |
04-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 62da588a2eb70166e1b6cc332d8084f03117dc12 |
04-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for the GHC calling convention.
This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185592 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCallingConv.td
|
| 8e2e5ff0240dfb90c6dbc93e7fc441f71bfde400 |
03-Jul-2013 |
Quentin Colombet <qcolombet@apple.com> |
[ARM] Improve the instruction selection of vector loads.
In the ARM back-end, build_vector nodes are lowered to a target specific
build_vector that uses floating point type.
This works well, unless the inserted bitcasts survive until instruction
selection. In that case, they incur moves between integer unit and floating
point unit that may result in inefficient code.
In other words, this conversion may introduce artificial dependencies when the
code leading to the build vector cannot be completed with a floating point type.
In particular, this happens when loads are not aligned.
Before this patch, in that case, the compiler generates general purpose loads
and creates the floating point vector from them, instead of directly using the
vector unit.
The patch uses a vector friendly sequence of code when the inserted bitcasts to
floating point survived DAGCombine.
This is done by a target specific DAGCombine that changes the target specific
build_vector into a sequence of insert_vector_elt that get rid of the bitcasts.
<rdar://problem/14170854>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185587 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 79c163d6ddeb84ea1743eca0644688951bfc5a97 |
03-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.
The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.
This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.
Fixes <rdar://problem/14224440>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 365ef0b197d7c841f8e501da64296df65be4ca23 |
03-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
15SDOptimizer.cpp
|
| b81b477cd4392a51112c3af0659ea9fc176e74f1 |
03-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| a10c01a6c62792be825c562314a646437b21bfec |
03-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.
This patch makes use of that quirk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a3863ea2dacafc925a8272ebf9884fc64bef686c |
02-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove address spaces from MC.
This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 0a39e264330c5f6eb9e5e9e60d276613985e178d |
02-Jul-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix ARM EHABI compact model 1 and 2 without handlerdata.
According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes. The handler data consists of several words, and
should be terminated by zero.
In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| e29e2afc738348c74966ed81b3568779247c9fbd |
01-Jul-2013 |
Chad Rosier <mcrosier@apple.com> |
[ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values. This should be the last fix due to fallout from r185094.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 40d0492cdea1023463a9902ee81b3c5251204039 |
01-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.
Thanks for pointing it out Eli!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d59fc0af0a3ebd13c7004511e64e3233dfe87b17 |
01-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.
A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 75f29256f3587b19740398adb9678b6ba376912f |
28-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Remove unused member
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185219 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| f52578c08c71dc356428c25b0ba8759fd7ee2c66 |
28-Jun-2013 |
Eric Christopher <echristo@gmail.com> |
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185180 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 10ddc4d7f232507933c266180d0052f12e65c4ab |
28-Jun-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM
This patch assigns paired GPRs for inline asm with
64-bit data on ARM. It's enabled for both ARM and Thumb to support modifiers
like %H, %Q, %R.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185169 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
|
| bcd8e7ad4d1dd486675e774778b3409464380f62 |
28-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: ensure fixed-point conversions have sane types
We were generating intrinsics for NEON fixed-point conversions that didn't
exist (e.g. float -> i16). There are two cases to consider:
+ iN is smaller than float. In this case we can do the conversion but need an
extend or truncate as well.
+ iN is larger than float. In this case using the NEON conversion would be
incorrect so we don't perform any combining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185158 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a744d41a3f8af25938e12617abe2a8d32f6eabf6 |
28-Jun-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Fix pseudo-instructions for SRS (Store Return State).
The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is:
srsfa -> srsib
srsea -> srsia
srsfd -> srsdb
srsed -> srsda
This fixes <rdar://problem/14214734>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 31d2f08f8893f38d2d7293195f3707edfefbeeb6 |
27-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a Subtarget feature 'v8fp' to the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185073 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMBuildAttrs.h
RMSubtarget.cpp
RMSubtarget.h
|
| 165a7a925d73286abfc826b3d6339843b02c09e0 |
27-Jun-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Clarify and doxygen-ify comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185030 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 6b97ebe9a32342207b24a5f73ebbf3070ec8d189 |
26-Jun-2013 |
Stephen Lin <stephenwlin@gmail.com> |
ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is not used for incompatible calling conventions.
(Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185024 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMISelLowering.cpp
|
| 8b9962d514c1834c17254e53b169bf618079562c |
26-Jun-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185016 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 849eedce9921eb8f285cd0df0ad69ee5133459d1 |
26-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a subtarget feature 'v8' to the ARM backend.
This allows for targeting the ARMv8 AArch32 variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMBuildAttrs.h
RMInstrInfo.td
RMSubtarget.cpp
RMSubtarget.h
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| c19bd321362166805194cbaf170e06a4790d2da9 |
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| c1a91dd97b000128189421eda6c5bb7905b1f467 |
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| fce567aec90610e81e0b23968d8935ecf5b04505 |
26-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
Remove the 'generic' CPU from the ARM eabi attributes printer.
Make v4 the default ARM architecture attribute, to match CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184962 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6e0857e0b6b241e8b698417659a5821f15290a63 |
26-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: operands should be explicit when disassembled
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184943 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| ebc3938ae717d7352de800344c3ad5a1bceb74e5 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 07c3e159d8fffc8b16bcd52cc395a78007c62910 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: rGPR is meant to be unpredictable, not undefined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184706 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| ff08da15cf3d0412ee9cc325fc5a720bcad178f2 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix IT decoding
mask == 0 -> UNPRED
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184702 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 0c9f0c047dfba91bc7c0fb66f7e868e917d37c4c |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enable decoding of pc-relative PLD/PLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 1948910e3186d31bc0d213ecd0d7e87bb2c2760d |
22-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: Don't lose unreferenced non-trivial by-value parameters
A FastISel optimization was causing us to emit no information for such
parameters & when they go missing we end up emitting a different
function type. By avoiding that shortcut we not only get types correct
(very important) but also location information (handy) - even if it's
only live at the start of a function & may be clobbered later.
Reviewed/discussion by Evan Cheng & Dan Gohman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184604 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2b7cdf09a142b7f3e9a0ec8c7044eaf89bc59caa |
21-Jun-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Remove a (false) dependency on the memoryoperand's value as we do not use
it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.
<rdar://problem/13978317>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184492 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 4cbbbf49b69646ff990203ef3feae6a2726b8753 |
20-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
This reverts r155000.
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.
VFP instructions on v8/AArch32 share the same encoding space as cdp2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0159ae4295720c5ce8fc770ddb5fed67e90b8d3a |
19-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: PR14763/r183329 correct the location of indirect parameters
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.
Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184368 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| ba54bca472a15d0657e1b88776f7069042b60b4e |
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| f9fd58a44bbc7d9371ce39eb20eec16b0f1f7395 |
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184352 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| ea44281d5da5096de50ce1cb358ff0c6f20e1a2a |
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184349 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| a95e3091eb9ba5010f6c5f6f51958b01ca3a85f6 |
18-Jun-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add optional datatype suffix to NEON mvn asm syntax.
rdar://14194152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 41502e1af77443c31138cee309bd89898f23e33a |
18-Jun-2013 |
Michael Gottesman <mgottesman@apple.com> |
[ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implying that upper bits are always 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184231 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8493edfb4b61e5c63669fc19a55b640e1ad7aee1 |
18-Jun-2013 |
Michael Gottesman <mgottesman@apple.com> |
Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL.
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.
In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184230 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bf811d602d1d81b93846c6cbbd1cec85f2f153cb |
18-Jun-2013 |
Kevin Enderby <enderby@apple.com> |
Change the arm assembler to support this from the v7c spec:
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."
In the pre-matcher handler in the asm parser the ".w" (wide) qualifier
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.
Test cases for these were added.
rdar://14064574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 13769fa725b03a937335cf04d2b9cc1ca426060f |
18-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184213 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| beb920fce6ccc89b4735f280f94cb8c227f4ef5e |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly
This patch also makes the assembler look at the .w/.n specifier for
loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| f8b60d6f30a8f25c84a71d36ff3a86fe1f52f671 |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: add operands pre-writeback variants when needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184181 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| ce046b98ed6c351779fc43599a80d588752bc1ca |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
|
| cea0032f73a56a62b692b25ca4084850cd51763b |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: thumb stores cannot use PC as dest register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 99cb622041a0839c7dfcf0263c5102a305a0fdb5 |
18-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 |
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 6d9dbd5526e3161db884fc4fe99c278bb59ccc19 |
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.
Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a5ce5f36d3a1e312304e8312ca64a1342f5f55a6 |
15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Update machine models. Specify buffer sizes for OOO processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
RMScheduleSwift.td
|
| b86a0cdb674549d8493043331cecd9cbf53b80da |
15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMScheduleA9.td
|
| a768a4954818456fa6fe2077a3cbe75979025c15 |
14-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fe532ad6d6643219669056dc268d63fb29a8d1ee |
14-Jun-2013 |
JF Bastien <jfb@google.com> |
Enable FastISel on ARM for Linux and NaCl, not MCJIT
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.
FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.
Thumb2 support needs a bit more work, mainly around register class
restrictions.
The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.
The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.
The test changes are straightforward, similar to:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.
I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183966 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9151f6474c0c3c696e75a12a605c48f54da4665f |
12-Jun-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r183849.
s/LLVM_HOSTTRIPLE/LLVM_HOST_TRIPLE
Add #include<ctype.h> to LinkModules.cpp for isdigit().
Add missing libLLVMObject to llc dependencies.
Android.mk updates:
Remove Linker.cpp
Remove JITDwarfEmitter.cpp
Remove MipsDirectObjLower.cpp
Add MCExternalSymbolizer.cpp
Add MCRelocationInfo.cpp
Add MCSymbolizer.cpp
Add ARMMachORelocationInfo.cpp
Add Mips16HardFloat.cpp
Add MipsOptimizeMathLibCalls.cpp
Add X86ELFRelocationInfo.cpp
Add X86MachORelocationInfo.cpp
Change-Id: I3f3dbc2b62e89ef9e303f5456c6a99f0937f6981
CTargetDesc/Android.mk
|
| 8117ac555d06b23f61ddd06aa54d3dfa3e5b8e56 |
13-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix B decoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183914 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1290ce00a372f10fa1667d3566477f86ede04c73 |
13-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix t2am_imm8_offset operand printing for imm=#-0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 1878f9a7874b1ff569d745c0269f49d3daf7203d |
12-Jun-2013 |
Stephen Hines <srhines@google.com> |
Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612
|
| 5ab770417bd230d2e319490261d300c50e932b71 |
12-Jun-2013 |
JF Bastien <jfb@google.com> |
ARM FastISel fix sext/zext fold
Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it.
This patch fixes both issues.
This patch fixes both, and the test should remain the same:
test/CodeGen/ARM/fast-isel-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183794 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6c921a55f4d5fc51a127fcc673ac1c9b46273899 |
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 55ab7315d04ce4f25a15e5cd50f6a23d950a00cf |
11-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a |
11-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMRegisterInfo.td
|
| aa8003712e8b28bc4f263aeb79d8851146273a05 |
11-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: Enforce decoding rules for VLDn instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 3862709058ecfe809c9d4b32e3bff0efe8ebe646 |
11-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| c139672407b6ad8d2929fd0c52591216fd32b4b6 |
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
- For now, The tests are marked as XFAIL for win32 hosts.
FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 6915854dd27bfedd2bc261cb19b148557670b98c |
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().
FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183727 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 2266ef3f5e7608d0ae491acd77b755b171cc6475 |
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183726 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 9bdd78501484a1add2d8a757fd29960dd9fc9de7 |
11-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.
rdar://14024354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 6c1bd2919ee76ef4953136f0b73192fbef3a69ab |
10-Jun-2013 |
Aaron Ballman <aaron@aaronballman.com> |
Silencing an MSVC warning about comparing signed and unsigned values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183682 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 38946caa431a3e790f82600047db10a4ec55743c |
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
Fix misleading comments in ARMAsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183657 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4e9a96d810eb0cc126ebe6f18e536b474c84940c |
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMBaseInfo.h
|
| 18cba562c8016f8095643b5dd8c4b34b294b62dd |
09-Jun-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:
* Fix multiple .save or .vsave directives. Besides, the
order is preserved now.
* For the directives which will generate multiple opcodes,
such as ".save {r0-r11}", the order of the unwind opcode
is fixed now, i.e. the registers with less encoding value
are popped first.
* Fix the $sp offset calculation. Now, we can use the
.setfp, .pad, .save, and .vsave directives at any order.
Changes to test cases:
* Add test cases to check the order of multiple opcodes
for the .save directive.
* Fix the incorrect $sp offset in the test case. The
stack pointer offset specified in the test case was
incorrect. (Changed test cases: ehabi-mc-section.ll and
ehabi-mc.ll)
* The opcode to restore $sp are slightly reordered. The
behavior are not changed, and the new output is same
as the output of GNU as. (Changed test cases:
eh-directive-pad.s and eh-directive-setfp.s)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMUnwindOpAsm.cpp
CTargetDesc/ARMUnwindOpAsm.h
|
| 1fe907e7f2de32df894373e24a10c8f54534d770 |
09-Jun-2013 |
JF Bastien <jfb@google.com> |
ARM FastISel fix load register classes
The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register.
These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183624 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9eefea009fb559cf441254f7022a2824386852c6 |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| ae50ddb2aeaec7dd91ef8db3918688c104a6baed |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 46e136c952e0242308db2682ba2ec4020cdcd006 |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.
Add some necessary safe guards in CPS decoding as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| c64835b0c57913b11abd648b76913390e62af8d6 |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix VCVT decoding
UNPRED was reported instead of UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 2c69e900644535d58292756c0a114c88ce51824c |
08-Jun-2013 |
JF Bastien <jfb@google.com> |
Fix unused variable warning from my previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183601 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8fc760cbe8d42e788f29b4a21537bc5e25d5ffa3 |
07-Jun-2013 |
JF Bastien <jfb@google.com> |
ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.
The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.
fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).
2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.
fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.
Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.
I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 57148c166ab232191098492633c924fad9c44ef3 |
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMHazardRecognizer.cpp
RMHazardRecognizer.h
RMInstrInfo.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| c6752d5565d77e1824eb08cfc2bd53b5f6229fdb |
07-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Use the right resources for DIV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183477 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 873ff29514f13f6919f172ba430994ff99becbd2 |
07-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add VFP div instruction on Swift
Reapply 183271.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183472 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 7f155d7d2bb8c702ed0f64393e38ec1cc26e2f08 |
07-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270 again (because three is a magic number).
This should now no longer seg fault after r183459.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183464 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 6b10d853039915aa24995fa7696e90323758e31b |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"
Breaks linux build bots (I thought the problem was something else).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183447 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 5bf5b96c2b61198c40b97a4f99973bd31d671ec2 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183445 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 5be946b4866989cddf16fd3d1977da3c77351098 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add integer VFP/SIMD instructions on Swift
Reapply 183269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183441 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| d9445b6221fd3e94f95a328504b739bf636a5dbf |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add integer load/store instructions on Swift
Reapply 183268.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183438 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 67c2056e006688dbfe36bcea2298863d4cc174a9 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add integer arithmetic instructions on Swift
Reapply 183267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183436 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| d8f8c35f4d524a4c90a8536551f726ce4e1d437c |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Cortex A9 - More InstRW sched resources
Add more InstRW mappings.
Reapply 183266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183435 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| f1f6dcefa8c445fa6bd2bba3d72a3e6adff16ca1 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch thumb instructions
Reapply 183265.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183432 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| a6db67719754168c7e491bb814264a3bddbd8534 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch thumb2 instructions
Reapply 183264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183430 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 87aab6dc968a617e5498c384c2dcdbb6cb19acea |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch instructions
Reapply 183263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3ba4778c9579739748810d78befd1752dc71acb6 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add preload thumb2 instructions
Reapply 183262.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183427 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e022a6b0f45184726afe0aa48ef04a9af3e94b62 |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add preload instructions
Reapply 183261.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f2988a00843bf5ddef7c9ee8b26534a1aa8c56cf |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP thumb instructions
Reapply of 183260.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183423 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 826de688b06552125b94a3d1e038f5326d53435f |
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP thumb2 instructions
Reapply of 183259.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183421 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6a2e7ac0b6647a409394e58b385e579ea62b5cba |
06-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 31588f300500d290e43952fcd8dd8e7f2bb460eb |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP instructions
Reapply of 183258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c82157378e452035e6244194f3778e4a558435f3 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.
Reapply of r183257. (Removed empty InstRW for division on swift)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| d87bd5627e5b78cb556d6c7b5aa76ae3d55d8acf |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARMInstrInfo: Improve isSwiftFastImmShift
An instruction with less than 3 inputs is trivially a fast immediate shift.
Reapply of 183256, should not have caused the tablegen segfault on linux either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183314 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2248cf590617cbe91eeb6a845ad06d675d9f2e91 |
05-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 00ed010d9ef388d718ac358132848661b286f7b0 |
05-Jun-2013 |
Evan Cheng <evan.cheng@apple.com> |
Cortex-R5 can issue Thumb2 integer division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 8a227084a5b07fa289c34f2b36e12f75b47473d6 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Revert series of sched model patches until I figure out what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| f500aa0b2465152d1bae390e4d4a48e3a17e85a5 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add VFP div instruction on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 858f6f8899e058412fc031f8b7231b9e13dca02a |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add SIMD/VFP load/store instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183270 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| e52041c16e1910b041513710031bafebe9cd5649 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add integer VFP/SIMD instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183269 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| f3a2329d3394c9a730aedbeaf2d761a9fe910fcf |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add integer load/store instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| 755d1295a52c8d3e0c74c5ee37c6bd27074b52a8 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add integer arithmetic instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183267 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleSwift.td
|
| eb9948e7815818c7c4c05a6fb13bd1bfae820bbd |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Cortex A9 - More InstRW sched resources
Add more InstRW mappings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 002faf20a7093ed0d7dfe84c72d1ce7f790e77a4 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch thumb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183265 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 16d915018b303e69c409bed15e29ac6906b1fe92 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 36ea7912800a281a62d2605ab15e5b02cabacd09 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fdbca2faac8ebc3fa5c17ffae5e6a0e5d38a4cb8 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add preload thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d3b8445d14593b76b10dc8aee4bebdcbf11443ad |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add preload instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 23cb39a3d915d6eaa2e053cae1c3158a2fdbe5c2 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP thumb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183260 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 1942e3254d2d50ccad3dce247fde4ec1e974a857 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4c53731e5b21fc953cd431074f83063b87f95585 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183258 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 611c6e135910779a8d1ed6db023d87f19799f6ac |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| ede7eeae328d455b00d600639adacda695a499b6 |
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARMInstrInfo: Improve isSwiftFastImmShift
An instruction with less than 3 inputs is trivially a fast immediate shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183256 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 35e7751af455f2cc559cdc2d3424b53706e09bb3 |
04-Jun-2013 |
David Majnemer <david.majnemer@gmail.com> |
ARM: Fix crash in ARM backend inside of ARMConstantIslandPass
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.
This fixes PR16215.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| bed23081860275c79137f65d592920e7991b8198 |
31-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.
In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| ee5e24cb3e987c74d4dce146b4f78e83fb2b56a8 |
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: permit upper-case BE/LE on setend instruction
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 242c9f4615feeee2fbdd1f29cd9a8e8ffd43c075 |
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
isassembler/ARMDisassembler.cpp
|
| e93c701cac2ac62bcd390b978604da76be9967d0 |
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix VEXT encoding corner case
The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).
Patch by Amaury de la Vieuville
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9e3e730417ec806f5a671e23d762795e550d0930 |
30-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert r182937 and r182877.
r182877 broke MCJIT tests on ARM and r182937 was working around another failure
by r182877.
This should make the ARM bots green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182960 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f567a6d39b05ebdcdb42b4183f6cfdada75ec189 |
29-May-2013 |
JF Bastien <jfb@google.com> |
Enable FastISel on ARM for Linux and NaCl
FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl.
Thumb2 support needs a bit more work, mainly around register class
restrictions.
The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.
The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.
The test changes are straightforward, similar to:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.
I ran all of test-suite on A15 hardware with --optimize-option=-O0 and
all the tests pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182877 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a9a8a128f807d46ce46971abf65578996c50cf2e |
29-May-2013 |
JF Bastien <jfb@google.com> |
Tidy some register classes for ARM and Thumb
Tidy up three places where the register class for ARM and Thumb wasn't
restrictive enough:
- No PC dest for reg-reg add/orr/sub.
- No PC dest for shifts.
- No PC or SP for Thumb2 reg-imm add.
I encountered this while combining FastISel with
-verify-machineinstrs. These instructions defined registers whose
classes weren't restrictive enough, and the uses failed
verification. They're also undefined in the ISA, or would produce code
that FastISel wouldn't want. This doesn't fix the register class
narrowing issue (where uses should restrict definitions), and isn't
thorough, but it's a small step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182863 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMInstrThumb2.td
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
|
| de7cbbfcce5c068f0699bdcb6dac093c0c91ba6f |
25-May-2013 |
Quentin Colombet <qcolombet@apple.com> |
Follow up of the introduction of MCSymbolizer.
- Ressurect old MCDisassemble API to soften transition.
- Extend MCTargetDesc to set target specific symbolizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182688 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAddressingModes.h
CTargetDesc/ARMMCCodeEmitter.cpp
humb2InstrInfo.cpp
|
| 49a6a8d8f2994249c81b7914b07015714748a55c |
24-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.
Defines away PR16132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| ef99356dfebb96f6f90efb912c2877214bad060e |
24-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
MC: Disassembled CFG reconstruction.
This patch builds on some existing code to do CFG reconstruction from
a disassembled binary:
- MCModule represents the binary, and has a list of MCAtoms.
- MCAtom represents either disassembled instructions (MCTextAtom), or
contiguous data (MCDataAtom), and covers a specific range of addresses.
- MCBasicBlock and MCFunction form the reconstructed CFG. An MCBB is
backed by an MCTextAtom, and has the usual successors/predecessors.
- MCObjectDisassembler creates a module from an ObjectFile using a
disassembler. It first builds an atom for each section. It can also
construct the CFG, and this splits the text atoms into basic blocks.
MCModule and MCAtom were only sketched out; MCFunction and MCBB were
implemented under the experimental "-cfg" llvm-objdump -macho option.
This cleans them up for further use; llvm-objdump -d -cfg now generates
graphviz files for each function found in the binary.
In the future, MCObjectDisassembler may be the right place to do
"intelligent" disassembly: for example, handling constant islands is just
a matter of splitting the atom, using information that may be available
in the ObjectFile. Also, better initial atom formation than just using
sections is possible using symbols (and things like Mach-O's
function_starts load command).
This brings two minor regressions in llvm-objdump -macho -cfg:
- The printing of a relocation's referenced symbol.
- An annotation on loop BBs, i.e., which are their own successor.
Relocation printing is replaced by the MCSymbolizer; the basic CFG
annotation will be superseded by more related functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182628 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 2c94d0faa0e1c268893d5e04dc77e8a35889db00 |
24-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Add MCSymbolizer for symbolic/annotated disassembly.
This is a basic first step towards symbolization of disassembled
instructions. This used to be done using externally provided (C API)
callbacks. This patch introduces:
- the MCSymbolizer class, that mimics the same functions that were used
in the X86 and ARM disassemblers to symbolize immediate operands and
to annotate loads based off PC (for things like c string literals).
- the MCExternalSymbolizer class, which implements the old C API.
- the MCRelocationInfo class, which provides a way for targets to
translate relocations (either object::RelocationRef, or disassembler
C API VariantKinds) to MCExprs.
- the MCObjectSymbolizer class, which does symbolization using what it
finds in an object::ObjectFile. This makes simple symbolization (with
no fancy relocation stuff) work for all object formats!
- x86-64 Mach-O and ELF MCRelocationInfos.
- A basic ARM Mach-O MCRelocationInfo, that provides just enough to
support the C API VariantKinds.
Most of what works in otool (the only user of the old symbolization API
that I know of) for x86-64 symbolic disassembly (-tvV) works, namely:
- symbol references: call _foo; jmp 15 <_foo+50>
- relocations: call _foo-_bar; call _foo-4
- __cf?string: leaq 193(%rip), %rax ## literal pool for "hello"
Stub support is the main missing part (because libObject doesn't know,
among other things, about mach-o indirect symbols).
As for the MCSymbolizer API, instead of relying on the disassemblers
to call the tryAdding* methods, maybe this could be done automagically
using InstrInfo? For instance, even though PC-relative LEAs are used
to get the address of string literals in a typical Mach-O file, a MOV
would be used in an ELF file. And right now, the explicit symbolization
only recognizes PC-relative LEAs. InstrInfo should have already have
most of what is needed to know what to symbolize, so this can
definitely be improved.
I'd also like to remove object::RelocationRef::getValueString (it seems
only used by relocation printing in objdump), as simply printing the
created MCExpr is definitely enough (and cleaner than string concats).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182625 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/ARMMachORelocationInfo.cpp
CTargetDesc/CMakeLists.txt
|
| 5a02fc4b5fa0eba4d0875db710400a74ada3b15f |
23-May-2013 |
Tim Northover <t.p.northover@gmail.com> |
ARM: implement @llvm.readcyclecounter intrinsic
This implements the @llvm.readcyclecounter intrinsic as the specific
MRC instruction specified in the ARM manuals for CPUs with the Power
Management extensions.
Older CPUs had slightly different methods which may also have to be
implemented eventually, but this should cover all v7 cases.
rdar://problem/13939186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b94a353242b26af5c0969926a6b84664e342b586 |
23-May-2013 |
Tim Northover <t.p.northover@gmail.com> |
ARM: Add Performance Monitor Extensions feature
Performance monitors, including a basic cycle counter, are an official
extension in the ARMv7 specification. This adds support for enabling and
disabling them, orthogonally from CPU selection.
rdar://problem/13939186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182602 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| 62c320a755ac27ac2b7f64e927892249e0f486e0 |
23-May-2013 |
Chad Rosier <mcrosier@apple.com> |
Simplify logic now that r182490 is in place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182531 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 30a7a7c1fdbd2607345dd1554e3436749fd75c6e |
20-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| bac932e9c3c4305a3c73598f3d0dc55de53d4c68 |
20-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 083bc97344d618884ef04bc1ba1fc4ddf14d867d |
20-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:
Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ...
FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.
We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.
This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMISelLowering.cpp
RMISelLowering.h
RMMachineFunctionInfo.h
humb1FrameLowering.cpp
|
| 4dc8bdf87d402ad8c91d9a72777d9576c5461e40 |
20-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace some bit operations with simpler ones. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| bab06ba696694e7f62f964af7ee5290a13f78340 |
18-May-2013 |
JF Bastien <jfb@google.com> |
Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store
for v6+ Darwin as well as for v7+ on Linux and NaCl.
The distinction is made because v6 doesn't guarantee support (but LLVM
assumes that Apple controls hardware+kernel and therefore have
conformant v6 CPUs), whereas v7 does provide this guarantee (and
Linux/NaCl behave sanely).
The patch keeps the -arm-strict-align command line option, and adds
-arm-no-strict-align. They behave similarly to GCC's -mstrict-align and
-mnostrict-align.
I originally encountered this discrepancy in FastIsel tests which expect
unaligned load/store generation. Overall this should slightly improve
performance in most cases because of reduced I$ pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 40df0d7a462c0febccc93f90dee105a0797f8ac6 |
16-May-2013 |
Derek Schuff <dschuff@google.com> |
Revert "Support unaligned load/store on more ARM targets"
This reverts r181898.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181944 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 6fc631978cdd1128a790854e497e267639d9325d |
15-May-2013 |
Derek Schuff <dschuff@google.com> |
Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for
v6+ Darwin as well as for v7+ on other targets.
The distinction is made because v6 doesn't guarantee support (but LLVM assumes
that Apple controls hardware+kernel and therefore have conformant v6 CPUs),
whereas v7 does provide this guarantee (and Linux behaves sanely).
Overall this should slightly improve performance in most cases because of
reduced I$ pressure.
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181897 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 101a36117c2e5e760ebb2b476d6c5b2b52cac6e8 |
15-May-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM ISel: Don't create illegal types during LowerMUL
The transformation happening here is that we want to turn a
"mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have
to make sure that X still has a valid vector type - possibly recreate an
extension to a smaller type. In case of a extload of a memory type smaller than
64 bit we used create a ext(load()). The problem with doing this - instead of
recreating an extload - is that an illegal type is exposed.
This patch fixes this by creating extloads instead of ext(load()) sequences.
Fixes PR15970.
radar://13871383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181842 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f86e436fb95670ed110818fefa403f21ae104639 |
13-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMInstrInfo.td
RMRegisterInfo.td
isassembler/ARMDisassembler.cpp
|
| d26c93d3a8a484c5b42f06163ae5de787f0ac276 |
13-May-2013 |
Lang Hames <lhames@gmail.com> |
Correctly preserve the input chain for potential tailcall nodes whose
return values are bitcasts.
The chain had previously been being clobbered with the entry node to
the dag, which sometimes caused other code in the function to be
erroneously deleted when tailcall optimization kicked in.
<rdar://problem/13827621>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 6e53180db120b30f600ac31611a9dd47ef7f4921 |
10-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| c24a374331fc97dd215937c8f0a9bf5271f39657 |
10-May-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Implement AsmParser for ARM unwind directives.
This commit implements the AsmParser for fnstart, fnend,
cantunwind, personality, handlerdata, pad, setfp, save, and
vsave directives.
This commit fixes some minor issue in the ARMELFStreamer:
* The switch back to corresponding section after the .fnend
directive.
* Emit the unwind opcode while processing .fnend directive
if there is no .handlerdata directive.
* Emit the unwind opcode to .ARM.extab while processing
.handlerdata even if .personality directive does not exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181603 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMELFStreamer.cpp
|
| 44b6b530e94d5b05e1b2ddbb174c477b0ce56638 |
08-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
For r181148: fixed warning 'enumeral and non-enumeral type in conditional expression'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181437 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9dbeb69a345d12b15571769cfacf1d5e1a7ce378 |
03-May-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r180947.
Change-Id: Ic9e7daa7ef3789298c49a7b308af92115f5d682d
CTargetDesc/Android.mk
|
| 0553e1efcd3f8ccd8b45302e033924d9f85a5d2f |
05-May-2013 |
Evan Cheng <evan.cheng@apple.com> |
ARM AnalyzeBranch should conservatively return true when it sees a predicated
indirect branch at the end of the BB. Otherwise if-converter, branch folding
pass may incorrectly update its successor info if it consider BB as fallthrough
to the next BB.
rdar://13782395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181161 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 46abfcf4187432da728cbe452c32143da077e07f |
05-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
For ARM backend, fixed "byval" attribute support.
Now even the small structures could be passed within byval (small enough
to be stored in GPRs).
In regression tests next function prototypes are checked:
PR15293:
%artz = type { i32 }
define void @foo(%artz* byval %s)
define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2)
foo: "s" stored in R0
foo2: "s" stored in R0, "s2" stored in R2.
Next AAPCS rules are checked:
5.5 Parameters Passing, C.4 and C.5,
"ParamSize" is parameter size in 32bit words:
-- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4.
Parameter should be sent to the stack; NCRN := R4.
-- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4.
Parameter stored in GPRs; NCRN += ParamSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181148 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 5c332dbd30d9398ed25b30c3080506f7b8e92290 |
05-May-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Add ArrayRef constructor from None, and do the cleanups that this constructor enables
Patch by Robert Wilhelm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1aef163a6815e7bff675f83ddec8b063d6082e86 |
04-May-2013 |
Amara Emerson <amara.emerson@arm.com> |
Revert r181009.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181079 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 5d446e61d992f105a05aade62d5305fd8a346081 |
03-May-2013 |
Amara Emerson <amara.emerson@arm.com> |
Add support for reading ARM ELF build attributes.
Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.
Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181009 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 38578c4919ea18ceb27e29988b2d857afe6215bf |
03-May-2013 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/master' into merge-20130502
Conflicts:
lib/Support/Unix/Signals.inc
unittests/Transforms/Utils/Cloning.cpp
Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
|
| 34f39841d3e7929c5722cee3c27aefbca482d81a |
30-Apr-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Text files should not be marked executable.
Patch by Oliver Pinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180797 91177308-0d34-0410-b5e6-96231b3b80d8
ICENSE.TXT
|
| 62d77858be88ca011b55f5b350152bf04d1ca7db |
30-Apr-2013 |
Mihai Popa <mihail.popa@gmail.com> |
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f65e4932f83ac0c36594d97fca73dc9a9fd26672 |
30-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Refactoring patch.
1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong.
This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method.
2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed.
3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180774 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMISelLowering.cpp
RMISelLowering.h
RMMachineFunctionInfo.h
humb1FrameLowering.cpp
|
| 1ad3a410beff11913db0573942fb51b651d01a13 |
26-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 4e8590c45d3c6a4756aa8967e2e631ecd5a5a24b |
26-Apr-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM/NEON: Pattern match vector integer abs to vabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180604 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 45c9e0b412495c2d660918b0e964529bcb5e05b8 |
25-Apr-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Integer div and rem is lowered to a function call
Reflect this in the cost model. I observed this in MiBench/consumer-lame.
radar://13354716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180576 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 81fef0267b6971b32a618a655d91f472cedfcaf2 |
23-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Add more tests for r179925 to verify correct handling of signext/zeroext; strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180138 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3a1b4f82233308b7551cdaa70f70a3f493e1b22d |
23-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Lowercase "is" boolean variable prefix for consistency within function, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180136 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2c55362848eab1a8552a31f8da1a47d17105b4d9 |
22-Apr-2013 |
Eric Christopher <echristo@gmail.com> |
No really, don't store anything to this since it's unconditionally
set below.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180015 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b929b13c77a316dd9efd278399b9577fafca9a84 |
22-Apr-2013 |
Eric Christopher <echristo@gmail.com> |
Remove variable store that is never read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180014 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 78e3c90419ffbe969bd38c7a198300af42fb66fc |
22-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix for 5.5 Parameter Passing --> Stage C:
-- C.4 and C.5 statements, when NSAA is not equal to SP.
-- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
variadic procedure.
Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
No exceptions, no CPRCs here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180011 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMCallingConv.td
RMISelLowering.cpp
|
| 0cb1019e9cd41237408eae09623eb9a34a4cbe0c |
22-Apr-2013 |
Jim Grosbach <grosbach@apple.com> |
Legalize vector truncates by parts rather than just splitting.
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.
Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again. For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
%inlo = v4i32 extract_subvector %in, 0
%inhi = v4i32 extract_subvector %in, 4
%lo16 = v4i16 trunc v4i32 %inlo
%hi16 = v4i16 trunc v4i32 %inhi
%in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
%res = v8i8 trunc v8i16 %in16
This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.
Update the ARMTargetTransformInfo to take this improved legalization
into account.
Consider the simplified IR:
define <16 x i8> @test1(<16 x i32>* %ap) {
%a = load <16 x i32>* %ap
%tmp = trunc <16 x i32> %a to <16 x i8>
ret <16 x i8> %tmp
}
define <8 x i8> @test2(<8 x i32>* %ap) {
%a = load <8 x i32>* %ap
%tmp = trunc <8 x i32> %a to <8 x i8>
ret <8 x i8> %tmp
}
Previously, we would generate the truly hideous:
.syntax unified
.section __TEXT,__text,regular,pure_instructions
.globl _test1
.align 2
_test1: @ @test1
@ BB#0:
push {r7}
mov r7, sp
sub sp, sp, #20
bic sp, sp, #7
add r1, r0, #48
add r2, r0, #32
vld1.64 {d24, d25}, [r0:128]
vld1.64 {d16, d17}, [r1:128]
vld1.64 {d18, d19}, [r2:128]
add r1, r0, #16
vmovn.i32 d22, q8
vld1.64 {d16, d17}, [r1:128]
vmovn.i32 d20, q9
vmovn.i32 d18, q12
vmov.u16 r0, d22[3]
strb r0, [sp, #15]
vmov.u16 r0, d22[2]
strb r0, [sp, #14]
vmov.u16 r0, d22[1]
strb r0, [sp, #13]
vmov.u16 r0, d22[0]
vmovn.i32 d16, q8
strb r0, [sp, #12]
vmov.u16 r0, d20[3]
strb r0, [sp, #11]
vmov.u16 r0, d20[2]
strb r0, [sp, #10]
vmov.u16 r0, d20[1]
strb r0, [sp, #9]
vmov.u16 r0, d20[0]
strb r0, [sp, #8]
vmov.u16 r0, d18[3]
strb r0, [sp, #3]
vmov.u16 r0, d18[2]
strb r0, [sp, #2]
vmov.u16 r0, d18[1]
strb r0, [sp, #1]
vmov.u16 r0, d18[0]
strb r0, [sp]
vmov.u16 r0, d16[3]
strb r0, [sp, #7]
vmov.u16 r0, d16[2]
strb r0, [sp, #6]
vmov.u16 r0, d16[1]
strb r0, [sp, #5]
vmov.u16 r0, d16[0]
strb r0, [sp, #4]
vldmia sp, {d16, d17}
vmov r0, r1, d16
vmov r2, r3, d17
mov sp, r7
pop {r7}
bx lr
.globl _test2
.align 2
_test2: @ @test2
@ BB#0:
push {r7}
mov r7, sp
sub sp, sp, #12
bic sp, sp, #7
vld1.64 {d16, d17}, [r0:128]
add r0, r0, #16
vld1.64 {d20, d21}, [r0:128]
vmovn.i32 d18, q8
vmov.u16 r0, d18[3]
vmovn.i32 d16, q10
strb r0, [sp, #3]
vmov.u16 r0, d18[2]
strb r0, [sp, #2]
vmov.u16 r0, d18[1]
strb r0, [sp, #1]
vmov.u16 r0, d18[0]
strb r0, [sp]
vmov.u16 r0, d16[3]
strb r0, [sp, #7]
vmov.u16 r0, d16[2]
strb r0, [sp, #6]
vmov.u16 r0, d16[1]
strb r0, [sp, #5]
vmov.u16 r0, d16[0]
strb r0, [sp, #4]
ldm sp, {r0, r1}
mov sp, r7
pop {r7}
bx lr
Now, however, we generate the much more straightforward:
.syntax unified
.section __TEXT,__text,regular,pure_instructions
.globl _test1
.align 2
_test1: @ @test1
@ BB#0:
add r1, r0, #48
add r2, r0, #32
vld1.64 {d20, d21}, [r0:128]
vld1.64 {d16, d17}, [r1:128]
add r1, r0, #16
vld1.64 {d18, d19}, [r2:128]
vld1.64 {d22, d23}, [r1:128]
vmovn.i32 d17, q8
vmovn.i32 d16, q9
vmovn.i32 d18, q10
vmovn.i32 d19, q11
vmovn.i16 d17, q8
vmovn.i16 d16, q9
vmov r0, r1, d16
vmov r2, r3, d17
bx lr
.globl _test2
.align 2
_test2: @ @test2
@ BB#0:
vld1.64 {d16, d17}, [r0:128]
add r0, r0, #16
vld1.64 {d18, d19}, [r0:128]
vmovn.i32 d16, q8
vmovn.i32 d17, q9
vmovn.i16 d16, q8
vmov r0, r1, d16
bx lr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179989 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 4cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86cc |
21-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Use ldrd/strd to spill 64-bit pairs when available.
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179977 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
|
| 335dd0d1a60b317dd5fed7016e6b29af5d509828 |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: don't add FrameIndex offset for LDMIA (has no immediate)
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.
This removes the invalid 0-offset from the instruction being
produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179956 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 8b71994fde0f0fcdf7a8260dc773fb7376b1231f |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 456ca048af35163b9f52187e92a23ee0a9f059e8 |
20-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| 69394f2997561788c3b2e4688ac0fcc99d259256 |
20-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179913 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 75299e3a95c0cfcade8515c603e7802351a11bee |
20-Apr-2013 |
Eli Bendersky <eliben@google.com> |
Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d3af696c08923d4d376641b52c3b2cb5baa00487 |
19-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Permit "sp" in ARM variant of STREXD instructions
Patch from Mihail Popa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 4521019c6fd23680c583abe086067fc1c569bad1 |
19-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 88eb89b89f9426feb7be9b19d1a664b37c590bdb |
19-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[asm parser] Add support for predicating MnemonicAlias based on the assembler
variant/dialect. Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d050e96133fac8565e3bb1eabe9a587dd5a6ac4d |
18-Apr-2013 |
Hao Liu <Hao.Liu@arm.com> |
Fix for PR14824, An ARM Load/Store Optimization bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| df39be6cb4eb44011db3d3e86f8fe463f81ce127 |
17-Apr-2013 |
Peter Collingbourne <peter@pcc.me.uk> |
Add support for subsections to the ELF assembler. Fixes PR8717.
Differential Revision: http://llvm-reviews.chandlerc.com/D598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 7c4cf030a898b5b4e0d2c66adf8dc068b1f1f070 |
17-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)
Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| a363b117f41700da0200753e6df62b5e2cb38378 |
16-Apr-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix build failure introduced in 179591 when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179593 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 532854d7ab47d4ec20fd8cec703aa8c89d4eefb2 |
16-Apr-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Implement ARM unwind opcode assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179591 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMUnwindOp.h
CTargetDesc/ARMUnwindOpAsm.cpp
CTargetDesc/ARMUnwindOpAsm.h
CTargetDesc/CMakeLists.txt
|
| d0132ba7225883b2f7b828561d46fa6e203db6bb |
16-Apr-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add VACLT and VACLE assembly aliases.
These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.
rdar://13638090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| d64ee4455a9d2fcec7e001c7f4c02d490bed5158 |
12-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 |
10-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| 7fba6cd3d0a9565e86f50bd3d6ac403eadbcb00c |
08-Apr-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179001 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 84581daf2058eb9d37e24a50ad3be198529bdf28 |
05-Apr-2013 |
Renato Golin <renato.golin@linaro.org> |
Reverting 178851 as it broke buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178883 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 992347f27131a403043a1e2f1bec4da82568df35 |
05-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178854 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 89becbb97423fb608a4dd85ec10c3fde4398d956 |
05-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instruction vldmia at incorrect position".
Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass.
It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4
But it also tracks conflicts between different register classes (e.g. D2 and S5).
For more details see:
Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824
LLVM Commits discussion:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| fc61e635fd09e0cb852313f5533fb7fe694158fb |
05-Apr-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM scheduler model: Add scheduler info to more instructions and resource
descriptions for compares
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| 08da4865576056f997a9c8013240d716018f7edf |
05-Apr-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM scheduler model: Swift has varying latencies, uops for simple ALU ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMSchedule.td
RMScheduleSwift.td
|
| ee27cac9fac622d3198d4a53130f04653ad09d37 |
04-Apr-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid high-latency false CPSR dependencies even for tMOVSi.
The Thumb2SizeReduction pass avoids false CPSR dependencies, except it
still aggressively creates tMOVi8 instructions because they are so
common.
Avoid creating false CPSR dependencies even for tMOVi8 instructions when
the the CPSR flags are known to have high latency. This allows integer
computation to overlap floating point computations.
Also process blocks in a reverse post-order and propagate high-latency
flags to successors.
<rdar://problem/13468102>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 55097ff56765b9a1e41a7e676df764a8749bc81f |
01-Apr-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Reapply r177968:
After commit 178074 we can now have undefined scheduler variants.
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
Incooperate Andrew's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178460 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a |
29-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ce888351106a72825e2a107cb08d7130f3dce0ee |
28-Mar-2013 |
Gordon Keiser <gkeiser@arxan.com> |
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
They should always be zero-extended, not sign extended. Added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 93b10789c6ca1c7c5ca8a453a4709f47099ec819 |
28-Mar-2013 |
Gordon Keiser <gkeiser@arxan.com> |
Testing commit access to llvm. Remove two lines of whitespace from the Thumb README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178256 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| a210db781f17b5ab8e2b71d53276153a9d15eead |
27-Mar-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178134 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMTargetMachine.cpp
|
| afaeb8152c79a9f3c157a614331d6919a0a0fa6a |
26-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.
"fatal error: error in backend: Expected a variant SchedClass"
Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| b78821d380b6f9514bd3b56b1c27ba367660228b |
26-Mar-2013 |
Joe Abbey <jabbey@arxan.com> |
Patch by Gordon Keiser!
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| a5dbe29ff54ce5bb3aecefc7d42af6f31bd7e903 |
26-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177968 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSchedule.td
RMScheduleA9.td
RMScheduleSwift.td
|
| 1b618f8848c1fe672ea32009a27322e48bca46f2 |
26-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM Scheduler Model: Partial implementation of the new machine scheduler model
This is very much work in progress. Please send me a note if you start to depend
on the added abstract read/write resources. They are subject to change until
further notice.
The old itinerary is still the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177967 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
|
| c82fba27fe6205e5ecdc80fb53e10675db07dfff |
25-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
[arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores. This was already being done for loads.
Unfortunately, it is rather difficult to create a test case for this issue. It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| dc3beb90178fc316f63790812b22201884eaa017 |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.
To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.
In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1RegisterInfo.cpp
|
| 3382a840747c42c4a98eac802ee7b347a8ded1e4 |
21-Mar-2013 |
Renato Golin <renato.golin@linaro.org> |
Avoid NEON SP-FP unless unsafe-math or Darwin
NEON is not IEEE 754 compliant, so we should avoid lowering single-precision
floating point operations with NEON unless unsafe-math is turned on. The
equivalent VFP instructions are IEEE 754 compliant, but in some cores they're
much slower, so some archs/OSs might still request it to be on by default,
such as Swift and Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 580f9c85fd7a3c90884ed7ee7c2d613923a53bb3 |
20-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
Fix pr13145 - Naming a function like a register name confuses the asm parser.
Patch by Stepan Dyatkovskiy <stpworld@narod.ru>
rdar://13457826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5ad5f5931e34d5be410b1e901640bc1c2d308612 |
19-Mar-2013 |
Renato Golin <renato.golin@linaro.org> |
Improve long vector sext/zext lowering on ARM
The ARM backend currently has poor codegen for long sext/zext
operations, such as v8i8 -> v8i32. This patch addresses this
by performing a custom expansion in ARMISelLowering. It also
adds/changes the cost of such lowering in ARMTTI.
This partially addresses PR14867.
Patch by Pete Couperus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177380 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetTransformInfo.cpp
|
| d212f3fdfcfd01d5bc24ac4614b7e23478432f80 |
19-Mar-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r177342.
Change-Id: Ie489c8fab15789330f6ac968087ba14953dfacca
ndroid.mk
|
| 2d4629c5d7dcc6582fa7b85a517744f1a3654eba |
19-Mar-2013 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge_2013_03_18
|
| bf37bf9e21653f2439960d906a9c28cc19042bb0 |
18-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Make some vector integer to float casts cheaper
The default logic marks them as too expensive.
For example, before this patch we estimated:
cost of 16 for instruction: %r = uitofp <4 x i16> %v0 to <4 x float>
While this translates to:
vmovl.u16 q8, d16
vcvt.f32.u32 q8, q8
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://13445992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177334 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 01f25710148721f9fc2dece5eec17899ca414bcc |
18-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Correct cost for some cheap float to integer conversions
Fix cost of some "cheap" cast instructions. Before this patch we used to
estimate for example:
cost of 16 for instruction: %r = fptoui <4 x float> %v0 to <4 x i16>
While we would emit:
vcvt.s32.f32 q8, q8
vmovn.i32 d16, q8
vuzp.8 d16, d17
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://13434072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177333 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 5193e4ebe216dd5a07ab9cc58d40de5aafaa990c |
15-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Fix costs for some vector selects
I was too pessimistic in r177105. Vector selects that fit into a legal register
type lower just fine. I was mislead by the code fragment that I was using. The
stores/loads that I saw in those cases came from lowering the conditional off
an address.
Changing the code fragment to:
%T0_3 = type <8 x i18>
%T1_3 = type <8 x i1>
define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2,
%T1_3* %blend, %T0_3* %storeaddr) {
%v0 = load %T0_3* %loadaddr
%v1 = load %T0_3* %loadaddr2
==> FROM:
;%c = load %T1_3* %blend
==> TO:
%c = icmp slt %T0_3 %v0, %v1
==> USE:
%r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1
store %T0_3 %r, %T0_3* %storeaddr
ret void
}
revealed this mistake.
radar://13403975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5 |
15-Mar-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8
15SDOptimizer.cpp
RM.h
RMBaseInstrInfo.cpp
RMTargetMachine.cpp
MakeLists.txt
|
| 133c0d36e1fdeda88d784017bafa8a1b22af8aca |
15-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Fix an old refacto.
Fixes PR15520.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c0d8dc0eb6e1df872affadba01f60e42275e2863 |
15-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Fix cost of fptrunc and fpext instructions
A vector fptrunc and fpext simply gets split into scalar instructions.
radar://13192358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177159 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| a286fc065a5bc846d73c8407a534a1d3c1d70b59 |
15-Mar-2013 |
Eric Christopher <echristo@gmail.com> |
Silence anonymous type in anonymous union warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0cc52c67dbc2e073e3f7f34e05e3e7cd17ba9745 |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Move estimateStackSize from ARM into MachineFrameInfo
This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| d81511f0a671a9271d7ba10cce6c27331b57f553 |
14-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Increase cost of some vector selects we do terrible on
By terrible I mean we store/load from the stack.
This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update)
where we decide to vectorize a loop with a VF of 8 resulting in a 25%
degradation on a cortex-a8.
LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32
LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32
The bug that tracks the CodeGen part is PR14868.
radar://13403975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| b6f4872d29136637a3a5dfdf185f5afcbcdd3b2a |
12-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Increase the cost for vector casts that use the stack
Increase the cost of v8/v16-i8 to v8/v16-i32 casts and truncates as the backend
currently lowers those using stack accesses.
This was responsible for a significant degradation on
MultiSource/Benchmarks/Trimaran/enc-pc1/enc-pc1
where we vectorize one loop to a vector factor of 16. After this patch we select
a vector factor of 4 which will generate reasonable code.
unsigned char cle[32];
void test(short c) {
unsigned short compte;
for (compte = 0; compte <= 31; compte++) {
cle[compte] = cle[compte] ^ c;
}
}
radar://13220512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176898 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| f793de7a2331edea161eae20f9bdfa86b0d7fd3c |
09-Mar-2013 |
Lang Hames <lhames@gmail.com> |
Don't glue users to extract_subreg when selecting the llvm.arm.ldrexd
intrinsic - it can cause impossible-to-schedule subgraphs to be
introduced.
PR15053.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176777 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3853f74aba301ef08b699bac2fa8e53230714a58 |
07-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ArrayRefize some code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5adb136be579e8fff3734461580cb34d1d2983b8 |
06-Mar-2013 |
Stephen Hines <srhines@google.com> |
Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226
Conflicts:
include/llvm/Support/ELF.h
lib/Support/DeltaAlgorithm.cpp
Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
|
| 7bf504c58fcf1345f0278d6dab3840a45a623965 |
02-Mar-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Creating a vector from a lane of another.
The VDUP instruction source register doesn't allow a non-constant lane
index, so make sure we don't construct a ARM::VDUPLANE node asking it to
do so.
rdar://13328063
http://llvm.org/bugs/show_bug.cgi?id=13963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 65da9f1ce14800c137fcd8c32f3ad12c9bebd9bf |
02-Mar-2013 |
Jim Grosbach <grosbach@apple.com> |
Clean up code format a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176412 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7ccf46395e02ecaff6e6cab6ad258c69893efd55 |
02-Mar-2013 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176411 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 21c0aa74bdeae6303204c9b0c2fc154562fbb373 |
02-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM NEON: Fix v2f32 float intrinsics
Mark them as expand, they are not legal as our backend does not match them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b8f307b2d6b5fb1380803ff91696902bebbef7c6 |
01-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
Add support for using non-pic code for arm and thumb1 when emitting the sjlj
dispatch code. As far as I can tell the thumb2 code is behaving as expected.
I was able to compile and run the associated test case for both arm and thumb1.
rdar://13066352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176363 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a6ca70369366d549f104ee72822c6f591ea0ece0 |
28-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
Tidy up; no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176288 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 279706e90e12e9418d4e8f9415d5f3ed33a99bdb |
28-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
Style; no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176285 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b302a4e6b572a360d7153d2e1e14b53f053c282d |
27-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: FMA is legal only if VFP4 is available.
rdar://13306723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176212 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0a4da9c6a12371bb8bb36ef5cbb6922e0138dde2 |
27-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
Remove this instance of dl as it's defined in a previous scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176208 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d65dfd83421f4d26e6dc20476718d7d9b6ba3f3b |
27-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit full range of valid ADR immediates.
This fixes an issue where trying to assemlbe valid ADR instructions would cause
LLVM to hit a failed assertion.
Patch by Keith Walker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176189 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| efd0d71fcd03c347ac615ef7f066438f6fac2aa2 |
27-Feb-2013 |
Stephen Hines <srhines@google.com> |
Fix dependencies for llc/ARMAsmPrinter.
We were incorrectly pulling the source file in from a subdirectory and
not using the appropriate static library to build llc.
Change-Id: Id5512a918f66e437c36a2cc737795f05173f8b25
ndroid.mk
|
| fe88aa0d148510e41bc3080dea4febcb1445855c |
26-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Make sure the FastLowerArguments function checks to make sure the
arguments type is a simple type.
rdar://13290455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176066 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1e8ed2537b3e4b2175cd9e62626f07606c62cfa0 |
23-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Convenience aliases for 'srs*' instructions.
Handle an implied 'sp' operand.
rdar://11466783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 29e05fe7a885bd03d8570d2bcf14193013776bcd |
22-Feb-2013 |
Kristof Beyls <kristof.beyls@arm.com> |
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameLowering.cpp
RMFrameLowering.h
humb1FrameLowering.cpp
humb1FrameLowering.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| b300455b5817f099d64aad8f9356e0e23fa9a87e |
21-Feb-2013 |
Evan Cheng <evan.cheng@apple.com> |
Radar numbers don't belong in source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175775 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| cb2ae3d98e3bb36e5813f8f69b00d39efd026dcd |
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
MCParser: Update method names per coding guidelines.
s/AddDirectiveHandler/addDirectiveHandler/
s/ParseMSInlineAsm/parseMSInlineAsm/
s/ParseIdentifier/parseIdentifier/
s/ParseStringToEndOfStatement/parseStringToEndOfStatement/
s/ParseEscapedString/parseEscapedString/
s/EatToEndOfStatement/eatToEndOfStatement/
s/ParseExpression/parseExpression/
s/ParseParenExpression/parseParenExpression/
s/ParseAbsoluteExpression/parseAbsoluteExpression/
s/CheckForValidSection/checkForValidSection/
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175675 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| af3a5420aeb421e83694745c53141683caa123cb |
20-Feb-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix thumbv5e frame lowering assertion failure.
It is possible that frame pointer is not found in the
callee saved info, thus FramePtrSpillFI may be incorrect
if we don't check the result of hasFP(MF).
Besides, if we enable the stack coloring algorithm, there
will be an assertion to ensure the slot is live. But in
the test case, %var1 is not live in the prologue of the
function, and we will get the assertion failure.
Note: There is similar code in ARMFrameLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175616 91177308-0d34-0410-b5e6-96231b3b80d8
humb1FrameLowering.cpp
|
| 909a0e0e95e2b96f5d07d40fb53c5892bea20f83 |
19-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM NEON: Don't need COPY_TO_REGCLASS in pattern
In my previous commit:
"Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers."
I added a pattern containing a copy_to_regclass. The copy_to_regclass is
actually not needed.
radar://13191881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175555 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4fd4c91c40fa40ae4cd671b03056de8c3c961046 |
19-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Allocation hints must make sure to be in the alloc order.
When creating an allocation hint for a register pair, make sure the hint
for the physical register reference is still in the allocation order.
rdar://13240556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175541 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 26a5c4dd3176a7e3a7cc9601d32ccad8f41d3104 |
19-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Make ARMAsmPrinter pass name more precise and fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175527 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.h
|
| 2e750c12e91ab09949ef1617ab3af14e1b6cd239 |
19-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.
The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.
radar://13191881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175520 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 848c25ddfa8530fd9349bdf5ed8a8633f27eb388 |
18-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Remove an invalid assert.
If the memcpy has an odd length with an alignment of 2, this would incorrectly
assert on the last 1 byte copy.
rdar://13202135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175459 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b26f98fa1f098b527cc84ef7535fe84d89953c21 |
16-Feb-2013 |
Renato Golin <renato.golin@linaro.org> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175371 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 901d80065c9afa0ba33e8546c2e1e99a00aceb14 |
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget so that they can be reset with the new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| ba6867d0ce3de9b7b4385f98d215edfcd36c4b32 |
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Temporary revert of 175320.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 9be8b4fc92e1ace819a78db512c1f945c1471be7 |
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 4788d14b484ba9e2fe19855fd6c97a3659980fca |
15-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Support changing the subtarget features in ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175315 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 48e841d41c57712f4d6a94b1123f198bdf0bda7d |
15-Feb-2013 |
Joel Jones <joel_k_jones@apple.com> |
The ARM NEON vector compare instructions take three arguments. However, the
assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.
This patch uses TwoOperandAliasConstraint to add the two argument form.
It also fixes an 80-column formatting problem in:
test/MC/ARM/neon-bitwise-encoding
<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 7248451c4307c05cf3ddfa8133f0c5334bab6455 |
14-Feb-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM
Update test case to use -mtriple=arm-linux-gnueabi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
|
| b1d081230e40e5c86f3cc44a7cfd7241732eabfb |
14-Feb-2013 |
Kristof Beyls <kristof.beyls@arm.com> |
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c0c2816fb3d137c096d0bd20b8ad2d92ce25a976 |
14-Feb-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
temporarily revert the patch due to some conflicts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
|
| 3019fbbe6ab4c23a5a580f0cc6ba1ba1b124e1da |
13-Feb-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
|
| e68542e67e5c0f8d4bbdae0dde6ccd24525a18e3 |
13-Feb-2013 |
David Peixotto <dpeixott@codeaurora.org> |
Test commit. Fixed typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175020 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6851623c54b35673f6e9a0ed0fd12378c93f48c4 |
12-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Add vector reverse shuffle costs
A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad
word).
radar://13171406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174933 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| d9316dacf5bb8c02631f782c7f2fc24fb8d788f3 |
12-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM NEON: Handle v16i8 and v8i16 reverse shuffles
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.
uint8_t Arr[N];
for (i = 0; i < N; ++i)
Arr[N - i - 1] = ...
radar://13171760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 092e5e75661fdd5d54a748fb00fab59d21031268 |
11-Feb-2013 |
Evan Cheng <evan.cheng@apple.com> |
Currently, codegen may spent some time in SDISel passes even if an entire
function is successfully handled by fast-isel. That's because function
arguments are *always* handled by SDISel. Introduce FastLowerArguments to
allow each target to provide hook to handle formal argument lowering.
As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle
functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It
completely eliminates the need for SDISel for trivial functions.
rdar://13163905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174855 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fb55a8fd7c38aa09d9c243d48a8a72d890f36a3d |
08-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Address computation in vector mem ops not free
Adds a function to target transform info to query for the cost of address
computation. The cost model analysis pass now also queries this interface.
The code in LoopVectorize adds the cost of address computation as part of the
memory instruction cost calculation. Only there, we know whether the instruction
will be scalarized or not.
Increase the penality for inserting in to D registers on swift. This becomes
necessary because we now always assume that address computation has a cost and
three is a closer value to the architecture.
radar://13097204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174713 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 66f535a273e52d56199c7ce8f975796017b6cbb2 |
07-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Add costs for vector selects
Vector selects are cheap on NEON. They get lowered to a vbsl instruction.
radar://13158753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 5bc79cc4e833fea68f15780f191cbf4881679646 |
06-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Use MCTargetAsmParser::validateTargetOperandClass().
Use the validateTargetOperandClass() hook to match literal '#0' operands in
InstAlias definitions. Previously this required per-instruction C++ munging of the
operand list, but not is handled as a natural part of the matcher. Much better.
No additional tests are required, as the pre-existing tests for these instructions
exercise the new behaviour as being functionally equivalent to the old.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174488 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fc7432744476281511704c7e07bf89e20c215601 |
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to ARM return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174406 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMInstrInfo.td
|
| e2d5590c33f1b5203c0104c1c82bf8e0f28b828e |
05-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Cost for scalar integer casts and floating point conversions
Also adds some costs for vector integer float conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174371 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| a7ad84851b018602487779d97195bad0536f9a7a |
04-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM cost model: Penalize insertelement into D subregisters
Swift has a renaming dependency if we load into D subregisters. We don't have a
way of distinguishing between insertelement operations of values from loads and
other values. Therefore, we are pessimistic for now (The performance problem
showed up in example 14 of gcc-loops).
radar://13096933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174300 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 27aacedf7d975243170206efb948a20d6fd4a2c1 |
01-Feb-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch the code added in r173885 to use the new, shiny RTTI
infrastructure on MCStreamer to test for whether there is an
MCELFStreamer object available.
This is just a cleanup on the AsmPrinter side of things, moving ad-hoc
tests of random APIs to a direct type query. But the AsmParser
completely broken. There were no tests, it just blindly cast its
streamer to an MCELFStreamer and started manipulating it.
I don't have a test case -- this actually failed on LLVM's own
regression test suite. Unfortunately the failure only appears when the
stars, compilers, and runtime align to misbehave when we read a pointer
to a formatted_raw_ostream as-if it were an MCAssembler. =/
UBSan would catch this immediately.
Many thanks to Matt for doing about 80% of the debugging work here in
GDB, Jim for helping to explain how exactly to fix this, and others for
putting up with the hair pulling that ensued during debugging it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174118 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmParser.cpp
|
| 5da3665cc501ed8928e63678254357214ec0b9eb |
01-Feb-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Give the MCStreamer class hierarchy LLVM RTTI facilities for use with
isa<> and dyn_cast<>. In several places, code is already hacking around
the absence of this, and there seem to be several interfaces that might
be lifted and/or devirtualized using this.
This change was based on a discussion with Jim Grosbach about how best
to handle testing for specific MCStreamer subclasses. He said that this
was the correct end state, and everything else was too hacky so
I decided to just make it so.
No functionality should be changed here, this is just threading the kind
through all the constructors and setting up the classof overloads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174113 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 108fb3202af6f500073cdbb7be32c25d7a273a2e |
31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 72062f5744557e270a38192554c3126ea5f97434 |
31-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCExpr.h
|
| 0f156af8312a0f3ce88e5c006bf2a52691039ceb |
30-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMFastISel.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 620d5bd8e43331a9b5ba2437c1de0d3f4a43a34d |
30-Jan-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Add missing header and test cases for r173939.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173941 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMUnwindOp.h
|
| 52b1b3bbc6c8a7c7e5669e3169984a48b3f1a4b3 |
30-Jan-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Override virtual function for ARM EH directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173939 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 97130e2b3de080e231caac86dbce1500e4e7af16 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch implements runtime ARM specific
setting of ELF header e_flags.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmParser.cpp
|
| 9a7bf438b50fed2c77f0e2bc835defa5b4728f82 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch reworks how llvm targets set
and update ELF header e_flags.
Currently gathering information such as symbol,
section and data is done by collecting it in an
MCAssembler object. From MCAssembler and MCAsmLayout
objects ELFObjectWriter::WriteObject() forms and
streams out the ELF object file.
This patch just adds a few members to the MCAssember
class to store and access the e_flag settings. It
allows for runtime additions to the e_flag by
assembler directives. The standalone assembler can
get to MCAssembler from getParser().getStreamer().getAssembler().
This patch is the generic infrastructure and will be
followed by patches for ARM and Mips for their target
specific use.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| 0261cea689c71a15175faf37fdc6bd1d9f69c46e |
30-Jan-2013 |
Renato Golin <renato.golin@linaro.org> |
Adding simple cast cost to ARM
Changing ARMBaseTargetMachine to return ARMTargetLowering intead of
the generic one (similar to x86 code).
Tests showing which instructions were added to cast when necessary
or cost zero when not. Downcast to 16 bits are not lowered in NEON,
so costs are not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173849 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.h
RMTargetTransformInfo.cpp
|
| 0adfdedacbb87df8cc8b8311365a15fae004977e |
29-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Fix 64-bit atomic operations in Thumb mode.
The ARM and Thumb variants of LDREXD and STREXD have different constraints and
take different operands. Previously the code expanding atomic operations didn't
take this into account and asserted in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4a9256f265a7fcccd1f04518b55fd751f3a920a8 |
25-Jan-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3aef70314b053a1df4f85ca4a6f3890d06ebbdd6 |
09-Jan-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r171905.
Android.mk
lib/Analysis/Android.mk
lib/CodeGen/Android.mk
lib/CodeGen/MachineScheduler.cpp - specify std::pop_heap()
lib/IR/Android.mk - new from lib/VMCore
lib/MC/Android.mk
lib/MC/MCAssembler.cpp - put back pointer param (from reference).
lib/Support/DeltaAlgorithm.cpp - iterator -> const_iterator !
lib/TableGen/Android.mk
lib/Target/ARM/ARMJITInfo.cpp - Removed unused legacy JIT changes
lib/Target/ARM/Android.mk
lib/Target/ARM/AsmParser/Android.mk
lib/Target/ARM/Disassembler/Android.mk
lib/Target/ARM/MCTargetDesc/Android.mk
lib/Target/Android.mk
lib/Target/Mips/Android.mk
lib/Target/Mips/Disassembler/Android.mk
lib/Target/Mips/MCTargetDesc/Android.mk
lib/Target/X86/Android.mk
lib/Target/X86/AsmParser/Android.mk
lib/Target/X86/Disassembler/Android.mk
lib/Transforms/IPO/Android.mk
lib/Transforms/Instrumentation/Android.mk
lib/Transforms/Scalar/Android.mk
lib/Transforms/Utils/Android.mk
lib/Transforms/Vectorize/Android.mk
lib/VMCore/Android.mk - moved to lib/IR
llvm-gen-intrinsics.mk - new Intrinsics.td location
utils/TableGen/Android.mk
Change-Id: Ifebdb1716c372fd917a844c44be9d10df66434b0
RMJITInfo.cpp
ndroid.mk
smParser/Android.mk
isassembler/Android.mk
CTargetDesc/Android.mk
|
| 059800f9e3fee2852672f846d91a2da14da7783a |
21-Jan-2013 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/master' into merge-llvm
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/MC/MCAssembler.cpp
lib/Support/Atomic.cpp
lib/Support/Memory.cpp
lib/Target/ARM/ARMJITInfo.cpp
Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
|
| 19d54337169ae4af2d44ae39664d0bac1ae0309c |
14-Jan-2013 |
Quentin Colombet <qcolombet@apple.com> |
Follow up of commit r172472.
Refactor the big if/else sequence into one string switch for ARM subtype selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172475 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 398db9368d72d1d60d40b2e18c16ca2c14aa7f39 |
14-Jan-2013 |
Quentin Colombet <qcolombet@apple.com> |
Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively cortex-m0, cortex-m3, and cortex-m4 on the backend side.
Adds new subtype values for the MachO format and use them when the related triple are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172472 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 5573de8493ac11564fba02b7407176a98b45d7ce |
09-Jan-2013 |
Joel Jones <joel_k_jones@apple.com> |
Fix description of ARMOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172011 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 14925e6b885f8bd8cf448627386d412831f4bf1b |
09-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172010 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 1ced208be9cab0f994c5df9000da36bc313b2507 |
09-Jan-2013 |
Eric Christopher <echristo@gmail.com> |
Last in the series of removing unnecessary '0' arguments for
address space. Reordered the EmitULEB128IntValue arguments to
make this easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171949 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmParser.cpp
|
| 47579cf390c42e0577519e0a2b6044baece9df00 |
09-Jan-2013 |
Andrew Trick <atrick@apple.com> |
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.
I converted some in-order scheduling tests to A2. Hal is working on
more test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 68ca56285f9b6e82eb16ff8ea02a301f2c489fae |
09-Jan-2013 |
Eric Christopher <echristo@gmail.com> |
These functions have default arguments of 0 for the last arg. Use
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171933 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 83be7b0dd3ae9a3cb22d36ae4c1775972553b94b |
09-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Cost Model: Move the 'max unroll factor' variable to the TTI and add initial Cost Model support on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171928 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| 251040bc18eedfa56d01fe92836e55cfd8c5d990 |
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 00b53c1ad717056e4f0e06a93d907b09ba1e5154 |
07-Jan-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Copy-paste error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171790 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.h
|
| 54f2187eacaa962fe9b25708c9ea01ec2b19dba3 |
07-Jan-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fix a few copy-paste errors.
s/X86/ARM/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171789 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
|
| 3ebe59c892051375623fea55e977ff559fdb3323 |
07-Jan-2013 |
Jordan Rose <jordan_rose@apple.com> |
Change SMRange to be half-open (exclusive end) instead of closed (inclusive)
This is necessary not only for representing empty ranges, but for handling
multibyte characters in the input. (If the end pointer in a range refers to
a multibyte character, should it point to the beginning or the end of the
character in a char array?) Some of the code in the asm parsers was already
assuming this anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171765 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0c63e64af6b2b25f44e33dcdf0b42968cbd0a581 |
07-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add LICENSE.TXT covering contributions made by ARM.
Absent a Contributor's License Agreement (CLA) with an LLVM legal entity and as
reviewed and agreed with Chris Lattner, add a patent license covering future
contributions from ARM until there is a CLA. This is to make explicit ARM's
grant of patent rights to recipients of LLVM containing ARM-contributed
material.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171721 91177308-0d34-0410-b5e6-96231b3b80d8
ICENSE.TXT
|
| be04929f7fd76a921540e9901f24563e51dc1219 |
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move TargetTransformInfo to live under the Analysis library. This no
longer would violate any dependency layering and it is in fact an
analysis. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171686 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetTransformInfo.cpp
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelLowering.cpp
RMISelLowering.h
RMTargetMachine.cpp
RMTargetMachine.h
RMTargetTransformInfo.cpp
MakeLists.txt
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCallingConv.h
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMMCInstLower.cpp
RMSelectionDAGInfo.cpp
RMSubtarget.cpp
RMTargetMachine.h
argetInfo/ARMTargetInfo.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 58a2cbef4aac9ee7d530dfb690c78d6fc11a2371 |
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.
Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
humb2SizeReduction.cpp
|
| 8b62abdd7b9c8fc5d78dad86093f4afdfeba949d |
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
humb2SizeReduction.cpp
|
| 791dbb3e5fbe5910b84e3f2bd26cf272e2bde128 |
24-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Use a std::string rather than a dynamically allocated char* buffer.
This affords us to use std::string's allocation routines and use the destructor
for the memory management. Switching to that also means that we can use
operator==(const std::string&, const char *) to perform the string comparison
rather than resorting to libc functionality (i.e. strcmp).
Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171042 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 4e23ebe7665f2e03c0bb8db3ae5ab90eb0f724e5 |
21-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C++ style casts.
Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170917 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
|
| 38b06020dbd804f01ee3802779a52c05cffdf87d |
21-Dec-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove duplicate includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170902 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| e0f1d712f656d3f958b616013f1d6008c5678949 |
21-Dec-2012 |
Quentin Colombet <qcolombet@apple.com> |
Add ARM cortex-r5 subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170840 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| be06aacaa9a270384599bbfa850b967e9996b9fb |
20-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to MI::copyImplicitOps().
This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.
Also add a corresponding MachineInstrBuilder method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMLoadStoreOptimizer.cpp
humb1FrameLowering.cpp
|
| b9efafe54d61e85ca5209c4043aa814f89785195 |
20-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
MachineInstrBuilderize ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170795 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 103b4a571ef01e4717c3c6d9db6506a3abd6cc0b |
20-Dec-2012 |
Bob Wilson <bob.wilson@apple.com> |
Revert "Adding support for llvm.arm.neon.vaddl[su].* and"
This reverts r170694. The operations can be represented in IR without
adding any new intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170765 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 139e407d526193017d42473c8d4892933de78f14 |
20-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,
are more expensive than the non-flag setting variant. Teach thumb2 size
reduction pass to avoid generating them unless we are optimizing for size.
rdar://12892707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
humb2SizeReduction.cpp
|
| 6af228a92a7b8414fa3c1b3c37ee659d32e66e1b |
20-Dec-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove MCTargetAsmLexer and its derived classes now that edis,
its only user, is gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170699 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
smParser/CMakeLists.txt
|
| 332bd799512142e23d35105483520acbffff72c8 |
20-Dec-2012 |
Renato Golin <rengolin@systemcall.org> |
Adding support for llvm.arm.neon.vaddl[su].* and
llvm.arm.neon.vsub[su].* intrinsics.
Patch by Pete Couperus <pjcoup@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170694 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| fbf3b4a07690751f72302757058ab0298dfb832e |
20-Dec-2012 |
Jim Grosbach <grosbach@apple.com> |
MC: Add MCInstrDesc::mayAffectControlFlow() method.
MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 37a942cd52725b1d390989a8267a764b42fcb5d3 |
19-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the explicit MachineInstrBuilder(MI) constructor.
Use the version that also takes an MF reference instead.
It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.
Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 733c6b1db1a9a3f78da4fece933ccc7e509bfba0 |
19-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
LLVM sdisel normalize bit extraction of the form:
((x & 0xff00) >> 8) << 2
to
(x >> 6) & 0x3fc
This is general goodness since it folds a left shift into the mask. However,
the trailing zeros in the mask prevents the ARM backend from using the bit
extraction instructions. And worse since the mask materialization may require
an addition instruction. This comes up fairly frequently when the result of
the bit twiddling is used as memory address. e.g.
= ptr[(x & 0xFF0000) >> 16]
We want to generate:
ubfx r3, r1, #16, #8
ldr.w r3, [r0, r3, lsl #2]
vs.
mov.w r9, #1020
and.w r2, r9, r1, lsr #14
ldr r2, [r0, r2]
Add a late ARM specific isel optimization to
ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the
'base + offset' address computation; change the mask to one which doesn't have
trailing zeros and enable the use of ubfx.
Note the optimization has to be done late since it's target specific and we
don't want to change the DAG normalization. It's also fairly restrictive
as shifter operands are not always free. It's only done for lsh 1 / 2. It's
known to be free on some cpus and they are most common for address
computation.
This is a slight win for blowfish, rijndael, etc.
rdar://12870177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 759e3fa641d0ad01012d16d913015c9f69c8d2ab |
19-Dec-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove edis - the enhanced disassembler. Fixes PR14654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
isassembler/ARMDisassembler.cpp
akefile
|
| 0340557fb830e3669c4c48a2cd99d7703bdda452 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
humb2SizeReduction.cpp
|
| b519351b87204966d6548b198b88f2ab0f4d0b4b |
18-Dec-2012 |
Quentin Colombet <qcolombet@apple.com> |
Disable ARM partial flag dependency optimization at -Oz
To not over constrain the scheduler for ARM in thumb mode, some optimizations for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency).
Disables this check when code size is the priority, i.e., code is compiled with -Oz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170462 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| bcc9a89c16269cead71ba1f7063a8fb83fb8f57f |
18-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Repair bundles that were broken by removing and reinserting the first
instruction.
This isn't strictly necessary at the moment because Thumb2SizeReduction
also copies all MI flags from the old instruction to the new. However, a
future patch will make that kind of direct flag tampering illegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170395 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 8413d2c70fe9c6b6edc1037c4bab3c42fe4b0f5d |
18-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Extract a method, no functional change intended.
Sadly, this costs us a perfectly good opportunity to use 'goto'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170385 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 6290b936bf71fded40b8b765f8f7aef577fada24 |
17-Dec-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Minor cleanup. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170379 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 316a5aa0a510e6183dd1981dd8bf328ffe7361f5 |
17-Dec-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Fast-isel only handles simple VTs, so make sure the necessary
checks are in place. Some minor cleanup as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170360 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3d170e64ca1af491e2aa58f882f93b8e8111eef8 |
17-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert/correct some FastISel changes in r170104 (EVT->MVT for
TargetLowering::getRegClassFor).
Some isSimple() guards were missing, or getSimpleVT() were hoisted too
far, resulting in asserts on valid LLVM assembly input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170336 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a827a47923700c16256036ca0bda8c0ff6108fdb |
15-Dec-2012 |
Kevin Enderby <enderby@apple.com> |
Make sure the alternate PC+imm syntax of LDR instruction with a small
immediate generates the narrow version. Needed when doing round-trip
assemble/disassemble testing using the alternate syntax that specifies
'pc' directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a61b17c18a67f1b3faef2f2108379c4337ce9bb7 |
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170104 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 37c7461fc3f1983a81bfe934855d707fd6572e78 |
12-Dec-2012 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Add ARM NONE and PREL31 relocation types.
Add R_ARM_NONE and R_ARM_PREL31 relocation types
to MCExpr. Both of them will be used while
generating .ARM.extab and .ARM.exidx sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169965 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 7d34267df63e23be1957f738de783c145febb7af |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 61f4dfe3693bf68b20748d82ac4dd9bf2f356699 |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e202f8c3eeff6948f5df97958e243480020295cc |
12-Dec-2012 |
Jim Grosbach <grosbach@apple.com> |
Trim unneeded header #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169933 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c8cd8aa9d8582d2632db8fee8b2932efcdec34f1 |
12-Dec-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Remove old testing option.
Pre-regalloc frame allocation and referencing has been on by default
for ages. No need for the testing option that disables it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169931 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 48aa2cf76da5f9354f84329de798e00cbe7206da |
12-Dec-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Remove old testing options.
Base pointer referencing has been enabled for ages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169930 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e07f85eb76a0254d3adbdf8b5d61ff5c07858cef |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace TargetLowering::isIntImmLegal() with
ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined
term for something like integer immediate materialization. It is always possible
to materialize an integer immediate. Whether to use it for memcpy expansion is
more a "cost" conceern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169929 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMTargetMachine.h
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| bade0345d190427a08b2b947bc94f4d8ca5d7717 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 8163ca76f0b0d336c5436364ffb3b85be1162e7a |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 6a1b5cc7c60d54608bbe579b06497b7ade42dbc8 |
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Stylistic tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 425e951734c3a0615e22ec94ffa51cc16ce6e483 |
11-Dec-2012 |
Chad Rosier <mcrosier@apple.com> |
Fall back to the selection dag isel to select tail calls.
This shouldn't affect codegen for -O0 compiles as tail call markers are not
emitted in unoptimized compiles. Testing with the external/internal nightly
test suite reveals no change in compile time performance. Testing with -O1,
-O2 and -O3 with fast-isel enabled did not cause any compile-time or
execution-time failures. All tests were performed on my x86 machine.
I'll monitor our arm testers to ensure no regressions occur there.
In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue
and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While
it's theoretically true that this is just an optimization, it's an
optimization that we very much want to happen even at -O0, or else ARC
applications become substantially harder to debug.
Part of rdar://12553082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrThumb2.td
|
| 0c66e07863f2bcb054ffc4d58ae30a048b7406c7 |
08-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify code. Sort includes. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169676 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 0956ae5ac2d5fac56248a03a9dd8caa398a39cc5 |
08-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Fix a use-after-free bug found by ASan. You can't assign a temporary
std::string to a StringRef. Moreover, the method being called accepts
a Twine to simplify these patterns.
Fixes this ASan failure:
==6312== ERROR: AddressSanitizer: heap-use-after-free on address 0x7fd558b1af58 at pc 0xcb7529 bp 0x7fffff572080 sp 0x7fffff572078
READ of size 1 at 0x7fd558b1af58 thread T0
#0 0xcb7528 .../llvm/include/llvm/ADT/StringRef.h:192 llvm::StringRef::operator[]()
#1 0x1d53c0a .../llvm/include/llvm/ADT/StringExtras.h:128 llvm::HashString()
#2 0x1d53878 .../llvm/lib/Support/StringMap.cpp:64 llvm::StringMapImpl::LookupBucketFor()
#3 0x1b6872f .../llvm/include/llvm/ADT/StringMap.h:352 llvm::StringMap<>::GetOrCreateValue<>()
#4 0x1b61836 .../llvm/lib/MC/MCContext.cpp:109 llvm::MCContext::GetOrCreateSymbol()
#5 0xe9fd47 .../llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp:154 (anonymous namespace)::ARMELFStreamer::EmitMappingSymbol()
#6 0xea01dd .../llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp:133 (anonymous namespace)::ARMELFStreamer::EmitDataMappingSymbol()
#7 0xe9f78b .../llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp:91 (anonymous namespace)::ARMELFStreamer::EmitBytes()
#8 0x1b15d82 .../llvm/lib/MC/MCStreamer.cpp:89 llvm::MCStreamer::EmitIntValue()
#9 0xcc0f9b .../llvm/lib/Target/ARM/ARMAsmPrinter.cpp:713 llvm::ARMAsmPrinter::emitAttributes()
#10 0xcc0d44 .../llvm/lib/Target/ARM/ARMAsmPrinter.cpp:632 llvm::ARMAsmPrinter::EmitStartOfAsmFile()
#11 0x14692ad .../llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:162 llvm::AsmPrinter::doInitialization()
#12 0x1bc4677 .../llvm/lib/VMCore/PassManager.cpp:1561 llvm::FPPassManager::doInitialization()
#13 0x1bc4990 .../llvm/lib/VMCore/PassManager.cpp:1595 llvm::MPPassManager::runOnModule()
#14 0x1bc55e5 .../llvm/lib/VMCore/PassManager.cpp:1705 llvm::PassManagerImpl::run()
#15 0x1bc5878 .../llvm/lib/VMCore/PassManager.cpp:1740 llvm::PassManager::run()
#16 0xc3954d .../llvm/tools/llc/llc.cpp:378 compileModule()
#17 0xc38001 .../llvm/tools/llc/llc.cpp:194 main
#18 0x7fd557d6a11c __libc_start_main
0x7fd558b1af58 is located 24 bytes inside of 29-byte region [0x7fd558b1af40,0x7fd558b1af5d)
freed by thread T0 here:
#0 0xc337da .../llvm/projects/compiler-rt/lib/asan/asan_new_delete.cc:56 operator delete()
#1 0x1ee9cef .../libstdc++-v3/include/bits/basic_string.h:535 std::string::~string()
#2 0xea01dd .../llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp:133 (anonymous namespace)::ARMELFStreamer::EmitDataMappingSymbol()
#3 0xe9f78b .../llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp:91 (anonymous namespace)::ARMELFStreamer::EmitBytes()
#4 0x1b15d82 .../llvm/lib/MC/MCStreamer.cpp:89 llvm::MCStreamer::EmitIntValue()
#5 0xcc0f9b .../llvm/lib/Target/ARM/ARMAsmPrinter.cpp:713 llvm::ARMAsmPrinter::emitAttributes()
#6 0xcc0d44 .../llvm/lib/Target/ARM/ARMAsmPrinter.cpp:632 llvm::ARMAsmPrinter::EmitStartOfAsmFile()
#7 0x14692ad .../llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:162 llvm::AsmPrinter::doInitialization()
#8 0x1bc4677 .../llvm/lib/VMCore/PassManager.cpp:1561 llvm::FPPassManager::doInitialization()
#9 0x1bc4990 .../llvm/lib/VMCore/PassManager.cpp:1595 llvm::MPPassManager::runOnModule()
#10 0x1bc55e5 .../llvm/lib/VMCore/PassManager.cpp:1705 llvm::PassManagerImpl::run()
#11 0x1bc5878 .../llvm/lib/VMCore/PassManager.cpp:1740 llvm::PassManager::run()
#12 0xc3954d .../llvm/tools/llc/llc.cpp:378 compileModule()
#13 0xc38001 .../llvm/tools/llc/llc.cpp:194 main
#14 0x7fd557d6a11c __libc_start_main
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169668 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
|
| 6eb3e87df04f8b035562d9865292c23f5b79f1a2 |
07-Dec-2012 |
Tim Northover <Tim.Northover@arm.com> |
Added Mapping Symbols for ARM ELF
Before this patch, when you objdump an LLVM-compiled file, objdump tried to
decode data-in-code sections as if they were code. This patch adds the missing
Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D).
Patch based on work by Greg Fitzgerald.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169609 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFStreamer.cpp
CTargetDesc/ARMELFStreamer.h
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/CMakeLists.txt
|
| c4e8ddff0c29bfc2eb1d5bf13e947bd04d4454ff |
07-Dec-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Add a 'using' declaration to suppress GCC's -Woverloaded-virtual while we
decide what pattern we want to follow in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169561 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 2766a47310b05228e9bbc536d9f3a593fc31cd12 |
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace r169459 with something safer. Rather than having computeMaskedBits to
understand target implementation of any_extend / extload, just generate
zero_extend in place of any_extend for liveouts when the target knows the
zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169536 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c9758b13668013dea491a08b4f0c9256263927c2 |
06-Dec-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Make the fast-isel implementation of memcpy respect alignment.
rdar://12821569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169460 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8a7186dbc2df4879f511b2ae6f2bce25ad37d965 |
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
%tmp2 = load i16* %ptr, align 2
br label %bb2
bb2:
%tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
%cmp = icmp ult i16 %tmp3, 24
br i1 %cmp, label %bb3, label %exit
bb3:
call void @bar() nounwind
br label %exit
exit:
ret void
}
This compiles to the followings before:
push {lr}
mov r2, #0
cmp r1, #99
bhi LBB0_2
@ BB#1: @ %bb1
ldrh r2, [r0]
LBB0_2: @ %bb2
uxth r0, r2
cmp r0, #23
bhi LBB0_4
@ BB#3: @ %bb3
bl _bar
LBB0_4: @ %exit
pop {lr}
bx lr
The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| f2a1c83c86ceefb9a241aa728d1d1239a64b894e |
05-Dec-2012 |
David Sehr <sehr@google.com> |
Correct ARM NOP encoding
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which
causes the emission of a coprocessor instruction rather than "mov r0, r0"
as indicated in the comment. The test also checks for the wrong encoding.
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169420 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 14ccc9007a932a23201251ced4be4c898a62d6a5 |
05-Dec-2012 |
Kevin Enderby <enderby@apple.com> |
Added a option to the disassembler to print immediates as hex.
This is for the lldb team so most of but not all of the values are
to be printed as hex with this option. Some small values like the
scale in an X86 address were requested to printed in decimal
without the leading 0x.
There may be some tweaks need to places that may still be in
decimal that they want in hex. Specially for arm. I made my best
guess. Any tweaks from here should be simple.
I also did the best I know now with help from the C++ gurus
creating the cleanest formatImm() utility function and containing
the changes. But if someone has a better idea to make something
cleaner I'm all ears and game for changing the implementation.
rdar://8109283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 105ab4fe4bffcaf339e4943b98c6155a0883284a |
05-Dec-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Appease GCC's -Wparentheses.
(TIL that Clang's -Wparentheses ignores 'x || y && "foo"' on purpose. Neat.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169337 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c8e7045c8a3b3fb9ee8f4a7d4d4a52a46b3d420a |
04-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
ARM custom lower ctpop for vector types. Patch by Pete Couperus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169325 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f659c0de6c7a4684a2a30c344ce6827ea87032d8 |
04-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Make NaCl naming consistent. The triple OSType is called NaCl and is represented
textually as NativeClient. Also added a link to the native client project for
readers unfamiliar with it.
A Clang patch will follow shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169291 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| a1514e24cc24b050f53a12650e047799358833a1 |
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMISelLowering.h
RMJITInfo.h
RMMachineFunctionInfo.h
RMSubtarget.h
RMTargetMachine.h
|
| f71415646053e66f8a5b63a74ac06287eeab53d5 |
04-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.
These functions have been replaced by TRI::getRegAllocationHints() which
provides the same capabilities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 303da1baf2a90d18a709f29f4f7cd0e1962be5f9 |
03-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement ARMBaseRegisterInfo::getRegAllocationHints().
This provides the same functionality as getRawAllocationOrder() for the
even/odd hints, but without the many constant register arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169169 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMMCInstLower.cpp
RMSelectionDAGInfo.cpp
RMSubtarget.cpp
RMTargetMachine.cpp
RMTargetObjectFile.cpp
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCExpr.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMachObjectWriter.cpp
LxExpansionPass.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2ITBlockPass.cpp
humb2RegisterInfo.cpp
humb2SizeReduction.cpp
|
| cb4953089bb845afedeaaf5dfd03d8d5639fd656 |
30-Nov-2012 |
Sebastian Pop <spop@codeaurora.org> |
Codegen failure for vmull with small vectors
Codegen was failing with an assertion because of unexpected vector
operands when legalizing the selection DAG for a MUL instruction.
The asserting code was legalizing multiplies for vectors of size 128
bits. It uses a custom lowering to try and detect cases where it can
use a VMULL instruction instead of a VMOVL + VMUL. The code was
looking for input operands to the MUL that had been sign or zero
extended. If it found the extended operands it would drop the
sign/zero extension and use the original vector size as input to a
VMULL instruction.
The code assumed that the original input vector was 64 bits so that
after dropping the extension it would fit directly into a D register
and could be used as an operand of a VMULL instruction. The input
code that trigger the failure used a vector of <4 x i8> that was
sign extended to <4 x i32>. It was not safe to drop the sign
extension in this case because the original vector is only 32 bits
wide. The fix is to insert a sign extension for the vector to reach
the required 64 bit size. In this particular example, the vector would
need to be sign extented to a <4 x i16>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169024 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1c83093cd5f4f6d33e732c817bb5afd033531beb |
30-Nov-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
which would then cause an assert when printed. rdar://11437956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 8facb9ecf21fc97409121842882dbc1dfd87b944 |
29-Nov-2012 |
Quentin Colombet <qcolombet@apple.com> |
Add cortex-a5 subtarget to the supported ARM architectures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168933 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 35b3df6e31f9aac70fb471d74e39f899dfbd689f |
29-Nov-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 350c00843bad22c5391e33e9e39a78d5d0983c8c |
28-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Implement CanLowerReturn so large vectors get expanded into sret.
Fixes 14337.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| a9fa4fd9736f7d1066223f32fa54efbe86c0fceb |
28-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove all references to TargetInstrInfoImpl.
This class has been merged into its super-class TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb2InstrInfo.cpp
|
| 6e99a8cb37916dbd2fcc9d150fee006d383a4c54 |
27-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Appease the machine verifier by using the proper register
classes. The vast majority of the remaining issues are due to uses of
invalid registers, which are defined by getRegForValue(). Those will be
a little more challenging to cleanup.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168735 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b1146a242c423a1f703ccdf75f1a7c6649d60f72 |
27-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Appease the machine verifier by using the proper register
classes.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168733 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ac3158b5718ad724a02694c9f1c08bbfaf5fec11 |
27-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Appease the machine verifier by using the proper register
classes. Also a bit of cleanup.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168728 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fc17ddd889e3dcb608e8e97c4c791755c21d7b14 |
27-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Appease the machine verifier by using the proper register
classes. The associated test case still doesn't pass, but it does have far
fewer issues.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168657 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ed9e442cf098663ce213cb16778b44be466b441f |
26-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Decouple MCInstBuilder from the streamer per Eli's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 391271f3bbcec02e0da26d7c246bfabff5cb4ddf |
26-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder.
Simplify some repetitive code with it. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| cb4028b91d7c1b0163d1b6c85911668d3d19c75a |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Share applyFixup between ELF and Darwin.
The implementations already diverged a bit, merge them back together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168542 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 43147afd71f6da4e7369a4ab9c681e5b4e0cf8c7 |
17-Nov-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8b149cbfc6cb420016eff52f6380d1eba5daea20 |
17-Nov-2012 |
Weiming Zhao <weimingz@codeaurora.org> |
Rename methods like PairSRegs() to createSRegpairNode() to meet our coding
style requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168229 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e56764bad10621ac9dcf9d3541533ff2cb0f88b4 |
16-Nov-2012 |
Weiming Zhao <weimingz@codeaurora.org> |
Remove hard coded registers in ARM ldrexd and strexd instructions
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| b1a392e7c50da5789cf5da879c5b81b72c751c21 |
16-Nov-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make sure FABS on v2f32 and v4f32 is legal on ARM NEON
This fixes PR14359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 846ce8ea67362d8b6d93ebae66f23e3c68dce9df |
15-Nov-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
case to vector legalization so this actually works.
Patch by Pete Couperus. Fixes PR12540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 79c07d2a36282b09b9c5d0aa65ebf4bff017621b |
15-Nov-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Use empty parens for empty function parameter list instead of '(void)'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168049 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
RMISelLowering.h
|
| 116bd168e1dd46ed5b1b46aabfc566128836fb70 |
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Revert changing FNEG of v4f32 to Expand. It's legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168030 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b916904e685208a815a32e1ef24c1b49b3abb0cd |
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Make FNEG and FABS of v4f32 Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168029 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 490104720db9e1e0eb9cc27e88e2d7288ac27ff0 |
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 50b66387e3eda89ba0097fedc237e41eac5d6808 |
14-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number.
This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.
rdar://12028498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 25efd6d556718295a63d37f5294985746af354f6 |
14-Nov-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TARGET2 relocation for TType references on ARM.
Do some cleanup of the code while here.
Inspired by patch by Logan Chien!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| 9b5caaa9c452f262a52dd5ac7ebbc722da5a63de |
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.
A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b341fac05a890272024dcc5c7e47d10b22d62b92 |
10-Nov-2012 |
Evan Cheng <evan.cheng@apple.com> |
Disable the Thumb no-return call optimization:
mov lr, pc
b.w _foo
The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.
rdar://12663632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelLowering.cpp
RMInstrThumb2.td
|
| 12cfa119600418d31ceb748d077b3e6f7057a22a |
09-Nov-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.
Based on the patch by Logan Chien!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167633 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| b3235b128f383559a7a9b9119896e406b347879c |
09-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r167620; this can be implemented using an existing CL option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| d054eda44114df411a2749e7b6b85d27509a0af1 |
09-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Add support for -mstrict-align compiler option for ARM targets.
rdar://12340498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| 214fd3d2449738bbe0215dce24406dc29d9e49f7 |
08-Nov-2012 |
Amara Emerson <amara.emerson@arm.com> |
Recommit modified r167540.
Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 162d91c1e0bf5c14e2838dd623b3e054e7537de6 |
07-Nov-2012 |
Amara Emerson <amara.emerson@arm.com> |
Revert r167540 until regression tests are updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167545 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 19a1fcf8683a2a459a8aac93c1b4d1bf63b018fb |
07-Nov-2012 |
Amara Emerson <amara.emerson@arm.com> |
Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167540 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6aa6e5a2852ad5c83cef5eb52f62f9267e3511ea |
07-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm fast-isel] Appease the machine verifier by using the proper register
classes. For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167508 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e7bd51980a1341fb60322e5922cfcc0c9b92b165 |
07-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers. Previously, the register we being marked as implicitly defined, but
not killed. In some cases this would cause the register scavenger to spill a
dead register.
Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCallingConv.td
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| 43934aee71746576b6e16663f382401b8693c83a |
02-Nov-2012 |
Quentin Colombet <qcolombet@apple.com> |
Vext Lowering was missing opportunities
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167318 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ece6c6bb6329748b92403c06ac87f45c43485911 |
01-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the series of commits starting with r166578 which introduced the
getIntPtrType support for multiple address spaces via a pointer type,
and also introduced a crasher bug in the constant folder reported in
PR14233.
These commits also contained several problems that should really be
addressed before they are re-committed. I have avoided reverting various
cleanups to the DataLayout APIs that are reasonable to have moving
forward in order to reduce the amount of churn, and minimize the number
of commits that were reverted. I've also manually updated merge
conflicts and manually arranged for the getIntPtrType function to stay
in DataLayout and to be defined in a plausible way after this revert.
Thanks to Duncan for working through this exact strategy with me, and
Nick Lewycky for tracking down the really annoying crasher this
triggered. (Test case to follow in its own commit.)
After discussing with Duncan extensively, and based on a note from
Micah, I'm going to continue to back out some more of the more
problematic patches in this series in order to ensure we go into the
LLVM 3.2 branch with a reasonable story here. I'll send a note to
llvmdev explaining what's going on and why.
Summary of reverted revisions:
r166634: Fix a compiler warning with an unused variable.
r166607: Add some cleanup to the DataLayout changes requested by
Chandler.
r166596: Revert "Back out r166591, not sure why this made it through
since I cancelled the command. Bleh, sorry about this!
r166591: Delete a directory that wasn't supposed to be checked in yet.
r166578: Add in support for getIntPtrType to get the pointer type based
on the address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167221 91177308-0d34-0410-b5e6-96231b3b80d8
RMSelectionDAGInfo.cpp
|
| 9a419f656e278b96e9dfe739cd63c7bff9a4e1fd |
30-Oct-2012 |
Quentin Colombet <qcolombet@apple.com> |
Change ForceSizeOpt attribute into MinSize attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167020 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8ba1474181fc3997cc8449d75065e1021c72d49b |
30-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Better disassembly for pc-relative LDR.
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.
rdar://12154503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 445ba85b8d7bc8fb4689ca22131cadc80a034705 |
30-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| 0d91c0b519e0053931bf9502ebeaf44d397812f0 |
28-Oct-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove TargetELFWriterInfo.
All the credit goes to Jan Voung for noticing it was dead!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
RMELFWriterInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
MakeLists.txt
|
| 80acd97266f6f165285ae9303dea9654f87a2a87 |
27-Oct-2012 |
Quentin Colombet <qcolombet@apple.com> |
[code size][ARM] Emit regular call instructions instead of the move, branch sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166854 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 17f42e02a10bd4d43e4ba904c640224de2c48f51 |
27-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."
Keep the integer_insertelement test case, the new coalescer can handle
this kind of lane insertion without help from pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166835 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 61fac6810ff8686c5302dedb35d52cc662a983fe |
27-Oct-2012 |
Kaelyn Uhrain <rikka@google.com> |
Avoid an unused-variable warning when asserts are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166834 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| be5ec8c4b2c1495faef5fd11f212ef1a655538fb |
26-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
80 col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166818 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| b1f994af589af28dead4826d2e58a0138105e452 |
26-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove ARMBaseRegisterInfo::isReservedReg().
It is just as easy to use MRI::isReserved() now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166817 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameLowering.cpp
|
| cd275f5687799e63956beabe35fc1718dc022f70 |
26-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add GPRPair Register class to ARM.
Some instructions in ARM require 2 even-odd paired GPRs. This
patch adds support for such register class.
Patch by Weiming Zhao!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166816 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMRegisterInfo.td
|
| f4a5a613faa1a0eca6b884a6dfe83e8b1eb957b2 |
26-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the canCombineSubRegIndices() target hook.
The new coalescer can already do all of this, so there is no need to
duplicate the efforts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 6a020a71173a3ea7738a9df69982e85ddbfe0303 |
25-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for creating AsmRewrites in the target specific
AsmParser logic. To be used/tested in a subsequent commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166714 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d258eb3ec5cc5c9a28d3a8cd80241c9df24ce3a1 |
24-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a miscompilation caused by a typo. When turning a adde with negative value
into a sbc with a positive number, the immediate should be complemented, not
negated. Also added a missing pattern for ARM codegen.
rdar://12559385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 270483466124fe1e19d5439e958fef63cebd43cd |
24-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| aa76e9e2cf50af190de90bc778b7f7e42ef9ceff |
24-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in support for getIntPtrType to get the pointer type based on the address space.
This checkin also adds in some tests that utilize these paths and updates some of the
clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166578 91177308-0d34-0410-b5e6-96231b3b80d8
RMSelectionDAGInfo.cpp
|
| e1d4a8813427b76c5f59cf5b70a9df734b7e9284 |
24-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Make branch heavy code for generating marked up disassembly simpler
and easier to read by adding a couple helper functions. Suggestion by
Chandler Carruth and seconded by Meador Inge!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166515 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 8f47fc8f00fbb1cc2215fc90942b0948e3ca121b |
23-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
When a block ends in an indirect branch, add its successors to the machine basic block.
The CFG of the machine function needs to know that the targets of the indirect
branch are successors to the indirect branch.
<rdar://problem/12529625>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166448 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3ed0316f756e2f1730f46654776fcf77f5ace7aa |
23-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Add support for annotated disassembly output for X86 and arm.
Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.
rdar://11764962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 0d3c8d5d16caa4c4f1310699722aa2cbe2844f21 |
19-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
ARM:
Removed extra stack frame object for fixed byval arguments,
VarArgsStyleRegisters invocation was reworked due to some improper usage in
past. PR14099 also demonstrates it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166273 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| cbd9a19b5d6ff93efa82c467508ede78b8af3bac |
19-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 88d12663abdac344f312b09edfe4934143436132 |
18-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug where a 32-bit address with the high bit does not get symbolicated
because the value is incorrectly being signed extended when passed to
SymbolLookUp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166234 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 3b9a911efcf280950f878a050728450423875639 |
18-Oct-2012 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang. I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.
This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 9aa6e0a134358c681cc5918ec65b1ec9726b778e |
17-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().
All callers of these functions really want the isPhysRegOrOverlapUsed()
functionality which also checks aliases. For historical reasons, targets
without register aliases were calling isPhysRegUsed() instead.
Change isPhysRegUsed() to also check aliases, and switch all
isPhysRegOrOverlapUsed() callers to isPhysRegUsed().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166117 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| b52ba9f8a896b6717d6395ad59f6550e1fa475b0 |
16-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Issue:
Stack is formed improperly for long structures passed as byval arguments for
EABI mode.
If we took AAPCS reference, we can found the next statements:
A: "If the argument requires double-word alignment (8-byte), the NCRN (Next
Core Register Number) is rounded up to the next even register number." (5.5
Parameter Passing, Stage C, C.3).
B: "The alignment of an aggregate shall be the alignment of its most-aligned
component." (4.3 Composite Types, 4.3.1 Aggregates).
So if we have structure with doubles (9 double fields) and 3 Core unused
registers (r1, r2, r3): caller should use r2 and r3 registers only.
Currently r1,r2,r3 set is used, but it is invalid.
Callee VA routine should also use r2 and r3 regs only. All is ok here. This
behaviour is guessed by rounding up SP address with ADD+BFC operations.
Fix:
Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and
8 byte alignment, we waste odd registers then.
P.S.:
I also improved LDRB_POST_IMM regression test. Since ldrb instruction will
not generated by current regression test after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 64ba6352097d38db5a57f4bf62dcdf14b0e6e147 |
15-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: v1i64 and v2i64 VBSL intrinsic support.
rdar://12502028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165981 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2c39b15073db81d93bb629303915b7d7e5d088dc |
15-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
|
| bb1078ea1370fd0cc32f52b1b53f0b245ded42e7 |
15-Oct-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed PR13938: the ARM backend was crashing because it couldn't select a VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code didn't check that the size of the input vector was correct for using VDUPLANE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165929 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 84125ca43c758fd21fdab2b05196e0df57c55c96 |
13-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Remove the MatchInstruction() function. Previously, this was
the interface between the front-end and the MC layer when parsing inline
assembly. Unfortunately, this is too deep into the parsing stack. Specifically,
we're unable to handle target-independent assembly (i.e., assembly directives,
labels, etc.). Note the MatchAndEmitInstruction() isn't the correct
abstraction either. I'll be exposing target-independent hooks shortly, so this
is really just a cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165858 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e6c3cc8dc5437069f71a38188173835ba4fb0dc1 |
13-Oct-2012 |
Manman Ren <mren@apple.com> |
ARM: tail-call inside a function where part of a byval argument is on caller's
local frame causes problem.
For example:
void f(StructToPass s) {
g(&s, sizeof(s));
}
will cause problem with tail-call since part of s is passed via registers and
saved in f's local frame. When g tries to access s, part of s may be corrupted
since f's local frame is popped out before the tail-call.
The current fix is to disable tail-call if getVarArgsRegSaveSize is not 0 for
the caller. This is a conservative approach, if we can prove the address of
s or part of s is not taken and passed to g, it should be okay to perform
tail-call.
rdar://12442472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165853 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4346fa9437116bbdb10acddb982c230f46696737 |
13-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Mark VSELECT as 'expand'.
The backend already pattern matches to form VBSL when it can. We may want to
teach it to use the vbsl intrinsics at some point to prevent machine licm from
mucking with this, but using the Expand is completely correct.
http://llvm.org/bugs/show_bug.cgi?id=13831
http://llvm.org/bugs/show_bug.cgi?id=13961
Patch by Peter Couperus <peter.couperus@st.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165845 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6e006d3de882784527d4d9cc92b1a91f6773505e |
13-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Use the new API introduced in r165830 in lieu of the
MapAndConstraints vector. Also remove the unused Kind argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ed84062812c7b8a82d0e8128a22aa1aa07a14d79 |
12-Oct-2012 |
Sean Silva <silvas@purdue.edu> |
Remove unnecessary classof()'s
isa<> et al. automatically infer when the cast is an upcast (including a
self-cast), so these are no longer necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
CTargetDesc/ARMMCExpr.h
|
| fb384d61c78b60787ed65475d8403aee65023962 |
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
|
| f3840d2c16a4ec4c879a8ded402835746de380f8 |
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
|
| 6b61491de3f361a149919936e6264eff3746d80b |
11-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e3d0e86919730784faaddcb5d9b0257c39b0804b |
11-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 2c2cb3c09f856975027becadb22dcca370683f30 |
10-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix for LDRB instruction:
SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer
that described in .td.
7 ops is needed, but SDNode with only 6 is created.
In more details:
In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset
operand is defined as am2offset_imm. am2offset_imm is complex parameter type,
and actually it consists from dummy register and imm itself. As I understood
trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy
register was not added to SDNode, and it cause crash in Peephole Optimizer pass.
The problem fixed by setting up additional dummy reg when emitting
LDRB_POST_IMM instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165617 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 661afe75e81431a66de3ed8e22d5aa91443367b3 |
10-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Issue description:
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
objects and byval parameters. So loading byval parameters from stack may be
inserted *before* it will be stored, since these operations are treated as
independent.
Fix:
Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
FixedStack MachinePointerInfo. To fix the problem we need to store byval
registers with MachinePointerInfo referenced to first the "byval" parameter.
Also commit adds two new fields to the InputArg structure: Function's argument
index and InputArg's part offset in bytes relative to the start position of
Function's argument. E.g.: If function's argument is 128 bit width and it was
splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
but different offset values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 412cd2f81374865dfa708bef6d5b896ca10dece0 |
10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.
Allows the HazardRecognizer to be disabled along with itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 2d15d641aa8aa9e48c268170f1a9825bb9926fc7 |
10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165601 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 3e2d76c946ba753c2b11af192a52e25b6f9b46ff |
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Use the attribute enums to query if a parameter has an attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
|
| 102b8ccfe673b4e3aa189f85b0fa06f59f19a199 |
09-Oct-2012 |
Craig Topper <craig.topper@gmail.com> |
In parseMSRMaskOperand, add an explicit check for the operand being an identifier instead of just having an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165480 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7747496736376c97d8bbf71302151287d1056abc |
09-Oct-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some dead code from ARMAsmPrinter. Add virtual and LLVM_OVERRIDE to the other methods. Mark some of the helper methods as private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165479 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMELFWriterInfo.cpp
RMFastISel.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMSelectionDAGInfo.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 9ba9d4d76bfa8de2b05cbce02a5a3ff7d46cb331 |
05-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add a few typedefs to simplify future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 837c28a84076e1cd63bbf29057b791ebe6b03de0 |
04-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: locate user-defined text sections next to default text.
Make sure functions located in user specified text sections (via the
section attribute) are located together with the default text sections.
Otherwise, for large object files, the relocations for call instructions
are more likely to be out of range. This becomes even more likely in the
presence of LTO.
rdar://12402636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165254 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 847d165459a8d4c30b57c896c7a7e2722f800f82 |
03-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Add methods which query for the specific attribute instead of using the
enums. This allows for better encapsulation of the Attributes class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165132 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 22685876ed7231f32f7d1698c00acab22825b74c |
02-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add the convertToMapAndConstraints() function that is used to
map constraints and MCInst operands to inline asm operands. This replaces the
getMCInstOperandNum() function.
The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164979 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b4316028b3978e65cc2b97042292637857dfad49 |
02-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
MachO: direct-to-object attribute for data-in-code markers.
The target backend can support data-in-code load commands even when
the assembler doesn't, or vice-versa. Allow targets to opt-in for
direct-to-object.
PR13973.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| eb1641d54a7eda7717304bc4d55d059208d8ebed |
29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add LLVM support for Swift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb2.td
RMInstrVFP.td
RMRegisterInfo.td
RMSchedule.td
RMScheduleSwift.td
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMCTargetDesc.cpp
LxExpansionPass.cpp
|
| 154418cdd82b3d8dcf23efd65f5647833e43bc45 |
29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164898 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 8f50647662560167b88851f92c3c891d2e7c1696 |
27-Sep-2012 |
Jush Lu <jush.msn@gmail.com> |
[arm-fast-isel] Add support for ELF PIC.
This is a preliminary step towards ELF support; currently ARMFastISel hasn't
been used for ELF object files yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164759 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMFastISel.cpp
RMInstrInfo.cpp
RMMachineFunctionInfo.h
RMTargetMachine.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
|
| d6d10ae1519f0eb71c1db46c2cc77321d02c6ee6 |
26-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164685 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fe2d5f848764dff8f9ba734a5e2438ca1535890e |
25-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Darwin BL/BLX relocations to out-of-range symbols.
When a BL/BLX references a symbol in the same translation unit that is
out of range, use an external relocation. The linker will use this to
generate a branch island rather than a direct reference, allowing the
relocation to resolve correctly.
rdar://12359919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| fbc21fabaef9a74334c54574a4949f864451f1b6 |
25-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.
rdar://9795790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2590c2e1e9e2f2a7f28672c10c2df55566238dfa |
25-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Rather then have a wrapper function, have tblgen instantiate the implementation.
Also remove an unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 00796a1b15a83247e19c2445a6ff7a31e72299a4 |
24-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Rather then have a wrapper function, have tblgen instantiate the implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d15e2a08578fe7028196037d9a35c834f0e0b7f8 |
22-Sep-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164459 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 2d67eac2e6c866e6181d159f5c0e71b6e804f672 |
22-Sep-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164458 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| bb5174246b5d0dfbd057b3641f5e134fe74ea0f4 |
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix edge cases of ARM shift operands in arith instructions.
As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 93c7c449a1351542fa5a275587187154dbedb8e0 |
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| d717a066c6ddaff401b9259579b265eeafb83b6e |
22-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4a6203a31b28d76d9e0d802a900b64bef285db9c |
21-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164414 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e5e674ba1191d9e9c528eb363babdcbea1359e10 |
21-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
non-aligned i32 loads/stores.
rdar://12304911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164381 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2f1d5d44c088d7f600fb63aef07f785a0f9c4c1f |
21-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Cortex-A9 latency fixes (w/ -schedmodel only).
Quick review against the manual revealed a few obvious mistakes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164361 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| d70c98e884d19c4d94b5e83efd32888b8ee47869 |
21-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
non-halfword-aligned i16 loads/stores.
rdar://12304911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164345 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d314ab525db93cdb51ede18830b95c97af497e3c |
21-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164344 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCExpr.h
|
| 1f9f599e7017968859e84d796ba8a827357a700b |
21-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164343 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ced674e470bb949d0adce90d79563789439333a8 |
21-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Use a dedicated intrinsic for vector bitwise select.
The expression based expansion too often results in IR level optimizations
splitting the intermediate values into separate basic blocks, preventing
the formation of the VBSL instruction as the code author intended. In
particular, LICM would often hoist part of the computation out of a loop.
rdar://11011471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| aa258442b9c9f764845660a8f3233c7887e7cf6f |
20-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Change enum type in a static table to uint8_t instead. Saves about 700 hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164285 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| b37b6ca4bb9a46bdf3788e7a45454e1cdeca17bd |
18-Sep-2012 |
Evan Cheng <evan.cheng@apple.com> |
MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164169 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 536a88ad5bf160232205192a7ce72e50bfadbded |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.
Fixes PR11212.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| 97ecb83dffb5ff78ff84e9da21189268f52c63b2 |
18-Sep-2012 |
James Molloy <james.molloy@arm.com> |
More domain conversion; convert VFP VMOVS to NEON instructions in more cases - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164114 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e127dfd0b175b5a336e61fecaad7fc2aec65d95c |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| d10eab0a95dcfff6390cc73b50ca07fd8b98b0bc |
18-Sep-2012 |
Evan Cheng <evan.cheng@apple.com> |
Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte
aligned address. Based on patch by David Peixotto.
Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| e1b53287179b4b9b5c3c549586f688d3fa2ae8ef |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| db7afac4575168c239ac9c570cb7897808f12e30 |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| c8bf0f86624f025ca7c2b5cfc35ef3fb904a3930 |
17-Sep-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Removed the VMLxForwarding feature for the Cortex-A15 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164030 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 86a1c32e67b23c5e9e42dff9eb86e99ba15bb42f |
15-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 9eed53379f19f836769a0c4a14042eeb1b587769 |
14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163922 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| dcf31ed4139df19b14e599adaaa4f09901553ede |
14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Cortex-A9 instruction-level scheduling machine model.
This models the A9 processor at the level of instruction operands, as
opposed to the itinerary, which models each operation at the level of
pipeline stages.
The two primary motivations are:
1) Allow MachineScheduler to model A9 as an out-of-order processor. It
can now distinguish between hazards that force interlocking vs.
buffered resources.
2) Reduce long-term maintenance by allowing the itinerary and target
hooks to eventually be removed. Note that almost all of the complexity
in the new model exists to model instruction variants, which the
itinerary cannot handle. Instead the scheduler previously relied on
processor-specific target hooks which are incomplete and buggy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163921 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| c5252da873d547a19069eaf9030fec203f128f66 |
14-Sep-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Fix Doxygen issues:
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
with the rest of the codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163902 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 78c041bd883d86c81c42b98f326660277e6d0d9a |
14-Sep-2012 |
Stephen Hines <srhines@google.com> |
am 1c4ad5ef: Merge branch \'upstream\' into merge-2012_09_10
* commit '1c4ad5ef4fab105f0c8af7edd026e00502fb6279': (446 commits)
Revert r163556. Missed updates to tablegen files.
Update function names to conform to guidelines. No functional change intended.
test/CodeGen/X86/ms-inline-asm.ll: Relax for non-darwin x86 targets. '##InlineAsm' could not be seen in other hosts.
[ms-inline asm] Properly emit the asm directives when the AsmPrinterVariant and InlineAsmVariant don't match.
Update test case for Release builds.
Remove redundant semicolons which are null statements.
Disable stack coloring because it makes dragonegg fail bootstrapping.
[ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() function and update the printOperand() function accordingly.
[ms-inline asm] Add support for .att_syntax directive.
Enable stack coloring.
Don't attempt to use flags from predicated instructions.
[Object] Extract Elf_Ehdr. Patch by Hemant Kulkarni!
Stack Coloring: Handle the case where END markers come before BEGIN markers properly.
Enhance PR11334 fix to support extload from v2f32/v4f32
Add "blocked" heuristic to the Hexagon MI scheduler.
Fold multiply by 0 or 1 when in UnsafeFPMath mode in SelectionDAG::getNode().
whitespace
Add boolean simplification support from CMOV
Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types.
Minor cleanup. No functional change.
...
|
| 616471d4bfe4717fa86259ff4534703357b3b723 |
13-Sep-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
This patch introduces A15 as a target in LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163803 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMHazardRecognizer.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMSubtarget.h
RMTargetMachine.cpp
LxExpansionPass.cpp
|
| 828ded66831c0caaeecd2291a6bfb084f373d0e4 |
12-Sep-2012 |
Ying Wang <wangying@google.com> |
Use O0 for the win_sdk build too
To avoid the super long compilation with /usr/bin/i586-mingw32msvc-g++
4.2.
Change-Id: I4b434893ca4789e10b6fb0d44275eb82cb1be040
smParser/Android.mk
|
| 3d1f75a3d5748c87a1f1b248313047abecc09360 |
12-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Rename the isMemory() function to isMem(). No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163654 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1c4ad5ef4fab105f0c8af7edd026e00502fb6279 |
11-Sep-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge-2012_09_10
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/Support/DynamicLibrary.cpp
lib/Support/LockFileManager.cpp
Change-Id: I91e94c3a7a76e19c688307c5a480a640a3bd2b7e
|
| 2de0572caec55e3779857cae0bbcd962af2e495d |
10-Sep-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove redundant semicolons which are null statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 519daf5d2dd80614ac4e529b199e6f3e595bfc80 |
10-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't attempt to use flags from predicated instructions.
The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.
Don't do that if the sub is predicated - the flags are not written
unconditionally.
<rdar://problem/12263428>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163535 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a1fb1d2ed7342c7e6b491a78af073b5320bc9867 |
08-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a7390fadbaa8da49649d76786555c93bcb680de6 |
07-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Custom DAGCombine for and/or/xor are for all ARMs.
The 'select' transformations apply to all ARM architectures and don't
require hasV6T2Ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 39646d96e76aea5d20bffb386233a0dbb5932a21 |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCAsmInfo.cpp
|
| 24b9f258f194c5e472bf133f9bbf5ca26ad500d3 |
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Diagnose invalid alignments on duplicating VLDn instructions.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| eae1d34029c159306ce4a0472294de6cf9baedac |
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 64eacd9136dc45e54dd2728117f71403701fd39c |
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Use correct part of complex operand to encode VST1 alignment.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e757640df0615510dbc42921cf6271aa76c405ee |
06-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Fix a few old-GCC warnings. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163309 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 951543491fcc01486a926f0dcb37815ffff2051f |
06-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Fix self-host; ensure signedness is consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163306 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ba8562af4440753ba6175ccd54d71f79f5c4f3dc |
06-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Improve codegen for BUILD_VECTORs on ARM.
If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163304 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6c822eea47dbef96940819b1ea085fabc49a1e71 |
06-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| f632d80e0c83248909b2dbbe2decef7de84718f9 |
06-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove predicated pseudo-instructions.
These pseudos are no longer needed now that it is possible to represent
predicated instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163275 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 098c6a547fe540b3bbace4c3d4713f400c67b8a9 |
06-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 59324297650c12a8dccf1a7ad650a9e895fdc17e |
06-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Stop casting away const qualifier needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 7bebddf55ece46995f310d79195afb4e5b239886 |
05-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Strip old MachineInstrs *after* we know we can put them back.
Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163230 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5d637d7e93c1f6058c16b41b8ac7dd36c61b4a5c |
05-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix function name per coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 67514e90669ec9ffd954c1fcb6f8979bafcabe8a |
04-Sep-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 2cc97def7434345e399e4f5f3f2001d6d7a93c6f |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 038f3e31276f8cc86d91d0e4513e1a3ddb8509ba |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the
MCTargetAsmParser class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c4d2560a2010456f4eea0007eb71829d5668e7dd |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Removed unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3a86e1396230748f17a521915bc802939a787eac |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Expose the Kind and Opcode variables from the
MatchInstructionImpl() function.
These values are used by the ConvertToMCInst() function to index into the
ConversionTable. The values are also needed to call the GetMCInstOperandNum()
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9f40cb32ac31283f8636d516e7b10f3ad921955c |
02-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Not all targets have efficient ISel code generation for select instructions.
For example, the ARM target does not have efficient ISel handling for vector
selects with scalar conditions. This patch adds a TLI hook which allows the
different targets to report which selects are supported well and which selects
should be converted to CF duting codegen prepare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 89f49808ee79eebbc3267b6c595514d4ca1f3247 |
01-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Limit domain conversion to cases where it won't break dep chains.
NEON domain conversion was too heavy-handed with its widened
registers, which could have stripped existing instructions of their
dependency, leaving them vulnerable to scheduling errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163070 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 8fccd013d87c4b12edb4c9982fd9f3517917d2f7 |
01-Sep-2012 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix Thumb2 fixup kind in the integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163063 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| 756d2cc2f7f6745603fdc0ec1ed4476d06385845 |
01-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()
function nowadays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 429af6fa4124d8b6dd310069e0a44dcacb35fc8a |
31-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Add a comment to explain what's really going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163005 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5d04a560a875eef5cc7ae2bfadaf7d46ea8a60c5 |
31-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
The ConvertToMCInst() function can't fail, so remove the now dead Match_ConversionFail enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163002 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 05e80f27148b1dc19925755d56b6466df840da44 |
31-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a couple of typos in EmitAtomic.
Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.
rdar://problem/12203728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162968 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 359956dc1be35df4f8179eb14cea617c3ef10dd7 |
31-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
With the fix in r162954/162955 every cvt function returns true. Thus, have
the ConvertToMCInst() return void, rather then a bool. Update all the cvt
functions as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162961 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fafa283e65bca1473eace94057077129a76dbdcc |
31-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix for r162954. Return the Error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162955 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 64b3444cbf7f5976502ff4cf6fc89aed4986b59c |
31-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Move a check to the validateInstruction() function where it more properly belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162954 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1122fc40c16785d510025daeb6c72a075f7e2e5b |
31-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162952 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c4a32e6596f3974a6c00322db1f5f31ea448bd58 |
30-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Add support for moving pure S-register to NEON pipeline if desired
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162898 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 20599ea4bced03634a54b52e98d261018366f279 |
29-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Refactor setExecutionDomain to be clearer about what it's doing and more robust.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162844 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7611a88b58e0a6960cdb5c72dc18a6c93e44cdc2 |
29-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup sloppy code. Jakob's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162825 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| c4dc2490c4ea2c75e451eec5950179f06d2610a2 |
29-Aug-2012 |
Jush Lu <jush.msn@gmail.com> |
[arm-fast-isel] Add support for ARM PIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162823 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f26e43df26bb7b0c7bf4853477e36611e2c90dea |
29-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Fix ARM vector copies of overlapping register tuples.
I have tested the fix, but have not been successfull in generating
a robust unit test. This can only be exposed through particular
register assignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162821 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d79dedd458c1de07fbc568ea8c3b4194e94df48e |
29-Aug-2012 |
Andrew Trick <atrick@apple.com> |
cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162820 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cff9baa95273bc279bf5fadb9e27afbd25cca20b |
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.
We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| dd364419ee64cd5bb234af006ce0cb285e4a84ca |
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| 47aa9a2bb521994509d21179b968471531986eed |
28-Aug-2012 |
Bill Wendling <isanbard@gmail.com> |
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1144af3c9b4da48cd581156e05b24261c8de366a |
25-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 36ff8f25c559f291a8790584b725e0b54ddf2240 |
25-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Missed tLEApcrelJT.
ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7778ee1ed9f9e8a3aa4911ff4adcf15e46588e03 |
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Explicitly mark LEApcrel pseudos with hasSideEffects.
It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.
This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 0745b649ed5c362f1c2f7db59254a76041ddef05 |
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix call instruction operands in ARMFastISel.
The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.
The argument registers should be added as implicit uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ea47628cbafb48bf2a51554328a6dd77be40f4df |
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing SDNPSideEffect flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d62cdbe700ab288e9ad447824066edb7d17167d9 |
23-Aug-2012 |
Stephen Hines <srhines@google.com> |
Add new files for Mips + fixups for merge to upstream r162314.
Change-Id: Ib545c0c991575c14b0b74e3b8fd4cc8c789b25d0
RMJITInfo.cpp
|
| 31675153bd2d7617db8cb6aeb58054934c7b9f73 |
24-Aug-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge_2
Conflicts:
lib/Target/ARM/ARMCodeEmitter.cpp
Change-Id: I6702d340c733e9721499b5d85b13b96ad9c14eb5
|
| aaf217953bef3b2cc0e0f26bf474616cc20cf7f0 |
24-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix undefined behavior (negation of INT_MIN) in ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 05d96f98cbd96dab7f4ea1ea4ebe4285597e7e88 |
22-Aug-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Reduce duplicated hash map lookups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162362 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 96601ca332ab388754ca4673be8973396fea2ddd |
22-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 53799048071ad5746fcbc2dca55cdcf5c5593870 |
21-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a missing def flag.
*** Bad machine code: Explicit definition marked as use ***
- function: test_cos
- basic block: BB#0 L.entry (0x7ff2a2024fd0)
- instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def>
- operand 0: %D11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162247 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 416bb6a168a9316547db6ce3909c515f70a84f52 |
20-Aug-2012 |
Ying Wang <wangying@google.com> |
Use -O0 to speed up compiling of ARMAsmParser.cpp
Change-Id: I0d4b647180dbb2c3025c9d3f9a68b97de650ce41
smParser/Android.mk
|
| a0708d1109c2c1a3cf911a4761a10ad69a28455e |
20-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock.
The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating
duplicate successor list entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162222 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0a8f8980000b753ef77dfc64cc7d9803d5dcc8ce |
18-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the CAND/COR/CXOR custom ISD nodes and their select code.
These nodes are no longer needed because the peephole pass can fold
CMOV+AND into ANDCC etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162179 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 35fc62bf70074349d74357900dd65f08384970c5 |
18-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove virtual from many methods. These methods replace methods in the base class, but the base class methods aren't virtual so it just increased call overhead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162178 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 864c8702ba0da2208212e84f146fbbe5c77866ed |
18-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dcd2342d32e92912cc457fe6ce4cd8a72c93c06b |
18-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:
(and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
(or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
(xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
The selects can then be transformed to a single predicated instruction
by peephole.
This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6d655a50f93520e73c4154e3642227d665bd6966 |
18-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
fp16-to-fp32 conversion instructions are available in Thumb mode as well.
Make sure the generic pattern is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162170 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| a7fb3f68047556a7355e1f1080fb3d1ca9eb7078 |
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid folding ADD instructions with FI operands.
PEI can't handle the pseudo-instructions. This can be removed when the
pseudo-instructions are replaced by normal predicated instructions.
Fixes PR13628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162130 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1f1ab3e9c4dbef6a2d610b29903592986be09a10 |
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add comment, clean up code. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162107 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3c8ad92455ff06c8e69085702ef1f13944eab4dd |
17-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Implement NEON domain switching for scalar <-> S-register vmovs on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 960fb7437003dcb96c6af093e2d55e06e4c8bd43 |
17-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary include of ARMGenInstrInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 083b48af14c8bfa0e96f63ebc889704d09655fd4 |
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add ADD and SUB to the predicable ARM instructions.
It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.
Then the pseudo-instructions can go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 053b5b0b3c34d4763511b6dcd8e0150f8e9dd083 |
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle ARM MOVCC optimization in PeepholeOptimizer.
Use the target independent select analysis hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162060 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 2ff4e9d5afa2074b91940a601fba0a0c154f6a83 |
16-Aug-2012 |
Jush Lu <jush.msn@gmail.com> |
[arm-fast-isel] Add support for fastcc.
Without fastcc support, the caller just falls through to CallingConv::C
for fastcc, but callee still uses fastcc, this inconsistency of calling
convention is a problem, and fastcc support can fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162013 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2860b7ea3a1d60213ee7228bd274bc4f8b170772 |
16-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fold predicable instructions into MOVCC / t2MOVCC.
The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.
This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| a99c508c8d34c073619b71d4f50cb28110cb1a2a |
15-Aug-2012 |
Evan Cheng <evan.cheng@apple.com> |
Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| 65bf80e2b7d3c839331be63cdd28a8d101936bca |
15-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing Rfalse operand to the predicated pseudo-instructions.
When predicating this instruction:
Rd = ADD Rn, Rm
We need an extra operand to represent the value given to Rd when the
predicate is false:
Rd = ADDCC Rfalse, Rn, Rm, pred
The Rd and Rfalse operands are different registers while in SSA form.
Rfalse is tied to Rd to make sure they get the same register during
register allocation.
Previously, Rd and Rn were tied, but that is not required.
Compare to MOVCC:
Rd = MOVCC Rfalse, Rtrue, pred
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161955 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 652199961a8acf3314b15bb3d5133e8a9a56b615 |
15-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
The names of VFP variants of half-to-float conversion instructions were
reversed. This leads to wrong codegen for float-to-half conversion
intrinsics which are used to support storage-only fp16 type.
NEON variants of same instructions are fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 6eef0e2f8767ee691413bf8344e1d2db527c8a43 |
15-Aug-2012 |
Eric Christopher <echristo@apple.com> |
This needs braces. Spotted by Bill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161906 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| fc1a161d76f5cc0204bed3bce3e27cf36ac76d22 |
14-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 617792679c90897e49ae6f8bbe3a30a5723b15f5 |
13-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Use correct loads for vector types during extending-load operations.
Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit
accesses being selected, so we need to use an appropriate width load in those
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 43600e95ec3690b37d458a6d3d56941ad84cddcb |
13-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.
The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.
When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| a41db53f664f2ea943004f72be5cf575ba2d5d39 |
13-Aug-2012 |
Manman Ren <mren@apple.com> |
ARM: enable struct byval for AAPCS-VFP.
This change is to be enabled in clang.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161789 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| df8320313bf31c77d6dde4010235d82d871518cb |
13-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ISDNode has more than one user.
rdar://11876519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161775 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 001d219b9729684ea514068cff1cf79cd2e71121 |
13-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the %H output modifier.
Patch by Weiming Zhao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161768 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| e0b464f291f69f26661f58f6073a27d808fc672c |
13-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Use correct loads for vector types during extending-load operations.
Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit
accesses being selected, so we need to use an appropriate width load in those
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a7016d6fc1c9935ede7b3dc2f39c8cdab14e40e0 |
12-Aug-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM
architecture
It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7
thumb O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 0faf46c640c6747f1add89ba06631cebc4fa3afd |
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Change addTypeForNeon to use MVT instead of EVT so all the calls to getSimpleVT can be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161735 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d9b45125935b05578255501a7e05fba9de603609 |
10-Aug-2012 |
Manman Ren <mren@apple.com> |
ARM: enable struct byval for AAPCS.
This change is to be enabled in clang.
rdar://9877866
PR://13350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161693 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| df1c637ac4b6f6587c037be55cafed665c732d8f |
10-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Remove getARMRegisterNumbering and replace with calls into
the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.
One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMExpandPseudoInsts.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
smParser/ARMAsmParser.cpp
CTargetDesc/ARMBaseInfo.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| bcc4c1d2d1b6877418de92835c537d79d44363a6 |
09-Aug-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 529f3140507c4b4479ffd58d8008f38b5de6c5c4 |
09-Aug-2012 |
Eric Christopher <echristo@apple.com> |
This field isn't used anymore, use it with HWEncoding instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161564 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| d43b5c97cff06d7840b974ca84fa0639d2567968 |
08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMSubtarget.cpp
RMSubtarget.h
|
| d598bd3aeea64fb0d2d3bd18de739a8a59cf043d |
08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161469 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| ad62e92279bc0b14c54db94dd794082c8b8edd9e |
04-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Skip impdef regs during eabi save/restore list emission to workaround PR11902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161301 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 161474d198d44ab505861c1ec55f022b27314b35 |
04-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack stuff
(this corresponds by spilling/reloading regs in DTriple / DQuad reg classes).
No testcase, found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161300 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b58d7d03125526c152ade0c75be302b3c9eab997 |
04-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add stack spill / reload instructions for DTriple and DQuad register classes, which
were missed for no reason. This fixes PR13377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| c3f0e98f40f1382870c679b6aef1c5d01540637f |
03-Aug-2012 |
Shih-wei Liao <sliao@google.com> |
Apply changes to migrate to LLVM-160668-20120724.
- Update Android.mk for removed files and new files.
- llvm-ld has been removed in upstream, so we remove it as well.
Change-Id: I613ada916156a43993d4bba9cae6dcb6bf40ed2f
RMCodeEmitter.cpp
|
| 7744acd1ab73b3eec6f1449f47083abe3fb1b527 |
03-Aug-2012 |
Shih-wei Liao <sliao@google.com> |
Merge with LLVM upstream r160668 (Jul 24th 2012)
Conflicts:
include/llvm/Support/ELF.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/Support/Memory.cpp
lib/Transforms/Instrumentation/AddressSanitizer.cpp
Change-Id: Iddd658cf2eadc7165b2805b446d31af2c5c9917f
|
| d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3 |
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 2946549a2817681f9117662139cc0f2241939965 |
03-Aug-2012 |
Jush Lu <jush.msn@gmail.com> |
[arm-fast-isel] Add support for shl, lshr, and ashr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e94ac8871a1ac79bece57335d2abece0feed9c02 |
03-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the ARM GHC calling convention, this patch was in 3.0,
but somehow managed to be dropped later.
Patch by Karel Gardas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCallingConv.td
RMFastISel.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
|
| 55499db9a00e9bb7ba9943b2f1b5bc4645bbab1e |
03-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tidy up. Remove unused template parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161222 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9249ef3b994ec94b1a70c0c1f8e60115ec70144b |
02-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: More InstAlias refactors to use #NAME#.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161220 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5c6c128b8162ab23f6330f8b8b5e66494458ec65 |
02-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Refactor instaliases using TableGen support for #NAME#.
Now that TableGen supports references to NAME w/o it being explicitly
referenced in the definition's own name, use that to simplify
assembly InstAlias definitions in multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161218 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1c3781496081b47412fc70393bcdc5b67b440b02 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Support fpv4 for ARM Cortex-M4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161163 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
|
| c1b7ca5ba28ded2d83ae534c8e072c2538d43295 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMBaseInfo.h
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| cc5fc665e3f68bd70b42516adaf4a2f9879f2940 |
01-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Remove redundant instalias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161134 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 046eea5247b62c9c8b230800d224c0be48fd75e0 |
01-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
Clean up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161133 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 2769028ab4732ce6083a71c67dc19b8901f55d5a |
01-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161132 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5af4de18ef244d2ce52b2f2ac0a703409b6fdfe6 |
30-Jul-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cpp
where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.
rdar://10038370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160978 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 242204784bae63da503c2f509a38c532085f0eb1 |
25-Jul-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Don't assume an SDNode is a constant.
Before accessing a node as a ConstandSDNode, make sure it actually is one.
No testcase of non-trivial size.
rdar://11948669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160735 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c8e41c591741b3da1077f7000274ad040bef8002 |
23-Jul-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| ee649839a243bb29b59b322203b982b2f132e7c5 |
19-Jul-2012 |
Jush Lu <jush.msn@gmail.com> |
[arm-fast-isel] Add support for vararg function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160500 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8d8d961de4878b17dca9d8b23666df223f6d654b |
18-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.
Based on Evan's suggestion without a commitable test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160441 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 49b446fa0a0daabebdb18a8ef884acda353399cf |
18-Jul-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160440 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7c82e6a32a84e238c9e4e57dd43eaba540a79ce1 |
18-Jul-2012 |
Joel Jones <joel_k_jones@apple.com> |
More replacing of target-dependent intrinsics with target-indepdent
intrinsics. The second instruction(s) to be handled are the vector versions
of count set bits (ctpop).
The changes here are to clang so that it generates a target independent
vector ctpop when it sees an ARM dependent vector bits set count. The changes
in llvm are to match the target independent vector ctpop and in
VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM
dependent vector pop counts with target-independent ctpops. There are also
changes to an existing test case in llvm for ARM vector count instructions and
to a test for the bitcode upgrade.
<rdar://problem/11892519>
There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 06a6a300c5f7100e4665667c689369e078d2ad59 |
14-Jul-2012 |
Joel Jones <joel_k_jones@apple.com> |
This is one of the first steps at moving to replace target-dependent
intrinsics with target-indepdent intrinsics. The first instruction(s) to be
handled are the vector versions of count leading zeros (ctlz).
The changes here are to clang so that it generates a target independent
vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp
to update any existing bc files containing ARM dependent vector ctlzs with
target-independent ctlzs. There are also changes to an existing test case in
llvm for ARM vector count instructions and a new test for the bitcode upgrade.
<rdar://problem/11831778>
There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 135fb455b72b1db12d93aa13b13872780db6315b |
13-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove variable_ops from ARM call instructions.
Function argument registers are added to the call SDNode, but
InstrEmitter now knows how to make those operands implicit, and the call
instruction doesn't have to be variadic.
Explicit register operands should only be those that are encoded in the
instruction, implicit register operands are for extra dependencies like
call argument and return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 9af64303fa887a3d9b75e715787ba587c3f18139 |
12-Jul-2012 |
Manman Ren <mren@apple.com> |
ARM: fix typo in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 45ed19499b8f7025d9acf91cc37fbf6ea63abc4f |
12-Jul-2012 |
Manman Ren <mren@apple.com> |
ARM: Fix optimizeCompare to correctly check safe condition.
It is safe if CPSR is killed or re-defined.
When we are done with the basic block, check whether CPSR is live-out.
Do not optimize away cmp if CPSR is live-out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| fae96f17b4b022fccd94a143698112a17d8ddf05 |
10-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
isassembler/ARMDisassembler.cpp
|
| a4fba5eaf8e62bd08d75cd3e79fb40fc4fb71c16 |
10-Jul-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Allow more flexible patterns in NEON formats.
Some NEON instructions want to match against normal SDNodes for some
operand types and Intrinsics for others. For example, CTLZ. To enable this,
switch from explicitly requiring Intrinsic on the class templates to using
SDPatternOperator instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 270e3625b23174688aa5b6f1e1d0cd42086541de |
09-Jul-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
isassembler/ARMDisassembler.cpp
|
| 874b863f2ab9158db6f7f1b773b77e6334e31c41 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Some formatting to keep Clang happy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 83cfff6229c4afe9af9d48d4109df9a503233a7c |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Oops - correct broken disassembly for VMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 2e7e34ba5485320a84ca69c83d242e24433f7acd |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
isassembler/ARMDisassembler.cpp
|
| 8ed97ef5f6980c689a5770ec30488601201e17c3 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c985e6ece66cf2046f0113da9eb2dec331a6b09f |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Spelling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2b6652fb10d7005e41010b0e0800afe16ae18a34 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2661b411ccc81b1fe19194d3f43b2630cbef3f28 |
07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMScheduleA8.td
RMScheduleA9.td
|
| 70cfaa34645bf8ad232c400f0fe7c48a9d715586 |
07-Jul-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix the naming of ensureAlignment. Per the coding standard function names
should be camel case, and start with a lower case letter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| db6faeb19d59deab232502da7d529abc4404171a |
06-Jul-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add test cleanup entry to the README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159864 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bd985efa99b7540e664b7fc2d636348c23f63d75 |
06-Jul-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Revert r159804, "[arm-fast-isel] Add support for vararg function calls."
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a8c4d739f2e763ae6dea7661a3af8393eeebd8ba |
06-Jul-2012 |
Jush Lu <jush.msn@gmail.com> |
[arm-fast-isel] Add support for vararg function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3fb99a73686c39d9855b3f8881add977af3868cb |
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Consistently use AnalysisID types in TargetPassConfig.
This makes it possible to just use a zero value to represent "no pass", so
the phony NoPassID global variable is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 564fbf6aff8fb95646a1290078a37c2d4dbe629f |
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add all codegen passes to the PassManager via TargetPassConfig.
This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 14ccc7b963861a856b593cc4fff62decd8ce248a |
02-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Revert accidental checkin.
My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159548 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 218ee74a011c0d350099c452810da0bd57a15047 |
02-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| ac03af4ea9f6a33164dbb5a0bc59ccc738939a4c |
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Do not attempt to use ROR for Thumb1.
Patch by Matt Fischer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159538 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 76c6ccbd4cee0637c961e32435177ab89e931fed |
30-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: Clean up optimizeCompare in peephole, no functional change.
Use getUniqueVRegDef.
Replace a loop with existing interfaces: modifiesRegister and readsRegister.
Factor out code into inline functions and simplify the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159470 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| de7266c611b37ec050efb53b73166081a98cea13 |
29-Jun-2012 |
Manman Ren <mren@apple.com> |
Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare
instructions with two register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 3e4b3b9043b1ced24e07d8d1174feeee06c6912e |
29-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 0d9513c74f3e4c019406273cce49e43508dc4dcf |
29-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Make NumMicroOps a variable in the subtarget's instruction itinerary.
The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.
Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 0bcbd1df7a204e1e512f1a27066d725309de1b13 |
28-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.
The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4acefe192f02849bcb2fd620a9f507c00d39a686 |
27-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Teach assembler to handle capitalised operation values for DSB instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b69182095ce19c07a7207ab546f61bffc5111d8e |
27-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Prevent ARM Assembler crashing on unrecognised assembly format for DSB instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159257 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d096479f31eb51bcbd418b6e852a34210141d80e |
27-Jun-2012 |
Evan Cheng <evan.cheng@apple.com> |
Add a missing check to avoid dereference null. No sensible test case possible. Sorry. rdar://11745134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159236 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0518fca843ff87d069ecb07fc00d306c1f587d58 |
26-Jun-2012 |
Jack Carter <jcarter@mips.com> |
There are a number of generic inline asm operand modifiers that
up to r158925 were handled as processor specific. Making them
generic and putting tests for these modifiers in the CodeGen/Generic
directory caused a number of targets to fail.
This commit addresses that problem by having the targets call
the generic routine for generic modifiers that they don't currently
have explicit code for.
For now only generic print operands 'c' and 'n' are supported.vi
Affected files:
test/CodeGen/Generic/asm-large-immediate.ll
lib/Target/PowerPC/PPCAsmPrinter.cpp
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
lib/Target/ARM/ARMAsmPrinter.cpp
lib/Target/XCore/XCoreAsmPrinter.cpp
lib/Target/X86/X86AsmPrinter.cpp
lib/Target/Hexagon/HexagonAsmPrinter.cpp
lib/Target/CellSPU/SPUAsmPrinter.cpp
lib/Target/Sparc/SparcAsmPrinter.cpp
lib/Target/MBlaze/MBlazeAsmPrinter.cpp
lib/Target/Mips/MipsAsmPrinter.cpp
MSP430 isn't represented because it did not even run with
the long existing 'c' modifier and it was not apparent what
needs to be done to get it inline asm ready.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 540cda34b03388b510ded4546acfc7e276700daa |
25-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: update peephole optimization.
More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".
rdar: 11725965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d5c407d2d01ff8797c29343e4da5f765fe52fb5f |
24-Jun-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| fc47253294047a62b30a2347a0bf421d934fb69c |
23-Jun-2012 |
Evan Cheng <evan.cheng@apple.com> |
(sub X, imm) gets canonicalized to (add X, -imm)
There are patterns to handle immediates when they fit in the immediate field.
e.g. %sub = add i32 %x, -123
=> sub r0, r0, #123
Add patterns to catch immediates that do not fit but should be materialized
with a single movw instruction rather than movw + movt pair.
e.g. %sub = add i32 %x, -65535
=> movw r1, #65535
sub r0, r0, r1
rdar://11726136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159057 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 70c9bf3c1a77b5707c92a7cfe74104c320480391 |
23-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a better diagnostic for some out of range immediates.
As an example of how the custom DiagnosticType can be used to provide
better operand-mismatch diagnostics, add a custom diagnostic for
the imm0_15 operand class used for several system instructions.
Update the tests to expect the improved diagnostic.
rdar://8987109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| d85934b3e5a96040e199e1b098705eb56cde584a |
22-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Use "NoItineraries" for processors with no itineraries.
This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSchedule.td
|
| e2b32bb20ee76f24708b3c9e19b6fbc651c25637 |
22-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM scheduling fix: don't guess at implicit operand latency.
This is a minor drive-by fix with no robust way to unit test.
As an example see neon-div.ll:
SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill>
val SU(1): Latency=2 Reg=%Q8
...should be latency=1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158960 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ef2d9e59aba381c42e018df9c26f9025c1995a64 |
22-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM scheduling fix: compute predicated implicit use properly.
Minor drive by fix to cleanup latency computation. Calling
getOperandLatency with a deliberately incorrect operand index does not
give you the latency you want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158959 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e0231413225cf47aaf3238bf21afd0d59025028d |
22-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from a
boolean flag to an enum: { Fast, Standard, Strict } (default = Standard).
This option controls the creation by optimizations of fused FP ops that store
intermediate results in higher precision than IEEE allows (E.g. FMAs). The
behavior of this option is intended to match the behaviour specified by a
soon-to-be-introduced frontend flag: '-ffuse-fp-ops'.
Fast mode - allows formation of fused FP ops whenever they're profitable.
Standard mode - allow fusion only for 'blessed' FP ops. At present the only
blessed op is the fmuladd intrinsic. In the future more blessed ops may be
added.
Strict mode - allow fusion only if/when it can be proven that the excess
precision won't effect the result.
Note: This option only controls formation of fused ops by the optimizers. Fused
operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic)
will always be honored, regardless of the value of this option.
Internally TargetOptions::AllowExcessFPPrecision has been replaced by
TargetOptions::AllowFPOpFusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dc13d2ed2feb3fd9d4953a1dd49d6a93d6867bc5 |
21-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Add a missing llvm.fma -> VFNMS pattern to the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| d693cafcfb9e67ba7040cb810e4409a166421482 |
20-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Add DAG-combines for aggressive FMA formation.
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or
FSUB + FMUL. The combines are performed when:
(a) Either
AllowExcessFPPrecision option (-enable-excess-fp-precision for llc)
OR
UnsafeFPMath option (-enable-unsafe-fp-math)
are set, and
(b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of
the FADD/FSUB, and
(c) The FMUL only has one user (the FADD/FSUB).
If your target has fast FMA instructions you can make use of these combines by
overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for
types supported by your FMA instruction, and adding patterns to match ISD::FMA
to your FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c9a4e269d00dc9e2ba0c7b77721fa54cfb5a59fa |
19-Jun-2012 |
Jan Wen Voung <jvoung@google.com> |
Have ARM ELF use correct reloc for "b" instr.
The condition code didn't actually matter for arm "b" instructions,
unlike "bl". It should just use the R_ARM_JUMP24 reloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158722 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| d6b43a317e71246380db55a50b799b062b53cdce |
19-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the support for using .init_array from ARM to the generic
TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM,
on X86 it is not easy to find out if .init_array should be used or not, so
the decision is made via TargetOptions and defaults to off.
Add a command line option to llc that enables it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| eda9fdf979bd1c017304f8e9331f2c7df5df2d1c |
19-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: use NOEN loads and stores if possible when handling struct byval.
This change is to be enabled in clang.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158684 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7e99a60857532ca2973cf9dabc790d84a2e15a8a |
18-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Define generic HINT instruction.
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.
rdar://11600518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
|
| 96ef284da415cccd60cf5066929a4683dec5dd79 |
18-Jun-2012 |
Joel Jones <joel_k_jones@apple.com> |
This change handles a another case for generating the bic instruction
when a compile time constant is known. This occurs when implicitly zero
extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't
need to be handled, as the 8 bit constants are encoded directly, thereby
not needing a separate load instruction to form the constant into a register.
<rdar://problem/11481151>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158659 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f49a4092bcf679d1634a8023efc593e98a3e5663 |
16-Jun-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 307473dec0e2fa966037d04725a40b33669dddc8 |
15-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: optimization for sub+abs.
This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi
For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.
rdar: 11633193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d628a587b654ba737b570ee0611f70a1deb58bbc |
15-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve <undef> flags in ARMExpandPseudo.
This probably mostly shows up in bugpoint-generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158527 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| a1c7367a5bed459acc88e3ea2a482b4b5dac942a |
14-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Replace assertion failure for badly formatted CPS instrution with error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158445 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| efc967e04459753a588ebf5820e526d790fe1cfa |
14-Jun-2012 |
Jush Lu <jush.msn@gmail.com> |
Cleanup whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158443 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 49d6fc02efc45932e4d889fa56bbbfeefafbdc85 |
12-Jun-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] Add support for -arm-long-calls.
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158368 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ad5c8808923ed5b24b586cec544e45cee539e529 |
11-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Re-enable the CMN instruction.
We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/7569620>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 397f4e3583b36b23047fec06b1648f0771cd6fe3 |
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 68b16541cc58411c7b0607ca4c0fb497222b668d |
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM getOperandLatency rewrite.
Match expectations of the new latency API. Cleanup and make the logic consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f377071bf8393d35797107c753da3e84aea94ebe |
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM getOperandLatency should return -1 for unknown, consistent with API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ed7a51e69209af87f3749d5f95740f69a1dc7711 |
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Fix ARM getInstrLatency logic to work with the current API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a7542d5f870c5d98960d1676e23ac1d1d975d7e5 |
06-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused private fields found by clang's new -Wunused-private-field.
There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| c8f2fcc9a381f1e024656568f2face2f600e0328 |
06-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Correct decoder for T1 conditional B encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| b7e0289fb320c8440ba5eed121a8b932dbd806a2 |
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa |
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM itinerary properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMSubtarget.cpp
|
| fc992996f751e0941951b6d08d8f1e80ebec1385 |
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: Added MultiIssueItineraries.
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| e061053051a8eaafe020b2d0a81f9e4ee910c1d0 |
05-Jun-2012 |
Joel Jones <joel_k_jones@apple.com> |
Revert commit r157966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157972 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| dd52bf2ed806229732115400b2a060204f24dea3 |
05-Jun-2012 |
Joel Jones <joel_k_jones@apple.com> |
This change handles a another case for generating the bic instruction
when a compile time constant is known. This occurs when implicitly zero
extending function arguments from 16 bits to 32 bits.
<rdar://problem/11481151>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157966 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d9b0b025612992a0b724eeca8bdf10b1d7a5c355 |
02-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix typos found by http://github.com/lyda/misspell-check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 396618b43a85e12d290a90b181c6af5d7c0c5f11 |
02-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch all register list clients to the new MC*Iterator interface.
No functional change intended.
Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.
This makes it possible to do so without changing all clients (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| bbff4ee92d91de4c7ee6657a1eea95c5ed8105de |
01-Jun-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0
then DestReg is undefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157840 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 68f25571e759c1fcf2da206109647259f49f7416 |
01-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: properly handle alignment for struct byval.
Factor out the expansion code into a function.
This change is to be enabled in clang.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 763a75dbf719242e7f99c6447d20b9bffb75dfa2 |
01-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: support struct byval in llvm
We handle struct byval by inserting a pseudo op, which will be expanded to a
loop at ExpandISelPseudos.
A separate patch for clang will be submitted to enable struct byval.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157793 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 4c91bdafacd7387fd92fb153de3d48ef7722bbd2 |
31-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid depending on list orders and register numbering.
This code is covered by test/CodeGen/ARM/arm-modifier.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157720 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ada759d5fa8a3ecc0e97d88761badfba9193587f |
30-May-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157696 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSelectionDAGInfo.cpp
|
| 51f50c110651cedebdb7194e5e686d3a27dcce4e |
24-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Make some opcode tables static and const. Allows code to avoid making copies to pass the tables around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157373 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 032f441afcdd70eb6bda477d32e8c372443b4e6f |
24-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark a static array as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157368 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cd2859eef83708c00330c94f6842499b48d5ed02 |
24-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157367 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1c8fccbc12e6348c8003aff9b89078324257fc4e |
23-May-2012 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] Add support for non-global callee.
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157336 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dd051a0414d0c807388bdc9584b71729b3158571 |
22-May-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMDisassembler.cpp: Fix utf8 char in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157292 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| b3a119a257978857c1d62ad74ed4123198ea6703 |
22-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: .end_data_region mismatch in Thumb2.
32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.
rdar://11499158
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157221 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b551f0cc7882cd9cc9c3a3b2e4d35bc942a9cb44 |
21-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2: RSB source register should be rGRP not GPRnopc.
t2RSB defined the operand correctly, but tRSBS didn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157200 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 027c32a14ee953079e768b84ff329b37c442e208 |
20-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the right register class for LDRrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157152 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6e6269a976baee45717265dbd12996367df6a201 |
20-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Transfer memory operands to the right instruction.
They need to go on the PICLDR as the verifier points out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157151 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 3e96531186ba574b0c25a4be62d24b8b7d752c9f |
18-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.
Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.
data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"
The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.
rdar://11459456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
CTargetDesc/ARMMCAsmInfo.cpp
|
| 0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe |
18-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 44600d708154e09f4e53719f503e2446eb2b7f53 |
17-May-2012 |
Tim Northover <Tim.Northover@arm.com> |
Remove incorrect pattern for ARM SMML instruction.
Patch by Meador Inge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156989 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 918f55fe239f00651e396be841f2b3b6e242f98d |
15-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| 9cc178726f323fb859acd7f8fc657a939fe96566 |
14-May-2012 |
David Blaikie <dblaikie@gmail.com> |
Fix use of uninitialized variable.
Found by GCC's maybe-uninitialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156780 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 226ddf5278dd9a9d2d74d859d387bf5b6bac1926 |
11-May-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for selecting @llvm.trap().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2b3b335f2d2886bbffa005998972de689a9f3e21 |
11-May-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2a2e9d54e95f01eaa5626dcdf57950e9e6f95f2c |
11-May-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
retval. Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2f6ae41f14af87d1019d771b101580381cdfc44f |
11-May-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f4bd21c256f6aabdc13f54ff7bf5d69e8305302c |
11-May-2012 |
Chad Rosier <mcrosier@apple.com> |
The return type is an unsigned, not a bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4949e98cccb98abb0ba3f67c22be757d446ab108 |
11-May-2012 |
Manman Ren <mren@apple.com> |
Add space before an open parenthesis in control flow statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23 |
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| ca3cd419a52c1dedee133d79772ef97f30e5d20b |
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 247c5ab07c1c136f37f5ad8ade9a1ee086ca452e |
11-May-2012 |
Manman Ren <mren@apple.com> |
ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| fe65d98dadbedf2650266ac71c1c093c3b97da1f |
10-May-2012 |
Manman Ren <mren@apple.com> |
Revert: 156550 "ARM: peephole optimization to remove cmp instruction"
This commit broke an external linux bot and gave a compile-time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 8ae4f062e4aefe60732b3fc135769aaedddf082d |
10-May-2012 |
Manman Ren <mren@apple.com> |
ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMLoadStoreOptimizer.cpp
LxExpansionPass.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| e5f31ad55ef67231b6e415a4a7dc7f1eb7c0871c |
05-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Nuke a few dead remnants of the CBE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCAsmInfo.cpp
|
| aaf723dd2bccc052d2dd28e3cc4db76f2a3e2fb0 |
05-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3610a15c3581dee713820f72d8ffe2e2a632b057 |
05-May-2012 |
Kevin Enderby <enderby@apple.com> |
Tweak to the fix in r156212, as with the change in removing the shift the
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| ce734d5ffe53273caa7df762f70803050b0ce929 |
05-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the ARM disassembler for wide branch conditional instructions
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 2c7e5c714c8675f757c4936a3a2132c2466a626c |
04-May-2012 |
Sebastian Pop <spop@codeaurora.org> |
Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 39af9449a26054ffbf879f5a7f75da2022e4b235 |
04-May-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Pacify GCC's -Wreturn-type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fd5abd546e8e035755005a654d60d6f5f74cfe2c |
04-May-2012 |
Hans Wennborg <hans@hanshq.net> |
Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 338607ae0ddab00e197222e769748e2e0c0b4e18 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 2d524b0765145f1c7888166c985a25452f16b2bc |
04-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMAsmBackend.cpp
|
| b422d0b65e15435b6aef4a92f5663db9ec6659d4 |
03-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 2727930ab4ce260fef0487bc878c1cd4c3769cef |
02-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0a552d611efe9d1070aff1d35c7f169dd1ab0be7 |
02-May-2012 |
Richard Barton <richard.barton@arm.com> |
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 54319e2a8c22e7ee7044e398fbd8d4287e2b7c4f |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
adds.w r2, #-16
adds.w r2, r2, #-16
addw r2, #-16
addw r2, #-16
addw r2, r2, #-16
rdar://11330769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 94b590f8faf4dbba406f263e6a839882b0c68a94 |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.
rdar://10550147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 7c4ce30ea6a9d0410f306e805403dd224c3df65c |
01-May-2012 |
Bill Wendling <isanbard@gmail.com> |
Change the PassManager from a reference to a pointer.
The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 7a3afa91ad8f68428373948fc16375e99bff3c6f |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Diagnostics for out of range fixups.
Replace some assert() calls w/ actual diagnostics. In a perfect world,
there'd be range checks on these values long before things ever reached
this code. For now, though, issuing a better-late-than-never diagnostic
is still a big improvement over assert().
rdar://11347287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155851 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 887d095fb6c6fb0980ab90a9211fb2420d0da7c0 |
30-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix address calculation error from r155744.
This was exposed by SingleSource/UnitTests/Vector/constpool.c.
The computed size of a basic block isn't always a multiple of its known
alignment, and that can introduce extra alignment padding after the
block.
<rdar://problem/11347135>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155845 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ff73d8fef9a94ceb2fc35d9371deeb0214c0eeee |
30-Apr-2012 |
Bob Wilson <bob.wilson@apple.com> |
Don't introduce illegal types when creating vmull operations. <rdar://11324364>
ARM BUILD_VECTORs created after type legalization cannot use i8 or i16
operands, since those types are not legal. Instead use i32 operands, which
will be implicitly truncated by the BUILD_VECTOR to match the element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155824 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9b10dae0bf3a796ac06e94f072ac67126e30a255 |
28-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a problem with blocks that need to be split twice.
The code could search past the end of the basic block when there was
already a constant pool entry after the block.
Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155753 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a9cc08f24f61e2663a131d7ac16c329b75162e7b |
28-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.
rdar://11219154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| bb32f1d545241ab957f402165cec359d4473c0ca |
28-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ARMDisassembler.cpp
|
| 456ff46e668f361f79e8e91f145152089cd7d933 |
28-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Track worst case alignment padding more accurately.
Previously, ARMConstantIslandPass would conservatively compute the
address of an aligned basic block as:
RoundUpToAlignment(Offset + UnknownPadding)
This worked fine for the layout algorithm itself, but it could fool the
verify() function because it accounts for alignment padding twice: Once
when adding the worst case UnknownPadding, and again by rounding up the
fictional block offset. This meant that when optimizeThumb2Instructions
would shrink an instruction, the conservative distance estimate could
grow. That shouldn't be possible since the woorst case alignment padding
wss already included.
This patch drops the use of RoundUpToAlignment, and depends only on
worst case padding to compute conservative block offsets. This has the
weird effect that the computed offset for an aligned block may not be
aligned.
The important difference is that shrinking an instruction can never
cause the estimated distance between two instructions to grow. The
estimated distance is always larger than the real distance that only the
assembler knows.
<rdar://problem/11339352>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155744 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 7787800481ad854eed5d976778dd493eb49bfaf9 |
27-Apr-2012 |
Lang Hames <lhames@gmail.com> |
Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
<rdar://problem/11325085>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| 04a09a461beb4ec629fe53e601b7665547ac35c3 |
27-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4d2f077df1b46a126b5595d983f233ec896b757e |
27-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
|
| afb3b5ebe61b480527de86311d2a0770fc857d38 |
27-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Implement a bastardized ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMSubtarget.cpp
|
| 97a454317af1903b269d42d368d2263ab79b6ed1 |
27-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
CTargetDesc/ARMMCTargetDesc.cpp
|
| 9da7892fbe1c9e7c592c5928e36724a0e190a777 |
26-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb ldr(literal) base address alignment is 32-bits.
The base address for the PC-relative load is Align(PC,4), so it's the
address of the word containing the 16-bit instruction, not the address
of the instruction itself. Ugh.
rdar://11314619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 37abe8df4a4e74513e2daa0cdf0b801bec94dade |
26-Apr-2012 |
Tim Northover <Tim.Northover@arm.com> |
Use VLD1 in NEON extenting-load patterns instead of VLDR.
On some cores it's a bad idea for performance to mix VFP and NEON instructions
and since these patterns are NEON anyway, the NEON load should be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155630 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e38993f89288f8dd96451fe3ba514950520757ad |
26-Apr-2012 |
Tim Northover <Tim.Northover@arm.com> |
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155626 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e67a4163f5d2ad8e42a3aa0ccdaa27d85f6d5be4 |
26-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.
rdar://11318438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| b56e4115ed33dae56108ed4ce88ee3a0e0392bfc |
25-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 8030e1a0df630ec6ed1cd5ec673f6472558a4dbe |
25-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 14ce6fac242228dacc5c08040e544141a96880e5 |
25-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 95a7e80b5e6423f4daf4c674100706b0036d4fe0 |
24-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Nuke remnant bogus code.
r154362 was supposed to delete this bit, but obviously didn't.
rdar://11305594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| cf5a1461acaace0f3e7d11fbbcfbf635b8c8ea9d |
24-Apr-2012 |
Shih-wei Liao <sliao@google.com> |
Merge with LLVM upstream r155090.
Conflicts:
lib/Support/Unix/PathV2.inc
Change-Id: I7b89833849f6cbcfa958a33a971d0f7754c9cb2c
|
| f4478f99dd63503bf0f0e763bc6d684e738bfe3d |
24-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| c92ba4e90501e407c8f71a18e62b8858513085ed |
24-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns, whitespace, et. al.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 1d52184cd1714876f0a691c98153a8abef204845 |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: VSLI two-operand assmebly aliases are tblgen'erated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155393 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e1d866e3c33ac1c3ad01f4bca4485a711c4fe42c |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155392 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 13b7352fe4883f8ef937a7324309e94398d8cf17 |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: vqdmulh two-operand aliases are tblgen'erated now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155387 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| bfae1fd1fce97e73299e8ad67a22ae18de5112e9 |
22-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Initialize the HasRAS bit.
Found by valgrind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155313 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 8e3c17aabf558e19dcd63e159862022d31951d62 |
21-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: tblgen'erate more NEON two-operand aliases.
VMUL and VEXT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155258 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d83c9ea7d10d8ea5ca8b6cb8a5227b747c505afc |
21-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: tblgen'erate more NEON two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155254 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d8b3ed8f25c1ba76a6db875cd2d6eaa016bd4646 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Update NEON assembly two-operand aliases.
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 420761a0f193e87d08ee1c51b26bba23ab4bac7f |
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 181b14797518e714e1b6112db849ca53192b8f23 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM some VFP tblgen'erated two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2a22b691b6b7c4412a66f80519e504b15e732a18 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM let TableGen handle a few two-operand aliases.
No need for these explicit aliases anymore. Nuke 'em.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155173 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4c8fab82874a29dcd2b242533af3ebe7f66bfd74 |
18-Apr-2012 |
Shih-wei Liao <sliao@google.com> |
Revert "-arm-long-calls of zone."
This reverts commit 316d9307583d2bf375ba6f93ded63a60f7a80c0d.
RMFastISel.cpp
|
| 35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 6b9f97dd892b0d61d8a1f0ee4f837058f2ca4552 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fa1ebc6abe95b79b7f82030eea53586a8704eb7e |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| e546c4c9c3004274c8e275e8303ca078b794bf28 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9e71231309e8924b89aa94ca86cae883db1d2916 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 316d9307583d2bf375ba6f93ded63a60f7a80c0d |
18-Apr-2012 |
Shih-wei Liao <sliao@google.com> |
-arm-long-calls of zonr.
Change-Id: Id7ce13f166a6663d42c164010aad0920264d4594
RMFastISel.cpp
|
| 3f5966b85ea572002bfd0bb2f7c371ed087ae260 |
17-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154953 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ef1a3a25b3398768b9fad5526782675b1a8c128f |
17-Apr-2012 |
Jay Foad <jay.foad@gmail.com> |
Remove unused CCIfSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154921 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 72aadc057c3fb92b5ccbc4c856306abd3b9d3b83 |
17-Apr-2012 |
James Molloy <james.molloy@arm.com> |
Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1 |
17-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| bf42f24e6e2347fbd28abb9d442a6cd9d95fcc3b |
17-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand forms for vhadd and vhsub instructions.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b8768dc32df0bf3edfa2777cdef57bb066e54344 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM handle :lower16: and :upper16: after a '#' prefix.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154862 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 199366a6a6b59717cd1b98d8d5df521e3981de19 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly two-operand forms for VRSHL.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 705e2572b442c34d65a3b667e008327b50bac06b |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VRHADD instructions.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e15660acc226291da49379051c0bf0a02262deb6 |
15-Apr-2012 |
Shih-wei Liao <sliao@google.com> |
Non-static arm-reserve-r9.
Change-Id: I96d9a7cb594d89e0377616ad613f8201e9aa8136
RMSubtarget.cpp
|
| 362a05a635379ca1151e5ccf735295aed814dd4b |
15-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Wire up support for diagnostic ranges in the ARMAsmParser.
As an example, attach range info to the "invalid instruction" message:
$ clang -arch arm -c asm.c
asm.c:2:11: error: invalid instruction
__asm__("foo r0");
^
<inline asm>:1:2: note: instantiated into assembly here
foo r0
^~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154765 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7ece9539c287dd536f56e81c69291454186ad262 |
13-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
On Darwin targets, only use vfma etc. if the source use fma() intrinsic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154689 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6c22695c6d10036f5635caec7ea84dbe84cc6bea |
13-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
For ARM disassembly only print 32 unsigned bits for the address of branch
targets so if the branch target has the high bit set it does not get printed as:
beq 0xffffffff8008c404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 2a7d3a93735f97c2a4cabcc08a88d702c28cb0d4 |
13-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a few more places in the ARM disassembler so that branches get
symbolic operands added when using the C disassembler API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| b54efe809f258af2bd1cfbde6e196f70a8a33081 |
12-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'adr' fixups don't need the interworking addend tweaking.
They reference the PC directly, so things work properly that way.
rdar://11231229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154576 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| b318cc16c9e959adb96294b3aa4940e74f68dde3 |
12-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1835547ec195c35b3a59bf834f4df942c61a5c53 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.
rdar://11222366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 6073b30b053da2c2ac6150dd67cecb304bc614f1 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.
rdar://11221911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 14b4c0358055c3de5ab404e953ba8c8a678c61ae |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Add more fused mul+add/sub patterns. rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154484 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| bee78fe5fcd8464f58bc729dede1a87d763ac3ae |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 92c904539a5e8c021c41d6f134e5df1f90c3eddd |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Match (fneg (fma) to vfnma. rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154469 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| a69da35c127dd7e35ae6216d965670643dc55bb6 |
11-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| a5378ebe7890aa9a4974f2872aa6632f1b7f2400 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 82509e5c62a99912c636b22e227b810eaf6eda78 |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a number of problems with ARM fused multiply add/subtract instructions.
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrNEON.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
RMSubtarget.h
smParser/ARMAsmParser.cpp
|
| 3aef2ff514c879f98571fb91ddbe1142466a6266 |
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Handle llvm.fma.* intrinsics. rdar://10914096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154439 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
RMInstrVFP.td
|
| a23ecc2ba945c9685a76552276e5f6f41859b4ab |
10-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix cc_out operand handling for t2SUBrr instructions.
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.
rdar://11216577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| bf010eb9110009d745382bf15131fbe556562ffe |
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a long standing tail call optimization bug. When a libcall is emitted
legalizer always use the DAG entry node. This is wrong when the libcall is
emitted as a tail call since it effectively folds the return node. If
the return node's input chain is not the entry (i.e. call, load, or store)
use that as the tail call input chain.
PR12419
rdar://9770785
rdar://11195178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 2d620c571cb53993b788893b6ef73a6e2805411f |
10-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM LDR/LDRT has the same encoding collision as STR/STRT.
Generalized logic of r154141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154362 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 7f354557089d93cc681c440f9e064c906e1fbd58 |
09-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
When performing a truncating store, it's possible to rearrange the data
in-register, such that we can use a single vector store rather then a
series of scalar stores.
For func_4_8 the generated code
vldr d16, LCPI0_0
vmov d17, r0, r1
vadd.i16 d16, d17, d16
vmov.u16 r0, d16[3]
strb r0, [r2, #3]
vmov.u16 r0, d16[2]
strb r0, [r2, #2]
vmov.u16 r0, d16[1]
strb r0, [r2, #1]
vmov.u16 r0, d16[0]
strb r0, [r2]
bx lr
becomes
vldr d16, LCPI0_0
vmov d17, r0, r1
vadd.i16 d16, d17, d16
vuzp.8 d16, d17
vst1.32 {d16[0]}, [r2, :32]
bx lr
I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll,
but I couldn't think of a way to judiciously apply this combine.
This
ldrh r0, [r0, #4]
strh r0, [r1]
becomes
vldr d16, [r0]
vmov.u16 r0, d16[2]
vmov.32 d16[0], r0
vuzp.16 d16, d17
vst1.32 {d16[0]}, [r1, :32]
PR11158
rdar://10703339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154340 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 96b66d65c23a596447ce3b14775f5c803fec47b3 |
09-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Update comments and remove unnecessary isVolatile() check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154336 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 93abbc272a1445d5108dfe9bddd323f6ac7b96a2 |
07-Apr-2012 |
Bob Wilson <bob.wilson@apple.com> |
Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/11203543>
The tLDRr instruction with the last register operand set to the zero register
prints in assembly as if no register was specified, and the assembler encodes
it as a tLDRi instruction with a zero immediate. With the integrated assembler,
that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which
is broken. Emit the instruction as tLDRi with a zero immediate. I don't
know if there's a good way to write a testcase for this. Suggestions welcome.
Opportunities for follow-up work:
1) The asm printer should complain if a non-optional register operand is set
to the zero register, instead of silently dropping it.
2) The integrated assembler should complain in the same situation, instead of
silently emitting the operand as "r0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154261 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d4f020a3af325630973df8d3a084d0b0e3b68ebc |
07-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFastISel.cpp
RMISelLowering.cpp
RMTargetMachine.cpp
humb2SizeReduction.cpp
|
| 967cbbd8b5a328498b27a70bfa5f621c853692df |
06-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARMPat is equivalent to Requires<[IsARM]>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154210 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| aa395e8c5dcc6d13f1f8ae65ce89f36383cb714a |
06-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Eliminate iOS-specific tail call instructions.
After register masks were introdruced to represent the call clobbers, it
is no longer necessary to have duplicate instruction for iOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154209 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| ba4d45737f6e1094195823b33fb9868570ae1701 |
06-Apr-2012 |
Chandler Carruth <chandlerc@gmail.com> |
There is no portable std::abs overload for int64_t, use the llvm::abs64
which exists for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154199 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 70fbea7c7598c8803a325ffca98069ff013a2994 |
06-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Allow negative immediates in ARM and Thumb2 compares.
ARM and Thumb2 mode can use cmn instructions to compare against negative
immediates. Thumb1 mode can't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154183 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f16936e5923156863906c915de657b134db4fb16 |
06-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Deduplicate ARM call-related instructions.
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMFastISel.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 3ef737608ab005f320c2e20fcb3b914c677616ed |
06-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.
The load/store optimizer splits LDRD/STRD into two instructions when the
register pairing doesn't work out. For negative offsets in Thumb2, it uses
t2STRi8 to do that. That's fine, except for the case when the offset is in
the range [-4,-1]. In that case, we'll also form a second t2STRi8 with
the original offset plus 4, resulting in a t2STRi8 with a non-negative
offset, which ends up as if it were an STRT, which is completely bogus.
Similarly for loads.
No testcase, unfortunately, as any I've been able to construct is both large
and extremely fragile.
rdar://11193937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154141 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 4e53fe8dc61ad48650ac6fe30d7268ec92b7fc1a |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.
rdar://11192734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 1c01249191ba5d3648e7bedaf8233c41cc103551 |
05-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 82e1bba0e4afaf3769fc46819c1601e387ffb56e |
05-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for handling unpredictable arithmetic instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 22378fd664fed97c296878d8d188ab06e2c89395 |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://11189467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b657a90929867716ca1c7c12d442bb5d32281bd4 |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for 'msr' plain 'cpsr' operand.
Plain 'cpsr' is an alias for 'cpsr_fc'.
rdar://11153753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c5041cac7d3aeaa7350abadf2a7ada92e8da27dc |
04-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.
<rdar://problem/11182914>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154033 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.td
RMInstrThumb2.td
EADME.txt
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 75e3b7fb8fdf069b6f9f1e1db9634ca5701cbe96 |
03-Apr-2012 |
Dylan Noblesmith <nobled@dreamwidth.org> |
ARMDisassembler: drop bogus dependency on ARMCodeGen
And indirectly, a dependency on most of the core LLVM optimization
libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153957 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/LLVMBuild.txt
|
| c97ef618d2d849a272a353c2b4343fc5902cd921 |
02-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
All implementations used the same code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 7c0b3c1fb6395475e262d66ee403645f0c67dee2 |
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 17463b3ef1a3d39b10619254f12e806c8c43f9e7 |
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 3ee3661f8f10e7f82094a89c40d9118630ab0a40 |
31-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a 2 byte safety margin in offset computations.
ARMConstantIslandPass still has bugs where jump table compression can
cause constant pool entries to go out of range.
Add a safety margin of 2 bytes when placing constant islands, but use
the real max displacement for verification.
<rdar://problem/11156595>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 101c03a8c9042781b6c9ba1fcc366e14fc8534ce |
31-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add more debugging output to ARMConstantIslandPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| bf3c322640fdaf6e4a60a59ed8cb108a7f6685ad |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix encoding fixup resolution for ldrd and friends.
The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.
rdar://11158641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| ad353c630359d285018a250d72c80b7022d8e67e |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler should prefer non-aliases encoding of cmp.
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a45e3747e612c00ca4933087d883db77f4547571 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8f1148bd07d57a1324ed39250642119baa540b7c |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM can only use narrow encoding for low regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2d30d947ec2626e8b1a9b577cdfa4121f476c3f5 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM integrated assembler should encoding choice for add/sub imm.
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.
rdar://11156277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c0164f86080bc9d7a41fd5eabd0d6556396f5b38 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing needs to be paranoid about negative immediates.
Make sure to treat immediates as unsigned when doing relative comparisons.
rdar://11153621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cb0809b82b126e79b99755ae4fc3d9733faea038 |
30-Mar-2012 |
James Molloy <james.molloy@arm.com> |
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMFixupKinds.h
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| 1c80f56268fa91f9c0c4d0a32b5d61e7b900c6d4 |
30-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7a4c071cd9f67599eba21e902079d0e85f2abf97 |
30-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Invalidate liveness in ARMConstantIslandPass.
This pass splits basic blocks to insert constant islands, and it
doesn't recompute the live-in lists. No later passes depend on accurate
liveness information.
This fixes PR12410 where the machine code verifier was complaining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ccca22e9e2e03bdd782b1d4bf880ebf79e7b7e77 |
30-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Prefer even-odd D-register pairs.
We are sometimes allocatinog from the DPair register class which
contains odd-even pairs in addition to the Q registers.
Place the Q registers first in the DPair allocation order as they can be
copied with a single instruction. The odd-even pairs should only be
allocated as a last resort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| c0a9f820d851baf66577a87c69ef383df41bbe32 |
29-Mar-2012 |
Lang Hames <lhames@gmail.com> |
Try using vmov.i32 to materialize FP32 constants that can't be materialized by
vmov.f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b22e70d835a88753d3ec6d5ee5e85b23fa6834b1 |
29-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 85bdf2e76a0351468f231f48069c64bc6938f140 |
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle register copies for the new ARM register classes.
ARM recently gained DPair, DTriple, and DQuad register classes.
Update copyPhysReg() to handle copies in these register classes.
No test case, it is difficult to make the register allocator emit the
odd copies reliably. The missing DPair copy caused a failure on
partialsums in the nightly test suite.
<rdar://problem/11147997>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 892143ff70b5e7d0cb06e7c4596c232347806b17 |
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't kill the base register when expanding strd.
When an strd instruction doesn't get the registers it wants, it can be
expanded into two str instructions. Make sure the first str doesn't kill
the base register in the case where the base and data registers are
identical:
t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg
t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg
<rdar://problem/11101911>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153611 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| dc909bf46ba94bf123bf5c7273fa867bddffc4a2 |
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve implicit defs in ARMLoadStoreOptimizer.
When a number of sub-register VLRDS instructions are combined into a
VLDM, preserve any super-register implicit defs. This is required to
keep the register scavenger and machine code verifier happy.
Enable machine code verification after ARMLoadStoreOptimizer.
ARM/2012-01-26-CopyPropKills.ll was failing because of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153610 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
|
| 5b2f9136644c58ae32e00d8317540692a697d1c9 |
28-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Spill DPair registers, not just QPR.
The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.
This fixes PR12389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 8d813de71e18dd73ed98e8d58407caba0265e38e |
28-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r153516: "Invalidate liveness in Thumb2ITBlockPass."
Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness."
These patches caused miscompilations in povray by turning off branch
folding's updating of live-in lists.
It turns out the the late scheduler depends on the live-in lists, even
if it doesn't need correct kill flags.
<rdar://problem/11139228>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153593 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
humb2ITBlockPass.cpp
|
| 6e9d66c756a3d3f0d1636a9f1143dedd2f58138b |
28-Mar-2012 |
Richard Barton <richard.barton@arm.com> |
Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 805543068eb7407d718b0359f54b342d7094d0ea |
27-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARMLoadStoreOptimizer invalidates register liveness.
This pass tries to update kill flags, but there are still many bugs.
Passes after the load/store optimizer don't need accurate liveness, so
don't even try.
<rdar://problem/11101911>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153519 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 33fa614b16db175d0687eb34aea3a080d0d237c2 |
27-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Invalidate liveness in Thumb2ITBlockPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153516 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 4e02f23de24375294005f88b5254a3775d39fcb2 |
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
smParser/ARMAsmLexer.cpp
CTargetDesc/ARMAsmBackend.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.h
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
|
| e279f5953e9c3d934248cd4d2f24b6179ad9d2e6 |
27-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
ARM has a peephole optimization which looks for a def / use pair. The def
produces a 32-bit immediate which is consumed by the use. It tries to
fold the immediate by breaking it into two parts and fold them into the
immmediate fields of two uses. e.g
movw r2, #40885
movt r3, #46540
add r0, r0, r3
=>
add.w r0, r0, #3019898880
add.w r0, r0, #30146560
;
However, this transformation is incorrect if the user produces a flag. e.g.
movw r2, #40885
movt r3, #46540
adds r0, r0, r3
=>
add.w r0, r0, #3019898880
adds.w r0, r0, #30146560
Note the adds.w may not set the carry flag even if the original sequence
would.
rdar://11116189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153484 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f1d0f7781e766df878bec4e7977fa3204374f394 |
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMELFObjectWriter.cpp
|
| 0e5233a9e5ee9385c6a940e3985194d77bee0bbb |
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMCallingConv.h
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
|
| acf2077ca497980a066e8e7bb81ceec0de82d5da |
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.h
RMJITInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.h
|
| 805853bc59ecdae1746473d2b4178e9275a1b997 |
25-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153415 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.h
|
| c59a7995d22e2889706810c90a20a51ecfec278b |
24-Mar-2012 |
Shih-wei Liao <sliao@google.com> |
Merge branch 'upstream' into sliao_d
|
| 7a465250564d2ae0cc53ebe58732a751daa43e8d |
24-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM tidy up ARMConstantIsland.cpp.
No functional change, just tidy up the code and nomenclature a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153347 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6fe310e1555dedba2b36dedae9a88eb900ad1804 |
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| b7c2ed66642b141a768b3074c465eba9d98665d8 |
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| a0c48eb8f69bcb619a2c2cc0044375bb4171cebe |
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f0586f08dfd5bf1889c15849e9c603b3985fce4a |
21-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 03a18525385bafdb6763629aed144b6b8063290d |
20-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 98a27acc6b1d4bc4bda6eb122851b3f9b39efeb8 |
20-Mar-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| aaa1e2f820e61a2f4b878d97599b3ca093bc96ed |
20-Mar-2012 |
Bob Wilson <bob.wilson@apple.com> |
Require a base pointer for stack realignment when SP may vary dynamically.
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls. Use hasReservedCallFrame() to
check for both. The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.
<rdar://problem/11075906>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 055a8127c9ffee287807fe7cc1b115d0f40162b0 |
20-Mar-2012 |
Bob Wilson <bob.wilson@apple.com> |
Remove some redundant checks.
ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
|
| 9f2e160f7ae90a7a80b17e38ad06f2c706515115 |
20-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix assembling ARM vst2 instructions with double-spaced registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 07cdd80ccc1a07edc565199c62d35ea0d80c6c1c |
20-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM non-scattered MachO relocations for movw/movt.
Needed when building -mdynamic-no-pic code.
rdar://10459256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 5c062ad92672f22e61a4b20a9954af3db3b72bd6 |
20-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| db9ca59759aeedfca9a9ceee55798587c4beceec |
20-Mar-2012 |
Richard Barton <richard.barton@arm.com> |
Test Commit - add a newline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fa1f74470a51a57b7b8feb4c4ba18501c3f2709a |
19-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM branch relaxation for unconditional t1 branches.
rdar://11059157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| ceee984302a1cf1d659a186cf94149c779866da5 |
19-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly, accept optional '#' on lane index number.
rdar://11057160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2d7ea04e2822bbe5faad0eefceb7a300ea01224e |
19-Mar-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Perform mul combine when multiplying wiht negative constants.
Patch by Weiming Zhao!
This fixes PR12212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c1f6f42049696e7357fb4837e1b25dabbaed3fe6 |
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes to match coding standards. Fix an issue or two exposed by that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMBaseRegisterInfo.cpp
RMCallingConv.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
humb1FrameLowering.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 5aeff3171c173dec9a6e6f89e428a0a78698c43e |
17-Mar-2012 |
Bill Wendling <isanbard@gmail.com> |
Check if we can handle the arguments of a call (and therefore the call) in
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 11d5dc3d50217711462b453ca9592e39d0c879e7 |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix silly typo in optional operand alias.
rdar://11065671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 66cba302f0e9de6f4e9401b24375d791aad32b6b |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM divided syntax fmrx/fmxr mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| be7cf2b377d987f46d10f54f89ae4e1a71c37f55 |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM ldm/stm register lists can be out of order.
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 213d2e7dc31bef3ceeef0cefa703cb4ce52de51a |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM optional operand on MRC/MCR assembly instructions.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 9426ac7b575de9e1297a01f27307d858343ac4ed |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vmrs system registers mvfr0 and mvfr1 handling.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMRegisterInfo.td
|
| 89eaa6f554c362799a86ca50bdbaab72402565d2 |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Remove inadvertant commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x
|
| 0ac754f6f43a0e5a56f712aebb663581ae512e4c |
15-Mar-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Address Eli's comments for r152847. Specifically, add a test case
and still allow immediate encoding, just not with cmn.
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 530b19b70212f02cffa971256501e77284c320a0 |
15-Mar-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Don't try to encode LONG_MIN using cmn instructions.
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b84ad4aa7dacfba5337520740d47770f2200201c |
15-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM case-insensitive checking for APSR_nzcv.
rdar://11056591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
smParser/x
|
| 6357caec785268d1e39059d03eb2034dee65467f |
15-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
rdar://11056647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 45b5f88938f59c495209512b545f289bf2cca90a |
15-Mar-2012 |
Lang Hames <lhames@gmail.com> |
Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on
register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 8a6bcc3722729803a16b5885de1ff85a3752e6a0 |
15-Mar-2012 |
Kristof Beyls <kristof.beyls@arm.com> |
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2bbb22b8ef571cc11e0c0bb0a0f13670b5ef5cff |
12-Mar-2012 |
Bob Wilson <bob.wilson@apple.com> |
Switch to unified syntax for VFP instructions in inline assembly.
<rdar://problem/11024696>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152548 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| c5eaae4e9bc75b203b3a9922b480729bc4f340e2 |
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMISelLowering.cpp
|
| b78ca423844f19f4a838abb49b4b4fa7ae499707 |
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers and opcode in static tables in the target specific backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
isassembler/ARMDisassembler.cpp
humb2SizeReduction.cpp
|
| fac259814923d091942b230e7bd002a8d1130bc3 |
08-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| fd03ccddedce13a216c9b6e04e9d0ca6b163170e |
08-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM don't use MCRelaxAll, as it's not safe on ARM.
The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.
rdar://11006355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 44c98b71148d11368c18ffb9c14e8a28a76a8021 |
07-Mar-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point
condition flags to CPSR. This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 05d88f4fea6f7565d3d89ab2ac54e54e32fbc09a |
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-v6 assembly parsing for umull/smull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0104dd3ffd75b9620610b63eaa72f573f5a20752 |
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-v6 alias for 'nop' to 'mov r0, r0'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ff3164a1893c61dc0b7169dba9705c2d8e80dfec |
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Remove dead code that slipped into previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 4d0983a4d734280d481bb56472fe44ad0ddc447d |
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMBaseInfo.h
|
| c0fc450f0754508871bc70f21e528bf2f1520da1 |
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| bde1b2a5a8cef66f67513c9f4309b7fae798c679 |
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Kill some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 14f87e01ca704b2916a4c0c5360f3d703c85806f |
06-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Allow the same types in DPair as in QPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 158c8a49c23d01297e7913c03c1fdb0760aee3a8 |
06-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 3247af294996ff8588077c06505b64966ad41542 |
06-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add <imp-def> operands when reloading into physregs.
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register. When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 4f92b5e6163b16d63eb63269c2aec670b55ea19a |
06-Mar-2012 |
Lang Hames <lhames@gmail.com> |
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFastISel.cpp
RMInstrVFP.td
RMRegisterInfo.td
|
| bc978a60d90a06b2d879b6f4db22b3760168df7f |
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
rdar://10988114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 8019aac390baf43b3907d92928bad7fbe62588c6 |
06-Mar-2012 |
Stephen Hines <srhines@google.com> |
Merge with upstream LLVM @152063
Removed call to getsid() from LockFileManager.cpp, since bionic doesn't have
support for it.
Build updates
+TableGenAction.cpp
+X86ModRMFilters.cpp
-InstrEnumEmitter.cpp
-JITDebugRegisterer.cpp
-MCLoggingStreamer.cpp
+Hashing.cpp
-ElfCodeEmitter.cpp
-ElfWriter.cpp
-ObjectCodeEmitter.cpp
+DataStream.cpp
+StreamableMemoryObject.cpp
+CmpInstAnalysis.cpp
+LockFileManager.cpp
+IntrusiveRefCntPtr.cpp
+ThreadSanitizer.cpp
+ARMMachineFunctionInfo.cpp
+ARMELFObjectWriter.cpp
+MipsAnalyzeImmediate.cpp
+MipsMachineFunction.cpp
+X86MachineFunctionInfo.cpp
+X86ELFObjectWriter.cpp
+X86WinCOFFObjectWriter.cpp
+ResourcePriorityQueue.cpp
+ScheduleDAGVLIW.cpp
+MachineCopyPropagation.cpp
+MachineScheduler.cpp
+RegAllocBase.cpp
+libLLVMVectorize
Change-Id: I69e700fe357e275ec509af1daaa7408cd3cde3a1
ndroid.mk
CTargetDesc/Android.mk
|
| c02a5c5e8d9c1fd2a20ad4aed40f328564e95b40 |
05-Mar-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge-20120305
Conflicts:
lib/Support/Atomic.cpp
Change-Id: I563b3bc2a82942ccbae5bed42e53b9149a8bf3a0
|
| c3384c93c0e4c50da4ad093f08997507f9281c75 |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM Refactor VLD/VST spaced pair instructions.
Use the new composite physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| af9f4bc752292b3282f110c11aeb2a1ffb710bbf |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM Remove a bit of dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 28f08c93e75d291695ea89b9004145103292e85b |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMFrameLowering.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMBaseInfo.h
|
| c6449b636f4984be88f128d0375c056ad05e7e8f |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Make MCRegisterInfo available to the the MCInstPrinter.
Used to allow context sensitive printing of super-register or sub-register
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 74bebde7c4e2d1cfd4a16c19ce3c87521df67639 |
05-Mar-2012 |
Sebastian Pop <spop@codeaurora.org> |
updated patch for the ARM fused multiply add/sub
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.
Patch by Ana Pazos <apazos@codeaurora.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 9ebfbf8b9fd5f982e0db9293808bd32168615ba9 |
05-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| fce711cb65716f86b4e150f42cbb597bbecf7dbe |
04-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use <def,undef> operands when spilling NEON bundles.
MachineOperands that define part of a virtual register must have an
<undef> flag if they are not intended as read-modify-write operands.
The old trick of adding an <imp-def> operand doesn't work any longer.
Fixes PR12177.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152008 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b6632ba380cf624e60fe16b03d6e21b05dd07724 |
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameLowering.cpp
RMISelLowering.cpp
humb1FrameLowering.cpp
|
| fc501a3ec9d97e372ecb1bd9cf32d861da46b2c9 |
02-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
Neuter the optimization I implemented with r107852 and r108258 which turn some
floating point equality comparisons into integer ones with -ffast-math. The
issue is the optimization causes +0.0 != -0.0.
Now the optimization is only done when one side is known to be 0.0. The other
side's sign bit is masked off for the comparison.
rdar://10964603
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151861 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b24b820bd7ddfe118141422f4d0cf378b2c9a6fd |
01-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().
This function could have r12 live across a function call when compiling
thumb1 code.
The test case for this is not included because it is very long. It must
provoke emergency spilling near a function call. The behavior is
provoked by MultiSource/Applications/JM/lencod, and it triggers an
assertion in the scavenger.
<rdar://problem/10963642>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151855 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| e751c0069aee16e85156d6539f4b724f71c341c6 |
01-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM use the right opcode for FP<->Integer move in fast-isel.
rdar://10965031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151850 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b0578512c79134136e8b53c62a8677ab8e600be2 |
01-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
runs into the undefined 15 condition code value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| adef06a71458ded0716935a61b3d43d164d4df12 |
29-Feb-2012 |
Derek Schuff <dschuff@google.com> |
Make MemoryObject accessor members const again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151687 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| c01810eeb7227010f73cb39e3c4fa0197a3c4ef0 |
29-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM implement TargetInstrInfo::getNoopForMachoTarget()
Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| c94206e5521d06d196a290e0c4431150e6be031b |
28-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vbit/vbif/vbsl assembly optional size suffix.
These instructions accept but do not require a size suffix.
rdar://10947225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151646 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMSelectionDAGInfo.cpp
RMSubtarget.h
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMSelectionDAGInfo.cpp
RMSubtarget.h
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMSelectionDAGInfo.cpp
RMSubtarget.h
|
| 0f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9 |
28-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable ARM base pointer when calling functions with large arguments.
When an outgoing call takes more than 2k of arguments on the stack, we
don't allocate that call frame in the prolog, but adjust the stack
pointer immediately before the call instead.
This causes problems with the emergency spill slot because PEI can't
track stack pointer adjustments on the second pass, and if the outgoing
arguments are too big, SP can't be used to reach the emergency spill
slot at all.
Work around these problems by ensuring there is a base or frame pointer
that can be used to access the emergency spill slot.
<rdar://problem/10917166>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151604 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1RegisterInfo.cpp
|
| 7b25ecf6adbf3c4709c48033acfeb6ebbb4452ab |
27-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMFixupKinds.h
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| 0943303d31b1d1f2111725e2fa6906c0a785b96e |
27-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the symbolic operand added for the C disassmbler API for the ARM bl
thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151530 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 120cfdf0e0a53f858970874476a21cffb8069847 |
24-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused cl::opt, make another opt static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151398 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 9e931f6a64d329276d6253ec1baec9df96f4bbd6 |
24-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 asm aliases for wide bitwise w/ immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4df4f5b49baa108271ae29473bf45cb6b6ec4cc1 |
24-Feb-2012 |
Jia Liu <proljc@gmail.com> |
comment fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151339 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMFixupKinds.h
|
| c54f6348861517398f17e85f41b30c4dd079fc3d |
24-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARM target to register masks.
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.
This patch does cause some assembly changes. Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected. MachineCopyPropagation may sometimes
leave a dead copy behind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| d1b220a33b16d97ef4194b4da625ba1c57974dee |
24-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Make sure the regs are low regs for tMUL size reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151318 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| fdf7c850321bba542e181ae035507d9c71d95364 |
24-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 size reduction fix for tied operands of tMUL.
The tied source operand of tMUL is the second source operand, not the
first like every other two-address thumb instruction. Special case it
in the size reduction pass to make sure we create the tMUL instruction
properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151315 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| db9538923eb95df48e9a6abe7e3b0ba8435915d7 |
24-Feb-2012 |
Dan Gohman <gohman@apple.com> |
When emitting a cmp with 0 for a lowered select, mask out the high
bits of the value carying the boolean condition, as their contents
are undefined. This fixes rdar://10887484.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151310 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b80d571ea85db5d52fafed0523cf59e693502198 |
23-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1b14f20ef7b35b9209ba6ab394773278936babe9 |
23-Feb-2012 |
Duncan Sands <baldrick@free.fr> |
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151251 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5fb468a6b308b643edf61f1731b6d95fd1a03bf4 |
23-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bits
of x are zero. This optimizes rev + lsr 16 to rev16.
rdar://10750814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151230 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c892aeb26601cc5109490d30c7e170cb07f84428 |
23-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 90f20044ade3712c8b0c3f4ebe47d57ad15ae6ce |
22-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Remove extra semi-colons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 209600bb8830036f981238494ab0188c25364837 |
22-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clarify ARM calling conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151113 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a1aa8db51715bdd21770fbe4f7d7abf2c5d28829 |
22-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Calls don't really change the stack pointer.
Even if a call instruction has %SP<imp-def> operands, it doesn't change
the value of the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151104 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 07043279f60622243d16d8a3f60805960482083c |
21-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Proper support for a bastardized darwin-eabi hybird ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
RMSubtarget.cpp
|
| 873fd5f75332023ee8d8b4f9a85351f25e7f1e90 |
20-Feb-2012 |
James Molloy <james.molloy@arm.com> |
Improve generated code for extending loads and some trunc stores on ARM.
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| b0934ab7d811e23bf530371976b8b35f3242169c |
19-Feb-2012 |
Ahmed Charles <ace2001ac@gmail.com> |
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 9ad012a29c72881623fdfb135f4faa81807ea29b |
19-Feb-2012 |
Jia Liu <proljc@gmail.com> |
comment fix ARM.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150904 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMAsmPrinter.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMBuildAttrs.h
RMCallingConv.h
RMCallingConv.td
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMExpandPseudoInsts.cpp
RMFrameLowering.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.cpp
RMMachineFunctionInfo.h
RMPerfectShuffle.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMRelocations.h
RMSchedule.td
RMScheduleV6.td
RMSubtarget.cpp
RMSubtarget.h
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMAddressingModes.h
CTargetDesc/ARMMCAsmInfo.cpp
CTargetDesc/ARMMCAsmInfo.h
CTargetDesc/ARMMCExpr.h
CTargetDesc/ARMMCTargetDesc.cpp
LxExpansionPass.cpp
humb1FrameLowering.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
|
| 2420b558de5d291d8503c1339004e5b5bf99a48a |
17-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle regmask operands in ARMInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150833 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb2InstrInfo.cpp
|
| 8c3b87cf19df5631125254784d57446b80e12397 |
17-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix ARMBaseInstrInfo::getInstrLatency for calls.
Calls always clobber CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150831 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b8703fe265d44a3eb909c289cb5d31b840ca893c |
17-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for returning non-legal types with no sign- or zero-
entend flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59 |
17-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a69feb0f33788b13aa4c25736e50afc6f2b4ce44 |
16-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Remove unnecessary assignment to temporary, ResultReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150737 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1834df8384354217c59e1c5dd8bc091c11b8ca43 |
16-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Oop - r150653 + r150654 broke one of my test cases. Backing out for now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| afae28b1c67171a567c6f0274a7dede83ac5d8f1 |
16-Feb-2012 |
Lang Hames <lhames@gmail.com> |
FPSCR shouldn't be reserved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150654 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 40d552e0be0ba66a3d8e31bf797f1acba4c91b17 |
15-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Add braces to if clause to make symmetric with associate else clause.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150591 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4a1ff2fb3ecaa2576ecf9ed84816b174c235ac1d |
15-Feb-2012 |
Bill Wendling <isanbard@gmail.com> |
Strip the pointer casts from the constants here.
The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150572 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 92fd01736484262fef049b7358366d8eab2f857e |
15-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Use a temporary variable, rather then a series of redundant calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150536 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5793a6586d94a5032a815af97113c3ba47cbdf8a |
14-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Remove unnecessary assignment to temporary, ResultReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150520 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1a4cb1caf0be953e5d7b201aca4ad54579751020 |
14-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Third time's the charm...?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150447 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6b0e9d97fad402b269b580bd372bed9ecb836645 |
14-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Unswap swap operands, partially reducing confusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150444 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| bdf9db6f4905fcbbcdbdfed328ea8b36b655dd45 |
14-Feb-2012 |
Bill Wendling <isanbard@gmail.com> |
Don't reserve the R0 and R1 registers here. We don't use these registers, and
marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2cc494b963e68895d6b6173bcc2ea02995d71442 |
14-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Make operands for VSWP read-modify-write.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150433 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 88b6fc06db667bd26d6ef661597affaa6abfdd0d |
11-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make the EDis tables const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| f06dfa786064edc3bb6de92bb3783d0c23f4d34a |
10-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Revert r150222, as the clang driver now handles this properly.
Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150274 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 1de886c1fa932b9c33d1f9d34698bafa9cdabebd |
10-Feb-2012 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Make valgrind happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150251 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e009860049c0062fc1c708e46c7d868a84e3a41f |
10-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM on darwin, v6 implies the presence of VFP for the assembler.
rdar://10838899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150222 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 3015dfb7d739f4cc0b1408555889ecea880ffac9 |
09-Feb-2012 |
James Molloy <james.molloy@arm.com> |
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 1dd8c8560d45d36a8e507cd014352f1d313f9f9e |
08-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.
While cleaning up declarations, cleaned up comments (sorry for large diff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 743e19983effd486c1911f5b797aea7133ea154c |
08-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for SUBs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6fde8756215a725578b6afe678757f60d7f55d06 |
08-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for ORs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 60c8fa6bb9db791acf6846fe250c184e3f1df168 |
08-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4ee1c5cf6c18db0fa4946437f0bca3dbb313e21b |
07-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed
load / store) if the ADD / SUB has a live definition of CPSR.
Bug reported by David Meyer. Alas, no test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149970 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMConstantPoolValue.cpp
RMELFWriterInfo.cpp
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMMCInstLower.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAddressingModes.h
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCExpr.cpp
humb1RegisterInfo.cpp
|
| 3901c3e75009f2ec7b4e67c354170dadab9e5a02 |
07-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for ADDs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2ea93875b2f2900b9d244dfd7649c9ed02a34cd7 |
06-Feb-2012 |
Derek Schuff <dschuff@google.com> |
Enable streaming of bitcode
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| dc7c716a1cfc27a12f3bbfa44bd80904ee782779 |
05-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
DefinesPredicate should only look for def operands. Patch by Ludwig Meier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149846 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5b8a1db7ea6510a2589f710d50754599da742de9 |
05-Feb-2012 |
Duncan Sands <baldrick@free.fr> |
Persuade GCC that there is nothing worth warning about here (there isn't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 061efcfb3e79899493d857f49e50d09f29037e0a |
04-Feb-2012 |
Andrew Trick <atrick@apple.com> |
TargetPassConfig: confine the MC configuration to TargetMachine.
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 769422f0fce4def419c8cdb72ee967437ffd2f4f |
03-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for URem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149716 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ae46a3362d6c7fd2d4b1bf3b40982d289d7418fb |
03-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Rename isZExt to isSigned. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149714 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7ccb30b5964675a70559ec25a6bff32f7dea1025 |
03-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for UDIV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149712 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ee8901c08fb27e98078326706a49dba70e1768a3 |
03-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 36b7beb42921c428fc9f5b5a9cc9feb7fe7dd4b3 |
03-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Add support for selecting UIToFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 843ee2e6a46b2b2d74a84c2eea68dec35cb359cc |
03-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetPassConfig. The first little step toward configuring codegen passes.
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 42865588d7263593d102dcdf2f8f0994dca4bba4 |
02-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add pseudo-registers for pairs, triples, and quads of D registers.
NEON loads and stores accept single and double spaced pairs, triples,
and quads of D registers. This patch adds new register classes to
accurately model those constraints:
Dn, Dn+1 Dn, Dn+2
----------------------
DPair DPairSpc
DTriple DTripleSpc
DQuad DQuadSpc
Also extend the existing QQ and QQQQ register classes to contains all Q
pairs and quads instead of just the aligned ones.
These new register classes will make it possible to accurately model
constraints on NEON loads and stores, and we can get rid of all the NEON
pseudo-instructions. The late scheduler will be able to accurately
model instruction dependencies from the explicit operands.
This more than doubles the number of ARM registers, but the backend
passes are quite good at handling this. The llc -O0 compile time only
regresses by 1.5%. Future work on register mask operands will recover
this regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149640 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 521804a1f702b80158b6490c8f22d1dc6a8b9c65 |
02-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move ARM subreg index compositions to the SubRegIndex itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149557 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 24dda217052b48373ed89d043a778aabb2f65080 |
01-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. One more return type mismatch fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149452 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0c3cfefca62eeaf1f98a49756e3bcb2c451b3374 |
31-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Refactor loop for better readability.
Excellent suggestion from Ben Kramer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149417 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| c73f42b54028e0fce3e7159b76cd59e78107023d |
31-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Add explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149416 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6edd5884c91aea72661ed899b0c91dfb4f0ea80f |
29-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleanups for EABI standard functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149195 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f349cb8f33665bf854b4d0a05012d958072febd4 |
29-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use base AAPCS for varargs functions even for AAPCS-VFP CC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149194 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7750ff1e3cbb87e68f406e6fa7c43a80a61a0ccb |
28-Jan-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add a note about a potential optimization for clz/ctz patterns for ARM
(and other targets).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149182 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2d8955a77c6920d1a50de5ec9094faaa1b2f4e88 |
28-Jan-2012 |
James Molloy <james.molloy@arm.com> |
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
Fixes PR11877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| 6b4bcd69d02e67bb00496db4d296fa7ab768d36f |
27-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Better user diagnostics for more ARM MachO relocation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149102 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 42e6bd38e02e2e1c2cc50d2f12036c38c4ea3ab0 |
27-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Keep source information, if available, around for ARM Fixups.
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149093 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| ef4d3ebe2a36ebfd9370e1efbe74dff13f64c40f |
26-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Fix mismatched return types for error handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149062 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 34982576a43887e7f062ed0a3571af2cbab003f3 |
26-Jan-2012 |
James Molloy <james.molloy@arm.com> |
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
CTargetDesc/ARMELFObjectWriter.cpp
|
| 4a99f59aef358fb93eac180e49f6dcef03822046 |
25-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly emit ctors / dtors with priorities into desired sections
and let linker handle the rest.
This finally fixes PR5329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| 74423e32ce7f426b624bfb0c31481bcf6a36394d |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| a57a36abe7d0b769a495ed886246db157aff4add |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 6cd6a6824fa611b8da8b01daa5239256fe0661e9 |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Rename VLD4DUP patterns for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148883 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5e59f7e15ed3770b32481cd72d2c15b159e991e6 |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 88a54de799240d5de2e79dfff4671ad5653e7ceb |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 4f8dc7b17accf4f2ec953b80b2cc79786207492e |
24-Jan-2012 |
Owen Anderson <resistor@mac.com> |
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| e983a134e7e40e214f590c3d8ba565bb85f39628 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 1ac2060678edd88726e06ff19c9468211b41fc37 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSRA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5e497d39927d2ddf6bf6adbfac39fe9102a1a305 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d8ee0cc4e8b67f9d85d08bd55e53ac14c5ca533d |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 78d13e191e0f6bcb4bef5bc5c8c5f6e5be1f4070 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON add correct predicates for some asm aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148815 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 46de2d5f5b83dfb8c1e56242fa656a3444ec7f3d |
24-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use correct register class for am2offset register operands.
This pacifies machine verifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148782 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 539aab771fea06bd230789e19c9672ef80ad1c7e |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 8abe7e33641fccfa70a7e335939e83dfbf654fe8 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 7945eade3d8db8c1dd52a291cee5d55ac0539586 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Remove some vertical space for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148761 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3eb4be0ace6263f35a2f3aae9e964a752ebe55af |
24-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert r148686 (and r148694, a fix to it) due to a serious layering
violation -- MC cannot depend on CodeGen.
Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.
Fixing this is likely going to require some non-trivial refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
CTargetDesc/ARMMCAsmInfo.cpp
|
| 7b426cee22a3cac030ec7ace0be04ee8569f18c7 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148757 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4adb18234278d6d40e5791e0dd6970be9a4b0b57 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST3(single element from one lane) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| d7433e2873706265d545edc5cdd0a728dd71ef66 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| c387fc66bd52e4276fdc2704a3aaed57cc1f9a11 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 2c6d0f2625b4509d50006b931d053bed08e19fc2 |
23-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add missed mayStore flag to STREXD / t2STREXD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148742 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 3a678af71dec76a7e1474ad85a99b3588516906d |
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3 lane-indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 8b31f95bdde1e3809a1c9fdb6926b1840effcf9c |
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| db4b85f532314e5972fedb1c1e04820de3cabc83 |
23-Jan-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148694 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7908480e4caf2f7ecb0b62c900039d49e7d51ebb |
23-Jan-2012 |
Evgeniy Stepanov <eugeni.stepanov@gmail.com> |
An option to selectively enable parts of ARM EHABI support.
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCAsmInfo.cpp
|
| 4b4e62219be91839091f9e35d8accf877f925d81 |
22-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMSchedule.td
RMSubtarget.cpp
RMSubtarget.h
|
| 12a8863828879168ffd634df09f3aa91b0b256ee |
21-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148601 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMELFWriterInfo.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| 1e9ccd68d40c3d79b2f25f471553914d73bdee58 |
20-Jan-2012 |
Bob Wilson <bob.wilson@apple.com> |
ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext. Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6d56730ab8a08a3530a029e9b681590d88b00bc0 |
20-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
VST2 four-register w/ update pseudos for fixed/register update.
rdar://10724489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 51222d1551383dd7b95ba356b1a5ed89df69e789 |
20-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| e545ee20f1b6ea6c03919cc9bc1a4a059c2f03b6 |
19-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Silence warnings about mixing enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148495 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 73dd8bbce3ff54c318233027fb5e29f8298e01d6 |
19-Jan-2012 |
Evgeniy Stepanov <eugeni.stepanov@gmail.com> |
Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ae69f703d59410fc96f04be3c1afeaa1c17a45ce |
19-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly diagnostic caret in better position for FPImm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148459 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9363c58dc2473a6470d3e7037afe8a215bee7e3e |
19-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 relaxation for tADR to t2ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148456 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| d26bad079d6977309699e0bc9203451904acbd86 |
19-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Add comment and fix range check in condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148455 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| bca15f9c8059ccb9244853f86593c35ac35c8801 |
19-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Slight change to finalizeBundle() interface. LastMI is not exclusive (pointing
to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
will find the last instruction in the bundle by following the 'InsideBundle'
marker. This is useful in case bundles are formed early (i.e. during MI
scheduling) but finalized later (i.e. after register allocator has finished
rewriting virtual registers with physical registers).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148444 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 9b159710ebe8a37cba38ca0c5b465e362bd68af7 |
19-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Rename Finalizebundle to finalizeBundle to conform to coding guideline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148440 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 71f0fc1ca88965b69b4b2c8794a7144bc93d4bba |
19-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Ignore register mask operands when lowering instructions to MC.
This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| 0b4c6738868e11ba06047a406f79489cb1db8c5a |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 5aa5368ccd6b4711d67e00a190e1da1f41b713a0 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Replace FIXME with explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148427 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 256ba4f42a16da2b3ffc757aa7bf191890765580 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 relaxation for LDR(literal).
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| a2ee0fa3ee4ae46c3dc655a5a57e9db539912e14 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Rename pattern for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148422 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| ec3433852dd11e8ff60c9610b4c84468e5935f2b |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. MCAsmBackend naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 5a7efa7f134dd6f8f927c162d9f4062eaa3eb4ac |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 load/store fixups don't set the thumb bit.
Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.
rdar://10348687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148366 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 9b5b125c34b47e0e7eef2548acee8bf1448c4b71 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Move some ARM specific MCAssmebler bits into the ARMAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148364 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 31867660cb81ea2b1d1a6ffa7d09c91acb754a8b |
18-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 3ee7d15284f188672e9e429e9e5cf7b870698677 |
18-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement ARMBaseRegisterInfo::getCallPreservedMask().
Move ARM callee-saved lists into ARMCallingConv.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148357 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCallingConv.td
|
| 2dd674fdce68f8fd59d78a3bbab2cf5b8d220290 |
17-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
smParser/ARMAsmParser.cpp
|
| 810d6d3354a31f24125abef831e4afccbbbe973d |
16-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Refactor variables unused under non-assert builds (& remove two entirely unused variables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148230 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ed4c8c633c52a40ad1a3e8687f290be4aeb1f0e8 |
15-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bfe8afaaec03795fe6c78daa9817e54c186a699d |
14-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
After r147827 and r147902, it's now possible for unallocatable registers to be
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
cbnz r6, LBB89_12
...
LBB89_12:
ble LBB89_1
The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.
rdar://10676853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148168 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ece8b73eb28426b7cec82b1a91e83155a8343ad0 |
13-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use RegisterTuples to generate pseudo-registers.
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.
This makes the call clobber lists longer, but I intend to get rid of
those soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148151 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMRegisterInfo.td
|
| fae699a580380b910740e1cb17ab950ba91ce4a1 |
11-Jan-2012 |
Eric Christopher <echristo@apple.com> |
Fix assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147966 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 08c66642d70879cc479b502c048df4f5fdeaefae |
11-Jan-2012 |
Andrew Trick <atrick@apple.com> |
ARM Ld/St Optimizer fix.
Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits.
Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147922 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 19d0bf3a9273d337b776ca33c284fd2b5da485ab |
10-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Consider unknown alignment caused by OptimizeThumb2Instructions().
This function runs after all constant islands have been placed, and may
shrink some instructions to their 2-byte forms. This can actually cause
some constant pool entries to move out of range because of growing
alignment padding.
Treat instructions that may be shrunk the same as inline asm - they
erode the known alignment bits.
Also reinstate an old assertion in verify(). It is correct now that
basic block offsets include alignments.
Add a single large test case that will hopefully exercise many parts of
the constant island pass.
<rdar://problem/10670199>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147885 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f1f16c832f92829f47573620c20d8420c47bde6c |
10-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM updating VST2 pseudo-lowering fixed vs. register update.
rdar://10663487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147876 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| ea7ad3b3e60f91a5256053b26988806f1dbfdd27 |
10-Jan-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Move default case for covered enum outside of switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147870 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMBaseInfo.h
|
| 95789d0ff90c24297947c778b256de0e8dc26cd6 |
10-Jan-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix a -Wreturn-type warning in g++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147867 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMBaseInfo.h
|
| 2bd335470f8939782f3df7f6180282d3825d4f09 |
10-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unnecessary default cases in switches that cover all enum values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
CTargetDesc/ARMBaseInfo.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| dae412bd320f1522bd1d850be0276212fca0331f |
10-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Accurately model hardware alignment rounding.
On Thumb, the displacement computation hardware uses the address of the
current instruction rouned down to a multiple of 4. Include this
rounding in the UserOffset we compute for each instruction.
When inline asm is present, the instruction alignment may not be known.
Constrain the maximum displacement instead in that case.
This makes it possible for CreateNewWater() and OffsetIsInRange() to
agree about the valid displacements. When they disagree, infinite
looping happens.
As always, test cases for this stuff are insane.
<rdar://problem/10660175>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147825 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 169db15717e77f2893d1868ef934ce42c2e9e956 |
09-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Catch runaway ARMConstantIslandPass even in -Asserts builds.
The pass is prone to looping, and it is better to crash than loop
forever, even in a -Asserts build.
<rdar://problem/10660175>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147806 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 79aa048d2102a7d4c8abbba82b4b8a41dbc32214 |
08-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to transfer implicit uses of return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147752 91177308-0d34-0410-b5e6-96231b3b80d8
humb1FrameLowering.cpp
|
| 8f37a2422ea948b71d0992ab3f82dab07a54ce52 |
07-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Match SelectionDAG logic for enabling movt.
Darwin doesn't do static, and ELF targets only support static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147740 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| f321e1075eabae96f62b1f2570d9dee5d10b8200 |
07-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4964ba01f96d5b3a8fb27a7847c01666ee9b4ebd |
07-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use getRegForValue() to materialize the address of ARM globals.
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147720 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ccec74738d0fc34f4bc2ac6909324e62705f1c38 |
07-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug is
exposed with an upcoming change will would delete the copy to return register
because there is no use! It's amazing anything works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147715 91177308-0d34-0410-b5e6-96231b3b80d8
humb1FrameLowering.cpp
|
| 45ca7c6336f174fae3a9521d5161a498ca27fd13 |
07-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use movw+movt in ARMFastISel::ARMMaterializeGV.
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147712 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bad1e6b8e0dd51a15f6f2cae4f9d7815120f2471 |
06-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable aligned NEON spilling by default.
Experiments show this to be a small speedup for modern ARM cores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147689 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 59ecaae7b61ef0023ed1db4643937f7a57f61d10 |
06-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Abort AdjustBBOffsetsAfter early when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147685 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 7255a4e1332ccb69918ebe041dff05f9e4e5815d |
05-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Reapply r146997, "Heed spill slot alignment on ARM."
Now that canRealignStack() understands frozen reserved registers, it is
safe to use it for aligned spill instructions.
It will only return true if the registers reserved at the beginning of
register allocation allow for dynamic stack realignment.
<rdar://problem/10625436>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
|
| 54f3b7a9109d1916cf25ffdb2ed5045f03121b5a |
05-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid reserving an ARM base pointer during register allocation.
Once register allocation has started the reserved registers are frozen.
Fix the ARM canRealignStack() hook to respect the frozen register state.
Now the hook returns false if register allocation was started with frame
pointer elimination enabled.
It also returns false if register allocation started without a reserved
base pointer, and stack realignment would require a base pointer. This
bug was breaking oggenc on armv6.
No test case, an upcoming patch will use this functionality to realign
the stack for spill slots when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147578 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| afad0fe59a791cb4fd87fbd7ea2b1aba8d67a7af |
04-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix more places which should be checking for iOS, not darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 6d5b7cc235e284130350045a320426afceb82874 |
03-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r146997, "Heed spill slot alignment on ARM."
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.
<rdar://problem/10625436>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
|
| 19055cc2712223f6834fc3cf5b547803ba83f066 |
03-Jan-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Fix malformed assert.
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 43ea32ca042214c28b7abba9c10f470ac5ade405 |
24-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix Comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| f06f6f50e9844b88cfbb9fb896fff9c3a752966b |
23-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Experimental support for aligned NEON spills.
ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.
Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.
This feature is off by default, controlled by an -align-neon-spills
command line option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMFrameLowering.h
RMMachineFunctionInfo.h
|
| f4aea8f34946d4d2b101b8e3c6db95c18be80173 |
23-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| 4050bc4cab61f8d3c7583a9b60f17c7da47bbf69 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| d2355e72c56f0fe8fe032afc171c5622ad029c6a |
22-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
Noticed by inspection; I don't have a testcase for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 21bcca81f4597f1c7d939e5d69067539ff804e6d |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Use predicate function a bit more liberally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b975c27adc2371a9666fa9b8cecd9487966ec5b1 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix incorrect relocation generation. Patch by Kristof Beyls.
Fixes PR11214.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| c7448f8d47de96333d6854113fb9f0e7affb31cd |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 8c748113eb5df50ce1e44e5cb92be941aa94f4bd |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some bogus comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 1aa149f5acea364aa8bc9cfc3a167f78eff2e96b |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-UAL aliases. fcmp[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 8d9550bde95c8d128e7bf62e9e65dec1854e2d1d |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| de626ad8726677328e10dbdc15011254214437d7 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 18c8d12dea944086ef0ce2f674ca8a34de2bbd74 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f1a88fc474b87d66906689f5bf76d67cb5b1a4c7 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke invalid comment from copy/paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6db2d926033a5b35ca01293167353a15637ac7f2 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make the virtual methods in ARMELFObjectWriter public.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| 81fafde8a6465fbf2809dd77e4672477359f78a6 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Hopefully fix the cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
|
| 7609785d2b9b79b9aafc3b3afabcb691cfc8afa5 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix name in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMELFObjectWriter.cpp
|
| 74cab51aa5cdc955b1de0c93d3785479c3ed2d18 |
22-Dec-2011 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Unbreak cmake build after r147115.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
|
| 69bbda03918a18bd4477bb254d51346ee3033567 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the ARM specific parts of the ELF writer to Target/ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMELFObjectWriter.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| f7c66fa0de7c18a030480d2581051510c574da4b |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON mnemonic aliase for vrecpeq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| af33a0cfe092afd327e1b8b05c655d9eab689eed |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP optional data type on VMOV GPR<-->SPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 5f669fa8ba41e1794af1624c25186b941cf1dfb4 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON optional data type on VSWP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4553fa3128cb582426fb02c2f2779d659f1073a0 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON mnemonic aliases for vzipq and vswpq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| de4d83943a5206690fbe1e39dd33770f5ab29595 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM asm parser should be more lenient w/ .thumb_func directive.
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 520dc78d92a47af5e644b09f401d278cb1d5d196 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2cc5cda464e7c936215281934193658cb799c603 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07 |
21-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move common code into an MRI function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| e6949b13997e6d31aa4719a0e80c4b6b405e42a9 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 8d0447c506eceddcebb1d4eb3bb869a83de19d84 |
21-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dc9a8a378daf432d8dcfc178507afe149706f9a6 |
21-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce the exposure of Triple::OSType in the ELF object writer. This will
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 1e33e8b715299dd014931be388cf593d6a55dc69 |
21-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c931325d99a93c273844c38d3c762705c454ae93 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing allows constant expressions for lane indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| aee718beac4fada5914d773db38002d95cae5e0d |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .req register name aliases are case insensitive, just like regnames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3cbe43fe69680df772d83947ced97ca445861213 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Move comment to appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 52346e964ff1108729c2b8990b859c10f09a1822 |
20-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Heed spill slot alignment on ARM.
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
|
| 5b484312c66f8d125c072517947538f301c5a805 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VST2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 95fad1c6034cdf8010428e61b71cd196ee1698ad |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| afff941211526a31f931aa9fcac84ae42ff60ef0 |
20-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFastISel.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| d7c9e08b6bcf15655919960e214b9b91677cdde9 |
20-Dec-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
First steps in ARM AsmParser support for .eabi_attribute and .arch
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cfb75fba735edd44841eb21c72c3a9736a7d9af2 |
20-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Fix up the CMake build for the new files added in r146960, they're
likely to stay either way that discussion ends up resolving itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 2d24e2a396a1d211baaeedf32148a3b657240170 |
20-Dec-2011 |
David Blaikie <dblaikie@gmail.com> |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
CTargetDesc/ARMMCAsmInfo.cpp
CTargetDesc/ARMMCAsmInfo.h
|
| c0b0e57a87aa5e52e0a45af75fc1cee78d8f2bc6 |
20-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 04b5d93250bef585631a583a85f6733b1bdc8c52 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9b0878512fb57ee4b0bc483509e4d9f4f0b9e426 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 2f196747f15240691bd4e622f7995edfedf90f61 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMFixupKinds.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| d22170e16a42aed0212e1e52f189bfb8b7c7105d |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VPADD.
rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6849019079794c573b72c1ec55613cb6ba1297a5 |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 9c39789c361d4fe2632f28fca74c9ea5fff3dafc |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 61b74b42478474534827070cdd703811ddc9ce19 |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON implied destination aliases for VMAX/VMIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| eeaf1c1636c664c707fd9ecc96916fd20ddf137a |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 3346dcef02a5b43bbd03d0b84803b60b4b77bf63 |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9897c622e049e0008747381505b406d8ecc40bec |
19-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove a register class that can just as well be synthesized.
Add the new TableGen register class synthesizer feature to the release
notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 570f9a972e02830d1ca223743dd6b4cc4fdf9549 |
19-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| b16db8171970f7390895f1e36d5887e6baa9abc3 |
17-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 2027379985f1cbb965be808adad5b819a66dd97f |
17-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve more memory operands in ARMExpandPseudo.
I don't think this affects anything but verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| b076fb7762498289718dbe4cb5de03e6e93bd4e7 |
17-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix off-by-one error in bucket sort.
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f9aabb8f32d61d19f57fb4710c06d01a12fedce7 |
16-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't adjust for alignment padding in OffsetIsInRange.
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f5bb45f89564129fcaca25b9dd84750ffc02beed |
16-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Note ARM constant island alignment in the release notes.
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a1e6e241a813f81be2d2f36ab60c950ca297574b |
16-Dec-2011 |
Logan Chien <loganchien@google.com> |
Merge with LLVM upstream r146714 (Dec 16th 2011)
Change-Id: Ied458adb08bf9a69250cbcee9b14b44d17e8701a
|
| ddecfe54a35ffbe0675f7f33e493734fd60b2495 |
16-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON aliases for vmovq.f*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b6744db06f088e1c8a8563c0cb6c202de9ef8aaa |
16-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADR assembly parsing w/o the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2f21e8c5ba62ec98e7dec9c65e35a3b4e7fdaf4d |
15-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a738da7bd30819f1bc710d313c9ecb06c56f1a4f |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 60d99a5278e4a0e7116a05c01cececb07ca1362a |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| b6ff6ec85e589b8ad3bede4533dc71a09655bb1e |
15-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable proper constant island alignment by default.
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146690 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 276ed0344c05822617934fa4a6a9920d864193a5 |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0aaf4cd9b34454eb381e1694f520504779c6b7f8 |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-register double spaced register list parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 299b059cd675f1e5beac1a2383a44e062e2eef43 |
15-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Consider CPE alignment in CreateNewWater().
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146609 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 799ca9d1b7cfa8910ac27f8de4929bfbd278114d |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 9b1b3902882675e5ce35eacd639456bd648324b7 |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| ec04a3f8db9ab9db3bbec3ce32baaa2ea2cb853f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON fix alignment encoding for VST2 w/ writeback.
Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2dbab5c33db5eb08f909f5b9a036d75c9ac88a25 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke old code. Missed in last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146590 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| bb3a2e4d0defc6854d37384d80858037dbbc5f20 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON refactor VST2 w/ writeback instructions.
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 20accfc6c7b22b22193eb90c53921f71c1202a73 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON improve factoring a bit. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146585 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 020f4106f820648fd7e91956859844a80de13974 |
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| e90ac9bce9aa6de288568df9bf6133c08534ae2f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 5e46dcbb4b6f6e82f7bb88490800ed09ac02f105 |
14-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix speling and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146575 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 5dca1c9f633e3657189afaf9a672a7715c7be22d |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy/pasto that skipped the 'modify' step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4677708d4f3a9f2fd76d589a604936b294da309f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 mov vs. mvn alias goes both ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 6762f8f302f5c01a26e848cdcac20bddde0dd22c |
14-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
VFP2 is required for FP loads. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 64ac91b4b6e62f82d608fe9602b28c00171f88a0 |
14-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8d11c6349f9bf276534907245946518042c1bb60 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 404ed3c2239ff394270053bdcb76a5a4908af7ce |
14-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix 80-column violation and extraneous brackets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a39cda7aff2d379ad9c15500319ab037baa48747 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for the target-specific .req directive.
rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ddfd1377d2e4154d44dc3ad217735adc15af2e3f |
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMFastISel.cpp
RMHazardRecognizer.cpp
RMHazardRecognizer.h
RMTargetMachine.cpp
LxExpansionPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 863d2af9477e331955a9bee8be1969ce658b59b5 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler aliases for "mov(shifted register)"
rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 27debd60a152d39e421c57bce511f16d8439a670 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM/STM system instruction variants.
rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| b0659873e6d983eae1e29ecddedcfabb9cdc1eea |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 pre/post indexed stores can be from any non-PC GPR.
rdar://10549786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d7ea73a4909fc3200a1cecd2b420d7ace2180b70 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 tweak for ccout handling in RSB parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146516 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 55b02f28c1a2960ebb88cf5019cc5b36bb2eabf4 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb2 parsing of "rsb rd, rn, #0".
rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0f293de207fa0e9461a9dbee95bed9a6a2c52f76 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VQDMULH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| e91e7bcadc445381adef5c5154e8e2cba074505f |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| f10154010ec01a6965f86e8c136db79732c92eee |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146508 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 485d8bf7e5537a19d3ad63e65f841bd7e63d4d06 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM add more 'gas' compatibility aliases for NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 8a9bce978fa4ca60d3a0ba42a1d44c41463a3c33 |
13-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2e29024d2e3aa23a1ec049c30dbce903e57d5f9b |
13-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Account for CPE alignment when searching for new water.
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146458 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b0c594fd422417e1e290da166b566c7bee74644b |
12-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Introduce a common section which currently has a list of the
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146436 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| 9cd2b9562d23909937ab2e4bb45c2a1ed4c86816 |
12-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146417 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4ab406d7fc06b1272d02cd8be46f0c5ebe51a3da |
12-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Remove trailing newline, which irked me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/LLVMBuild.txt
isassembler/LLVMBuild.txt
nstPrinter/LLVMBuild.txt
LVMBuild.txt
CTargetDesc/LLVMBuild.txt
argetInfo/LLVMBuild.txt
|
| 8552821e578d693ec14007b21e9468010485ae76 |
12-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a postOffset() alignment argument.
This computes the offset of the layout sucessor block, considering its
alignment as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146401 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| bd1ec17caf8fc393b112e6c01fe0e9cd7db213ae |
12-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146400 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| cca33a3f24106cfdb6cb892b76efc76f1ad91806 |
12-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also set the proper alignment on inner islands and the function itself.
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.
This is all gated by -arm-align-constant-islands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146391 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| dbf350a5a8f5fb5321a4e11e381f0023fbe61d15 |
12-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make MF a class member instead of passing it around everywhere.
Also add an MCP member pointing to the machine constant pool.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146382 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b813f924a749396ffb4a4bd087ee1dbb678551f3 |
12-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a -arm-align-constant-islands flag, default off.
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment. When the command line
flag is set, also align the basic block containing the constant pool
entries.
This is only a partial implementation of constant island alignment. More
to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146375 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 3e0dc0606aed30b1fa6e1abcecf2cbf5e9ac1af9 |
11-Dec-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d440f678fb0fd6a8735bc315bd6f63fe8a71e8bd |
10-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert r146322 to appease buildbots. Original commit message:
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8c0b807e8fc9a14f61cc81589e4e81ea78ac57b4 |
10-Dec-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 77caaf0fc000a1e2e2afe949b6205ea5db668be9 |
10-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Try to align the point where a large basic block is split.
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146314 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 2d5023bbcf816de39e37d9fea6dfa8f7aadb393f |
10-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
More debug output formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146313 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 48171e7fbe58bb418f09717813779d03903d35e4 |
10-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| effab8fa2413e96b6a2ce2bbeefe35fe478ee028 |
10-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Splats can contain undef's; make sure to handle them correctly. PR11526.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 21d7fb814adcedc7b2f156e003d2083ad1d8ac6a |
10-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 8a12e3b5df13b279eff3cfc29e0d7808ff86aa44 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM allows '' syntax, not just '#imm' for assembly.
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146285 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 840bf7eda7c81059a0aae9abd51262147c60d814 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 4332983e7757018f388ba24f58765571e0d134ed |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON data type aliases for VBIC(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146281 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a4e3c7fc4ba2d55695b0484480685698132eba20 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 493ad6b95d153763b4b4fec456918f6c0d72d1ea |
09-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
User a helper overload for a common pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146270 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 2af50d981d605c007ef45f6a6117e17134bed9df |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Better base class factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1f94ec7b5990b424b4209e38a2daf87455bf105b |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Better base class factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146266 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3c4615eef2cb6b1bacb9b5fffe98359f9659f7c2 |
09-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Tweak debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146264 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 976c0da213bb9a4f07d4ca2a82765b5e590be05d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM convenience aliases for VSQRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 8759c3f548e03f7caff45f35fde49ed3e8c1cf71 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6b044c26094a9f86da7d12945b00a47a5f07cf6d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSHR implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| a62d11ea942ab99ba74589f74d390138654b6197 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM asm parser, just issue a warning for a duplicate reg in a list.
For better 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146185 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 120313435d217d869bd2141b0cd8f4d99ae4b9a4 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSUB implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9e7b42a40eb8fbeac92ad2272d983d559a554c37 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VQADD implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1c2c8a9389526518164ab6386ffcd6a1fa01124d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM a few more VMUL implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 40e285554773c51f6dd6eb8d076256e557fab9c3 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for register name aliases.
rdar://10550084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3b0887e291eec345c4848888c4604aff4f5f1e19 |
08-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 72590c973837f7d56638feb511a79574391f0eac |
08-Dec-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 730fe6c1b686fe71c8e549b0f955e65a6a49d3ff |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VSHL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| e6f9e9d8365346330c782c82860a6b77df8ee829 |
08-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Drop the HasInlineAsm flag.
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146124 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ff4cbb4c9a66d313a9f52830620f06c88b43397c |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VSHL(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 99486be8bad67f70445df99fd0c07d17eb8b1c05 |
08-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify offset verification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146121 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 517a013a4fb6ead3b395e05dfdc04a622931eb36 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy/past-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2b8810c500973ce96e476cff49c023cff24a86fc |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 540c6d9d2651310d88eb9a147177ccd52eec7cd5 |
08-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't include alignment padding in BBInfo.Size.
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 8254f02231faeb15b0abaad96a99ac9e40feb908 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 67ca1adf822c6cbc2f2bb78b8f94eefd099a8eb6 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP support 'flds/fldd' aliases for 'vldr'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| a44f2c4a28cd9c43a3d34cbad4f47df77ec686cf |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional destination operand variants for VEXT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3bc8a3d3afe3ddda884a681002e24850099b719e |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| af4edea67b007592f9474e07d27182956e37f7f5 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9fa0a743e6afef4ea5fe7b5115607947696774a8 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VAND/VEOR/VORR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 30a264eb7fa6c961e94a7eb3d3eaf72d9bc8a44c |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VADDW instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d900441e134564aa396522ab6e4617a98db91e34 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VADD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4f66a050a2f74fc065bbe5c5a564feb40ea03bae |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke inadvertant debugging commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 577b09155f9a6fa38e5a7918da9701e120b3642f |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Darwin assembler improved relocs when w/o subsections_via_symbols.
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 8524bca75076a5e94ba3263968fa4b9e4fc6234f |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alias for long-form pop and friends.
rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9a70df99ca674b288d50dbf454779ed75d6e48dd |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM support the .arm and .thumb directives for assembly mode switching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 470855b24ff4e82360ce1f84a1088332f3b4c8ea |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMHazardRecognizer.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
LxExpansionPass.cpp
humb1RegisterInfo.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 2fe71c5ef4b1816993bafeec501e742a7fa69b46 |
07-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Eliminate delta argument from AdjustBBOffsetsAfter.
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a26811ec83d00344a739d84f4b8584e5548b94ce |
07-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute some alignment information for each basic block.
These fields are not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1ceef1a49122cec6d79c0714719d99db27ab1764 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 5bb32530bc1adb970eee2ac18508ea2876a2f410 |
07-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move common expression into a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9f3d220c632a9c18b424248592d2bc7b023956d2 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Implement ARM ARM Table A7-3 via TokenAlias.
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a3f331bd81f9d468654635df4428ecc8d8ebb5ea |
07-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 3b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: NEON SHLL instruction immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 4e4139588c78389099e67b555f8f6a57a321e850 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: Parameterize the immediate operand type for NEON VSHLL.
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6fbea43b0b35e2a3f6f91a92edeffa873c5cd794 |
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r145971: "Use conservative size estimate for tBR_JTr."
This caused more offset errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
|
| 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b |
06-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
|
| d25c27807ef6b3d80ffa218b1fa5441fe40d3ce6 |
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use conservative size estimate for tBR_JTr.
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
|
| 305e5fe797cbba32d8091d687d47e98c8f3ee1f4 |
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove alignment from deserted constant islands.
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 23261af193e462b73257445053f9f6515e60e8c9 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cf9814ddd277dfcbb4ec5727e2cb510b8a451e04 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2: MUL two-operand form encoding operand order fix.
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 encoding choice correction for PLD.
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cb86509e7a0f831e28c89f84c22a409115d01c38 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up value checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| ed42c5f778dd0128429e4feffe2c028b2352b534 |
06-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] Doublewords only require word-alignment.
rdar://10528060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3e572ac2fbdf6aa538500be07b9b050ac008669e |
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Align ARM constant pool islands via their basic block.
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantIslandPass.cpp
|
| d9a6e8978dd65c85d68bf1141d992da576878cd8 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM handling of tBcc branch relaxation.
rdar://10069056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| e80fba0e6c976039c132c3d5d4fcad569d2259a8 |
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use an existing function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 370b78d795154899a22ca2b4674e890661ff1d59 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Move target-specific logic out of generic MCAssembler.
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| f503ef6800fcbda99d6ae581ee8cfe3204becb3c |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Simple branch relaxation for Thumb2 Bcc instructions.
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 713c70238c6d150d2cd458b07ab35932fafe508e |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ADDrr fix. Bad check for explicit .w
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 927b9df4c678371d3fb1308be90e76ed44af72f8 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 prefer ADD register encoding T2 to T3 when possible.
rdar://10529664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| da84786bee8304588a4325b15e297be1995a5d41 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 253ef7a77930f6855a5bf24037e9dfbc65a1ee85 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for the rest of the VMUL data type aliases.
Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 422faab909db99cc4936298e47fbf8d355fb9cd1 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix previous commit. Oops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 45755a77ec08d460fefc08e99bd0225a9da9769c |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| afb500ace12698a99daa5d7c10bfedcbfef48022 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assmebler parsing for two-operand VMUL instructions.
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 6ce2deacefa5fd2565983d513d07a06d6a8af602 |
04-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix 80-column issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0cb2a45cceaefb48ec7efb902c453aaae4e24cb2 |
04-Dec-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit the ctors in the proper order on ARM/EABI.
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
|
| 9eff1e33f616ad2d0134740ac4595ed2e79e3d74 |
03-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] Unaligned stores of floats require special care.
rdar://10510150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 587f5062b9e4532c4f464942e593cb87c58ac153 |
03-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VEXT aliases for data type suffices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| e40ab244c19ff73d086188526dbb81537f3af6c1 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VEXT tighten up operand classes a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 84defb51ca183d136e08e87d95e2c907654405f9 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VST1 single lane assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseRegisterInfo.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 872eedbb3a46618e333db42ee9c41fda34eb1e9b |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1 single lane assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 204aa64f30911f28c11e05ba2acf475d25c45fa0 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoder method needs the physical register number, not the enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| b74c865841481074539bdf4de35024939854f2e6 |
02-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
[arm-fast-isel] After promoting a function parameter be sure to update the
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dad2f8e7fb2df5fb080a38fa4c33a01f19729f15 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 7636bf6530fd83bf7356ae3894246a4e558741a4 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM start parsing VLD1 single lane instructions.
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 7b8e12152011ee21b1781113805a68cd3dc3d46b |
30-Nov-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 096334e25ea68ac970942ecb680a82fbb8ad206c |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 all lanes, with writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 13af222bab6fdc77d8193eb38e78a9cbed1d9d1f |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 two register all lanes, no writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 98b05a57b67d1968381563c8cccbbb6c6cb65e3d |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing aliases for VLD1 single register all lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 6029b6ddafad45791c9e9d8e8ddd96978294beef |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| bd1cff5b2c367459329b291b929c9b645470b320 |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145456 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1ec7bf0c0d82f091b66aa52e63c99a538fe4653b |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing aliases for data-size suffices on VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145454 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4c7edb3ad8bd513c59190f6ebee9bee34af7d247 |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for four-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| d5ca201891d238ca2185831524a1e3f2670224df |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for three-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 7d8867d45361b737dcd48db961488a35d9ac0e52 |
29-Nov-2011 |
Andrew Trick <atrick@apple.com> |
comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145422 91177308-0d34-0410-b5e6-96231b3b80d8
RMHazardRecognizer.h
|
| d782bae970e888572f0458ac05369bbd7752f05a |
29-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build/CMake: Finish removal of add_llvm_library_dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
MakeLists.txt
isassembler/CMakeLists.txt
nstPrinter/CMakeLists.txt
CTargetDesc/CMakeLists.txt
argetInfo/CMakeLists.txt
|
| 6200611dffd301c49cb19d52eaedff79623adb98 |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Better fix for ARM MOVT relocation encoding of thumb bit.
Replaces r145318 with a more targetted fix for the relocation handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145346 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMachObjectWriter.cpp
|
| 4c0c5451c78423bcc08e23f230e912e35d11dc4d |
28-Nov-2011 |
Duncan Sands <baldrick@free.fr> |
Silence wrong warnings from GCC about variables possibly being used
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145239 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0861f5793a1834f02b522fb86fb037cd592c134f |
27-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move code into anonymous namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145154 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 70aaf37c11bbfffc8d3e007556da46c810e822a3 |
25-Nov-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145129 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 1429059dc0129c1cec938c29d6fce89e14293241 |
25-Nov-2011 |
Logan Chien <loganchien@google.com> |
Merge with LLVM upstream r145126 (Nov 25th 2011)
Change-Id: I30d08ae004a4c3c74092ad2537ab30cce4280e1d
|
| 424fe0e422826f4962b58428b6aef48e1a66c30a |
18-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 944d82ba06bcb6bf92ca1fbcbdf1a882cd009363 |
17-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add TODO comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2fb82ce75d193d5287d32bb3225b8008d8a133fa |
17-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3bdb3c9b511b89d38696587d61b82949e06a7729 |
17-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Don't unconditionally set the kill flag.
rdar://10456186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2abba8496cb394af53b531e95067d5cae78bb9ee |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| b84acd24687c721e3da46bb56a94d393bc5a8cbc |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding of NOP used for padding in ARM mode .align.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 40a86ee20f903cf797d3c957e87cfd61e10a024f |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for shifted register operands for MOV instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up debug printing of ARM shifted operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b598b044091d9bc0651a3c93195c9fb9f8b453a9 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 48b368bcd5fd6d1857de137230ac019b8530f1cd |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for RRX mnemonic.
rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 508a1f4db16baea5c0d5b1c4797d005dff1ee30f |
16-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Check to make sure we can select the instruction before trying to put the
operands into a register. Otherwise, we may materialize dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 23f220705a74685edd743e84861a3e0d6d109828 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode aliases for bitwise instructions w/ register operands.
rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| d0405aaabcb0d6cf34bb8cd0716b959cd9eb8741 |
16-Nov-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5c283e98c9da41c744c63a3ea13231d2f919fe9a |
16-Nov-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144794 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 |
16-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| eaab6ef6eb12fc950f1d4371b297d9b7ca9d4c66 |
16-Nov-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| f56c60b5713c57a3f9223d4ed3d9c88088132fad |
16-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add FIXME comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3805d85e38c29d9106c758b63851eb847201f315 |
16-Nov-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable -widen-vmovs by default.
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144734 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e43862b6a6130ec29ee4e9e6c6c30b5607c9a728 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5b2fb2083c387009607f438a2a986c3e0a2cd0be |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for data type suffices on NEON VMOV aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 9f302c4fb3feeb36561a6eee0168ee5242d8ac20 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing two operand forms for shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 88d012a9c37e7610fbc73a73e541f0bbc35f9cc1 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 6cb4b081829880ba97a729bcf33fd59517ca5450 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM accept an immediate offset in memory operands w/o the '#'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5c984e451d604e3ff3cfdc5db7c0b6ca6be7a14f |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| eaf2056709c8a5c6a1b9d27f1963a68aefaba8fa |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM size suffix on VFP single-precision 'vmov' is optional.
rdar://10435114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 25e0a87e9190cdca62aee5ac95cfc8ef44f35e92 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 19885de61ddbfe1a0db858e303baf19a190bc57a |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM alternate size suffices for VTRN instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 22925d93e9c5d6159f24853457c858be5f08af04 |
15-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix a misplaced paren bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| a68e90c36e6a53fb1889b608f44d6244a36b3e97 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| bfb0a1717bb140c418e070042e852f925e92de01 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| d2586daf069f480e924cd7dd2079dd39de331541 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7f1ec9570d673aedd13c5621407085400bab8299 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 two-operand 'mul' instruction wide encoding parsing.
rdar://10449724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| b589be9334ee5352dd263c406b99a90d413c0b2f |
15-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 1de0bd194540f8bab399fb39c4ba615a7b2381d3 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing for mul.w in IT block fix.
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c5a6a687fd2fda61295acf38886016b4d54db1a5 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 36abbec01815964352d4f3d391c0a03896c0095a |
15-Nov-2011 |
Logan Chien <loganchien@google.com> |
Apply changes to migrate to llvm upstream r144606.
Change-Id: Id22edd55de42831bdc3fc1a143ebec10cf8476d2
RMJITInfo.cpp
|
| bf8356b37c2138376b7d42bf0c2b0189ae5032a0 |
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 978e0dfe46e481bfb1281e683aa308329e879e95 |
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| d9190c0f148b218ab046deadd0c7ae475414cde5 |
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| f9c1b92c27bf4ac40a52e0f1ef6d006d7e74bed3 |
15-Nov-2011 |
Logan Chien <loganchien@google.com> |
Merge with LLVM upstream r144606 (Nov 15th 2011)
Conflicts:
Makefile.rules
configure
docs/ReleaseNotes.html
lib/Analysis/ScalarEvolution.cpp
lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
lib/CodeGen/ExecutionDepsFix.cpp
lib/CodeGen/MachineBlockPlacement.cpp
lib/CodeGen/MachineBranchProbabilityInfo.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/ExecutionEngine/JIT/LLVMBuild.txt
lib/MC/LLVMBuild.txt
lib/MC/MCDisassembler/LLVMBuild.txt
lib/MC/MCDwarf.cpp
lib/Object/LLVMBuild.txt
lib/Target/ARM/ARMExpandPseudoInsts.cpp
lib/Target/ARM/ARMFastISel.cpp
lib/Target/ARM/ARMInstrInfo.td
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
lib/Target/ARM/Disassembler/LLVMBuild.txt
lib/Target/ARM/TargetInfo/LLVMBuild.txt
lib/Target/CBackend/TargetInfo/LLVMBuild.txt
lib/Target/CellSPU/MCTargetDesc/LLVMBuild.txt
lib/Target/CellSPU/TargetInfo/LLVMBuild.txt
lib/Target/CppBackend/TargetInfo/LLVMBuild.txt
lib/Target/LLVMBuild.txt
lib/Target/MBlaze/Disassembler/LLVMBuild.txt
lib/Target/MBlaze/TargetInfo/LLVMBuild.txt
lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt
lib/Target/MSP430/TargetInfo/LLVMBuild.txt
lib/Target/Mips/CMakeLists.txt
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
lib/Target/Mips/Mips64InstrInfo.td
lib/Target/Mips/MipsAsmPrinter.cpp
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/Mips/MipsMCInstLower.cpp
lib/Target/Mips/TargetInfo/LLVMBuild.txt
lib/Target/PTX/LLVMBuild.txt
lib/Target/PTX/PTXAsmPrinter.cpp
lib/Target/PTX/TargetInfo/LLVMBuild.txt
lib/Target/PowerPC/TargetInfo/LLVMBuild.txt
lib/Target/Sparc/TargetInfo/LLVMBuild.txt
lib/Target/X86/TargetInfo/LLVMBuild.txt
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrSSE.td
lib/Target/XCore/MCTargetDesc/LLVMBuild.txt
lib/Target/XCore/TargetInfo/LLVMBuild.txt
lib/Transforms/IPO/LLVMBuild.txt
lib/Transforms/Utils/LLVMBuild.txt
test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
test/CodeGen/ARM/fast-isel-cmp-imm.ll
test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
test/CodeGen/CellSPU/call_indirect.ll
test/CodeGen/X86/avx2-logic.ll
test/CodeGen/X86/block-placement.ll
test/CodeGen/X86/sse-domains.ll
test/CodeGen/X86/sse3.ll
test/CodeGen/X86/vec_shuffle-39.ll
test/MC/ARM/neon-vld-encoding.s
test/MC/ARM/neon-vst-encoding.s
tools/llvm-config-2/llvm-config.cpp
utils/TableGen/LLVMBuild.txt
Change-Id: I70f454db6fc79d7799f56d0f6f2eb7b99561c504
|
| eaa192af18677c4dc5894e049514d8a6b1d6d7c2 |
15-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| bfc9429c2b814469adf3930dda31539d1c3319d8 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| dd47e0b5d4850fede4b2581c41f1e0a5eff5f05a |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e052b9afa1301419f8b52eed9ed370393fcad78d |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 04db7f7a7d5d9312d2e40032883b708e321d55b3 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Add explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0530d0d5d9dfaae2e3c78a52729abcbf9fcdd21b |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Split out the plain '.{8|16|32|64}' suffix handling.
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| ef448767a35148261d6c82a8e55e6e2f4be8e631 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 2c42b8c912b62071c27454182cdef60e3b584083 |
15-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ffc658b056b7cc0b3f6a2626694b6a4216ed728d |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 909cb4f2f2d227ea01852cb318c80a79c46bc9bf |
14-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for inlining small memcpys.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e489af8dce12249be26ac0c8e371557378886bc2 |
14-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix a performance regression from r144565. Positive offsets were being lowered
into registers, rather then encoded directly in the load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 02e3d9268fe456ebe4fe6ae277507bb7933ec3df |
14-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing type suffix options for VLDR/VSTR.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 57b299796685033c87a5414e179b95b5ae7dc8d4 |
14-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for Thumb load/stores with negative offsets.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 430052b084de7ab4eb6162b9f1a6a16bfb2a80ad |
14-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 column.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 39c747269a8cff12acacda0759146005c941e541 |
11-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for using MVN to materialize negative constants.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 45daa4d7f44c228a22888e1865485c5a86cc2261 |
11-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| fa2768fa992fec694f2a9fd2643c2960f5f7a953 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
rdar://10429490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 036bfcbe83604118c97699ff23d888a2bfc47da3 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM let processInstruction() tranforms chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2cb212c883b5a4a4c963919c8989a432390921cb |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a47505117e3b0c7db8f170c80eb5321b42226cb3 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 diagnostics for reglist on PUSH/POP fix.
Was not checking the first register in the register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 57cada0a51266e156a3eee845f7c6cdba2964d57 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d382fcf6d2c3aa7f147864a2dbaf2e8079aecec0 |
10-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
When in ARM mode, LDRH/STRH require special handling of negative offsets.
For correctness, disable this for now.
rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ffe92f37a2944b0406451a13c73b0fc5d2edf8fe |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .thumb_func directive for quoted symbol names.
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 668da49d3bcfa2fc1c8ef88fc2a7fbdfb433aa70 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 00a95c00bf3152e29584f511786efea95084eea0 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 82819266746c3b0a23887d44b57c9a6d6d5e89f3 |
10-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
For immediate encodings of icmp, zero or sign extend first. Then
determine if the value is negative and flip the sign accordingly.
rdar://10422026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e5345b6caee7f2f205e267ae56d532d39784ac5a |
10-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
llvm-build: Add --native-target and --enable-targets options, and add logic to
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| 4e2b002f5ba9ac7d21988c889ab2bfc602ec0e23 |
10-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
llvm-build: Add an explicit component type to represent targets.
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| 86de95024df48b78038fa3aa2e50a06d67d0e7e2 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 30b4e6b557868e16f89a9e09e632ae5d7f9a7654 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1e962ceee442598e146de8528d2bc248615e1da0 |
10-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 909511e7a6f8fa936c57d1e48e1dd4aa24234386 |
09-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6f4c56b00e58f8e06928eab6cee183493643ac04 |
09-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
remove a fair number of unnecessary materialized constants.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 099dcdbdf31d55dfb6b45cc47d1e51fe535113ae |
09-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide cpu name checking in ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMSubtarget.h
|
| 77e6488ed86045afdab8625c329683df71fa1322 |
08-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| a86af3ee1eacde8751d676ab9cf434690c265f81 |
08-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 22d43e3f0991cb2710cdb79eb6c37ae8ba53e4f4 |
08-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 67f02679340e056f50120a84b128b3c6188d693d |
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
|
| 337e63a9c8f57d33390ed90bbad63cb13ed2156d |
08-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7c1a2ac76a1bb72553419ae5911d1ee991fb3dde |
08-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMFastISel.cpp
|
| 00779a92fdd12dcf46d26fe3fddf116b8b5f7882 |
07-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144021 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 66f72397cca6924503cee5d4f03c7163ff384fce |
07-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 7b135ae6d5904bca27ae81ca3c4324f8c8b855fd |
06-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
|
| 011369bb7f212748831a026dae045b975e07124c |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 071de118421b012feecc35e2561ede2dcd65a4c3 |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Allow i1 to be promoted to i32 for ARM APCS calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143755 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 9c8c0966e0123dfaa8f91570bb670eb51c2924aa |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Cannot create a result register for non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143749 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1ed7ead8fa5b32379efd3ea895a03fde974b7586 |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143743 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5668649c23ddd77f6d322aed602aef6c1ccd2455 |
04-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Enable support for materializing i1, i8, and i16 integers via move immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143739 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0e063f5eaa7e122ac7737e4a2edb7bc84b77f244 |
04-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
added a layer of indirection with no value (not even conciseness).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 98520aaeb2b66e11ba668fb73fe7033fd7e6b7cb |
04-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143675 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a4c975b2a89e9a1c9f7057656d79635c0c4f7972 |
04-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143670 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2ec6ba0dbf3ce9cf7c2da96bafca0379a16290ed |
04-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add fast-isel support for returning i1, i8, and i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dd21ce80415edf09fa66a0bfebc812ce682409bf |
03-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 00ade8bab0045bde35b13d2489021b8642aeb0cc |
03-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build: Add initial cut at LLVMBuild.txt files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/LLVMBuild.txt
isassembler/LLVMBuild.txt
nstPrinter/LLVMBuild.txt
LVMBuild.txt
CTargetDesc/LLVMBuild.txt
argetInfo/LLVMBuild.txt
|
| 33ad4ccb5f7df4ae166f3a6d89de75199a2376f9 |
03-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for sign-extending non-legal types in SelectSIToFP().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e88f495b18462733efac557a21966c9f3dac94c7 |
03-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Fixed parameter name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143594 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 537a9f7685a8cd9d58fd7e448d89e513c1a45fb9 |
02-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 07fa757c770aa3b15727178283f71afe81271bdc |
02-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for comparing integer non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3a81c52a33c105d9282ea8bbde2a6b9ce1aa2731 |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| bd513eaa3bed78ba3b4d86f7c0935d0cf82cbbda |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143553 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 87f24f52f4b61f7ad67f71abf131d5852d87524c |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1e512f49e4eae4ee2d5c91197c1b4803a6530596 |
02-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor out an EmitIntExt function. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143547 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fe409dd67c7093684012818b6a64ab93d4b27928 |
02-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor out a SelectTrunc function. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143523 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d70b1786e86f70f83094068a95ea0e1237dfa625 |
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM label operands can be quoted.
For example, labels from Objective-C sources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143511 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1ae3b2de19e69ed7763c5926a3fbeaa18f6c6938 |
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM label operands can have an optional '#' before them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143510 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1a2a45b260d9b18aaa3a24a62cd296751027a4b7 |
01-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of some VST1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 06b29155dd1a7f5f0dfdc507e792dcd9452a3871 |
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD/VST assembly parsing for symbolic address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMAsmBackend.cpp
|
| c46f91288145bdfa2a19303121b549721b7f324d |
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VST1 w/ writeback assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 2dc68468a025ce2371ad7ccf0e82aae06dc38514 |
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM writeback vs. stride operands for VST/VLD.
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143356 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 65ebfa67036a032e0758de0ee9ba21ce2f852ba7 |
31-Oct-2011 |
Owen Anderson <resistor@mac.com> |
More not-crashing NEON disassembly updates for the vld refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 2ad3a89681d15d30b76c36bbd6355ddd78be7e45 |
29-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Revert r143206, as there are still some failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a47e0da9799d06ac0c7e8cfacfa7c6224a0ca924 |
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode 'mov' to 'mvn' assembler alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 5ac24b0a800258194647370798e5eeb296008d57 |
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 57838c6b1eacdb22fd448be34514c24b504aa1ef |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 101a983026371ab3fdc98fd4ed34962d606d1905 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 26b4f62e52845638a6e353b58ea72326a0aa7b06 |
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1752298d4d6fb06c155428b03b2d14522c392e78 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r143202.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143203 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a5679cbb920cf9a099db8cf724fd9b5dd82ac8e4 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Specify fixed bits on CPS instructions to enable roundtripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143202 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5ce8e933b4b5002f65050b4ba761a3ee4b1dcc64 |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 48665489a07cf7db7fb78f70e9cabb730f29e32e |
28-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0ffd02dc922213fed7eb0d055d76e260027adcdd |
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ae74e2d02beb3e78a1282d2c004731599a5ed9af |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.
rdar://10348896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f2652f509d055054974c9d90fa4c951b6fa48e16 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 47a896b5a74c6a3705d96c39117ba87bfe30ea7d |
28-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also set addrmode6 alignment when align==size.
Previously, we were only setting the alignment bits on over-aligned
loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d619acd5e0ff59556f563b66a4075d28900781c0 |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM isel for vld1, opcode selection for register stride post-index pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7861c3f93940b5112fda4dde9d797cb7594d863d |
27-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Avoid partial CPSR dependency from loop backedges. rdar://10357570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 2aee84ddb90faf76d0162dc478cdb5e34f85cd5e |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 195041f15bfeaaeec270fd4335aac1a22b1eea26 |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d11ed82017f80eee78a71c16bb53c0eec170f3d6 |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
A branch predicated on a constant can just FastEmit an unconditional branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143086 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1acd83af87340892e4b7309e1d1d69a43bd629ef |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Add a TODO comment. FastISel works by parsing each basic block from the bottom
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143079 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b9b7957ab80a1d8f3383d1c3e5f3edf6d89adade |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor a little more code into EmitCmp, which should have been done in the first
place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143078 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ac9946371cdbef20f0260e7a9f3e5e19a31b57b2 |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Use EmitCmp in SelectBranch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143076 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2e048e006f250648b2e8f719d1fbcfb8858fe0f6 |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor out an EmitCmp function that can be used by both SelectCmp and
SelectBranch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143072 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e6fd12e1c21314ede2b91e5653a16fe8aabed079 |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldr pc-relative encoding fixes.
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 78794d3986f6499cc4724df0185069f8b62a2b8e |
26-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parse parenthesized expressions for label references.
Partial fix for rdar://10348687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143063 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 23ac055f50505d4abedce97fd9e56e34d042fecb |
26-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Make sure short memsets on ARM lower to stores, even when optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143055 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 20d912fea6b66b4dda25da64457b57a9ee4a7892 |
26-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e5bef7f51e7f036631c1aa868066286cb096fd20 |
26-Oct-2011 |
James Molloy <james.molloy@arm.com> |
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143023 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| eb360aeb03307e598401d29e8d454f794090974f |
26-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143018 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 918bdf0925ae48b06560f27bd888794aa48f820f |
26-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert part of r142530. The patch potentially hurts performance especially
on Darwin platforms where -Os means optimize for size without hurting
performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143002 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fd927582491b94189901c15fa773f7d551add6c2 |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 6612871ef6b50ff9aec353d155d0fb17627a4806 |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 974c3ceceb4d7cee299a06e8095a0b746db62564 |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 2adfd841f62e261345f37640eb0c70e3ccff7097 |
25-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Don't crash on variable insertelement on ARM. PR10258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142871 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 452c9fa1c219c96881fe2430984fd6747555a67c |
25-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
ARMConstantPoolMBB::print should print BB number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142867 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| f121d4f9a66dba013c4fd6bb2c8f578a5a904ea1 |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| a028cb524487151b2462e0daa849eee3fc50564e |
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor am6offset usage for VLD1.
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 1d4b94ff66bc2b3b9b75d2896a0582712abd5531 |
24-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 887422c3752cbefb67e6a4367358a38bfcd99c0a |
24-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ea830cd77510d8035bbcb868518ec8bc27267214 |
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 LDM instructions can target PC. Make sure to encode it.
PR11220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1c7cab083974e6411e750150c8643918074220f6 |
22-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move various generated tables into read-only memory, fixing up const correctness along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 3b55bcbf2342bd8c93b789d3feea7a301beea120 |
22-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The different flavors of ARM have different valid subsets of registers. Check
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7d59e9476bf03201dc2e121fba9727f8fbddb8c5 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| abe29f3ae72e94c5a97203fd4cd4429b4918a21e |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 795974e62ca656aece0bea6bbc1bd203e47dec9a |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 9f769c6463fbb58242d8d656dee4025bf4d8f665 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 4d2df7abe37c4a77e1f8704e885b8318e69dd70b |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| a55723f31ed5f46e4697f1b27f3d35b11f8a682c |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4ba8dae7e2d52964666bee7d16282ce609d361e3 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke an #if0 that got accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f7dc1f6031ff101afaf1443b407ce5ffc0ea63e8 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 3a312b8e4a5e88d20f0d93307bcc56807fa3d00e |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some outdated comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142653 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 773762c84df485b924e54bc0ce8e6c8e02f8a3b6 |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e9f08e0ed1d0e1779109f7ecb28f1d0fec8c003f |
20-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 531d3add6b131902c163876b792023bcf845afa3 |
20-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add missing operand. <rdar://problem/10313323>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 28e780947cea28a1f3b7ec7a0ae4c05aa42c4c03 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| cc5c6167d27edd29d05f65dddaa6750e31bfcffb |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3e8ba1d79be1cf9813b83d00117c05f1199e3dda |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBX (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 514e5381301eec702b3ee20cdee008e72c21f411 |
20-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| dc9205d9c29171f1ddcf2de7eb172a583cadbe63 |
14-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for ARM halfword load/stores and signed byte loads with negative
offsets.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9eb674880b98cbeca0cd5b3f0265b77282d48b4a |
13-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a517ab155b371e2911450d0048fb158931b8e68c |
13-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5be833de769608254fdfc56e8173000e874a8154 |
13-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b29b950bf227b65e193abf924f77ef3fa4eceaae |
13-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for emitting both signed- and zero-extend loads. Fix
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b8ebca83f4dff04ba21cc97673003f0bd35a2e49 |
12-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/LLVMBuild.txt
CTargetDesc/CMakeLists.txt
argetInfo/LLVMBuild.txt
|
| 9588c10b69121d9746b09e868fcc8879cbd98e3a |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor simple immediate asm operand render methods.
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 742c4bac07e2800275a69259296fba7c3e3f651b |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Re-apply 144430, this time with the associated isel and disassmbler bits.
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 4d06138d53b5e3248eccd04b2b31277fce66f260 |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Oops. Missed the isel half of this. revert while I sort that out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 10a630dea6d03e8cfc9575c81a996e1644b0d660 |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for VST1 two-register encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c7352f8ca0fc716c38cb3d81e63e943d47d578b3 |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional size suffix for VLDR/VSTR syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 11add26ec2bdf5109f0ff2ee19d237664687b914 |
12-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7aef99b677452724100145c81f76f32e494cc5a7 |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vldm and vstm VFP instructions can take a data type suffix.
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c3937b97c00a857dff3528895e71ecfbc7ff3a28 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke no longer accurate comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 95bc85e4eefdfc1aabfde85daf752f05d2a60701 |
11-Nov-2011 |
Andrew Trick <atrick@apple.com> |
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
Fixes PR8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ce485e7f70faed6d19daafff91bb20509403d432 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM allow Q registers in vldm/vstm register lists.
rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| eea66f63d98771a2772f5173debf954a81f3f782 |
11-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1c47de87c74c3834c5cfab8a7e0fa67b1805f927 |
11-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Rename variables to avoid confusion. No functionallity change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a07d3fc693e2a3ac7c9ed2a59f62b21ab33d9fd4 |
11-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for using immediates with select instructions.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 15f58c56e9a4150abeea04469c9105edb8acad99 |
11-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 646abbfa30f881b5183b62e77a185fc48d9d82bd |
11-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
When loading a value, treat an i1 as an i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4e89d97e3a40dcbbf07648512f0e95133867a74f |
11-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for using MVN to materialize negative constants.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5ed5506f18fcc0a277c863f7a21b39f58e892ca5 |
11-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| 0352b4679e9289ded6b2d73a76a017e0d97fe70d |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
rdar://10429490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 83ec87755ed4d07f6650d6727fb762052bd0041c |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM let processInstruction() tranforms chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5402637ff283d7397513d5c1699cdf2274c47313 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fae02597bb90f4334079580441b8e5876be4a3d2 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 diagnostics for reglist on PUSH/POP fix.
Was not checking the first register in the register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1b332860aef0121cf4591f4377a7201ce0ef8366 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 16455ce1a4063348209e94f52afde653ded5eeb5 |
10-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
When in ARM mode, LDRH/STRH require special handling of negative offsets.
For correctness, disable this for now.
rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d475f8612b1c7959dbf50242c8fa9d4aea1ee1a9 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .thumb_func directive for quoted symbol names.
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ee10ff89a2934636570cb17b756bf31b2a38aab5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 71810ab7c0ecd6927dde1eee0c73169642f3764d |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 6cba97c5557ac51d8ae09b9f5cbad6891124db4d |
10-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
For immediate encodings of icmp, zero or sign extend first. Then
determine if the value is negative and flip the sign accordingly.
rdar://10422026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| affc6cf9d2b2b74532ce82027ac4524d1e29a658 |
10-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
llvm-build: Add --native-target and --enable-targets options, and add logic to
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| c352caf168094c83f05a8010ca14c2e643dbf618 |
10-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
llvm-build: Add an explicit component type to represent targets.
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| c27f6725b9ff019ca0bfc317669ed1db9d95bad5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3c5d6e4df495316c0d2e0a7bca5ec7a88aa400a5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 14e809c87210877a675977d247ff4453db82d9b2 |
10-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7346347674f03868e8c076c8c27a7f09f0a086c2 |
09-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2f2fe417f98406140504ba3bbb65676d4a00ed87 |
09-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
remove a fair number of unnecessary materialized constants.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 44ee4714a8c245d4fdfd03840efcf58c3f66c6bc |
09-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide cpu name checking in ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMSubtarget.h
|
| 3568a1051efb9a9edbd4914b04b44e9d7bc1b004 |
08-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 66dc8ca04b719f3ab4aa650609dbd56b055ecb34 |
08-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5207bf2177e9ef1e68d9408ea4b44f1c8a5ef9c0 |
08-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d752e0f7e64585839cb3a458ef52456eaebbea3c |
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
|
| 9f1f26aefaf0bc02e732a1d36e664165d228901a |
08-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0eff39f2e25e9d8dd52b1eb7fa4e7cc6cc77875f |
08-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMFastISel.cpp
|
| 62c8e8e3f65a2943cedbce37a6b9b47653f0ea0a |
07-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144021 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 70be28a5adba5bcae0c6dcd63f17592864c351fc |
07-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 590853667345d6fb191764b9d0bd2ff13589e3a3 |
06-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
|
| 42536af5ce152593f489ca88bd0732218594d536 |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 38f5c0da6d3097ddd65aaab15ce22c1b95d52902 |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Allow i1 to be promoted to i32 for ARM APCS calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143755 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 451afbc6a22a3a662eea7e86088c65c36e84949f |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Cannot create a result register for non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143749 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a4e07270bccb3cb6774af975300628e072bf03f1 |
05-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143743 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 44e895761f289029657a8d066f67f0c9d18693b3 |
04-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Enable support for materializing i1, i8, and i16 integers via move immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143739 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b0d9ce567f5aee3af94c290d7cd52b1582c27b4f |
04-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
added a layer of indirection with no value (not even conciseness).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| c39916b166dffba53d19e6189a4154d649e572b6 |
04-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143675 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8e4a2e4f730e691e116a4b2cee3a2c760a54ac09 |
04-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143670 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f470cbbad204caa85275873004151b92fba24375 |
04-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add fast-isel support for returning i1, i8, and i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 65fd6564b8aedd053845c81ede1ac594acb470e4 |
03-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a3a2dfd4a2a8265a9a0c962cb776e2e6ba123956 |
03-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build: Add initial cut at LLVMBuild.txt files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/LLVMBuild.txt
isassembler/LLVMBuild.txt
nstPrinter/LLVMBuild.txt
LVMBuild.txt
CTargetDesc/LLVMBuild.txt
argetInfo/LLVMBuild.txt
|
| 463fe24f1dd5132607abb3548a2acb1849e9aa99 |
03-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for sign-extending non-legal types in SelectSIToFP().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a1e78888d95375194e7513bef3e18d9f1b7d45bf |
03-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Fixed parameter name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143594 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 1a1d1fcc0b955420cdbe0b94bd01c46d4e96b429 |
02-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e07cd5e40ac06fabfb9d33ea7c79542f138f45ce |
02-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for comparing integer non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 81550dc0a866e27a1efbc5de616fb366ebb547cd |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 244006db5c4d48878dc5fdc86976acdaff96cfaa |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143553 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| e31b42a6f5598691498808673648211916bf4d0f |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 87633026d65acf8253e953bdcfd20bc351631f61 |
02-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor out an EmitIntExt function. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143547 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0d7b231c9b0acf2ea6bb99f75672751f64c6c6db |
02-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor out a SelectTrunc function. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143523 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6284afc293c8f6e84dffab8731aa9e679d437745 |
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM label operands can be quoted.
For example, labels from Objective-C sources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143511 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ed6a0c5243f4dc13169edc8e342c679f1bfc201c |
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM label operands can have an optional '#' before them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143510 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 60cb643f7561e5be7a3b5fe705535e96de72cbf5 |
01-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of some VST1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 681460f954e9c13ffd2f02f27bba048ccf90abaf |
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD/VST assembly parsing for symbolic address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMAsmBackend.cpp
|
| 4334e032525d6c9038605f3871b945e8cbe6fab7 |
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VST1 w/ writeback assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| f9f5a765adf8465530fe1aced6455ca9438bb29a |
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM writeback vs. stride operands for VST/VLD.
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143356 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| fb6ab2b30e822d292c557bda32f7eb0acd1004e2 |
31-Oct-2011 |
Owen Anderson <resistor@mac.com> |
More not-crashing NEON disassembly updates for the vld refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 6f3ddef7c51f03945644ad0e69068dfb24d4b092 |
29-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Revert r143206, as there are still some failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3 |
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode 'mov' to 'mvn' assembler alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 89a633708542de5847e807f98f86edfefc9fc019 |
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| b3727fe3ec3b3a718935a6d6c6561e9a58a14546 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| cb9fed665550376b7c65c7e1157a58911193e2e2 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| bf923b815d6da97367e3eedab69230918bf128a3 |
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 82418ff4d1156dfd30d89a4874a365509a0798de |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r143202.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143203 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7ccee5610a7100ddffe05f5eda1950f7d2cf66a6 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Specify fixed bits on CPS instructions to enable roundtripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143202 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5d0492cfc4521ccb13b4961227b279991a17c393 |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 62c1d00dfd38996f381edae55e1028b8e52a1107 |
28-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2ba60e593012ba9b2a9d20b86733eadca288bcb2 |
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c73d73eb881ebe7493e934c00ca1c474ffd0ed2d |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.
rdar://10348896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 04b12a4cfb74ac65ea86d57bde5999ef6ab09ad4 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| b0117eed84b7899c677a1da5e074fe3a2b7046dd |
28-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also set addrmode6 alignment when align==size.
Previously, we were only setting the alignment bits on over-aligned
loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 55dabaa73a7a0be4398fae58443f3ad8264e537e |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM isel for vld1, opcode selection for register stride post-index pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 824a70a384988aebbe3b46254a3631e81a8f0690 |
27-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Avoid partial CPSR dependency from loop backedges. rdar://10357570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 88484c00307274568ab068909cb38ecaedd41cbf |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 036a67d670413f8116415b87457f22d256f314ae |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6d64b3adab682aea9c0b4dd665acc5e863ac6d21 |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
A branch predicated on a constant can just FastEmit an unconditional branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143086 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8ff2664f2f3f4f5dbd847f94352ffc8b4e1b85e3 |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Add a TODO comment. FastISel works by parsing each basic block from the bottom
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143079 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ade620065d1ad591e0f3d39d40cc241f49cf0a99 |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor a little more code into EmitCmp, which should have been done in the first
place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143078 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 75698f346fc44bdd8803b5dda4071d4b5872d82b |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Use EmitCmp in SelectBranch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143076 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 530f7cefd3082e8aaa74b7d65636f30d0312b6ec |
27-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Factor out an EmitCmp function that can be used by both SelectCmp and
SelectBranch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143072 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a581328ceb4c9db165d79a4dabd6b28db799d70f |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldr pc-relative encoding fixes.
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 758a519a22b469ce8e2b8d0bf7a72813e87710d4 |
26-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parse parenthesized expressions for label references.
Partial fix for rdar://10348687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143063 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 75757f9fd13bffc51a6aa30eefe706c4f84d0913 |
26-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Make sure short memsets on ARM lower to stores, even when optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143055 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9c5edc00c41c29be5b088710a4a7ae8507179b64 |
26-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 015cca6c08a5da57b78796d82ab2679e8f5dabe1 |
26-Oct-2011 |
James Molloy <james.molloy@arm.com> |
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143023 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| de39d86f26c5fa244a11d79988f26f52accabaf0 |
26-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143018 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f31151f34ec37dd49bdf998e9e352d572f4a8e06 |
26-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert part of r142530. The patch potentially hurts performance especially
on Darwin platforms where -Os means optimize for size without hurting
performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143002 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 399cdca4d201f7232126c3a0643669971ede780a |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| b36e03d987c843ccb731627ffd2b1db17bd72e39 |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 5c89cb8cd613c5a9d2bb2d6ab68afe8c2b41db70 |
25-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Don't crash on variable insertelement on ARM. PR10258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142871 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| aed4952753e2af9e93dde0b18a4ca8af73ec6db5 |
25-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
ARMConstantPoolMBB::print should print BB number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142867 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 12431329d617064d6e72dd040a58c1635cc261ab |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 10b90a9bbf7dcae1568c03a03f9606f5395f2144 |
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor am6offset usage for VLD1.
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| a7c98f58ea939e1dfe40bba725fbac698f36c0bb |
24-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 692c1d85353249124caa1885cfeda513146c6d81 |
24-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f8e74f816df2d0b83e3fe08da3dff4e8c2421e5e |
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 LDM instructions can target PC. Make sure to encode it.
PR11220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1a2f9886a2a60dbd41216468a240446bbfed3e76 |
22-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move various generated tables into read-only memory, fixing up const correctness along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| b8dcb314f7f9c5c0f068a322c689a64881d78b70 |
22-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The different flavors of ARM have different valid subsets of registers. Check
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 224180e81b34c99d15e35a4d4de6729357c6d372 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 7784f1d2d8b76a7eb9dd9b3fef7213770605532d |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7926db82686be283ec4cdb68989806c69f388cb1 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke an #if0 that got accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 293a5f69fad6053a328bf454e3f28d724d989231 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| fe7b4998c603f181cad282894368028709a5c5e7 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some outdated comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142653 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2e5a5ee613fae456a8ed4282acede56860682f4f |
21-Oct-2011 |
Logan Chien <loganchien@google.com> |
Apply changes to migrate to upstream Oct 20th 2011.
Change-Id: I2bb819151f3fa5ce18690ef373bf071205d3f278
ndroid.mk
isassembler/Android.mk
nstPrinter/Android.mk
CTargetDesc/Android.mk
argetInfo/Android.mk
|
| cd20c58e980552daef182247005cf905fe8b06ba |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a3a6f215d0a56adb7fee009d3f0f8b55e26137fd |
20-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 767f8be9eed51f41c8ad03de7684761f82bf26c9 |
20-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add missing operand. <rdar://problem/10313323>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 01817c39a9d7ff864d0b5de4941eec93d2f9e3a8 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 6b09c77b7a831f57ccedb20c760031492a0af043 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d0b614754eb2d5ce9c2b0841270872129f956059 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBX (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6690bca623d1f6405b95db5b1760f7ba8436e3fb |
20-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 0ebc07a576037e4e36f68bf5cece32740ca120c0 |
19-Oct-2011 |
Logan Chien <loganchien@google.com> |
Merge with LLVM upstream 2011/10/20 (r142530)
Conflicts:
lib/Support/Unix/Host.inc
Change-Id: Idc00db3b63912dca6348bddd9f8a1af2a8d5d147
|
| cdd8e46bec4e975d00a5abea808d8eb4138515c5 |
19-Oct-2011 |
James Molloy <james.molloy@arm.com> |
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 922ad78776a2a45fd79602475636077edfdf94fc |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142485 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b677a135acb2fc5dabb94d8f7fd0839e43dea092 |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 62383e889e0b06fd12a6b88311717cd33a1925c4 |
19-Oct-2011 |
Shih-wei Liao <sliao@google.com> |
Fix AsmParser's spacing.
Change-Id: Ifb734b77c539fc53ec68461d1de7732f296239b0
smParser/Android.mk
|
| d2351e5c088147b5d71d5745cf07b5085a7f0073 |
19-Oct-2011 |
Logan Chien <loganchien@google.com> |
Add build rules for llc, opt, and llvm-link on target device.
Change-Id: I42f35da6f5ce77ab8969746131f5e6fdd42e5afa
smParser/Android.mk
|
| 15a1a226be46dfaaa15c537daa9722b6216a981d |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Emit the MOVT instruction only if the # LPads is > 64K.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142460 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a5871dc1044ff31906f3a2cfc639c7fcd0a14c76 |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
For Thumb mode, we need to use a constant pool if the value is too large to be
used with the CMP instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142458 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 862019c37f5b5d76e34eeb0d5686e617d544059f |
19-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBL (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 85f3a0a4c4c1953a06ea463c6b5d6b88d62b58b4 |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142440 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 952cb50fee7181265c0feb4f656dbbe8c0101dfb |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142437 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 564392bd3f6df4ba139d3be34017ed2a826f78bb |
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The value we're comparing against may be too large for the ARM CMP
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142431 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b9fecf4e077cfd54884ce96ef6bd9febf0d84191 |
18-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The immediate may be too large for the CMP instruction. Move it into a register
and use that in the CMP.
<rdar://problem/10305266>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142429 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a7d2e759ee3b428ec80f084b7c5265e286238632 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Yet more ARM NEON assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142416 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| aead579017d0f8c43dba3bcb049b1d2576b9f8e3 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 687656c6300138583f2e8e3cdaff6cfeb6261b7f |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmov assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 90b7b12f012d9234488277a323231e0b7a8d12ac |
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 9d45de252c7c3851c0159db4dcaa31e93598b29e |
18-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Use isIntN and isUIntN to check for valid signed/unsigned numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142395 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7f5f0dae33c8a105b51532d5ceb3339ac2ce0cbc |
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb2.td
|
| f7b0207f1e89f08b2e2d233b8cc6ba6fcb2a0f4d |
18-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
A landing pad could have more than one predecessor. In that case, we want that
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142390 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9120088979dbcd20e8643bc8f5b22bc605c7d974 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0a0374018f1d17d6d2895fb73026e2942ab111ed |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vqdmulh assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 970f787a7e3929c9cc1c0faabf224d26c1fcd252 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmul assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ad952ad8f05a1c5082a6b7ac8627008fa24d722a |
18-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e873d2a14820d2bfb007da43f382f322f8757ec8 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vqdmlal assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142365 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9858a48afcd39d41ad7d424b159422370cffca84 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142363 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f2f5bc60f61acf0490d856ddd09e461bf93c5459 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV.i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 17001ce25cc205ac1cd2604492c2bce310964220 |
18-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142350 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 928698b14e4bcd0f231dc28e246920a242d81fc1 |
18-Oct-2011 |
David Meyer <pdox@google.com> |
Remove NaClMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| fe04757f5e06ab15208ac0a2ab8d7e83c62b9f0d |
18-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for dynamic stack realignment when in thumb1 mode.
rdar://10288916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 895ede819f0558574fce66cc1eca80eee2deaa4e |
18-Oct-2011 |
Joe Abbey <jabbey@arxan.com> |
Commit test, capitalizing store... keep it simple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142336 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0851a29b6d592f6510b5ff17e7607bb3f492fca1 |
18-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix misc warnings. Patch by Joe Abbey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 6248a546f23e7ffa84c171dc364b922e28467275 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| ea46110f57b293844a314aec3b8092adf21ff63f |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| 3a7572ff61dbd659121b20791d67469a70e9324d |
18-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Add a few FIXME comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142299 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fa1ee880520d8da1168278c65575241487f871df |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142297 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 13a7121858238bc3490b27206a609bf8a2ce1f21 |
18-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Now Igor, throw the switch...give my creation life!
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.
It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.
Neat, huh?
<rdar://problem/10116753>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 0e387b2877e4eebeedfcb26b08253f9c1b946035 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smParser/ARMAsmParser.cpp
|
| a48ed4fc8fddc819460e7ea0646709a7fd701e67 |
17-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Don't renumber the blocks here. This could cause problems later on if another
pass renumbers the blocks again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142258 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6f9c28060f3630a1838ca5b0b3cee87d184937cf |
17-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Pseudoinstructions should not be less constrained than the instruction they are
lowered to. This fixes a lot of verifier failures on the test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 698f3b068fabe42bc775ebf6a964b7de9dcd2b75 |
17-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up organization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142248 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5bc85286ff8940e52edc7be1c8df120f98343ee1 |
17-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a call to EmitSjLjDispatchBlock.
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142245 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c378015d1cc073e5e8027491514f50e2c7413f9e |
17-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Removed set, but unused variables.
Patch by Joe Abbey <jabbey@arxan.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 9904056a7061f6e42d38dd565c23990f0a56e9e1 |
17-Oct-2011 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142204 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 827454e6e28cfed93db990b03b720ef7c23e6917 |
17-Oct-2011 |
Devang Patel <dpatel@apple.com> |
svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp
There is no reason to have simple IR level pass in lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142200 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
RMTargetMachine.cpp
|
| 24bb92556614434a5c5c2246b19e71d85426cab3 |
17-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add comment explaining that the order of processing doesn't matter here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| daada347b550353acbd94fa863bb810854ab6b7b |
16-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
These missing flags show up as errors when running -verify-coalescing on
test-suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d575137634377b0aa9f59d3ecb7c82eb2088033c |
16-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix an obvious typo found when looking at nearby code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 004a24b44ce79746a5333b7bf841b4234a936b51 |
15-Oct-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142080 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 534849687c8cc0e4b538d64be71670e2a028a1be |
15-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Mark tADDrSPi as having side effects again.
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142030 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d73462a1c9e9abae6d404c7830224814ef293f0d |
15-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Thumb1 does not support dynamic stack realignment.
rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8
humb1FrameLowering.cpp
|
| 918f2155e90613bcf222ac5499f845d231bdfd57 |
15-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Mark registers as DEAD because they're really just clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 46995fa7e2eead5759d13ddc64ef073c1d527f12 |
15-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5d79859f66fa1540d5a1c1e9e4f4e080e6e956f1 |
15-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Make sure that the register is in the register class before adding it as a machine op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 969c9ef0dd271905136f21a6c51dd0839ef01cce |
15-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Mark the invoke call instruction as implicitly defining the callee-saved registers.
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8223e45dff0f368ee40242f9e81f09b40e081756 |
14-Oct-2011 |
Richard Trieu <rtrieu@google.com> |
Fix a non-firing assert. Change:
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| ccbe603869681aa71b4140e3bf4b4459caf60622 |
14-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Ban rematerializable instructions with side effects.
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| ecb830e45c216209f4a8b95d687f1ef4e9185bee |
14-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix undefined shift. Patch by Ahmed Charles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 8e4d0429de3d44a4c5b02b3d27cb0b78520609ba |
14-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141903 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c18e940c5a1c050701594ee2b356cd40249505a3 |
13-Oct-2011 |
Owen Anderson <resistor@mac.com> |
SETEND is not allowed in an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 81b2928d80047cb6c8ae0048185742abae1d9dfa |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM addrmode5 represents the 'U' bit of the encoding backwards.
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| c66e7afcf2810a2c1ebf08514eaf45c478e5ff67 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDC/STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| b0786b33fa9090adee9a30796ead7969f948f4cd |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
addrmode2 is gone from these, so no need for the reg0 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 01208d56e8341c17bb7dbeaf6c081fdffe523786 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| bc9c80240bc922cffb02cae390181bf42ad231e5 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 1c062c24aba08962b4687f56b274f182e5b7a8e5 |
12-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix -widen-vmovs liveness issues.
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2bd0118472de352745a2e038245fab4974f7c87e |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| e575499d830008784b11499dae290ad0480c8f9d |
11-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 2cf8dd384e69593475e4e5e6cf98b5b15c778ab8 |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM addressing mode cleanup for LDC/STC.
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 57dcb85a30133a9bc008f0b9ead81be03a23521e |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parse alignment specifier for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| e53c87b302b3ae07c781405572170b0b6641b524 |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 142bd1a54e93f3f66d420717ecba53539a556035 |
11-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 3f56d4b957b04aaaf3ad27900713ea4d67f3189e |
11-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Simplify check that optional def is there and is CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| bb5b3f33594cfa40e9f53bf9a71af359b080a697 |
11-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Add a natural stack alignment field to TargetData, and prevent InstCombine from
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| f6c35c59f515505fa2e9b74b3d0f4ab06f8266d8 |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify operand Kind checks a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ef2c86f8760f717882821987664bf5e7604ffe20 |
11-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Reapply r141365 now that PR11107 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 38fbe323157a712e0b4334b7d73bcde6735c53a1 |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Add a name to sub-operand for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 721e1d266902f4d906645b130d1b2a905d75fa31 |
11-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
If the CPSR is defined by a copy, then we don't want to merge it into an IT
block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| eba564ceace5861a321c230acf5df32e55ed9be5 |
10-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 8129d213960bac2c9d01053922866fc0f552462e |
10-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
When getting the number of bits necessary for addressing mode
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 29b9d7e4ea7521be25bccdb66ecd9c9df5ed8b4b |
10-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Fix a regression from r138445. If we're loading from the frame/base pointer
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141523 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 2d4b60f3a40d4a1d60d43f5bb94c3c3dd19a6fc5 |
08-Oct-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 460a90540b045c102012da2492999557e6840526 |
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 21ff17ce1b57ad68ae01d6eee0ecc36b5dd318cf |
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM prefix asmparser operand kind enums for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2acf638216d98a4dcfed41828a4764cf9e68b4d4 |
08-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Take all of the invoke basic blocks and make the dispatch basic block their new
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f1083d4139720b41457528f81919d9587e442862 |
08-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ce370cfd891386d613d4bd0d28449d2705705d16 |
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
do. This will be useful later on with the new SJLJ stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 186ffac4d35c9ea669b03ac75f5e21bff1f01a7f |
07-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve ARM assembly parser diagnostic for unexpected tokens.
Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6d2f9cec715c50bca44816d9bdea97f8b63bf2a0 |
07-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Reenable tail calls for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 2fef4573df6fd645f4401302d21c16e72418e3a8 |
07-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 244455e6d6bb95c5e556ace66adb148dbcd16a27 |
07-Oct-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Peephole optimization for ABS on ARM.
Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 217f0e9ca494a1752c591f50f04b4143eb1763c5 |
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the correct vreg here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 083a8eb063657866ff595980fc03a16b791d08df |
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Generate the dispatch code for a 'thumb' function. This is very similar to the
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7011eee9b509f3a0f95a75f68787384f31ea3e01 |
07-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 95ce2e9c52ea220f5090d9e8bacabf8e62f88d06 |
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Generate the dispatch table for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e29fa1df55584b6f07290a91e33bf742f1c549e4 |
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 5e2cbc11337fca72ec962c8d8c29661d0e7c69ac |
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
Place the immediate to OR into a register so that it works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 04f15b4f2f38fb0dd8315676e6cff599cdbd6f0f |
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
* Set the low bit of the return address when we are in thumb mode.
* Some code cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| de8f33c199f3bf2049b0b732169f2bd8717469c6 |
06-Oct-2011 |
Peter Collingbourne <peter@pcc.me.uk> |
Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 930193cb5544bd010a0a2bc795c9006913e2c595 |
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add the MBBs before inserting the instructions. Doing it afterwards could lead
to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8f8aa815b46143e2e84a62dadf6f57daf25a4e24 |
06-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Always merge profitable shifts on A9, not just when they have a single use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d78ebe1e12a9aae01cb11d4d10a3d0600407e5ca |
06-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5cbef19a1d9860534a573f446970f5c65758fb66 |
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Get the proper call site numbers for the landing pads. Also remove a magic
number (18) for the proper addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31 |
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| fb77752253717bc9c26cd2f6915925dc19edb8a3 |
05-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add braces around something that throws me for a loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141173 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5ee02620146bda648a191da6323c34887b987a8a |
05-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
There is no point in setting out-parameters for a ComplexPattern function when
it returns false, at least as far as I could tell by reading the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141172 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bb73468e2bfb21160266691e9cdc4c4ea4256b22 |
05-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Look at the number of entries in the jump table and jump to a 'trap' block if
the value exceeds that number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2a85015313b585c2a6d2a59d5bfc99a5ebe88f30 |
05-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Checkpoint for SJLJ EH code.
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2fec6c5ff153786744ba7d0d302b73179731c5e9 |
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 9e5887b17e634b98f7c1cf0ee4f25c218097d08e |
05-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 9d39036f62674606565217a10db28171b9594bc7 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 2a3f19d7e3f77d4d2f8e2b030d6ec1fa11b2abea |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAddressingModes.h
|
| ff4216a68a5a142259c631b1370bff270bfd7e49 |
04-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 68259145d9ac1f8d4e2cc9fc73626254fcc5cf08 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing/encoding for VCMP/VCMPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f7e4aefd0f78441bef3b9eb683ecccbed9582b8a |
03-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Check-pointing the new SjLj EH lowering.
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 5cd5ac6ad455880395e34ac647f1e962a83763a0 |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMRS/FMSTAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| b95ed6ec464c7c675ac71a57dfd9cc8041533a1c |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB can take SP as a destination register.
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2bfaf521aed6d486b2d80dbf12b84b456100cb47 |
01-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
to appease nightly testers. Not quite there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 2e6b97bbf86d0825a060e190189fae7f884c79c9 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
No one should be using the method directly. Assert if they do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 405ca137a1bf5b08fbda3ba086fb013537ce8662 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a convenience method to tell if two things are equal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 3320f2a3bfd4daec23ba7ceb50525140cc6316da |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the ARMConstantPoolMBB class to handle the MBB values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 9c18f51daaf89b9c706aa0557bede2cbb0debb69 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 14a1a6b018c87bcf75cf5b430623d573fbed8905 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 9aca75c4f8249abf8ba2e558bbd1ae7cdfc6b81f |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove now dead methods and ivar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| fe31e673506ef9a1080eaa684b43b34178c6f447 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the new ARMConstantPoolSymbol class to handle external symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
|
| ff4a8023ecf328047c8f98c7f42bf5e8b46b2f11 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140938 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 3f4e4592c3da4d69478ca37d17cb1d6c7024ec50 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove now dead methods and ivar from ARMConstantPoolValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140937 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 5bb779976a7d8e48408051ec2289fe69206dc072 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Switch over to using ARMConstantPoolConstant for global variables, functions,
and block addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMFastISel.cpp
RMISelLowering.cpp
|
| 3e944e38ea2d7585d2ccbf1557746d6cf7132b23 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Some more refactoring.
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140935 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 029e93888d2ce07f4a81d2a927fd2e3cfe673afd |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a Create method that accepts 'kind' and 'pcadj' arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140934 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| f2b76aae2beec4780c271984070ad15a07bd2d50 |
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
pool value.
It's not used right now, but will be soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140933 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 52490411259ccc34b8c59f3532e78442a46fffd7 |
01-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| c8e2bb68bbc4a71cc10084c8f89565b9f05e12ef |
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f391e9f696183a8dfb6b0d1e791687a520552f85 |
01-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Correct for my over-eager delete finger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140892 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| d98f838284b7c539f274bb21820b2df3588a295e |
30-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Constify 'isLSDA' and move a method out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140868 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 6f09fcf5dae14d68ec9f8731b8c91c04868532e2 |
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Darwin default relocation model is PIC.
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 98602ac9a99c5243a9e1abdb0e72dd326ec4958d |
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Fixup valus for movt/movw are for the whole value.
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140861 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 4ebbf7b8a8e80532bd2ddf7209e62689c1698a96 |
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMAddressingModes.h
|
| e00897c5a91febe90ba21082fc636be892bf9bf1 |
30-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140824 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
|
| 4dd9b091cceaa62f72ed8370f8a946fbe474d8a2 |
30-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Support creating a constant pool value for a machine basic block.
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140823 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 13f4a6c940d00f0d0545ed309a4566279f20dccb |
29-Sep-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/ARM: Unbreak! CMake! Build!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| adcb634d85b1372f66dbafe24c026645bc3d447a |
29-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Delete NEONMoveFix, now unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
MakeLists.txt
EONMoveFix.cpp
|
| 8bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868 |
29-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use ExecutionDepsFix instead of NEONMoveFix.
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMTargetMachine.cpp
|
| 3511cedf36d0473292b8e8dca0b4eb7576e1064c |
29-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Move to ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMSjLjLoweringPass.cpp
RMTargetMachine.cpp
|
| 9b88d2d7827d19ef05d3f11faf56e4f28aaa7072 |
29-Sep-2011 |
Evan Cheng <evan.cheng@apple.com> |
Tighten a ARM dag combine condition to avoid an identity transformation, which
ends up introducing a cycle in the DAG.
rdar://10196296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b18abd077e168f38acb1633c4101fbe3c8a18e41 |
28-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Perform the lowering only if there are invokes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8
RMSjLjLoweringPass.cpp
|
| 39689c81542df0f40bec72464429b21012708efa |
28-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| acad68da50581de905a994ed3c6b9c197bcea687 |
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 833217bfb97486b621dfc6c39cbd629622bb1e87 |
28-Sep-2011 |
Ted Kremenek <kremenek@apple.com> |
Unbreak CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/CMakeLists.txt
|
| 13fd601e0f1c6d8558c4c2b027dacd148f19e6af |
28-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement TII::get/setExecutionDomain() for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 25ddc2bf7ed69f500dd4d3e003004bda28c3dd95 |
28-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0481d29d49cc26a944d0d502360f044cb493a4b5 |
28-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
This is the start of the new SjLj EH preparation pass, which will replace the
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMSjLjLoweringPass.cpp
RMTargetMachine.cpp
|
| 5405d58e21402a8ba3aaaa580ca65155bee00443 |
27-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
Naming conventions consistency. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 8e695eb5fa8ad9d62f92ec8ca8a542ffe5fd1ab5 |
27-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use existing function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8
EONMoveFix.cpp
|
| 2dafe200ca2708ec08656e51a52ce4d718e8a1d6 |
27-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Remove extraneous commit garbage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0afa0094afdfe589f407feb76948f273b414b278 |
26-Sep-2011 |
Owen Anderson <resistor@mac.com> |
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 8f418b11d23c05850c37d2f2c1933fefcae25719 |
26-Sep-2011 |
David Meyer <pdox@google.com> |
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4d2a00147d19b17d382644de0d6a1f0d3230e0e4 |
24-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 11ebe3d7c11521b2f092165ac712c9ea0f4c462f |
24-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also match negative offsets for addrmode3 and addrmode5.
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4a713570b60eb5c849d988d68057f6df4d1f3999 |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0781c1f700886f94f5430380a5e82d7ccf6bbdc0 |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
|
| 31d485ec9a2afcf83c5354061568b4280d61b574 |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| df0caeb6eca5c3424b4ccef5f489708392450982 |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Revert r140412. This affects more instructions than intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| d2560565810d40afea87f2dfbe51e125d0dc80ab |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 register-shifted-register loads cannot target the PC or the SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 61268701931d747fa95e0be8a368101e7f97b83c |
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| e1368729700f1a51ee5cf33431df985e232bcc68 |
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 519020adf1cf57e2e93cc4fd49c385c47f7ff0f7 |
21-Sep-2011 |
Owen Anderson <resistor@mac.com> |
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 3be654f8082dcbdff011a6716a7c90486e28fc9e |
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| e23dc9c0ef50b0a1934c04c1786f3a0478d62f41 |
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 317eaf19937813d630166bfec7b933a98ea89aa5 |
21-Sep-2011 |
Owen Anderson <resistor@mac.com> |
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 0d18174f0f138e98fcb8348b735a90add45428b8 |
20-Sep-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 83a8031336a1155e6b0c3e9a84164324e08d1c8b |
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 4815d56bb2c356a610f46753c5f1cefafa113b21 |
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 3af7a67629292840f0dbae8fad4e333b009e69dd |
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 50f1c37123968b7f57068280483ec78f6ff7973e |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 6053cd956fa6c781a4ee05cbc99ab15db3cf3d13 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8c9898454c1006e6d502e67f22f186f2de88b922 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect comments. These are not disassmebly only patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ab3bf97fe029e3ce6834b54c4c5a647c0b665546 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| abb8aacef279a468c4ee9e111a5a95064f3de4ff |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 26215425da200a7b4695b78521a7677397849ad1 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb CPS definition is not disassembler only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0efe213ed5a2c1d2647dc1306e684da6147a611e |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 range check on CPS mode immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d9346fbb06d64266c2fe46edef7a15cb9af7e7e8 |
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
tMOVSr is not allowed in an IT block either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 9f666b5f2e4a5e94cd667e5be0c5d513dd64ea67 |
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
CPS instructions are UNPREDICTABLE inside IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 32f36899e942a4bd7e25f61bf3d49a737699c481 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6729c48b940df5c141eec6375d14544cdbb2ed3f |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4032eaf98c63b0fb1f2418a1cdc56b72bc76c329 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 04c7877894492d6e8aa45567988cd7de100589d8 |
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| bc80e94865d139a60534ac40cbf12f2d214dad56 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 326efe58918d3f0a431d07938054870fcd0e240f |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 061c3c450660976411ee7ff02774ae491ab3ee79 |
19-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fb12f35545481e8b42bd547bc37d220ffee77f86 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM asm parsing should handle pre-indexed writeback w/o immediate.
For example, 'ldrb r9, [sp]!' is odd, but valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ecd1c557904815e568258fc5420de479589b0a93 |
19-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 8a8d28b0392a27ff8e0c60c04561671023a08dc2 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| cb775519279cd1471c490eb5bf4e3ce663fcdc7d |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 8b22778431cdeb112366ed5dc6283b3a7af19018 |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix bitfield decoding based on Eli's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| f67e8554bf4808ad447ffb5d2deebbb10b810391 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SUB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| e4f2df945a69e70f8e045baea3a14f3cdc076554 |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 89db0f690c3238544e59ea3bf2b7a0d6bc8a6544 |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 8a28bdcbcca3328364b86c4010fe96590d1952c8 |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR.
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 947a24cd64f9471511629e9db84bac2c334c73c2 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139944 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 705b48ff860e7484f0adee88362dbe1936ae936b |
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 642caea2c624aaeb492a112d60f419ee4d1a10c7 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR(immediate).
Add aliases for STRB/STRH while there. Tests forthcoming for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8213c96655e955a0b63b05580bc2f6a55be26083 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 50bd470d85c63860f887b7c3e5724c9fd43ef3a2 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b105b997a49c809bfd464ae7691d5ee45d34f446 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 05ec8f7ac90179cccb476512c872db95bfec418d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3443ed525a3bce98bacabb5aa8e67bee6def3b09 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7ff2472b8235d8702bd04bf297d573d06cf6b40d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 231948f860df79b7f0926305caa065a64d758265 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| db7e2e59dde94cfab4246ae694dd13295940fd62 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Kill some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139904 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fb9cffea4a650d7f60d2c24741656c52c2185945 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139903 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 837fc5e9d5138ed48a74a672dc4c1525e5975ce8 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| eeca7582faed76deb3a5ac9216dce6275ac99481 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139877 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 98c5ddabca1debf935a07d14d0cbc9732374bdb8 |
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| c075d45364190dfe06eda8aa93b6856d4f55f107 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 74bf18cceaa4d83c816ffda04592c00a16de60c4 |
16-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139869 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7cc156647ff448f03898b3d80ecdc22d46430b57 |
16-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb.td
|
| e4e4a93e9ec6040b6466bf067d5e02533471f093 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 191d33fd6d0a91e89f2a8f719e5adbdccf9effa9 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 689b86ed2e1f1daf9201f0ef83ff3bc1d5167232 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV16/REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ede042dc8d59ff48a48ef8e2271f2a7ee8324ba5 |
15-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 1b69a128d6b98456c666b4031cc46c3d0fbe6177 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b6e9a83349474d348b401f02c58f4a1754181127 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139796 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 57b21e437a4746e8c3c26531cb233bac953cc5e2 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 push/pop mnemonic recognition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0b69247b10ddbce5f0c476c3471918ffc6091ac5 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PKH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 21a05e7017fa4056f3241f9c31afa4664c389c8e |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARMv7a has the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139753 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| e1d58a6556fe8b00d119373aeefbbecc9b86a1c5 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tighten up the register classes for the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8adf62034a874adacff158e8adc9438cb3e67c01 |
15-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d32872f9ca446fc48084082fcb88255a55405cc2 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 34626acf7fb042c3a831e2f7dfb653ea79c7adec |
14-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 64944f48a1164c02c15ca423a53919682a89074c |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| bf841cf3360558d2939c9f1a244a7a7296f846df |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| c2d3164ab467bdfa8508b93177e69b99626cd8e2 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing for MOV in IT block.
Select the right 16 vs. 32 bit encoding in an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d0588e2a2ed1f7570f13b78c2042855dc4afae10 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix assembly parser handling of ranges in register lists.
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d300b94e51cf8c91928a66478c387c1c3d76faab |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove unnecessary scope resolution operator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139656 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7782a58b87923cc293d4e4422729ac0a582bb5c1 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
|
| d7a2b3bea8e8e4965cd7654f3a7537aba6ad7870 |
13-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
There's only 16 regs legal in a register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139637 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b04546ff5b1a7a03eec1076900c945223bf494cc |
13-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
humb1FrameLowering.cpp
|
| 8f310d978681b08e2e134a1d7b0433e43aa909f2 |
13-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139635 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 12c7e90d369b4605aac0ddbd252231beacb2aabb |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb2 shifted register operands with RRX shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 885f1a0c048e07fca56bc256702c58eae50ae71f |
13-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Zap some junk from the ARM instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 2d539691a1e4b9d61853aa99d1a5580dc88595db |
13-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cd00dc6852d17aa24f667a1060d2de83cd6423f0 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fd92d2e106acfbf13ed29b5d15f3a690cd8699b2 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative LDRSHW with an immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| a0737950233acc271e444b270498d4986b4d2d00 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139531 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a3157b402695ef9d5f6a03e8e3afc5bddf3a3df7 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
isassembler/ARMDisassembler.cpp
|
| 1ad60c2adc9ed765a968747d0c548cda53bfd384 |
10-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for MOV(immediate).
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 921d01ae1ff4e1dad2daeed22f8259a7a520412f |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
LDM writeback is not allowed if Rn is in the target register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 112fb73502d54dd7dd61ae2de24c92d4df181294 |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix an ambiguously nested if.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cd4338fff5cc9427003766519bebcfa213b32d61 |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMFrameLowering.cpp
RMISelLowering.cpp
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 468709e43dfff52f48af9ff411d461e22b6e2015 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MLA and MLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0811fe13d65c67e4c22d9113795deabbd0daa277 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMISelLowering.cpp
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 441462f9328cc7fb86af74c9568a7f70b7bd1fbc |
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| d2fc31b3f75700dc89305cb161f3bca7f1a39bef |
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| a77295db19527503d6b290e4f34f273d0a789365 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| e64fb28da191bc978ab99ea397e6108a15c364f8 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR post-indexed.
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| eeec025cf5a2236ee9527a3312496a6ea42100c6 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 170580e8f413271f665d78f349237c4bcaf9d8c4 |
08-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| f0eee6eca8c39b11b6a41d9b04eba8985655df77 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| ab899c1bcca7f1cc85342c3a686464ba4af035df |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 8bb5a861a0efae6b9c8f07936ad9bb3508ada23e |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8a83f71301fdf0e2cea8ecdf413f192ac48ddc5c |
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| a8307dd1c9279cbde1f3497e530d2ed9d014a0c5 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 94f914e3fd4b040edd81abb5f455ed2b99e2572a |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDMDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a5d585685493d85d5cb72b831a68ec747ae55a86 |
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| cfbb3a78dbb9f0e5de90ef2032f0ee9a7ceda8f1 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 76ecc3d35b4d16afb016bb14e29e12802b968716 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDMIA.
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6de3c6f1a926f49cca2fd207ab4eeb6c35e0e068 |
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| b950585cc5a0d665e9accfe5ce490cd269756f2e |
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| ffa5a763444e456cee17442af603fb4ef0843bb4 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 use 'ldm' as default mnemonic.
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 81d2e3901eed4bd70f551df8935c9ff224ccef6f |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Better diagnostic location information for mnemonic suffices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139232 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 218affc710a0165746ec21a3315c6cc68272cfd5 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ISB is HasDB, not just HasV7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| aa833e53dc74db6cb6789ef7f05c620d28980983 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 06c1a51241852bd652ae6473afaa71d96d48b0eb |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DMB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 77951908b76c00315f1a74d09fb45530029638ec |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ef88a926778b15aa4527a148a514ed0585af7cb1 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CMN and CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 34c4485b7479a12b5ef1cb15d27e96277e8a499a |
06-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139179 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ad2dad930d450d721209531175b0cbfdc8402558 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CLREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 4a51708448e8958d8d1a375c055f1b98c8e20926 |
06-Sep-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 98447daa9559d5bf7816f084581b5ca073d316f6 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .code directive should always go to the streamer.
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139155 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9b0e1e7a5b5a51fca3a86315a72d2bd49334436b |
06-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Atomic pseudos don't use (as in read) CPSR. They clobber it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1fac6b50ea720d75fc2bf01a288e99f239869e90 |
05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 7442a03dcc2ac7850a77ec7c639973d8dc6034ae |
05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139122 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 6c3e11ea55172def6f9829cc24cc5c3b071208ba |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BXJ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a110988b391652e3f4f85cb709a3eeb81c8cdd84 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding of B instruction.
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4136d23c4805c5403a3521bf03fbfeee75b9216b |
03-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5f25fb01b4061725124e34a942809e9c0c6f681c |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ASR.
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8e0c7697fd9b9354856074efc06eea9f6d80015c |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMExpandPseudoInsts.cpp
RMFrameLowering.cpp
|
| d2990107a9c10e41f4e6256147374afb2118b55f |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5c1ac5554229d5481b772cb017139bdd24d5114d |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for AND (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f0851e5d95a1d1f746a3b1e9633af76496e316e7 |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADD (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a1c110045a284190955f28b8f308ffb365cc2eda |
02-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
|
| a6804444e874b27aee5921d4c6049df573c5e249 |
02-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix 80 columns violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 36a16015ac108e2f0dd2d6d96a6d364bc74c50d7 |
02-Sep-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't drop alignment info on local common symbols.
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCAsmInfo.cpp
|
| 7df496d2ad1ecbc86d454a5cea2ae3e0928197ee |
02-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Null-initialize to shut up -Wuninitialized warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2f25d9b9334662e846460e98a8fe2dae4f233068 |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c047dcade506a5acaccb1548cb83a3f85f52d71d |
01-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Fix up r137380 based on post-commit review by Jim Grosbach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 7f17b5a483ea358f2b9e3958f16cf34d75d5b4da |
01-Sep-2011 |
Owen Anderson <resistor@mac.com> |
t2Bcc is allowed to have a predicate without a preceding IT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 20ed2e7939d6a8e804a51897c3af4588deb48be2 |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ADD(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| dd1e7517b5bdda245c907f7e36350ef862be2571 |
01-Sep-2011 |
Chad Rosier <mcrosier@apple.com> |
Fixup for functions that return a bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138918 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| de98273189700c1c66f06bcfbcc481cf481a8dee |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Static relocation model Thumb jump table interworking.
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138912 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b45b11bce1fd79b0973d2df8db295583b5477c62 |
01-Sep-2011 |
Owen Anderson <resistor@mac.com> |
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| c075510e43f768e79f0d66374f4d60529c4d3d85 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 721cb1fde07423fd1905338d443172a8028ad634 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding for tBcc with immediate offset operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| d84192fe4f6495e43ee0ff2ac591c14ba36e1e9d |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
<rdar://problem/10046188>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138885 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b80ab8e369d13673c7fec81f07d1c9718c6eec7b |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 559c277aa9242dd5b32d2f2ccc353d938f886ee9 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| c9a9b442853ee086492d6ad1384a2de2fea9b43b |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 72335d55d972dd7279fe68ed05fa3c4e7fce9345 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADC(register).
Also add instruction aliases for non-.w versions of SBC since they're the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4d3f3294535a3b622c715f2d9675d4f3e86c3378 |
31-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
64-bit atomic cmpxchg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 0f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak Thumb1 ADD encoding selection a bit.
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 61545829832ba0375249c42c84843d0b62c8f55f |
31-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Put VMOVS widening under a command line option, off by default.
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 3d93861c23b1bafa8ae609de94edd5740ffbf6b9 |
31-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Some minor cleanups for r138845.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2bdffe488203a08a2ca98548a157e0eaf39d4b2d |
31-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| eaca928a3798e1fa7072457b94eccdd5b53b5d5f |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| 21df36c57afc588c8073a070a47e3ba45fa87270 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| a7710edd98d71a81c43f8e3889cf0c790885d1b8 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 391ac65377f2ad5e48a796e75120959e22430605 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 10096dbdef22a10a6a4444437c935ab428545525 |
30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Clean up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138833 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 37fefc20d3a1e3934a377567d54a141f67752227 |
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 342e3161d9dd4fa485b47788aa0266f9c91c3832 |
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMRegisterInfo.td
|
| d3765189bfb8c0dd3aa377aaf2d644f321ea8e5a |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Revert 138781. It's not playing nicely with the immediate forms for ADC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138782 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e94a5b1218b9b5646da7f41f2020a1f024e2d0be |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138781 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 694e0ffb8aa3a8651003e448135aba0e663782bd |
30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add missing encoding information for some of the GPR<->FP register moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| f8e1e3e729473b8b2b7ee6134b6417976af84d05 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| acb274baacbc104d7ef3b826b443847f11548760 |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138766 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 1f267585104ee283872caef2a3f7b1cccb9ec042 |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c4e16de7652128545c252affa357c3a105ed59a3 |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138758 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 0da10cf44d0f22111dae728bb535ade2283d976b |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb |
29-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 07700d486ec790327723d2a81fe9c66b2fb52016 |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138746 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 63553c77cd1cf3b204d955fb65350db087aaff1d |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2753ae314f656eab6d42c918469ce4ebf422cee5 |
27-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Silence GCC warnings and make an array const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| d7568e1c355f5e364eddafc15c6d5553559f32a5 |
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct encoding of BL with immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 4af54a461fad6c98df72dd18e607bfb32bfc486f |
27-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing tweak for pldw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9f7e8319947c65d9aef2a0f0984557c3b3a20656 |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Spelling fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 89df996ab20609676ecc8823f58414d598b09b46 |
26-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler parsing and encoding of IT instruction.
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 2b568fb3ce0fa7a7ff3a01c83a0d04765214275c |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix ARM codegen breakage caused by r138653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138657 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9ab0f25fc194b4315db1b87d38d4024054120bf6 |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
|
| 1af7f7291d0689e2d58f900c9b5ecaddec56caa1 |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Update for feedback from Jim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 86ce852a15f0c66601dcaf55644d8c4ec268906f |
26-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARMDisassembler: Always return a size, even when disassembling fails.
This should fix PR10772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 96425c846494c1c20a4c931f4783571295ab170c |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 9bd655dcde1cfa1b97014e2d8e4f9845f7d474bb |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 069e2ed794a90cb5108a35627ee148866795f140 |
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Atomic load/store on ARM/Thumb.
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| b210cbf692f9b5f862557f399e914059e4cb77ee |
25-Aug-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Remove stray fullstop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138589 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 99906830e82cf70dbcbed22237c7bd24f9d9ffdb |
25-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| b9ca5124f8a5d593f57cbd0566867578a51d7055 |
25-Aug-2011 |
Andrew Trick <atrick@apple.com> |
ARM fix for missing implicit operands on ldmia_ret.
rdar://10005094: miscompile of 176.gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 51972da57615d7d31372dd1fef120333ef2d799c |
25-Aug-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138566 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 0c49ac05cd2374a99a3126ebe6c8370490a73ca5 |
25-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Explicitly disallow predication in Thumb1 assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 77eaaf0a0c37a1b01d73e0b7828081b185997572 |
25-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide -global-merge option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138540 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| b8cfe4ff411d92b150ce7ec6ec3568ad187dd517 |
25-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add a command line option to disable global merge pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138536 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 0f660260e69e9c6cb6662c14abfc67b8d7b39a40 |
25-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove a out-of-place comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138534 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| f44082091c5517a3275c57a8b58e36987c8227f0 |
25-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| b9d3ff872908bcf648b826c1c48db2cacd813b95 |
25-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM asm backend initialize isThumbMode based on target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138501 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 4d23e99d2a272a4de06ee31eee6d8e501809a573 |
25-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb .n mnemonic qualifiers can be ignored for now.
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f69c80403620ef38674e037ae2664f1bbe5a4f3c |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SUB (SP minu immediate).
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 12a1e3bbcbd4e8f740c8304379001d1e6731561c |
24-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be careful not to walk off the end of the operand info list while updating VFP predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 72f39f8436848885176943b0ba985a7171145423 |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| df9ce6bbc5b66c3c4d30c2f32b6f17c690cfa004 |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
rdar://10015134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138467 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| f95aaf951b628621c9c74bed6c450b8a52a1ae1e |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add missing explicit writeback operand to tSTMIA_UPD.
rdar://10014745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetMachine.cpp
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
CTargetDesc/ARMMCTargetDesc.cpp
argetInfo/ARMTargetInfo.cpp
|
| c7e0bb2325fac6b41f46e8b383119cc0da64a45b |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb add SP assembly syntax fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138448 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 5b81584f7403ffdb9cc6babaaeb0411c080e0f81 |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMInstrThumb.td
RMRegisterInfo.td
humb1FrameLowering.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
humb2SizeReduction.cpp
|
| e234d02204e0e546c3555e7e894b8521d22a2121 |
24-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| 5aa29a0cffc499331a2a24a03eb55643dace1d8d |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Move ARM frame-unwinding EHABI handling a touch earlier.
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138386 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d04f6a581ce06ef1cd5fe376088347ad0246e07d |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
[SU]XT[BH] are only available on ARMv6 and up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138373 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7801136b95d1fbe515b9655b73ada39b05a33559 |
23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some refactoring so TargetRegistry.h no longer has to include any files
from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| ec8b866434d530dee5b885e9db8da86db053c9ff |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 803b1aa8ef00698de62181b9205cfcc0ce6b0ceb |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 1e84f19337d44c04e74af4fb005550b525ef60e5 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dad |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Factor low reg checking into a helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138344 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 82265a2c72b0f2d0daeab4985c9509d8405f51ef |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 6153a036f544beb03dfc4d58edc28cf42712743d |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
|
| cefe4c9c483d8a50ff13f36881090ab44ec67f13 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb.td
nstPrinter/ARMInstPrinter.cpp
|
| e732cb004379a75efd6d1fd466dbea4cf249de28 |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 04d55f1905748b0d66655e2332e1a232a3f665f4 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SBC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 934755ac040c516eac7fdd974e87590543acd16a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8e1e60b5f8fd9c6233bdb8814ee40887555a0594 |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Reject invalid imod values in t2CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
isassembler/ARMDisassembler.cpp
|
| c6788c83b491b502482bf7d9a06b403d07f9e77e |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
t2SMLAD is a four-register instruction, not a three-register one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 22d35086fec34fa106d844b9b2204d7c3c20d8bc |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct operand naming of t2USAT16 to allow proper decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 86b5d2b02d2a7c673792753ab64b6396bd4e2ffa |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Revert r138278 now that r138289 has fixed the root issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138299 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 2379fc235f8979f7f1218523672a19af1505e29d |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Match operand naming to allow correct decoding of t2LDRSH_POST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6dcafc0d0b33bebcac28539257a9a5b250542f6a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve error checking for tPUSH and tPOP register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 796c3659c97c22e3cf2e7e331861a3944c5b90d5 |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Match operand names to provide correct decoding for Thumb2 SMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138294 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2c9f83533baa8802ab1d600fd76854125af53076 |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7260c6a4ea19f5eb94068296c1c8e01a99f17a01 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assemmbly parsing diagnostic improvements for LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5e8701002bc53672a4e6a902e385810abe2cf911 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Temporarilly mark tMUL as not commutable.
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138278 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 838130e3b97c2fa77fb9b89eabbdf149d8e519f1 |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 357ec6850be0dff0038ea3a14f16066705284c0b |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
isassembler/ARMDisassembler.cpp
|
| 11e03e7c2d0c163e54b911ad1e665616dc0bcc8c |
22-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tighten up ARM reglist validation a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2cbf2104507c855850b610ed910536058aa0c6ee |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| f1c8e3e70e222365b84f4cb7e87396ee85820711 |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| a33b31be451472e72e6dd88851061e239ad54606 |
22-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up predicates on ARM target instruction aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| b113ec55e897c85fda606409c1eedec4f89ec53f |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| fea95c6bade86fcfa5bd07efdda9bd902f53be8c |
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
Remove the VMOVQQ pseudo instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| bdc18572bef8408716b54d2a4956e6627fd5f40a |
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
Remove VMOVQQQQ pseudo instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138174 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ac3656ed7a67eaacb8d2c62e1841ed4df799f72a |
20-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add <imp-def> operands to QQ and QQQQ stack loads.
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e5038e191db82d4d92fdeec1b5bce5cae21f6d8f |
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
|
| 0780b6303b99441fef04340b7a083006484f4743 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 2c3f70e5d4b4f179f21ed1b2ba14674f9d65c9b0 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for NEG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3a244bd8b335a8747dd032ad1f6b187415ad6958 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix NEG alias
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138125 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7a010694209ce46c4f415c0b42c3bc03dc094a5c |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Be more lenient on tied operand matching for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7a32fa1c7825285afb5e570bb9c7a4311e6d6d79 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 88ae2bc6d53bbf58422ff74729da18a53e155b4a |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 4ec6e888ec6d12b5255afd685b05c8fee1f7fc73 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 73a1c2cea181a4463effaab8612c78cf11b83336 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Tab character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138072 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| b86e2dbf61425b195ac5c281e480d9f4414377af |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138066 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 1b7b68f08776dc9553399dc3b4e7ab54e5e596c0 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 05b01567349dc6c98f9e68c1d4a639aca7ad5ac4 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRSB and LDRSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 38466309d5c8ce408f05567fa47aeaa3b5826080 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 67b95f902a51b591b6178e370d23ffaca841275d |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(literal).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| ecd858968384be029574d845eb098d357049e02e |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(immediate) form T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 2f7232efd5fdc72aaa5a446e11a868eea666a6bf |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Use helper function to check for low registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138048 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 60f91a3d9518617e29da18477ae433b8f0069304 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(immediate) form T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| c6d7c653c9d4a54e62ac8da92518caa96d0a349c |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138042 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| a67f14bf53737f9bb0afefa28e08c4aac6ec4804 |
19-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make a bunch of symbols private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138025 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 78affc9ea1978d707b376180ec559b62fbf9ea05 |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 846dd95f87f62e2faa6092f99b521ecd9790121a |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1dd56f05e1bc3e7f66f2b0de4b5ea3692136a77f |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 14090bf2636edf5e46a2c12a312b1889f5335d7d |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 93b3eff62322803a520e183fdc294bffd6d99bfa |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 0d1511c022e78e6d8769290b451b98a3b656de63 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 11cca7a2ea1ea4d19433bf356b55845637561a39 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 90b5a08e1ffc4a1c18f7fa964ca561fa4b03c314 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb blx instruction fixup has same data range as bl.
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137947 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| 5f687decc84318b5997e38e7b2c540dde7af8141 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137946 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 3ce23d3d87d1ca437acb65ac01fac1c486507280 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add missing 'break'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137941 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2f815c0b50acc506a7bdcdfb63966c40a0d2e71b |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove extraneous newline from operand print method. PR10569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137900 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 421993f428c01e264fdb0346a8bfcddd4d583f13 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up patterns for Thumb1 system instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137897 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 395b453bed53a60c559b679eb92f75d0b140b307 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for B.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 00f5d982057574cf65a4a3f29548ff9fb0ecfbd0 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ASR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c40578250d391069d2d81ecaab58a83f2667e96e |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137881 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 70939ee1415722d7f39f13faf9b3644b96007996 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| ef3bf64bf8f1e3147c78b772c6c57139403e4022 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix predicate for imm1_32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137865 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5a1cd045cd4220f84dae81ab2079e2272dfc51c1 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 4372ca6fe4119d708d43d9c9ac3feafc7607952a |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137857 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 8884148b8e8f19d5484e735618cf188cfa02c626 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137856 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 0aa38ab1fb53c457ce90390aed2659eb085709f0 |
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137838 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 83e3f67fb68d497b600da83a62f000fcce7868a9 |
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
|
| 89e2aa6afd408f1b4c6b47c53bbf31d48463bcab |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb ADD(immediate) parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 16280308ac6f20d9da06eafcc19e4a6777f49750 |
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
isassembler/ARMDisassembler.cpp
|
| 194bd8982936c819a4b14335a4d08f28af8f3d42 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
smParser/ARMAsmParser.cpp
CTargetDesc/ARMBaseInfo.h
|
| 00c9a518886c4f2d1cd869c174c994c20a353906 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add missing exit for 'case'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137774 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3912b73c74dc9c928228504e9a23c577b57c4e12 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADD(register) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d54b4e612aa5d2d76a62f4409f82bd409f9af297 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Move some logic into a helper function and expand the commentary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137756 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 47a0d52b69056250a1edaca8b28f705993094542 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
CTargetDesc/ARMBaseInfo.h
|
| d0d3f7e01ff7f83575816f6e1d75aa2224ebc2cb |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
|
| ef2865a8eadffd7e346b9bc70c647578010b6afd |
16-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137686 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 19cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c537f3be0c4ff7030afcdcd9f55133ce68eef773 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 92be8ab6a410207a097a24dcbf2e2302f6634265 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Remove dead classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137643 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 5df7ef6cdbdaaa6bf3bf12b959557a44fbf250a6 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 305e046e539a2713190be6de5ffb3f57708ef45f |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7a2e1770ead7c2e3b7292ae466a41b560f3d272c |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
isassembler/ARMDisassembler.cpp
|
| 8757a4c6aba86111bacc49879d1f1c260f4631d4 |
15-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Update comment to reflect MC target machine refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137615 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 7dcd04abe0b0b1dbfb285faea2daece50f9aa502 |
13-Aug-2011 |
Bob Wilson <bob.wilson@apple.com> |
Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 10342123adec62151bf9060493dd13583c67ae52 |
13-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137525 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 4dfe220ad55e0f1e5edbf7cdd07f88497ddfdf25 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM expansion of pre-indexed store pseudos should maintain memoperands.
Partial fix for rdar://9945172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137513 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0d09499cf3e2d927cdc53ec79895303ac12808ac |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 79628e92e1f903d50340d4cd3d1ea8c5fff63a87 |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of ARM-mode STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 6368119c251a0862b48fbafcd4d00430a7f6ea02 |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137494 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7cdbf086e4676494fc6a5b26c169285ae0bb740b |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of pre-indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 3f3570a38be37ca18c545bd1b4c89604ecaf7e31 |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Separate decoding for STREXD and LDREXD to make each work better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 1f6a329f79b3568d379142f921f59c4143ddaa14 |
12-Aug-2011 |
Duncan Sands <baldrick@free.fr> |
Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
humb1RegisterInfo.cpp
|
| 857e1a7b3fcc848a6508f9205f22e8e0d293dcae |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vector compare to zero instruction assembly parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d30970fb6c269154176cb2ee09ed5b45b2bc6a2f |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove no-longer-true comments. These are for the assembler, also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137375 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 342ebd5f380637d965504dcc350f9d0d79bbe599 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 41ff834e91a7f56dab18fbd7cdc03895197a923f |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Make the USAT16 operand decoder auto-generate-able.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137371 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| adf2b094cb66e6b3ca318cf5b92d0b5232a7d420 |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add another accidentally omitted predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 1fb6673bc2f0a404f4f914bf381c627402ac7c6b |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add missing predicate operand on SMLA and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| dd32ba337aab88c215108ca8bf4a0267fce1e773 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load shifted register pre-index fix shift value asm parser encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 796d6b7602f0279b52ff5c105fb73fbdf444f030 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 05b0c9f41e7c6a091bacdfc1472f99ef204ee00e |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Making SEL decodings auto-generate-able.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 89958d50c38022b367ca3367e6694b7cdf3ac483 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cbfc044acd722d14d0687c9cf099f3dca45e26d5 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding support for STREXD and LDREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 7b8f46cf9e31d730acc25be771462e2a6a1a1dfb |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 508e1d3db536b736063385eb1f885b446a1385ca |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 45251b370733b167d1d0640a027365f7208f7d10 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Remove unused template parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 9fe72bcd3714d136b371aa85d293e16363c29914 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve operand validation for Thumb2 addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 14605d1a679d55ff25875656e100ff455194ee17 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 26d2f0ac919f6ae868fe901fd4ad64af6f92da4d |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| ade7d00f5afce5f79ca5c1eb1a854b777c8e0194 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 10348e70d567fb61f6c762d99e91e215c720ebd1 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 548340c4bfa596b602f286dfd3a8782817859d95 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(immediate) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 71156a6e00d3dc4c531a421a76b3b6ee0ae7d0ab |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 2b7b238e843cbbe0682a3cc001fe514f4270a984 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 3dac0bec7e7874ffb378385b6160bd2117184ca9 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| ae0bc5deaa30f1e20a6189e42ca412ba27ec7153 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve error checking in the new ARM disassembler. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| f6713916fb4504aab617f0e317689acd878cc37f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| f8fce711e8b756adca63044f7d122648c960ab96 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 59999264e6cfc7f5d59c9a92c8cd9baaa53434f4 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| e15defc56c4a29c59256415db63d49e6b6379415 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137277 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 623a454b0f5c300e69a19984d7855a1e976c3d09 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRH(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 251bf25e7ee9702fed2a66deeb404ce473f7bac1 |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 53642c533564c41d9a85ad28efe19b12fc2305ce |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix typo. Not quite sure how that slipped in there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137245 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 8533ebad6f6e407215497ca50771f323058f5576 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add initial support for decoding NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
isassembler/ARMDisassembler.cpp
|
| fd9085dca374f9f67a5c416be8056eb5bb4cb831 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tabs --> spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 10cbaab7b774e187c99790292dc1ed64dee2b0f3 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Cleanups based on Nick Lewycky's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| e66ef2d5f54391e53d2c0febb1ef854d060716f0 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f5ade5d39abe5cb12a8202c604321d5992e4a168 |
10-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the R and Q constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 33e57515b173baf572398fafeffcf4644c2a7381 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| c70c2cafe19d90ee0230cc4257772fe68567f06e |
10-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Promote VMOVS to VMOVD when possible.
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
...
vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| de317f40f7a9962372adea162a12ec35a628efa1 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| c36481c4744cdbddec91dc3eca9245acaf2982da |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking on memory barrier instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 35008c2f8dcfe55960fe4efea3a26e526d437ad6 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking on CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassembler.cpp
|
| 51c9805c4bcca635bc6a854e4a246ebd4258f512 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.td
isassembler/ARMDisassembler.cpp
|
| 793b811c5057365d847b7f9ae326358e76facfe2 |
10-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 51157d22348fdbd4b7975877d5b58e53a6d5d3a2 |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Silence an false-positive warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 65e95d950d9a1344f0f59aae47f2b0c3490b6514 |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Don't generate the old-style disassembler in CMake builds either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137153 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 9bd7c2836eea4ba6484a1eabb38cd084f45fed94 |
09-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| ad0d36b79ff6b13d0acb29d316517f55aab45f4d |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Don't continue generating the old-style decoder file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 6cd5716f611b1acb8f4ce02f6953fc68a29fc237 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix typo in pre-indexed store lowering.
rdar://9915869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e6afbabb637de11dd53b2983cdb3676db283565b |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Attempt to fix CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137147 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| bd9091c18d85d6649763165c4951d7b5ff2e31a9 |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten Thumb1 branch predicate decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 8d7d2e1238fac58c01ccfb719d0cc5680a079561 |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/CMakeLists.txt
isassembler/ThumbDisassemblerCore.h
akefile
|
| 719927a68f5b8ca34bacbeb7c970f281e27cbf63 |
09-Aug-2011 |
Renato Golin <renato.golin@arm.com> |
Emitting ARM build attributes and values as ULEB, rather than char.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 3148a654909e55e8511a1c23991bf0ae8d3f9204 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 648f9a75fdbba228e89389c34a2b3f1ceecd06be |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Thumb1 BL instructions encoding 22 bits of displacement, not 21.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137073 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 36ee0e640554b8cc6ad1658fc3049e05d9967160 |
08-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
They improve the verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137069 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 09176e10dbe575b0f4c68803695c47ccb4b81f81 |
08-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load/store label parsing.
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137064 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6d74631062e4464326eb5c680a4d62d340fa42eb |
08-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMInstrThumb2.td
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 2cb1dfa4464c8dc551d93e0ce34d7a2f797304db |
08-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 41ab14b725c8f2bb3e54553d0d7d96ff184786b1 |
08-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 0d6fac36eda6b65f0e396b24c5bce582f89f7992 |
06-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f4fa3d6e463e88743983ccfa027a7555a8720917 |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 19dec207fcc0f04902b7f097b7771ba7abba43fb |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
|
| 16578b50889329eb62774148091ba0f38b681a09 |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| ca8c70b9536bf351ee92395dae6f99a59c011a3d |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM use a dedicated printer for postidx_reg operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 9a45008e917b8c1aef01ab717f0df254cdf1af44 |
05-Aug-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add missing register constraint for some VLD3/VLD4 pseudo instructions.
<rdar://problem/9878189>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 14c903a76be7933cea746617d3f787fdf4de8203 |
05-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| 039c2e19c4237fb484315a62e95222ac28640bb7 |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 154c41dbbc06284efd56782a8bc137a25148918e |
04-Aug-2011 |
Owen Anderson <resistor@mac.com> |
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMAddressingModes.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 0bc8bbb58dbab40396df064667d7061e16f442a8 |
04-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix broken encoding of tCBNZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136837 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 26689ac37ebec3b358588089415509285e558de9 |
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 989f61e6c03b4717838b73aeaac7a38e2d8bb06a |
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136737 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 96279d0eff03f18eb5e21de285148be654171005 |
02-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136707 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| b93509d38274cc27425748070894c2971eb8842b |
02-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136705 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e39389a58d54208fe005aba1709c601ef78b3ec1 |
02-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 02c8460a7428b9721d8784bc320f045d022ce699 |
02-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| b2756afa273b548d950b612f4e936b46e82c1f13 |
01-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 32ab312e3f1987eeb8dbfe0917d980497e88a61c |
01-Aug-2011 |
Douglas Gregor <dgregor@apple.com> |
Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136621 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/CMakeLists.txt
|
| ef7f1e71f722fcca863c7d354f408e72181ff891 |
29-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'Q' constraint.
Fixes rdar://9866494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e1cf5902ec832cecdd5a94b9701930253d410741 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 33768dba54ebd6ba4315345316cf426af7a78639 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM CPS mode immediate is 5 bits, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2c6363a62df95b74468d9a561bbcb9edddeb3507 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 5a287483607773f74ac77ac0ce4ca2201d2a8bbd |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SRS and RFE instructions are not code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136475 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b48ce900f9c8d9c7706b82b346cf9c2212bb3be2 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM range checking for mode on CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136473 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 96e24fa8929974a28b9c3adb023b006264cf7f36 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136470 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bd4562e1638ea6dae205525b0ed84955b9a004af |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136468 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fe42808f44a91421d46e68e85e7486a22a5a26ee |
29-Jul-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.
This fixes the second problem in PR10520.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136440 91177308-0d34-0410-b5e6-96231b3b80d8
EONMoveFix.cpp
|
| e69438fb87623dd6fdeeb99b647a46e877eb6183 |
29-Jul-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.
The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136439 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| ac03e736c77bcf7e8deb515fc16a7e55d343dc8d |
29-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.
I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.
This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.
This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.
Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.
This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
MakeLists.txt
isassembler/CMakeLists.txt
nstPrinter/CMakeLists.txt
CTargetDesc/CMakeLists.txt
argetInfo/CMakeLists.txt
|
| 48c693ff564c422153733424ab845106161430ac |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
PLD and PLI are not predicable in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136427 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cf121c35c484ee17210fde1cecbd896348cd654a |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 293a2ee3063953bb6f5bc828831f985f054782a3 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| c29769b0e875013a594f47305a1e4ea3c19bcb75 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136375 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 354712c5a506449676e6fcac6b623af4092e7100 |
28-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136367 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 8313b48bbe23caefa46c5825f5ecd6c3f527bd99 |
28-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Fill in some encoding information for STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136366 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| aa3402e2800e85107a8f803be2942633b1c8c384 |
28-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 70a0915cd135b48c557a5bc81b37e33f54fe150e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4ebc5916e9b3a43af8aff8e1b8744b1644457a4b |
28-Jul-2011 |
Oscar Fuentes <ofv@wanadoo.es> |
Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.
GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:
../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136328 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
|
| 7b2958392c2be221ff1f0d2ffd45d453dec515dd |
28-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136295 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 5de728cfe1a922ac9b13546dca94526b2fa693b6 |
28-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCCodeEmitter.cpp
|
| addec77b54fd77e99fd01f462a3fb8c3c89066fa |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 14648468011c92a4210f8118721d58c25043daf8 |
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 49f2ceddd25c75373f8a39fa25e8b9db33bcdacc |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 71725a099e6d0cba24a63f9c9063f6efee3bf76e |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 06470311c574da4f83f91400234a1e1fc4c9ea1b |
27-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 766c63e78b6c14b7967790dcc2c613971a72e132 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing aliases for extend instructions w/o rotate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136229 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7032741e7bf84d144c408a47591add10f0a394ba |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| c5a8c861c9f008d777f5da6a77c253fea2bfe2f1 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| bd27f5adbd8f3b8ab8def5aa43fbc406ac9b8cbe |
27-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Support .code32 and .code64 in X86 assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136197 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCAsmInfo.cpp
|
| 45f3929ef0dcdf281a10f23e031ffaba7664e7c0 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
|
| 85bfd3b023d4d70936006eadd86588b03e5f40c0 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
CTargetDesc/ARMMCCodeEmitter.cpp
|
| 793e79601f0fd68ba082fa2016018f80b2379460 |
26-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFrameLowering.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
|
| 0d87ec21d79c8622733b8367aa41067169602480 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix over-zealous rename from r136095.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136132 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 189610f9466686a91fb7d847b572e1645c785323 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostics for ldrexd/stredx out of order paired register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| dfdf02dbada1ff9f87fe6efef0fc182a754f13f7 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix for LDREX source register encoding.
rdar://9842203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136102 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 4f6f13db1a8a491ecab6af64549fbdc23cb5ba56 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 1ef91417bd9677f04c34235dae24771eea321874 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SWP instructions store, too, not just load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136096 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1355cf1f76abe9699cd1c2838da132ff8b25b76b |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 3d5ab367b663324dbe889f19ef9e39f3f0bcefcc |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix asm parsing range check for [0,31] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136091 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ed8384806e56952c44f8a717c1ef54a8468d2c8d |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 28c85a81a17dd719a254dc00cbeb484774893197 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
|
| b35552d440581265a982d7523c33e7466437bfb0 |
26-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.
These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.
To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.
This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.
Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
MakeLists.txt
isassembler/CMakeLists.txt
nstPrinter/CMakeLists.txt
CTargetDesc/CMakeLists.txt
|
| 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/ARMMachObjectWriter.cpp
|
| f49433523e8a39db6d83503e312ae55160eed90a |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
|
| 275944afb55086d0b4b20d4d831de7c1c7507925 |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix more MC layering violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135979 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4b64e8a9e13ba782da2034e1dee52f077bdb759c |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Separate MCInstPrinter registration from AsmPrinter registration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| e4616ace025fcf5316fffdf7f7007e3e5e2d7a05 |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135968 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1b0fc9b4182d6bd0703cdfb3b0b91d1e093c946c |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135963 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
|
| af6981f2f59f0d825ad973e0bed8fff5d302196f |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM asm operand renaming. Make things a bit more explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135959 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 5f6c133d7d4451a78ffc39248fc69a8870b57c6a |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
More simple cleanup of ARM asm operand definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135958 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 54134708f5debe1631f9ea9b232f78758a2151e4 |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135954 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
CTargetDesc/ARMBaseInfo.h
|
| 43904299b05bdf579415749041f77c4490fe5f5b |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Make assembly parser method names more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135950 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 1610a709651d4844984212f61f04022a016a315e |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135946 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1e93b242461fcb01249d5f925e90f3eb3c2344ad |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135945 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 883d99f70ba41d334adc9fef321804a2f88c4468 |
23-Jul-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135837 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.h
|
| a7cfc08ebe737062917b442830eb5321b0f79e89 |
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMMachObjectWriter.cpp
|
| be74029f44c32efc09274a16cbff588ad10dc5ea |
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARM mc routines into MCTargetDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmBackend.cpp
RMBaseInfo.h
RMFixupKinds.h
RMMCCodeEmitter.cpp
RMMachObjectWriter.cpp
RMTargetMachine.cpp
MakeLists.txt
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAsmBackend.cpp
CTargetDesc/ARMBaseInfo.h
CTargetDesc/ARMFixupKinds.h
CTargetDesc/ARMMCCodeEmitter.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/ARMMachObjectWriter.cpp
CTargetDesc/CMakeLists.txt
|
| 4a5ffb399f841783c201c599b88d576757f1922e |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| bf2845c0d8a77d24e9971871badeba8cee7b2648 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e78085a3c03de648a481e9751c3094c517bd7123 |
22-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| b544f68b70475f06a8ec39c874297549edc0f695 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b206daaec1a2ec25e99fbdc413cd0866cec160b2 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e0a03143df398c17a435c136b14316fd43f27fb7 |
22-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Fix test failures caused by my so_reg refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135785 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7c9fbc0340aff9e20fd9009be23ffd279c1c0a7d |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 7931df3d74117d423f67f0406be5ef02f0557c57 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135781 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0fdf6ccf17479a4fc383a1c54eb7dc816c0b5838 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135779 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 063224781808eaf4d41d73f57759101dd899b523 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly support for SETEND instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135778 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| 53a89d6f38fc8a0758436038ed10a8aada48122c |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135777 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c27d4f9ea0cb9064d3e2cadb384d73e95e9de449 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
|
| 6c1bb77992ddc1b22c14268720c05c222255533c |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135771 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 152d4a4bb6b75de740b4b8a9f48abb9069d50c17 |
22-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 7c6e42e9273168ba9b1273a1580d569e1bac0e91 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Asm parser range checking for [0,31] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135719 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| f790193aec11747bb35206d2c79e0c5ffbc6dc7f |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 86fdff0fa79b2c00cb68a2961cca0466eb50d666 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 43d3b31cda187c5fab6fca53eb60739e03a20481 |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135706 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 10c7d70a4e843b3006db9f5f583d6f6f56cc245e |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 92a202213bb4c20301abf6ab64e46df3695e60bf |
21-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| f6c0525d421cb48119423a96e23289b473eddbd7 |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135682 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| dab3d29605a5c83db41b28176273ef55961120c1 |
21-Jul-2011 |
Jay Foad <jay.foad@gmail.com> |
Convert ConstantExpr::getGetElementPtr and
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135673 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMBaseInfo.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMFrameLowering.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMMCCodeEmitter.cpp
RMMCExpr.cpp
RMMCExpr.h
RMMCInstLower.cpp
RMSelectionDAGInfo.h
smParser/ARMAsmParser.cpp
MakeLists.txt
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
CTargetDesc/ARMAddressingModes.h
CTargetDesc/ARMMCExpr.cpp
CTargetDesc/ARMMCExpr.h
CTargetDesc/CMakeLists.txt
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
humb2SizeReduction.cpp
|
| dde038af59506c631ce181aff66e315a0c477f4d |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 1769a3df4a81309ec055a8586c8ac35755fa79a2 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135617 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
|
| a0472dc4205d5f2cc4e9cc5a08c51625573a26ce |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| ab40f4b737b0a87c4048a9ad2f0c02be735e3770 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 34ad6db8b958fdc0d38e122edf753b5326e69b03 |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| ebf5f0962932032481ae306b42c96c68c3a0be95 |
20-Jul-2011 |
Logan Chien <loganchien@google.com> |
Merge with LLVM upstream r135568 (Jul 20th 2011)
Conflicts:
lib/Bitcode/Reader/BitcodeReader.cpp
Change-Id: Iebed76d2f7d281e742947e31d9a0b78174daf2d6
|
| e76a33b9567d78a5744dc52fcec3a6056d6fb576 |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| b29b4dd988c50d5c4a15cd196e7910bf46f30b83 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 80d01dd3d19a84621324ac444c6749602df7a513 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.td
|
| f1a009007374d8ae1c1565f34d9cea3b83665e5f |
19-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| ccfd9313d11aa29551f93fe99428946837c97729 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 5f16057d1e4b711d492091bc555693a03d4a1b6e |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 558b66d3cd536cfba11e295816a15ea6476fcd16 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 731f2097944bfdf5b58ff1f19560a25ed15c9b2b |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tighten conditional for 'mov' cc_out.
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 5a18700470f0831b9b2af78862672561dd980345 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove unused code.
cc_out and pred operands are added during parsing via custom C++ now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6bc1dbc37695bcfc5ae23a1a9e17550ee50fe02f |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM range checking for so_imm operands in assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 439661395fd2a2a832dba01c65bc88718528313c |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
smParser/ARMAsmLexer.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| 565a0366974d82c3efe8a31e0ecc0609c67cad3e |
19-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135442 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
|
| 2d28617de2b0b731c08d1af9e830f31e14ac75b4 |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 91614aec48ae01452422faf0cf6a6770d6b2166c |
19-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135434 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 0af0dc8ac6d084bb04cf0188e48eecd6c98903ba |
18-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Re-apply r135319 with a fix for the constant island pass.
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135414 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| 39b5abf507b43da6b92f68b86406e0015ead18e9 |
18-Jul-2011 |
Frits van Bommel <fvbommel@gmail.com> |
Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMFastISel.cpp
RMGlobalMerge.cpp
RMISelLowering.cpp
RMISelLowering.h
RMSelectionDAGInfo.cpp
|
| 72fdeda08aedc76f6d04c484d83058e96c8af3a9 |
16-Jul-2011 |
Nowar Gu <nowar100@gmail.com> |
Fix Android.mk.
ndroid.mk
isassembler/Android.mk
nstPrinter/Android.mk
CTargetDesc/Android.mk
argetInfo/Android.mk
|
| a71642b2a4944eaa269d881cf71b02b8e8fe5638 |
16-Jul-2011 |
Nowar Gu <nowar100@gmail.com> |
Merge upstream to r135343 at Sat. 16th July 2011.
|
| 91ddfc4723f5857e0124192d71e625a7926cbc70 |
16-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Revert r135319 in an attempt to get to unbreak testers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135343 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| 49e163b6c749a6118939fbba19664b96c2089cfc |
16-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135319 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| 43967a97cf9a296623e1cf5ed643e2f40b7e5766 |
15-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
isassembler/ARMDisassemblerCore.cpp
EONMoveFix.cpp
|
| 167eb1f90392f196a62293bdee68b0d662546e7d |
15-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135283 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 20722b6cda6a8857a00e84133c8d8516400aca4d |
15-Jul-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135269 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 1be0e271a07925b928ba89848934f1ea6f1854e2 |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/ARMMCTargetDesc.cpp
|
| 4afa2b842b8ecc61c2023832c7cbbf6b6116837a |
15-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Major update to CMake build to reflect changes in r135219 in the
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.
Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135234 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/CMakeLists.txt
|
| 1abf2cb59b8d63415780a03329307c0997b2670c |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
RMMCAsmInfo.h
RMTargetMachine.cpp
CTargetDesc/ARMMCAsmInfo.cpp
CTargetDesc/ARMMCAsmInfo.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 33c16a27370939de39679245c3dff72383c210bd |
15-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 151bd17a8fb540c84c3c297d27cedf0512ce02d3 |
14-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add OperandTypes for Thumb branch targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135199 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 3be41b748e4be387eeb751531b7876a044afcc6e |
14-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Port operand types for ARM and X86 over from EDIS to the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135198 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMMCCodeEmitter.cpp
RMSubtarget.cpp
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| c83d504085c17697f2a24d0a9fbad4503105ec41 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Reorganize ARM assembler aliases.
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135179 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| eac0796542d098caa371856d545faa6cdab5aad3 |
14-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't leak operands when putting them into a shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135169 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3b14a5c5469176effb921d91d4494f0aa2919fd0 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9dec507ecb212a7c94659e9b5a9da66cb4b39ea3 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
|
| e77494e3e3da59afaa51d1bbcf732fa2851d865d |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 77f379e2a100e2fe778145cc3f28c6837adee33e |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
DMB instalias needs the same predicate as the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135112 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 032434d622b6cd030a60bb9045a520c93b0d7d68 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 20fcaffaf778169e669359ffb3938fab4814cc95 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update comments. These are for assembler, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135107 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 16884415db751c75f2133bd04921393c792b1158 |
14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMMCCodeEmitter.cpp
|
| 6f9f8845028d4d3b96c33417398034a71137d867 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 1cbb0c16a1f2bb0c6163198f626155640d677411 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Revert 135093. Think-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 91eb0aa5de61c76345bb70506c70732a528df36a |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Correct range for thumb co-processor immediate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| e35c5e06fe5b1fd6e754773168ad0281ecda7009 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0d8dae292a088c3a742f655c1787782abfe7e34c |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Parameterize away the ARM T1Cop class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 9bb098ad3a3c93aec50a4a63e6894472727f8d88 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 898e7e26a531d0ed8d3b31cb1976e7744a4e3bcb |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding for ARM BXJ instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135077 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d447ac6c8c962e62712cfe9dc1c0b940a5619163 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding of predicate bits on ARM BX_pred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fff76ee7ef007b2bb74804f165fee475e30ead0d |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 619e0d6d95879a08ede97c171e1c8712554c7951 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 21101d60ce94f51651f71eeb61ceb8264eccac83 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 19906729a490744ce3071d20e3d514cadc12e6c5 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 37ee464ea98544d3ed84cec6dde5f769ce003d5f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e8606dc7c878d4562da5e3e5609b9d7d734d498c |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| aa4cc1a6d75f621cbc5eb1db692068db072fbecc |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135047 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| b7f689bab98777236a2bf600f299d232d246bb61 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update MCParsedAsmOperand debug methods.
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135043 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3b737081e49ef7d640d50285b6cb5f686c75f63d |
13-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add an entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135024 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| e721f5c8d3ea2cc2cc8c3c308ce8bdd8a3fc3b32 |
13-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1
Previous codegen looks like this:
mov r1, r0
cmp r1, #1
mov r0, #0
moveq r0, #1
The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
cmp r0, #1
movne r0, #0
rdar://9758317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 5fdd6c8793462549e3593890ec61573da06e3346 |
12-Jul-2011 |
Jay Foad <jay.foad@gmail.com> |
Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134982 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 2280ebd61416b73d0b6137f275b25af82e268d1f |
12-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.
Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.
http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354
--- Reverse-merging r134893 into '.':
U include/llvm/Target/TargetData.h
U include/llvm/DerivedTypes.h
U tools/bugpoint/ExtractFunction.cpp
U unittests/Support/TypeBuilderTest.cpp
U lib/Target/ARM/ARMGlobalMerge.cpp
U lib/Target/TargetData.cpp
U lib/VMCore/Constants.cpp
U lib/VMCore/Type.cpp
U lib/VMCore/Core.cpp
U lib/Transforms/Utils/CodeExtractor.cpp
U lib/Transforms/Instrumentation/ProfilingUtils.cpp
U lib/Transforms/IPO/DeadArgumentElimination.cpp
U lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G include/llvm/DerivedTypes.h
U include/llvm/Support/TypeBuilder.h
U include/llvm/Intrinsics.h
U unittests/Analysis/ScalarEvolutionTest.cpp
U unittests/ExecutionEngine/JIT/JITTest.cpp
U unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U unittests/VMCore/PassManagerTest.cpp
G unittests/Support/TypeBuilderTest.cpp
U lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U lib/VMCore/IRBuilder.cpp
G lib/VMCore/Type.cpp
U lib/VMCore/Function.cpp
G lib/VMCore/Core.cpp
U lib/VMCore/Module.cpp
U lib/AsmParser/LLParser.cpp
U lib/Transforms/Utils/CloneFunction.cpp
G lib/Transforms/Utils/CodeExtractor.cpp
U lib/Transforms/Utils/InlineFunction.cpp
U lib/Transforms/Instrumentation/GCOVProfiling.cpp
U lib/Transforms/Scalar/ObjCARC.cpp
U lib/Transforms/Scalar/SimplifyLibCalls.cpp
U lib/Transforms/Scalar/MemCpyOptimizer.cpp
G lib/Transforms/IPO/DeadArgumentElimination.cpp
U lib/Transforms/IPO/ArgumentPromotion.cpp
U lib/Transforms/InstCombine/InstCombineCompares.cpp
U lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U lib/Transforms/InstCombine/InstCombineCalls.cpp
U lib/CodeGen/DwarfEHPrepare.cpp
U lib/CodeGen/IntrinsicLowering.cpp
U lib/Bitcode/Reader/BitcodeReader.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134949 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| af0a2e6730ffb59405352269e1500b6e83e42d6a |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Most MCCodeEmitter's don't meed MCContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134922 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 3f00e317064560ad11168d22030416d853829f6e |
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 589130fac11bc8c186736161600575c3ed6acc5b |
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| eeb64ae6e52ac2a7980884fe89c01508014af6a9 |
11-Jul-2011 |
Jay Foad <jay.foad@gmail.com> |
De-constify Types in StructType::get() and TargetData::getIntPtrType().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134893 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMMCCodeEmitter.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| f75ae4c977b8877bb8988109dc081d512874fb37 |
11-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix <rdar://problem/9751331>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134882 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| f81b7f6069b27c0a515070dcb392f6828437412f |
10-Jul-2011 |
Jakub Staszak <jstaszak@apple.com> |
Use BranchProbability instead of floating points in IfConverter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134858 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| ffc0e73046f737d75e0a62b3a83ef19bcef111e3 |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
|
| eb0caa115491019f7f7fe45fc70ad47682244187 |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134764 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 32869205052430f45d598fba25ab878d8b29da2d |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7e61a3120d70f743825e96e461368ade3bebd7d5 |
09-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Mark tBRIND as predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134758 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| aa8d1b80ff35a4370a75b9d08a3e94f19e0d3dae |
09-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize tBRIND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134755 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 25e6d48220330d17875d0ae0ad6a45597d5ac36c |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
humb1FrameLowering.cpp
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d28ec08eddf4cf8dc5ffe94c6cf72df32e257166 |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize tBX_RET and tBX_RET_vararg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134739 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 75ca4b94bd9dcd3952fdc237429342a2154ba142 |
08-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.
Found by valgrind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134738 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ead77cd6789041bb5c7e0ac2442f1205ab23fbc0 |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle productions around a bit.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134737 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0b44aea7b564c5c28ac0acaaba8805ce7c625fd3 |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134734 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
|
| af7f2d6b67070eae933402c9115514719d1628cf |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134732 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
RMInstrThumb2.td
|
| 8dc41f33f7ff668f7dd56f37bd33fbd4ed82889d |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add more info to FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134729 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e36e21e83097c7d1ec6704cb0d17d71336b2218e |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134727 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 480cee5d4396a380ada6ffd03551b5700d041fe0 |
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
TargetAsmParser doesn't need reference to Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134721 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 245f5e8e2ae2edc9053f72035ca6e1c9596d00c2 |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use ARMPseudoExpand for ARM tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 9ca2a778b65b8926e24ca235bb1eeb0b769086be |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle productions around a bit.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134714 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4559a7bcfd8ecee28e6c1426d321c15ddc58b92f |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134712 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 549a85138c4f83ef6292424d86ebe21661efa517 |
08-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Add CMake support for the new TableGen file introduced in r134705.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134707 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 53e3fc463e3d9ee840510b08ebd6db17694fa2c5 |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMMCInstLower.cpp
akefile
|
| ebdeeab812beec0385b445f3d4c41a114e0d972f |
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSubtarget.cpp
RMTargetMachine.cpp
smParser/ARMAsmParser.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| 4761a8d6549125e21d84371a9783bd41de2f55fa |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rewrite comment in English.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134627 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 963b03c1a9f6a9742671459f103ee9a566c6de58 |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| a8504111f6902e613a89352866843c00f58a007b |
07-Jul-2011 |
Oscar Fuentes <ofv@wanadoo.es> |
Update CMake library dependencies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134616 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 7f358da70faaac5f8ca7b05c8c44a5ab418e8d16 |
07-Jul-2011 |
Douglas Gregor <dgregor@apple.com> |
Fix CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134614 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 375db7f39af8da118f3947d24ea91967c4a6b526 |
07-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134609 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrVFP.td
|
| db068738e806753bc5735434cab9b9f930840c7a |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink feature IsThumb into MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
CTargetDesc/ARMMCTargetDesc.cpp
|
| 94ca42ff0407d71bacc41de4032d8dbe6358d33d |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
|
| 78a9f138ae95458bf6d922f38706eed045691d5a |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM MC registry routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
MakeLists.txt
CTargetDesc/ARMMCTargetDesc.cpp
CTargetDesc/ARMMCTargetDesc.h
CTargetDesc/CMakeLists.txt
CTargetDesc/Makefile
akefile
|
| d1689ae4b1ae5af191f71dcb9c59640a6dca7ebc |
06-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134540 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| d378b323826613f57a973c5eb6373f3fd8b012f0 |
06-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove un-used encoding info from Pseudo MLAv5.
Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134533 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b262799d49891b036daa00eddf51947487346c98 |
06-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
createMCInstPrinter doesn't need TargetMachine anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134525 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| bc20e4f2dc11e346505f11efea22d9a1d3919eca |
05-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM estimateStackSize() needs to account for simplified call frames.
If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.
rdar://9715469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134415 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 7c328f3347b42249c4178432bc29ca66271617a9 |
02-Jul-2011 |
Nowar Gu <nowar100@gmail.com> |
Fix Android.mk.
ndroid.mk
smParser/Android.mk
|
| 1ffcf07d9fb7a7db5737ca7307ae8e0aa713f278 |
02-Jul-2011 |
Nowar Gu <nowar100@gmail.com> |
Merge upstream to r134306 at Sat. 2nd July 2011.
|
| f899bd4a462884aa91b9d0c93ab2dbc605dac116 |
02-Jul-2011 |
Nowar Gu <nowar100@gmail.com> |
Fix Android.mk.
RMCodeEmitter.cpp
ndroid.mk
smParser/Android.mk
isassembler/Android.mk
nstPrinter/Android.mk
argetInfo/Android.mk
|
| 385e930d55f3ecd3c9538823dfa5896a12461845 |
02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
MakeLists.txt
akefile
|
| a7603982dbf9e240ecc7ed6eddcd1cdb868107ac |
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."
Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.
rdar://9572992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| eb03c3b22861e5fb6459aa055378e852df29b621 |
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix off-by-one error.
(low two bits always zero, so off by one bit of encoded value).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| efeedceb41cc0c5ff7918cad870d5820de84b03d |
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| 53d48080e55bf0c99cb7ca9de5b15a084d7324b5 |
01-Jul-2011 |
Nowar Gu <nowar100@gmail.com> |
Merge upstream to r134237 at Fri. 1st July 2011.
Conflicts:
lib/Target/ARM/ARMCodeEmitter.cpp
|
| 5e653c925c7da969c3fb5fa9a46263ffb160b81e |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d5dc9eca2beece0faa85e7cbf17182fe7fcd0b36 |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1070f82569be2602640e15e3a0a3eda55228b8aa |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
We'll return a null RC by default if we can't match.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 89bd71fc53fc95f2526e07ec338a8c998e9ead8d |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'x' constraint.
Part of rdar://9307836 and rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 09b4467ac556e82ba5ff368b035d38697d8459da |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Capitalize the unsigned part of the initializer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 35e6d4d6b6f975157beb1ff8c939fac6699d710c |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Rename Pair to RCPair lacking any better naming ideas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 |
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFrameLowering.cpp
RMInstrThumb.td
humb1FrameLowering.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2SizeReduction.cpp
|
| 73744df0c467895bac9e25d5c62f34a0a8fcc4f9 |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'h' constraint.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMRegisterInfo.td
|
| a8cca80d4ac9ad94223b31e1c2203a30825529ed |
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.
No functional change.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 63b46faeb8acae9b7e5f865b7417dc00b9b9dad3 |
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFrameLowering.cpp
RMInstrThumb.td
smParser/ARMAsmParser.cpp
humb1FrameLowering.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| ff97eb0cf4394090570feaa327d1237ba4b935e2 |
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrThumb.td
RMInstrThumb2.td
|
| 16f9924000a8d513353cd5c69d1d6307016fe280 |
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb2.td
|
| 4629d505011d6d88ce181985005761df0dd3cbef |
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the Thumb tPOP_RET instruction.
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
|
| dafc17e2c2a13697f7f80f5965104290e2912464 |
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Kill dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134131 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 41ca4b7b62fc40b3207eff0526171653605efa19 |
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Size reducing SP adjusting t2ADDri needs to check predication.
tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134130 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 4cc446bc400b2ff58af81c91f5e145b81d6beb26 |
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARMSubtarget feature parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134129 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
smParser/ARMAsmLexer.cpp
|
| f6fd90910a552ad9883f031350ae517e26dfdb44 |
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseRegisterInfo.cpp
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
humb2InstrInfo.cpp
humb2SizeReduction.cpp
|
| faff12731968c2d3f1ff56a43749d27e1696aafa |
30-Jun-2011 |
Cameron Zwarich <zwarich@apple.com> |
In the ARM global merging pass, allow extraneous alignment specifiers. This pass
already makes the assumption, which is correct on ARM, that a type's alignment is
less than its alloc size. This improves codegen with Clang (which inserts a lot of
extraneous alignment specifiers) and fixes <rdar://problem/9695089>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134106 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| fa6f5917af0ee34e6a8d6d6eaffe89024d5d7a04 |
29-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Remove getRegClassForInlineAsmConstraint from the ARM port.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134095 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 74472b4bf963c424da04f42dffdb94c85ef964bc |
29-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Refactor away tSpill and tRestore pseudos in ARM backend.
The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb.td
humb1FrameLowering.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
|
| ab8be96fd30ca9396e6b84fdddf1ac6208984cad |
29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFastISel.cpp
|
| 6844f7bcdec8c2691c8d1067d90e4a02cf658c27 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide more details in tablegen generated MCRegisterInfo ctor function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMBaseInstrInfo.cpp
RMInstrInfo.cpp
MakeLists.txt
isassembler/ARMDisassemblerCore.cpp
akefile
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMHazardRecognizer.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
RMMCCodeEmitter.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
LxExpansionPass.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
humb2SizeReduction.cpp
|
| 118c9a0c494c97fe23c43f3e2aca553aea3a4f16 |
28-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Remove warning: 'c0' may be used uninitialized in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134014 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| adf7366771ebc78b3eee3c86b95e255ff5726da7 |
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff
rdar://9672867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6b8f1e35eacba34a11e2a7d5f614efc47b43d2e3 |
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| df8fe9901df829a02d1257121f35a78a434aca0d |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Asm parsing of Thumb2 move immediate.
Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet)
encode the instruction properly, but this gets the parsing part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133945 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 15993f83a419950f06d2879d6701530ae6449317 |
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMLoadStoreOptimizer.cpp
LxExpansionPass.cpp
|
| d1f0bbee189ea7cd18d03c4f9f55d0a33b070814 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Add exception necessitated by 133938.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 660a9ec4aa08b42a1379e5caa3935d301b1e27b7 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly carry set/clear condition code aliases for 'hi/lo'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fbd01783a67dd2bedd8197308ef00d4ad767fcd3 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for ldmfd/stmfd mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0d06bb954881dc7ff0e2333d5a3e249b7bb304d0 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.
rdar://9683231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 0ff9220ccb6ef419ba4d3a4daf98f4658a9e5134 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
sub r2, r2, #6
sub r2, #6
rdar://9682597
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 |
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
MakeLists.txt
akefile
|
| ba8297ec08cdf7ae0c1e0c18ce07922e1f822643 |
25-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Refactor MachO relocation generaration into the Target directories.
Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachObjectWriter.cpp
|
| 8b45456700f1e156b0a14000124f274dfac86f14 |
24-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM movw/movt fixups need to mask the high bits.
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.
rdar://9635991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| ef01edf1e938ef89e598ec558c50ceb2681c5ac4 |
24-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
The Neon VCVT (between floating-point and fixed-point, Advanced SIMD)
instructions can be used to match combinations of multiply/divide and VCVT
(between floating-point and integer, Advanced SIMD). Basically the VCVT
immediate operand that specifies the number of fraction bits corresponds to a
floating-point multiply or divide by the corresponding power of 2.
For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a
combination of VMUL and VCVT (floating-point to integer) as follows:
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
vmul.f32 d16, d17, d16
vcvt.s32.f32 d16, d16
becomes:
vcvt.s32.f32 d16, d16, #3
Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a
combinations of VCVT (integer to floating-point) and VDIV as follows:
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
vcvt.f32.s32 d16, d16
vdiv.f32 d16, d17, d16
becomes:
vcvt.f32.s32 d16, d16, #3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d |
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
MakeLists.txt
akefile
|
| df214fa51715896d0cd5a407e8e4c57454619fc2 |
23-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetOptions.h dependency from ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133738 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMTargetMachine.cpp
|
| d095764b07f2e8f8c555ee2d4c3cdb8d42ad4a27 |
23-Jun-2011 |
Nowar Gu <nowar100@gmail.com> |
Fix source list of Android.mk.
ndroid.mk
|
| bb5c18c80e7ae4ce49eb9067b664f0559ec50965 |
23-Jun-2011 |
Nowar Gu <nowar100@gmail.com> |
Merge upstream to r133679 at Thu. 23th Jun 2011.
|
| d7d71a18597e7f3b88055e3f3dde09d8648233ee |
22-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Add missing header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133640 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 2fc689888623743502b62e979767dd5c71e692bb |
22-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Move ARMMachObjectWriter to its own file.
Just tidy up a bit. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133638 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmBackend.cpp
RMMachObjectWriter.cpp
MakeLists.txt
|
| 1312ca8be679b332bb712328085e50121d4b94ec |
22-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Handle the memory-ness of all U+ ARM constraints.
Noticed on inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133553 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 734f63bed974a0196e85b0f82c1b6b4e5b891192 |
21-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Reorg. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133533 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9568e5c3c3f1e25288d2ff375dba0fddbf161fd6 |
21-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Teach dag combine to match halfword byteswap patterns.
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
=> (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
=> (rotl (bswap x) 16)
This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.
rdar://9609108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 907af0f20f58f2ea26da7ea64e1f094cd6880db7 |
17-Jun-2011 |
Nowar Gu <nowar100@gmail.com> |
Merge upstream to r133240 at Fri. 17th Jun 2011.
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/Target/ARM/ARMCodeEmitter.cpp
|
| 1d4f9a57447faa0142a1d0301e5ce550cfe60c4f |
17-Jun-2011 |
Nowar Gu <nowar100@gmail.com> |
Suppress un-initialize warning.
We should do bitwise operation on un-initialized variable.
Maybe this stub lose some information, but I don't know.
Anyway, I clear it to 0.
RMCodeEmitter.cpp
|
| 1396c403897e3d3e04fbf59f6c5fe77cbbab74a6 |
18-Jun-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused but set variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133347 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0a074ed3ef7c87512d8562ff216e2ad4a29b6566 |
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARM to using AltOrders instead of MethodBodies.
This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:
Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After: %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133326 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 3b6434e360315849a65b1ac85e16d160131a77a4 |
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Reserve D16-D13 on subtargets that don't support them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133321 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6d6c55bc270d1bee8561d3ce00d2ca9ced3bb506 |
17-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 7982b43e731a17981eb2399bce20169933d52c3a |
17-Jun-2011 |
Shih-wei Liao <sliao@google.com> |
Optimizing away Binary &= ~(0x80000000 >> 12) and Binary |= (Imm & 0x80000000) >> 12
The key is that the classical JIT does: unsigned Binary = getBinaryCodeForInstr(MI);
As a result, it will get information from ARMInstrVFP.td. Because regardless of my
previous CLs I20394c2c and I9a8e7177, the old td and the new td will result in
the same immed{31}.
See Line 1080 of ARMInstrVFP.td: let Inst{19} = imm{31};
In short, we only need to fix the difference between old td and the new td.
Change-Id: I02695ece0f15e77f7bd712961db1a24bd3c487d7
RMCodeEmitter.cpp
|
| aa9bc19930f66ade30857fa50617f1e70952f8db |
17-Jun-2011 |
Shih-wei Liao <sliao@google.com> |
The reason for the Change is because LLVM upstream did this commit last year:
commit a4776de44edaa3c84035632c60247b97eab08ff2
Author: Bill Wendling <isanbard@gmail.com>
Date: Thu Oct 14 02:33:26 2010 +0000
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
Wendling's Change caused USE_OLD_JIT to break, so, when merging a while ago, we only
took part of commit a4776de. Now when we switch to USE_MCJIT, we have to take the
entirety of commit a4776de.
However, the entirety of a4776de implies that we have to fix ARMCodeEmitter.cpp here,
to make sure that classical JIT and MC JIT work at the same time.
This should have been done upstream, but LLVM upstream obviously deprecates
classical JIT (USE_OLD_JIT) during Q3 last year. But we are now just in the
process of switching to USE_MCJIT. Anyway, LLVM has the right to deprecate things
that are not ToT. When we stay close to ToT, we can avoid such mess next time.
Change-Id: I20394c2c6f2c3943b2afd64ca418891e9361ebe7
RMCodeEmitter.cpp
|
| cd4e0b593db6dfdb5cedbde47ea6603058b8ac6c |
17-Jun-2011 |
Cameron Zwarich <zwarich@apple.com> |
Update an insertion point iterator after replacing a return instruction with a
tail call pseudoinstruction. This fixes <rdar://problem/9624333>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133227 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| e1fd84af7affc08cda70a4c8261f52ac83195bc4 |
17-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Explicitly invoke ArrayRef constructor to keep gcc happy.
Patch by Richard Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133220 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| dd5a8471526ceadf9bceb1a1221299b3db49c33a |
17-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.
The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 1300f3019e5d590231bbc3d907626708515d3212 |
16-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c75448c74051200602a8006bab45d747e61a5c3c |
16-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Mark ldrexd/strexd w/ volatile memory by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133175 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 689edc8b2845f7a6cf9403722de2000598f68489 |
16-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Revision r128665 added an optimization to make use of NEON multiplier
accumulator forwarding. Specifically (from SVN log entry):
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f28987b76e758b5f2fcc2c5d2c8e073df54ca91e |
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| b460d4ba2d88c13480c2a6a8495de9d07a2c9f66 |
15-Jun-2011 |
Shih-wei Liao <sliao@google.com> |
Fix the wrong encoding of vmov.32's immed8 value in LLVM's ARMInstrVFP.td.
Taking Renderscript Balls as example,
fc: eeb00a03 vmov.f32 s0, #3
120: edd00a02 vldr s1, [r0, #8]
128: ee600a80 vmul.f32 s1, s1, s0
VFPexpand in ARM's hardware will expand #3 above to 0x4e180000. This corresponds
to floating point value of 2.375. However, in the original Balls code it is 6.0.
As a result, Balls got smaller recently.
Note that 6.0 in F32 is 0x40c00000 and 6.0 in F64 is 0x4018000000000000! This leads
to how I fixed the bug.
Change-Id: I9a8e71771884dc27d5b9392abe7dfa541b45f357
RMInstrVFP.td
|
| f60ceac9cd7230e0d5ff911fced396f6b5d8c815 |
15-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Another revsh pattern. rdar://9609059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 7a10ab7d6f50b59580cc8ab1eb52d562e81f28d8 |
15-Jun-2011 |
Bob Wilson <bob.wilson@apple.com> |
A minor simplification: no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133047 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bf188aeae7a579fb71480be7d32a2edc4d56d827 |
15-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
the bits being cleared by the AND are not demanded by the BFI.
The previous BFI dag combine rule was actually incorrect (or used to be
correct until BFI representation changed).
rdar://9609030
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 189531f317d0b3a082f78cc2da44128e4ff8e17d |
15-Jun-2011 |
Tanya Lattner <tonic@nondot.org> |
Add an optimization that looks for a specific pair-wise add pattern and generates a vpaddl instruction instead of scalarizing the add.
Includes a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a6eb2562b62fc293295f2fede2608753563e7005 |
14-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Also recognize ARM v4t and v5e variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133002 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 9a767330f555f21d6ef311d3a348d3a44f306d35 |
14-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| f921c0fe3418f96bd1e37beb582a368d3ac24295 |
14-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132946 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 7980f61f5ff408b947474cd1c3715896d28ea578 |
13-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix coordination for using R4 in Thumb1 as a scratch for SP restore.
The logic for reserving R4 for use as a scratch needs to match that for
actually using it. Also, it's not necessary for immediate <=508, so adjust
the value checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| a86686e643323762bf9383a0897a55257611aa74 |
10-Jun-2011 |
Cameron Zwarich <zwarich@apple.com> |
Provide an ARMCCState subclass of CCState so that ARM clients will always set
CallOrPrologue correctly and eliminate the existing setter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a2e979565b2704ccb76d8e8d384723702b770c53 |
10-Jun-2011 |
Cameron Zwarich <zwarich@apple.com> |
A CCState was being created without setting whether it is in the Call or Prologue state,
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.
This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 471e4224809f51652c71f319532697a879a75a0d |
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| a1099f184d5d3e88e12957f4ebe1fc4a985dd18d |
07-Jun-2011 |
Andrew Trick <atrick@apple.com> |
Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
rdar://problem/9556069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132699 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| cf714d44b89864cf92d9c73508154457d0c65d9c |
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Make the Uv constraint a memory operand. This doesn't solve the
addressing mode problem mentioned in r132559.
Backend part of rdar://9037836 and part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d6412c940ef863d02595f7be094d8cd3afc908a1 |
03-Jun-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
rdar://9431157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 4f3fb6d08be511a277f92279e803ae6e95b00126 |
03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Flag unallocatable register classes instead of giving them empty
allocation orders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 201cfcd6de70f45174567572028b6e53f7e7d92b |
02-Jun-2011 |
Tanya Lattner <tonic@nondot.org> |
Fix encoding for VEXTdf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132486 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| fa226bccaa90c520cac154df74069bbabb976eab |
02-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| cde4ce411b1ace4a80ea1dd38df97e8508aed0c9 |
02-Jun-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't hardcode the %reg format in the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 895c1e2deea3e6118b159c26b3f86d40a37e8501 |
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 6e032942cf58d1c41f88609a1cec74eb74940ecd |
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use the dwarf->llvm mapping to print register names in the cfi
directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 5f8fd54f0891aa47f467498454f6a3df8ae62704 |
29-May-2011 |
John McCall <rjmccall@apple.com> |
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7eebab2a82cf13d0166299c7eb4f6234e16c8a5d |
29-May-2011 |
John McCall <rjmccall@apple.com> |
I didn't mean to commit these residues of a personal project.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 832a9d1a76d30ffd295453e93e8eb52948e5813e |
29-May-2011 |
John McCall <rjmccall@apple.com> |
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c152aa6c86f87be6f3ca9b6e2d57ee31b9258385 |
28-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix ARM fast isel to correctly flag memory operands to stores. This fixes
-verify-machineinstrs failures on several tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132268 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a0112d0c39aa31fe555ecf7296923ca30f68f811 |
28-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| fea51fc007598176d48fb7319a9bf471efb93127 |
28-May-2011 |
Eric Christopher <echristo@apple.com> |
This actually starts at offset 0, not 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132246 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 3c14f24c9da3f811d3530e984e692acf1a471b91 |
28-May-2011 |
Eric Christopher <echristo@apple.com> |
Implement the 'M' output modifier for arm inline asm. This is fairly
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| de64aaf6c8ab3a170b2e5a5b0968595503b5aad4 |
28-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
and add some basic tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| be64b394317feb8d7bcb732bdfb35e0b286efd4c |
28-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5b23b7fe3150b2050d6fcd6981d64f30930fd3ef |
28-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make size computation less brittle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| 4abce0c90b0c7c7c859951069baf0c0a70e085a9 |
27-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a4d487fc1e2f95f4b47ad472071bfdd484eb3b40 |
27-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 33281b23616bea25decc838cb8707a2861f9d767 |
27-May-2011 |
Eric Christopher <echristo@apple.com> |
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
followed by a conditional and imm8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 86bbcbf4b046761ff5bed71ac530a899af331a04 |
27-May-2011 |
Eric Christopher <echristo@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132178 91177308-0d34-0410-b5e6-96231b3b80d8
RMFixupKinds.h
|
| 32bfb2c513c4efdc1db9967ddfecce8c922dda4f |
26-May-2011 |
Eric Christopher <echristo@apple.com> |
Reorganize these slightly according to operand type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 421b106872d9c8adb4f14d77a8c6a1afeaaa29f6 |
26-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Mark tBX as an indirect branch rather than a return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
|
| 76927d7303046058c627691bd45d6bff608f49f4 |
26-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ad70f6d2b1eacdc2c85e7cfec24e4c470325ef4e |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
|
| 7bb1c4054986e51682ff89170c740cc16b921236 |
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Clean up comment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132083 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 8f8946389418ce3cdbf69bbf34443efe0c874b40 |
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Implement the 'm' modifier. Note that it only works for memory operands.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 783c66414ae54ddc9879843b4bc878dc66a70478 |
25-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132073 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| da86a0828495948efd509262167a7f390cda3216 |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Restore an accidentally removed comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132044 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 8e9bace414b9c6bc853849fe767637bf8b8a4c97 |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move some code to a more logical place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132043 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 106acd4158768ff1948accc654a1892caa9e010b |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
fixes <rdar://problem/9495913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 328634598fb8dbb774709aebc61a97d63f7027b3 |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Change the order of tBX's operands so that the predicate operands come after the
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| 8f161c3a95d844746be41332c763fb308aae3c9c |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Rename tBX_Rm to tBX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| b36c1ae6d504168b496ac11031da4bdac0024f80 |
25-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
reflect their actual meaning and match the ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132039 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
|
| 56926a39619bd644c83c4128f0b55189e52707d7 |
25-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR9762
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4db7dec70b06a1d50a265c3666e126065e09f396 |
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Implement the arm 'L' asm modifier.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| e1739d598d2c980822cc42bbf9821b91ebbc829f |
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Implement the immediate part of the 'B' modifier.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| fef50062eae28fc6d893cd3ef528f8ca85cd50b0 |
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Add more unimplemented asm modifiers and some documentation of what they
do.
Part of rdar://9119939.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132015 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0628d38085b28a59a4b13d7e35760cce54f0af7a |
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the arm 'y' asm modifier.
Fixes part of rdar://9444657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d34d429401187f4251c38323a1bc517bc96763b9 |
23-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 1ec11fb8b502971071a57b8b2de129f86bd41de0 |
22-May-2011 |
Renato Golin <renato.golin@arm.com> |
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
|
| 75f4296c7c96499f4d8cdf90d5159f7965f94fd8 |
22-May-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
|
| b8adb8af0fa9d1405fcf2edb95f4b1b8d1904716 |
20-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
adds some attributes to attribute section when cpu is "xscale"
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 298c8e12ea063f7522c59d2a297b47a879b6ed55 |
20-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
fixes target address tBL and tBLX and sets relocation type
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 0b65599015f0b51304d941ba4a14aaf0d1734341 |
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 2e6496026f41d2c05ff038d14df9972f8a27fb94 |
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert r131664 and fix it in instcombine instead. rdar://9467055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 861b9c6a397f2ed4b5601cacbc9121d0b07d1f65 |
19-May-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
This fixes one divergence between LLVM and binutils for ARM in the
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 6635b04a4357caf6544cd0a7dbc4c107e7907a88 |
19-May-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 28e2b1d29ad409479f0c6a3aa3f663c847b5994a |
19-May-2011 |
Mon P Wang <wangmp@apple.com> |
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 462b6dc6bfd95b82eb8a0d2bd8f15a76e7b15957 |
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Reuse the TargetInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 21803721d538255e4d223c29b6c8d3c9e93d4d86 |
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Correctly constrain a register class when computing frame offsets, as the Thumb2
add instruction takes an rGPR. This fixes the last of PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| db28247522af0a6190c9cab8dc32e7d4df9f5509 |
18-May-2011 |
Tanya Lattner <tonic@nondot.org> |
Handle perfect shuffle case that generates a vrev for vectors of floats.
Add test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 955db42568ae61c9f381a5af3e354d4270d06d92 |
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| a96581f4f70fa305e4d0726f20b0ec687fca7b7c |
18-May-2011 |
Johnny Chen <johnny.chen@apple.com> |
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| b936e3006f04f60aca4c4de4a3604ec141ab0a45 |
18-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d48fda46f5b65f87e92a2bb94a722417bd5cc758 |
18-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2a8eb722c7bb0fac2fe09a876f3471dcb25f465e |
18-May-2011 |
Tanya Lattner <tonic@nondot.org> |
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMPerfectShuffle.h
|
| 141ec63962b6fca66ab0007ffc6e50de46a22b6f |
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7d336c0c68f00f18c214fe5e689628f099a0f6d7 |
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
compare-and-swap intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d6ffcd88baa95988c0158151ec1d188a8442bff9 |
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
take r13, so we can just make it a GPR. This fixes PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3c60ff4f3da9671597ed8fadd775255902616b71 |
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
were marked as taking a tGPR when in reality they take an rGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c81c9709ef219809b0d04c55a80a8d18c7194f6a |
17-May-2011 |
Tanya Lattner <tonic@nondot.org> |
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
RMPerfectShuffle.h
|
| 0c720761903394c4dd232b9fe49da7d5fb40172b |
17-May-2011 |
Jim Grosbach <grosbach@apple.com> |
Kill some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131431 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6469540adf63d94a876c2b623cb4ca70479647f7 |
16-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
sets bit 0 of the function address of thumb function in .symtab
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smParser/ARMAsmParser.cpp
|
| 18901d63bf0deb117bd7a1ad69b25faa422ce378 |
11-May-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 61512ba251097888963a8f07a35605564bcfc537 |
11-May-2011 |
Bill Wendling <isanbard@gmail.com> |
Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| f4351ceb93e472e82e99d67d3e05405f3a3698fb |
10-May-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
First cut at getting debugging support for ARM/MC/ELF/.o
DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131137 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 183c627d89be5d0e8f3255ab7f6d1204c2fabedf |
09-May-2011 |
Mon P Wang <wangmp@apple.com> |
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| ca66226e7e8368719f5b9937ed6523c7117a9d63 |
07-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Eliminate the ARM sub-register indexes that are not needed by the sources.
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131059 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 33c110e602bbdfee23cfb58fddef246a262647ab |
07-May-2011 |
Eric Christopher <echristo@apple.com> |
Fix the non-MC encoding of pkhbt and pkhtb.
Patch by Stephen Hines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| f2b04232006142eb7933972fb21d9ffb9b8c2646 |
06-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Dead code elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130984 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 64915dec2802714f80751291d9e8c86af5e65cc5 |
04-May-2011 |
Devang Patel <dpatel@apple.com> |
Do not emit location expression size twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2944b4fe059b727b1cbd2b85013610de137fac02 |
04-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| e1a56ae7478c7495a753229f4bbe27eb9a44442c |
03-May-2011 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily disable use of divmod compiler-rt functions for iOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0a69ba309f5a30d2dcfa1814eb50635539523304 |
03-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
it's possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 54ad87ab786cae4e5b654f4295e9697f0c72dbb1 |
03-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a few ARM coprocessor intrinsics. Testcases included
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| cca82149adef8306a295abdc963213ae3b11bbb6 |
03-May-2011 |
Dan Gohman <gohman@apple.com> |
Add an unfolded offset field to LSR's Formula record. This is used to
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 52f6c03a450aeed93b97cad9e5373029ebcad5e7 |
02-May-2011 |
Eric Christopher <echristo@apple.com> |
Apparently the check for direct calls is unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130716 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3983d243ad2386d7c2c835c798db141b176ef4e7 |
30-Apr-2011 |
Stephen Hines <srhines@google.com> |
Fix PKH encoding issue (predicate bits matter).
Change-Id: Ic4a982c49a8232f5a0942c185a21834966682cf4
RMCodeEmitter.cpp
|
| 5ac179ccd2a03996f7b5ae7f12b5f45b8d38d832 |
30-Apr-2011 |
Eric Christopher <echristo@apple.com> |
80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b451770b264f9ef58d9565fdcd13551a89606cd4 |
30-Apr-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Zap a couple now-unused functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130557 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c573e2c7ea646d29162a96a0707f4eb0f77f83bc |
30-Apr-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| d94bc549fcc34f1d97d27221ce5bbf46df207557 |
30-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but
if it ever did it needs the def machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130549 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 632ae892e6517e27791ac9e51188ca697ccc6515 |
29-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Some cleanup and optimize fallthrough more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130546 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9ebf57ae132369248c885a90bc3dd5e3cf589247 |
29-Apr-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Re-committing r130454, which does not in fact break anything.
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130539 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bcf26aee86b1ab15b3e1442483eaa7be9fa00a82 |
29-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Add trunc->branch support, this won't help with clang's i8->i1 truncations
for bools, but is a start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130534 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0eab5c4d85b4c4bb161bcdd959aa58a6f54415cc |
29-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics
that associate sections with expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130517 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCExpr.h
|
| d49ffe8284457953db68db063b527ee9c346b67a |
29-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Teach Thumb2 isel to fold and->rotr ==> ROR.
Generalization of Nate Begeman's patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d7d030a44796adc73a6eaa939cd17e52047734c1 |
29-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMLoadStoreOptimizer.cpp
humb2SizeReduction.cpp
|
| 6344a5f1464dade7735ac440d7a3d24bf009f298 |
29-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Update comments and checks to match reality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130464 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 299bbb23a421fce79c63e9f879ff3baef18c2f90 |
29-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130463 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6e6014cfb3e4dea3b0bd59bcc49ba8cd8dfcfa96 |
29-Apr-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Revert r130454; apparently this doesn't actually work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130462 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2f7fcd71982678879803b96574526f0a22b3918e |
29-Apr-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130454 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7a20a37bacfb2abc0622768fb9d25797518b1f0e |
28-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Be more layout aware here and swap the successor and branch condition
if it means we get a fallthrough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130404 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8f232d307ace42180961856f69541b95b3278295 |
28-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Let the immediate leaf pattern take transforms and switch the signed
immediate patterns in arm to using the pattern.
Handles rdar://9299434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| c26f5447e39b43a6dd9c1a9d88227f4adf3b5600 |
28-Apr-2011 |
Devang Patel <dpatel@apple.com> |
Teach dwarf writer to handle complex address expression for .debug_loc entries.
This fixes clang generated blocks' variables' debug info.
Radar 9279956.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| e23aea28f9ed4c1bb7dc81c92786ca49aa887088 |
27-Apr-2011 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the case that there is no add or subtract symbol and the offset
value is zero so it does not add a NULL expr operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130330 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0be77dff1147488814b8eea6ec8619f56e3d9f5e |
27-Apr-2011 |
Devang Patel <dpatel@apple.com> |
Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130326 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| 2b6760592d73723bd82eb7b33b58b7c65549b0b2 |
27-Apr-2011 |
Shih-wei Liao <sliao@google.com> |
Merge with upstream.
Here, use upstream first. Then, I will submit to upstream separately and then bring it back
to external/llvm.
Change-Id: I6d86ca1277abb681af5dce6cd03379150c98c961
RMCodeEmitter.cpp
|
| f7da8821b4c491b1c2ce7ac2374e46d8abdba518 |
26-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads.
rdar://9326019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| c9e5015dece0a1a73bec358e11bc87594831279d |
26-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.
The hook will be used by the register allocator when recomputing register
classes after removing constraints.
Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 0c99861836741911300587c579d4f9d3fe1d2a39 |
26-Apr-2011 |
Devang Patel <dpatel@apple.com> |
Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130178 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| dac4b9267bc4e61de9237c622cd5b145768302fc |
24-Apr-2011 |
Sebastian Redl <sebastian.redl@getdesigned.at> |
Fix Target/ARM/Thumb1FrameLowering.h header guard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130097 91177308-0d34-0410-b5e6-96231b3b80d8
humb1FrameLowering.h
|
| 1c3af779fc6b184204efd7e98dc16e475c251e7f |
23-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.
Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.
Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 5adfba283dc0795ba005545ce38fa5b0ada14511 |
23-Apr-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130046 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 597fa65373b824c840212cf238a73ae13dc35494 |
22-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.
rdar://problem/9267772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0a6ea83f393d06fb424c470777a1c3e8a8c50ab1 |
22-Apr-2011 |
Devang Patel <dpatel@apple.com> |
Add asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| db6cbe1ff16d5f18bf2469fa53744e680944dc56 |
22-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
In Thumb2 mode, lower frame indix references to:
add <rd>, sp, #<imm8>
ldr <rd>, [sp, #<imm8>]
When the offset from sp is multiple of 4 and in range of 0-1020.
This saves code size by utilizing 16-bit instructions.
rdar://9321541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129971 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMFrameLowering.h
|
| 71f3f1146f2ba2773f0467767b67c12258960f34 |
22-Apr-2011 |
Devang Patel <dpatel@apple.com> |
Fix DWARF description of Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129952 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 27f5acb7d49c3ca2e3f7fe13d97cc19a78b15e1a |
22-Apr-2011 |
Devang Patel <dpatel@apple.com> |
Fix DWARF description of S registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129947 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
|
| 64d3d12f372fe88cbff7bbac63ea148df678d9b6 |
21-Apr-2011 |
Devang Patel <dpatel@apple.com> |
As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129922 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| c8578948c9b35080dedd6527abf4f48fc4de43d3 |
21-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove -use-divmod-libcall. Let targets opt in when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.h
|
| 6bfba2e5af163442a1c6b11fe14aa9df9101cfd7 |
20-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.
Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.
Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| e341e8ce1ada854e7f8fcfcf18bb2e17be2ac0ee |
20-Apr-2011 |
Stuart Hastings <stuart@apple.com> |
Excise unintended hunk in 129858. <rdar://problem/7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c73158730d43e7c8bdef32b2107566a6e78a8538 |
20-Apr-2011 |
Stuart Hastings <stuart@apple.com> |
ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| f55066572ff8040747ff03a7fa71d88b85f41812 |
20-Apr-2011 |
Shih-wei Liao <sliao@google.com> |
Fix PKH* encoding.
Change-Id: Ib231fccf2bf51acf9bd283573a4ee55ae33e75b3
RMCodeEmitter.cpp
RMInstrInfo.td
|
| 4aaf3465f71afa4e156eb15df12095ebde1b0f6f |
20-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix typo in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129837 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 912225e18559a73228099330a4c253fdccf9fa3d |
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 2cc40138537abc39c360f0c83a7c78014b9b9ba1 |
19-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Remove some duplicate op action entries and reorganize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 84c5eed15baa3710d7fb8522c7a28c8e0b732c2b |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
This patch combines several changes from Evan Cheng for rdar://8659675.
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Enable these fp vmlx codegen changes for Cortex-A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129775 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMHazardRecognizer.cpp
RMISelDAGToDAG.cpp
RMTargetMachine.cpp
LxExpansionPass.cpp
|
| cd70496ad1e69656a0b3d2caada4ed1b2c543d7a |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 5dde893c2bac9e1569c38429f756c1d723e8edf2 |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
humb2SizeReduction.cpp
|
| f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| b34d837397053da8e9bff90dd714e24f2a3b98b3 |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Some single-precision VFP instructions can execute in either the VPF or Neon
pipelines, at least on Cortex-A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129771 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 11334dbd66581afb66bf17d07d970ca41265855e |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Improvements for the Cortex-A9 scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129770 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 75b41f1540f35ef0fd5e4a52c1840f1a19debb03 |
19-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMScheduleA9.td
|
| b58a340fa2affa0da27a46c94dd49ba079c9343c |
19-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not lose mem_operands while lowering VLD / VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
|
| 0d062c1e14af5653bb6a4719b06f168e2dc0f5db |
18-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
Trim a few unneeded includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129723 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| f6d9109124fa9ee5533dcc5a1c9f2af694890706 |
18-Apr-2011 |
Sean Callanan <scallanan@apple.com> |
Small fix to the ARM AsmParser to ensure that a
superclass variable is instantiated properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129713 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c5eecbc4ec3e8b6934b2c932735c8ebc1b78f537 |
16-Apr-2011 |
Stuart Hastings <stuart@apple.com> |
Correct result when a branch condition is live across a block
boundary. <rdar://problem/8933028>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129634 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3a96122c4ae4e7727ba976a9f658626c18997689 |
16-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb2 BFC was insufficiently encoded.
rdar://problem/9292717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| a704bc9354d8b03fd98da9bd7de5ae1dc49af961 |
16-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.315 VLD3 (single 3-element structure to all lanes)
The a bit must be encoded as 0.
rdar://problem/9292625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0cb11ac32fc09c5db42fb801db242ac9fb51f6b1 |
15-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
a case involving EOR, so I only added a test for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b485de5d8c3fe0c62c0b07f63f64bd10f6803c17 |
15-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
The AND instruction leaves the V flag unmodified, so it falls victim to the same
problem as all of the other instructions we fold with CMPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129602 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41f |
15-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add missing register forms of instructions to the ARM CMP-folding code. This
fixes <rdar://problem/9287901>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
RMSelectionDAGInfo.cpp
|
| 9eec66e604f09ed9779bc438d0dc4fa9d24db44c |
15-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
forget to right shift the source by 32 first. rdar://9287902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 188ce9c78bdd817f5aa84eff6f1929387ca329e6 |
15-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
For t2BFI, both Inst{26} and Inst{5} "should" be 0.
Ref: I.1 Instruction encoding diagrams and pseudocode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129552 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| de29a52940101cd162cc9a53cfd3d09d60547e6f |
15-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
(single element or n-element structure to all lanes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 06b2a60ef9a740b76d482347d615fdc11eb64548 |
15-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| cd695fdac16c206655a19fb1741ab71929f28711 |
14-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| e8d087ad351258f3db39f41dc595fae4ddb4f318 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb disassembler did not handle tBRIND (indirect branch) properly.
rdar://problem/9280370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 6c7e4147dc7faf2f7b4bdaaf7940c2fe65d6fbc5 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
rdar://problem/9280470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 471d73d5d387d52dc854145caca971dfd9fd506a |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
rdar://problem/9279440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| 5af60ce2a8d4dc820664c9dc5fbbcff428402c15 |
13-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9bb386a9330f9c26f648ce1009561833fbc59e4b |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
rdar://problem/9276651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 119af20c7b9d6aaae6941d5fc88392efe92eb9f1 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
rdar://problem/9276427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 6e3ccc3c85b960afd843288b701d08756add8e79 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129451 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5 |
13-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129429 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 55e6419b12a5f5c1c5b7e3f5f6bebd6b71df0bd0 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
rdar://problem/9273947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 836a7de15907e0368f7785684f156764ea6b7069 |
13-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add @earlyclobber constraints to the writeback register of all ARM store instructions.
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129409 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| ec51a6225c59fee9021b8b6c7c813228cb27a3fa |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The Thumb2 RFE instructions need to have their second halfword fully specified.
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| 32cefad4b39e28674805c4704bc8c4c3ca70134a |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add bad register checks for Thumb2 Ld/St instructions.
rdar://problem/9269047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| f9ce2cba42f76ad82bbb17436902f66a9e5f6367 |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| 49fdfe3ce5736e8c76cdf512cc0cd5afb3b8f2e6 |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.h
isassembler/ThumbDisassemblerCore.h
|
| d0aacbcc2e60fd06652280a9105eb2f8f9378efc |
12-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e77f72d7d236cabee6ce154ade0f5c666ecaaaca |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.16 B
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| de16508955698a0f8890e0d54fee24efc9277ecd |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb disassembler was erroneously rejecting "blx sp" instruction.
rdar://problem/9267838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
isassembler/ThumbDisassemblerCore.h
|
| 35563fee7b52f3bc9ef828abc139e8d9cb4ba2b9 |
11-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
rdar://problem/9266265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 78a546936d585a74c9c0a73ae44b4e5a5688792d |
11-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129294 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f18dfc3a318b6dae66f3439555f6d32900654425 |
11-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Trivial comment fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129288 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| e679d3331b5fb4747c5f03b546376f8fdb6a25d4 |
11-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
invalid instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| bd3327654b5708f1ba92aff3ab25b1bbf5034797 |
11-Apr-2011 |
Kevin Enderby <enderby@apple.com> |
Adding support for printing operands symbolically to llvm's public 'C'
disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/ThumbDisassemblerCore.h
|
| 562b84b3aea359d1f918184e355da82bf05eb290 |
11-Apr-2011 |
Jay Foad <jay.foad@gmail.com> |
Don't include Operator.h from InstrTypes.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129271 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3a5b41d8f8aae9ca8c9ebf95f49de1c46224ec0a |
09-Apr-2011 |
Jush Lu <jush.msn@gmail.com> |
Fix ARM 'B' instruction encoding for ARM JIT
RMCodeEmitter.cpp
|
| eeb84081f389b99547082b9867830ad4c46cb39a |
09-Apr-2011 |
Jush Lu <jush.msn@gmail.com> |
Fix LDMIA_RET encoding for ARM JIT.
RMCodeEmitter.cpp
|
| 8feda7ee332f1f91e4d3a42d9f7ad729012ed174 |
09-Apr-2011 |
Jush Lu <jush.msn@gmail.com> |
Merge upstream r129128
|
| 7c90e4662205c14da6a340501316b3059f7fd871 |
08-Apr-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Fix an apparent typo that made GCC complain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129160 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 4da0c7c0c9081107bea5f6bac440f0f1eb47748f |
08-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ee10b13a4408781fd5f255527e3c51cd24dc96ef |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check opcoe (dmb, dsb) instead of bitfields matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129148 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| c636074afcf95ecd9bb4069a49087a019d5e96b4 |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
PR9650
rdar://problem/9257565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 40de2b3f1529c23fee5de6e8324a1f023b361765 |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Sanity check the option operand for DMB/DSB.
PR9648
rdar://problem/9257634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 5b03a3a59aad2beca37829e4d357db592d18de6e |
08-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
Mark hasExtraDefRegAllocReq=1 on LDRD.
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.
rdar://9244161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129144 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 97fdff1d3f0d931247aa300a02679681d684b87d |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
Add more test cases to exercise the logical branches related to the above change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 274d8d4eba8224b64e0bbc7196011ae7e0477453 |
07-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e32cdef38e8a95dcc3685a1dc4ea6a4fba293f82 |
07-Apr-2011 |
Mon P Wang <wangmp@apple.com> |
Fixed encoding for VEXTqf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129101 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 22dc4d9f59213c51cefe4fe237030c91d92d388b |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
Add some test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 8dbda0b51b7a7a7b4fb16a34b421a658cb86f9f3 |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checking for invalid register encodings for saturating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 4d4e25740bd1225f413a10db6166b620d2f5fbbb |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add some more comments about checkings of invalid register numbers.
And two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0433b21c989e7d4817574b950387355fe05f59b5 |
07-Apr-2011 |
Tanya Lattner <tonic@nondot.org> |
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f16f4e09ec28fe2de13a1bcda391d7d16a368e3a |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Sanity check MSRi for invalid mask values and reject it as invalid.
rdar://problem/9246844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 8424a60fc9059d4ba7c45c80d28d86e3186fcf4e |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 2c69f8eec6a51114799e3e80fa4903c5e3fc429c |
07-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change -arm-divmod-libcall to a target neutral option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2455268cddf6d5507ab21b59007194e92b0b9af7 |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Should also check SMLAD for invalid register values.
rdar://problem/9246650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| df298c9ea64eb335f63fc075d8ef6306682ffe75 |
07-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ef7fb17936ef38153e0a8c8146229d618722eb15 |
07-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Cleanups from Jim: remove redundant constraints and a dead FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129036 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f22eefba68d7d128b2de26684df2d5debdf2005d |
07-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129034 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| d8b4c4d74f745e6d556e96e056fe774c7cbef697 |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.393
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 4d81c9a6ba076e86671eebb9a0c533a45f357d2d |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| a9611549fe5cd06000111851f88b951467695307 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 6a1220eeca1f3511bcf6ffed43a9ae77624eb8a8 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| b48c791515659c7572dea7e1d53059f58fb3121f |
06-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| 2c868d1eef1e52a2b3211050006344e00c461ac3 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 61f3cf3bc9c4db657eda5a4b9f4f8079e65aba8f |
06-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some code for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128953 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 493cba1b32ebd4064e56a2387099b790c8c32c0c |
06-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Revert r128946 while I figure out why it broke the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| c3281c10c94185e18338764b225a730a7c3e3ec4 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A7.3 register encoding
Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 76634dfabb02507b73c0baed6fdd98bd5e703c60 |
06-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Give RSBS and RSCS the pseudo treatment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| 5438d76416bdb074bd3135a7649b31c563a05dd9 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.
rdar://problem/9237734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| c584e317e9d5795129e747c9b0854165e39933f1 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 76706013131247121a3a153f378946a0cb0e319c |
05-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMInstrInfo.td
|
| 2c2130bc64d9a20b8a2681f230b2c03bd18a8c9b |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| bbc65bbb90e38a4066f0d4f5b403f85c1fecdf13 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 215e4fdbf9da460cb5e2d42a8df96530534ec382 |
05-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
Make second source operand of LDRD pre/post explicit.
Finish what r128736 started.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
|
| 12bb2958c4f335e79c831136d2dfed9f375f06ff |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| b26d8d7c493ec773661c1d3a7863f798f3786e40 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check for invalid register encodings for UMAAL and friends where:
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 15b81b51d64b04c71aa75788fcc418f52ec8b181 |
05-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| f05b1dcf870346094f8aaee8e387c92d3e47e98d |
05-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
Revamp the SjLj "dispatch setup" intrinsic.
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| 0435661582c5ccbd3984a710850fc8bc8939e566 |
05-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Just use BL all the time. It's safer that way.
Fixes rdar://9184526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128869 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 157536b1fb900e57efe042d48c7caeb87b1efd04 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 597028cc2840d9182523bd0179a1f95ddd931dae |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.105 MUL
Inst{15-12} should be specified as 0b0000.
rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 670a456c8323fc5da4752bdcf2b416ebef1bc66c |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
RFE encoding should also specify the "should be" encoding bits.
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 2d66cec9dd54b62c8b1e9b171e87fd17d419b13d |
04-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix incorrect alignment for NEON VST2b32_UPD.
rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| ac79e4c82f201c30a06c2cd05baebd20f5b49888 |
04-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 4071a711126a2a75585a32b96bb5d15ea267a915 |
02-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 04187ecd57c6ce2550fbcea43966c5cff234b39a |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 103bf951a4d221a9cff4a5a4766754cf0cb126f4 |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
rdar://problem/9224276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6da3fe68c6e3f5abd520a1bfc8dd8429e6ec6389 |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
rdar://problem/9224120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 857b1939dabefe931e1fd25b20185153ea389587 |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0539c159fb6e3f8d09d4790d8d6a4615c26d3e98 |
02-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1721324d97e2b05c9276ffe116dfb6c808521c2b |
01-Apr-2011 |
Owen Anderson <resistor@mac.com> |
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128739 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 9a3507f0913036615013d0218362d76cbe053b57 |
01-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ec30f6f5e5e53f384f3cbdade08ba654ef3680c7 |
01-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 5307da994aee85c22af26437d45254228898db2d |
01-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
rdar://problem/9219356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0e3ee43ea058a35ab5ce69cceafd316d49eaad34 |
01-Apr-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Initialize HasVMLxForwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 8e23e815ad1136721acdfcce76975a37c8a2c036 |
01-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
rdar://8911343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e3662cca5d204a3e0bceaead1b35361117630fab |
01-Apr-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ae0855401b8c80f96904b6808b0bc4c89216aecd |
01-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInfo.h
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 1db952d0c6c93f24619af5de2ea1b0550665479c |
01-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Provide a legal pointer register class when targeting thumb1.
The LocalStackSlotAllocation pass was creating illegal registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 463d358f1dfdd28a6900f2f109a160be71d2a8ef |
31-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMSubtarget.h
|
| a52d7da1d8c424276f79b80c89ed045166083730 |
31-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix single word and unsigned byte data transfer instruction encodings so that
Inst{4} = 0.
rdar://problem/9213022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8901e6ff3da1c1a68ee5c1c24f21e8572ceb57b6 |
31-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add BLXi to the instruction table for disassembly purpose.
A8.6.23 BLX (immediate)
rdar://problem/9212921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
|
| b41aaab5a1769f4df04d566da37866ac91b6ee9e |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r128632 again, until I figure out what break the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInfo.h
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| bcd3a9cd84d3bb143075d31bdf631f621f44f9e7 |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInfo.h
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| e4345c9977e65b14fa4b93d19c7e67a7b15f7f40 |
31-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 6a7d36a32026aa366d41c457898bd2d7a539f06c |
31-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128587 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| ee2e0e347e253d103ebbb0c59fcb48ca2d80b7ef |
31-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't try to create zero-sized stack objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 40829ed6f5e449fa33a9cd7022ce6c3941dace3d |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| c0e6d780cd7a0935f545a0ec0a9ad4a6ae8db2a9 |
31-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
can be recognized. This fixes <rdar://problem/9183078>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 92e3916c3b750f7eb4f41e14e401434b713e558b |
30-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.
Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.
First part of rdar://8832507, rdar://9203134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3007d3331b30dcb575125b81543cd145448dd673 |
29-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes
<rdar://problem/8875309> and <rdar://problem/9057191>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d0cfc99b308a805ffc130cde7317a0b0c626348f |
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128481 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 9eda569a74377bdcf8ce6073682fb9a4bd8a82ca |
29-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.188 STC, STC2
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9eae80051b6f6f5564b725221b2163a1f0d83672 |
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Add safety check that didn't show up in testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128467 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 848b0c39b11801614c47e460248b60e8d40eb257 |
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrNEON.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 78fe9ababead2168f7196c6a47402cf499a0aaf7 |
29-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128444 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d560a809251e54d7802728b9128dfd3b46f29b81 |
28-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| eca915fb5242442756a80bad7f285cb54d7b8ea4 |
26-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed the t2PLD and friends disassembly and add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ThumbDisassemblerCore.h
|
| 29aeed1bf8c70eec381d5cbf7de2710b5157d526 |
26-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Fix the bfi handling for or (and a mask) (and b mask). We need the two
masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1, #1
not #0, however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128320 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a2755b9829affb1c2ac07d7710228e80d222f588 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
Also add some test cases.
rdar://problem/9189829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| abeea57639b38b1c3c129a023aecb57eed61355e |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
rdar://problem/9182892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| ceceabd4b1e90bbddfa49799f1b3a4595dd6d99c |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
t2LDREX/t2STREX instructions. Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 6c3891067b6e2e2aa399a57ecae407677f22391d |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
rdar://problem/9184053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| f14d5cf33a0414637a874ef9a4cbc8e0cf1debee |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Also need to handle invalid imod values for CPS2p.
rdar://problem/9186136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| eb5067e0d9ca182f21db24949b63616ce4bb1eaf |
25-Mar-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Ignore special ARM allocation hints for unexpected register classes.
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a7078c4f274e2c2ad431ae9f578624335c81be36 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 1866af4a982be999e4d0c08c38ebec71f3ed4025 |
24-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Suppress an unused variable warning in -asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c39b6271be255a88fc9481d10894899b0f747ee3 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Handle the added VBICiv*i* NEON instructions, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 8cb988686d4d55eace0cb4aac408d790c02a120b |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 9091bf25d97b8b43bd26ea03976d1f320c770a92 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
T2 Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 83ccbff84fd38d8680ae39b3b629aee339478855 |
24-Mar-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Plug a leak in the arm disassembler and put the tests back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| e6d69e7dbee88a0a88f252a3e1e3f5f81472cf4b |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b4ac342ea0a416f463f47bf40c0bd7448844e00b |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| ce1868b21ce91245622964da1408cdec76af77a8 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| d700617193f3d11deb83cd56c4ababbc8e0ea19f |
24-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e4000595fbaf018ce2922294dfb9a1c28532dab0 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128192 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 3d793962becf3a345cfff96202f3c6c27a1fb5d4 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 571f290376ad7b84aac6e58dcecd19d9797a3892 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
We now tag them as IndexModePost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2abc9d2444c81bb5ac5aba0da0c863ec80d8f4b6 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The r128103 fix to cope with the removal of addressing modes from the MC instructions
were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 36dca60f5cfb9c858f3e962221ee5f2fa41794e8 |
24-Mar-2011 |
Devang Patel <dpatel@apple.com> |
Enable GlobalMerge on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128183 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 2c339156289d8398bea09c2bb4b735d00d39bdb3 |
23-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Cmp peephole optimization isn't always safe for signed arithmetics.
int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.
rdar://9172742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128179 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 741ad15e26d1717433f326743800f30c63c6a9c1 |
23-Mar-2011 |
Owen Anderson <resistor@mac.com> |
The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
This fixes 464.h264ref with the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128172 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| c59c87c3228b471140fb219dc9118ab9321486f2 |
23-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128122 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 27c6baeca23be295d13da6a010d203b280058444 |
22-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 758df297412df99d737dfcaea09b5e7857f320e5 |
22-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.399 VSTM:
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 7244d7cbcea232049f2676e4d204dddf6520821f |
22-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Migrate the fix in r128041 to ARM's fastisel support as well.
Fixes rdar://9169640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128100 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 026a42b170c7724dceec87b1c570360cde68deda |
22-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change MRC and MRC2 instructions to model the output register properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| ddb657c63dd0865c13cf677484b59fc5f9758d1b |
22-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Avoid -Wunused-variable in -asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| a5c177e70a42f48e4885075c4c48aad0816a2817 |
21-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.
This is part of a work-in-progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 485fafc8406db8552ba5e3ff871a6ee32694ad90 |
21-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 7a90e04fc76392972bd8bd0ddee5c934c22c1393 |
19-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ae16d6b9722dd6ff4a606308e3a14d200f3a903f |
19-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 94dad03a9626511cf16edc90284e873b696c8db2 |
19-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0082830cb26248178fe5cc9bbdbd00881556c33d |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 3f30af3f4563fc6987d123a024f05b3e7769d9a1 |
18-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Match a few more obvious patterns to revsh. rdar://9147637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 19f6f503d6638ab811f0da1b09db584e62a2b435 |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Clean whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127900 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 099e5553ebb868c06379ef05e56aae2346eaaa38 |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Reduce code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127899 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c9bd496aa206746d0bc114d15781650a5b543296 |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 PC-relative loads require a fixup rather than just an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5e5a40867a1adce1178ed226b77b0a1b0cb6a5c0 |
18-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
Remove the offending logic and update the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 670350bb782f6268126f7f8afefe86ab05b5b23d |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
There are two pseudos in this case that are Thumb mode, not one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127840 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| e68d8ec25296574109b586359d37318c725442ac |
17-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
It used to be that t_addrmode_s4 was used for both:
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| e27fa74d5f0f772e61b821dee45007f0b79899c1 |
17-Mar-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add "swi" which is an obsolete mnemonic for "svc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127788 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 276f6f9cf978fa7074687eead10a6db96c5afa6d |
15-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
There were two issues fixed:
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0d4c9d94f68fc561ebb11709ed99367e490af003 |
15-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
The VTBL (and VTBX) instructions are rather permissive concerning the masks they
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127700 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a24cb40be24e854faa8fb2c2148422a19c4a0ea5 |
15-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Some minor cleanups based on feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 019195229693c1829e6ed5a3f57209728fdcba8f |
15-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127683 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 085ea1b6337ff524edcff3368ee15b5acf9f5e53 |
15-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 5edf24efac40062766c643e08f11bc509d373370 |
15-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127637 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFrameLowering.cpp
RMInstrInfo.td
|
| 69a05a7b9205fd4628ed614d1845f3879f6be949 |
15-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Generate a VTBL instruction instead of a series of loads and stores when we
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| e2189144d45be78a89f0daf3df3cf12e38221d86 |
14-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 21a6179c9daaaa38be40b53d6993404856e20dc1 |
14-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127595 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| af3dce51494b366024958b6dc9a15b95cb03011f |
12-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Sometimes isPredicable lies to us and tells us we don't need the operands.
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127518 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 34e98e968f29852d89460ec68fdd4783c5c8dceb |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127516 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f859a545de30bbc848d1b0896b7ef8fa84fd631b |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127515 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| cea5afc98558b24bafee28a02ec21a6d42d2d8e7 |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127511 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 72422d38ba6fb2fb0bb9c0c75fe450b3e939ea21 |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the ARM 'B' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 3c5edaaf59dc051c6d540dd1041cf6bbbb12854f |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove dead code. These ARM instruction definitions no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f219f3135d0ec939acd42801766c17fad41c0173 |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize VMOVDcc and VMOVScc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrVFP.td
|
| b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3 |
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| dd11988c999c23eba2467e35892a2f42858c886b |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
effect that we get proper instruction printing using the "pop" mnemonic for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 958108ad14e91d0f778de07e791fce83cd5f20a9 |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
as for VDUP32d and VDUP32q, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8b8515c225c799e9df69bde8ffffa3c72cec9445 |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 1558df79b4b2b6558c6d107b62e4dab2564bd793 |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f0112a224ffcb6df3044ebb601437ba8ce5b033c |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
This FIXME has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127483 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e672ff84308434ad5517a5c6fc36e691893fca96 |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize ARM MVNCCi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| eb582d7ba202e06ea339def0b610bc31565250da |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127469 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3906276a8d4b308a19675d5a67b2d6ab3e3b9b6f |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| d4a16ad85d991ff12487b40ef248833448047ead |
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize MOVCCr and MOVCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| a4f809d8db5222708c9f4519f48916cc919fd19f |
10-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
DMB can just be a pat referencing MCR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127423 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bc908cfcc147a3494ebad86297cb6da737434064 |
10-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Reorganize a bit. No functional change, just moving patterns up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127422 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a768c3d45f73fff46fb9bbf4368c280ee4aaca49 |
10-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-instructions are codegenonly by definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127420 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 18b475f95478f130667faa8c74bea4efdf68b1ed |
09-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| e6fd111ddf8f32b7d63405e83678887292c34223 |
09-Mar-2011 |
Jush Lu <jush.msn@gmail.com> |
Move BR_JT* to pseudo instructions
RMCodeEmitter.cpp
|
| 260b29b71916d4176b0031bf794fd093344fffe6 |
09-Mar-2011 |
Jush Lu <jush.msn@gmail.com> |
JIT fix for Hi/Lo Imm16 encoding
RMCodeEmitter.cpp
|
| d5f8f75e62b9564890df9599eb916ea4bf68c307 |
09-Mar-2011 |
Jush Lu <jush.msn@gmail.com> |
Add encoding , which converts VFP to Thumb2
RMCodeEmitter.cpp
|
| cc7665f5895e1dd9682ee21d1e755d0de28c161b |
09-Mar-2011 |
Jush Lu <jush.msn@gmail.com> |
Update build scripts after merge r127116
ndroid.mk
|
| b5530586d68bd25831a6796b5d3199cb0769a35c |
09-Mar-2011 |
Jush Lu <jush.msn@gmail.com> |
Merge upstream r127116
|
| 620d0cc7ac8319fe66168288f8ca0509f87c46c1 |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
* Correct encoding for VSRI.
* Add tests for VSRI and VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c04a9dea7873bcf2a1e68b9eba9b5854021e989a |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Correct the encoding for VRSRA and VSRA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 7c6b608a7cb33e628e3906a8395a7ba47a6b966b |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
* Update the NEON shift instruction test to expect what 'as' produces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 79f56c9618e60c390932a6866929b82c9a6d6f96 |
08-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 1b772f99622dc89b807541c0d7477286aa369976 |
08-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127197 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3116dce33840a115130c5f8ffcb9679d023496d6 |
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMISelLowering.cpp
RMISelLowering.h
|
| e516379d2a2fd1ad7583b2fa289051da517d8a42 |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127106 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b3fcc06d2124f9d01e3b48097b44cc141309908e |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127105 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
humb1RegisterInfo.cpp
|
| 3daccd82d3151fa3629de430b55698a81084fc9e |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1FrameLowering.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 7a764168b9b3b3ebeaea224ed8c6ef93381c74d4 |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add unwind information emission for thumb stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127103 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7503fcb890155ac1b62542550c7248db4df890f8 |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle MI flags inside Thumb2SizeReduction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127102 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMFrameLowering.cpp
RMFrameLowering.h
RMMCAsmInfo.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
humb1FrameLowering.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| b5e16af9ea04cc1f94ca631104e5e6be96546aa1 |
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some first rudimentary support for ARM EHABI: print exception table in "text mode".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127099 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
RMTargetObjectFile.cpp
|
| 4faa0e19521f700ad10bfea69e141fc46c45f78b |
05-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused conditional negate operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127090 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrVFP.td
|
| 53dc40a45fae88be2ef023e3c49b58291b8440f9 |
04-Mar-2011 |
Devang Patel <dpatel@apple.com> |
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 58f04fd22a3bbbb5b2620b6feecc36cf1b878dbd |
04-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
PR8053: Fix encoding of S bit in some ARM instructions.
Patch by Zonr Chang!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126967 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| acc9e7315c450ca7cffd4a65c65e578211f9d945 |
03-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add a readme entry for the redundant movw issue for pr9370.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126930 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 181d3fe727022160ce8932e355eae8b3ff478592 |
03-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
pr9367: Add missing predicated BLX instructions.
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
|
| d39647d9130a52beb80bdc9116cb0f3a8affe12f |
03-Mar-2011 |
Kevin Enderby <enderby@apple.com> |
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
Patch by Ted Kremenek!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e89a05337a9946040251a5f19165c41b9a1a7b27 |
02-Mar-2011 |
Renato Golin <renato.golin@arm.com> |
Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126882 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| efb5c6d70817d10c1dd2450b87f423120fd00de8 |
01-Mar-2011 |
jush <jush.msn@gmail.com> |
Add a FIXME.
Emit MOVi32imm by PseudoMoveInstruction now.
Expanding MOVi32imm needs more encoding.
RMExpandPseudoInsts.cpp
|
| a656b63ee4d5b0e3f4d26a55dd4cc69795746684 |
01-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Narrow right shifts need to encode their immediates differently from a normal
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| 728ff0db783152ed4f21f7746bd7874b49708172 |
28-Feb-2011 |
Renato Golin <renato.golin@arm.com> |
Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126689 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4da434cd40b3ae9ea6ff3bef8881d17cca608420 |
28-Feb-2011 |
Kevin Enderby <enderby@apple.com> |
Add missing whitespace in the formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126687 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| d436d5b1c993c78b6c267b5fc1056d593f07921f |
28-Feb-2011 |
Kevin Enderby <enderby@apple.com> |
Fix the arm's disassembler for blx that was building an MCInst without the
needed two predicate operands before the imm operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| c24ab5c654debe47d5693e287d4dc2e151c0ba0e |
28-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix a typo which cause dag combine crash. rdar://9059537.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f222e595c0137b8a9571408257f7000c2fb95473 |
28-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Support for byval parameters on ARM. Will be enabled by a forthcoming
patch to the front-end. Radar 7662569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| 4485fa16ecd3a16ab2b670691fcbfd24cf0656e2 |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Avoid additional encoding for LDRBi12 and STRBi12.
RMCodeEmitter.cpp
|
| c70af345c10d7b6a652fc2825fe325c61525875f |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Add a FIXME.
NEON feature need to emit vector value.
RMCodeEmitter.cpp
|
| 30a4c49153cb859d72f6507ba361dd78bdfc2a01 |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Add handling of FP immediate operands.
RMCodeEmitter.cpp
|
| ee22f2b82b066c61e1249b4e62a5829fe73e557b |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Remove a assertion.
It conflicts with VFP encoding.
RMCodeEmitter.cpp
|
| facbbb139d11a2c238a98a19574ff14b9069ec29 |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Handle f32 in FCONSTS as a single,not a double.
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 28263e86e6e8b8f3e41ed67eab48a50d07772503 |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Fix Addressing Mode 5 encoding.
RMCodeEmitter.cpp
|
| 4671b174806e6c8577125a644aa85999598e4971 |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Update build script after merge.
ndroid.mk
nstPrinter/Android.mk
|
| 4d03e416be8cf1f0f502118826b7cbaeec0b79b2 |
28-Feb-2011 |
jush <jush.msn@gmail.com> |
Merge LLVM upstream r119309 into honey
|
| da52506792f1791682eda34d6319f5967116eb65 |
25-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
|
| 9831f2d585816fc293504ea66e40e8a6c5a5d702 |
25-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126467 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| acca09bd64080393a047204eafad46e2fc34ee68 |
25-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Each prologue may have multiple vpush instructions to store callee-saved
D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.
Sorry, can't reduce a small test case.
rdar://9043312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126457 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 2b943566f394eba5aac0c6c94a2375ea37c9341f |
23-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change VFPNeonA8 definition to make the code easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126298 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
EONMoveFix.cpp
|
| e573fb32556ba8430ccd723f71233cdf56b76340 |
23-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
More fcopysign correctness and performance fix.
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6557bce3ec8d5a82b2ea299a18cb51677b299633 |
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126238 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMHazardRecognizer.cpp
RMInstrFormats.td
RMInstrVFP.td
LxExpansionPass.cpp
EONMoveFix.cpp
|
| 0a921698b6d6f8a40df3893a72c7e6ced1c919a0 |
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Guard against de-referencing MBB.end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126192 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| af05c69ba024b1838ae6f1071d6fd0f9fe33999f |
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
available_externally (hidden or not) GVs are always accessed via stubs. rdar://9027648.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126191 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 872f4a224711ef55b821746fc7a24b9260fee370 |
22-Feb-2011 |
Eric Christopher <echristo@apple.com> |
Only use blx for external function calls on thumb, these could be fixed
up by the dynamic linker, but it's better to use the correct instruction
to begin with.
Fixes rdar://9011034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126176 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 557b297f35395a6104a77ed6a798f10c2b46bfbe |
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Skipping over debugvalue instructions to determine whether the split spot is in a IT block. rdar://9030770
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126159 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 68e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1 |
22-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 00d78f1348a5980a276bed8f9be09ce2412a6a12 |
20-Feb-2011 |
Oscar Fuentes <ofv@wanadoo.es> |
Use explicit add_subdirectory's for LLVM target sublibraries instead
of testing for its presence at cmake time.
This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126068 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 4b19c9865ee94367d7b3594c36e59e4c15ba82cc |
19-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Avoid dangling else warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126004 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8bba1a5ef0f8a71de2e58c7f05b8714a73464ca8 |
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix style and a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125949 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
|
| 6904f05e607b6bbdfa96a2ebb628ebf3a1f21455 |
17-Feb-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 5eda282cd1775afc2ec1e1b86c9e224d2db10302 |
16-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125624 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 79bb6dd363fd0a23040910b32d69a282063521bd |
15-Feb-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ab4c366274a582dd8146b2820c6b999cad5fce36 |
15-Feb-2011 |
Duncan Sands <baldrick@free.fr> |
Spelling fix: consequtive -> consecutive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125563 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 727961a1a3507a8f7e47ba80a1e37fc68bfc8199 |
15-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused bitvectors that record ARM callee-saved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125534 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
RMMachineFunctionInfo.h
|
| e98d646b1194c522b121e1a70906efe4ea578fc8 |
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
A fail to match coprocessor number and register number must fail instead of assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125521 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 0a9481f44fe4fc76e59109992940a76b2a3f9b3b |
13-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
Enhance ComputeMaskedBits to know that aligned frameindexes
have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.
Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f922c47143d247cbae14b294a0bada139bcd35f6 |
12-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
AsmMatcher custom operand parser failure enhancements.
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.
Update the ARM asm parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125426 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 7973f350b78e0bef8567f441f3255c846f5432ac |
11-Feb-2011 |
Nate Begeman <natebegeman@mac.com> |
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.
This avoids moving each element to the integer register file and calling __divsi3 etc. on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125402 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c143dd4f63889ca6b4f656200f43a1fa7bbf1c34 |
11-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix buggy fcopysign lowering.
This
define float @foo(float %x, float %y) nounwind readnone {
entry:
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
ret float %0
}
Was compiled to:
vmov s0, r1
bic r0, r0, #-2147483648
vmov s1, r0
vcmpe.f32 s0, #0
vmrs apsr_nzcv, fpscr
it lt
vneglt.f32 s1, s1
vmov r0, s1
bx lr
This fails to copy the sign of -0.0f because it's lost during the float to int
conversion. Also, it's sub-optimal when the inputs are in GPR registers.
Now it uses integer and + or operations when it's profitable. And it's correct!
lsrs r1, r1, #31
bfi r0, r1, #31, #1
bx lr
rdar://8984306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125357 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 971b83b67a9812556cdb97bb58aa96fb37af458d |
08-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMInstrThumb2.td
RMMCCodeEmitter.cpp
isassembler/ARMDisassembler.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
humb2SizeReduction.cpp
|
| 75396a998887220074b90f176e29054a35b6c0ed |
08-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Temporary workaround for a bad bug introduced by r121082 which replaced
t2LDRpci with t2LDRi12.
There are a couple of problems with this.
1. The encoding for the literal and immediate constant are different.
Note bit 7 of the literal case is 'U' so it can be negative.
2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run.
So we end up never using the Thumb2 instruction, which ends up creating a
lot more constant islands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125074 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
humb2SizeReduction.cpp
|
| 706d946cfe44fa93f482c3a56ed42d52ca81b257 |
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing dmb/dsb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| fafde7f0b7c70e08de719d9e33ce9f6fdaefc984 |
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove the MCR asm parser hack and start using the custom target specific asm
parsing of operands introduced in r125030. As a small note, besides using a more
generic approach we can also have more descriptive output when debugging
llvm-mc, example:
mcr p7, #1, r5, c1, c1, #4
note: parsed instruction:
['mcr', <ARMCC::al>,
<coprocessor number: 7>,
1,
<register 73>,
<coprocessor register: 1>,
<coprocessor register: 1>,
4]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125052 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| cfb9e3db360f9161eede09766fadb2cb178771cb |
07-Feb-2011 |
Kenny Root <kroot@google.com> |
Initial pass at adding X86 target support
Add some Makefile support for using X86 as a target as in "full_x86-eng"
However, this is not enough. More changes will be coming in future
changelists.
Change-Id: Id2765c9ba15404ebce09168738cebf5d00a2e15d
ndroid.mk
smPrinter/Android.mk
isassembler/Android.mk
argetInfo/Android.mk
|
| c046d64f1b5f19cb06616e519a45bc4b0693f9d3 |
07-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125025 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| aa26102db47ac7041a54728cf856de4dca700880 |
07-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious typo which caused an isel assertion. rdar://8964854.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125023 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1c3ef90cab9a563427bdd3c2fcd875c717750562 |
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for using post-increment NEON load/store instructions.
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 7de6814405ab02591235f0826b8e6d98fd76c8ba |
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Change VLD3/4 and VST3/4 for quad registers to not update the address register.
These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used. In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125013 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 6eb08dd9bfc25e0c9aafe059511fe23c28c64bbc |
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix some NEON instruction itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125012 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d3a076503bfa3cac293f9d92b810da031bbb2800 |
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment: addrmode6 no longer includes the optional writeback flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125011 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 09989945e204d3d3434ae9f3392c335b25a1ac84 |
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Remove inaccurate comments: so_imm and t2_so_imm operands are not encoded
until the instructions are emitted or printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125010 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 4e97e8ee5748a92326078d744f5fc2b581a7b5b0 |
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Move code for OffsetCompare struct closer to where it is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125009 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| f009a961caa75465999ef3bc764984d97a7da331 |
07-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Rework some .ARM.attribute work for improved gcc compatibility.
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124995 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 685c350ae76b588e1f00c01a511fe8bd57f18394 |
04-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| b412915ff6229b3e2dffedcfb0f3fb7e85259841 |
04-Feb-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Add support for allowing the conversion process to fail (via
custom conversion functions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124872 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 69df72367f45c0414541196efaf7c13b1ccd3f08 |
03-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix 80-column violations and whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124819 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 92e7195e433435eeb93d5f88de146878b76abb21 |
02-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Update comment to match my recent change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124725 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 31959b19a72608051888160514977875a8027dfc |
02-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Given a pair of floating point load and store, if there are no other uses of
the load, then it may be legal to transform the load and store to integer
load and store of the same width.
This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []
to
ldr r12, []
str r12, []
rdar://8944252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 692df93de427356d3ab7bb0438a3c998f28186ea |
01-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
PR9081: Split up LDM instruction with deprecated use of both LR and PC.
This is completely untested but pretty straightforward, so hopefully I
got it right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124694 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| e9a7ea68653689966417443b8ac2528c1d9d3ccf |
31-Jan-2011 |
Devang Patel <dpatel@apple.com> |
Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 98b928ea71576c243bdb203879d966be9cde5f3c |
30-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Save a mapping between original and cloned constpool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124570 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMMachineFunctionInfo.h
|
| d11c57a93753e7fd9fdac110e81c88eb56a847e4 |
28-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
Patch by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| c3a20bab7571ff95525252c379198e67b65d0f1d |
28-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix PLD encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9e56fb12c504c82c92947fe9c46287fc60116b91 |
28-Jan-2011 |
Kevin Enderby <enderby@apple.com> |
Changed llvm-mc arm target to give an error if .syntax divided is used. Since
only .syntax unified is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124454 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| bf7553210ae44f05e7460edeae1ee499d8a22dcb |
27-Jan-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Introduce virtual ParseRegister method in TargetAsmParser.
Create override of this method in X86/ARM/MBlaze.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4a2b31676217cbf710f74253ae6ab8306b115ba6 |
27-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Use the incoming VT not the VT of where we're trying to store to determine
if we can store a value. Also, the exclusion is or, not and.
Fixes rdar://8920247.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124357 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8cb415e4c0032300a1b728c942f8b31acec0a9f5 |
26-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Add support for printing out floating point values from the ARM assembly
parser. The parser will always give us a binary representation of the floating
point number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124318 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 1b10d5be40313b4e246e85cf375dfa3452ab306b |
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 717082b9bd634ea406ca63b3a9358ffd09091b9c |
26-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Add needed braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124273 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| fca9e9ec56dd811f99283f45f327a2646bda3bc0 |
25-Jan-2011 |
Stephen Hines <srhines@google.com> |
Fix encoding bug for ARM PKHBT/PKHTB instructions.
It looks like LLVM was encoding the shift type/amount and then not properly
decoding it when emitting the final assembly code.
Change-Id: I62912372b121e8edcf9273c4cc9304ee81b27d31
b: 3378908
RMInstrInfo.td
|
| 0f4db7efa1aa901d798df95f16d8361450b69fe1 |
25-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert 124230. It was causing test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124233 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 261b9c1a35e1c2ef7e4cc387443dd8544d8b48de |
25-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
The floating point value is encoded in its binary form as an Imm. Convert it
appropriately so that it prints out the decimal representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124230 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| 7cfa656ad84306ded61f0a3c7a8862505f48c239 |
25-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't merge restore with tail call instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124167 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 5899a60d2fb02f7e2d094d710babbe1d3bd97254 |
24-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide correct registers for EH stuff on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124151 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 96aa78c8c5ef1a5f268539c9edc86569b436d573 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the --noexecstack option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 584520e8e2c1f8cc04bc8dd4dc4ea6c390627317 |
23-Jan-2011 |
Ted Kremenek <kremenek@apple.com> |
Null initialize a few variables flagged by
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 1c13026e8f94bd332c0979baa9c777da99d48736 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove more duplicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124056 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
|
| c85dca66e68c9fa6ffa8471c64113b12d8d94fb1 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove duplicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124054 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
|
| 53519f015e3e84e9f57b677cc8724805a6009b73 |
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInfo.h
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
|
| 030160073d8ec7d5fc1d928d9c8b6173d3a5e0cc |
21-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4 |
21-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Convert -enable-sched-cycles and -enable-sched-hazard to -disable
flags. They are still not enable in this revision.
Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.
Generalized unit tests to work with sched-cycles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d7e3cc840b81b0438e47f05d9664137a198876df |
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e47f3751d7770916f250a00a84316d412e959c00 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding and parsing of clrex instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| 6456121d5c40f56d45ff4b8b183d5468e43b9717 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change instruction names for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123930 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8dd37f7b7dca7907f9f070dc96359f242e102163 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add cdp/cdp2 instructions for thumb/thumb2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| b32f7a5f4bc678c052db40cbb4ac8617c134aa24 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 6b3a999f227139a3be7df6b5aea7a7d01ce94851 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr*2 and mr*c2 support to thumb2 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| fa5bd27fbe5188ca708ac0dda4f32d90505da9f5 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr* and mr*c support to thumb targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
smParser/ARMAsmParser.cpp
|
| 8197754be57abba9bbce4733de8d887f341ea339 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123910 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 907276dc4439c04d675fbcdb121cbede7a99ff9d |
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Correct itinerary entry for t2MOV_pic_ga_add_pc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123907 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMRegisterInfo.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b |
19-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ec91d52a77abfe3cf56413a11f47b3ee8e67e41e |
19-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
ARM/ISel: Factor out isScaledConstantInRange() helper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123823 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9b72693d83d1c9dcda98a478c289d05306520a41 |
19-Jan-2011 |
Logan <tzuhsiang.chien@gmail.com> |
Add X86AsmParser and ARMAsmParser build rules.
smParser/Android.mk
|
| 32cec0a75678401ce079bb31fa748ae0d6613e2d |
19-Jan-2011 |
Andrew Trick <atrick@apple.com> |
For ARM subtargets with useNEONForSinglePrecisionFP, double count uses
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123811 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7fa75ce11d8f491d9f68c3cabe60f6fc70787748 |
19-Jan-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123810 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fc8475bde993cc0fa6101427e73e8a9cf7d1c3a4 |
19-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123809 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
|
| 61505907f54d4e7df2f9d90b1ed3a4caa0469d26 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMRegisterInfo.td
|
| e7255a80e308c7f67d25b0b247ed791a99ea3a4e |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix MRS encoding for arm and thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 892fc6d7b64364b230261daa967518a71748c01b |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of t2ISB by using the right class and also parse it correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smParser/ARMAsmParser.cpp
|
| fdcee77887372dbf6589d47cc33094965b679f24 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a461d4222877f43588da38c466145f38dd74e229 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| ff12a8bd999569ce76b3a9f5e167f6e89280e9d9 |
18-Jan-2011 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123769 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 4b462672d2b4950e5f059bd093db524aa10e8377 |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Use accessors where appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123746 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6ec56204f372df73e4a27085b188a72548b867ac |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Fill in ASMOperand::dump() for memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123745 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2637dc9a252f25fd1c63acfe0606860ee7c8cfdf |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Make ARMOperand use a union where appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123744 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 05d8b71424316ad7b014adbbb316f78c5bd46861 |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Unify ParseMemory() successfull return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123740 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0571093f4cf0414724674448fe6b973c0fa705b3 |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Early exit on failure (NEFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123739 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d3df5f32c059b3ac111f1c08571d5493aa1d48c6 |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic.
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123738 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 023835d51b6dd6e3a253deefa595b0d916b605ac |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Add a variety of asserts on the sanity of memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123737 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 81f453c4b91b8c681d82d63257a271107626648e |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Use a consistent marker for not-set OffsetRegNum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123736 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2e3cea3153ab957af01925580d912be060cb00cf |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Start marking T2 address operands as such, for the benefit of the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 955ed73d12f2b186ef3f80da872b702cd7f2895b |
18-Jan-2011 |
Jeffrey Yasskin <jyasskin@google.com> |
Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMFrameLowering.cpp
|
| 5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 |
17-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
RMBaseInfo.h
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMJITInfo.h
RMMachineFunctionInfo.h
RMSubtarget.cpp
|
| 1d8334eabc0ad9d6c3c3c5852315cca324383302 |
16-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide instruction sizes for ARMv5 variants of MUL instructions.
This fixes PR8987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123598 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 42c32daadbb1bd0626cced08c418d1b7a0b16fb4 |
14-Jan-2011 |
Logan <tzuhsiang.chien@gmail.com> |
Add LOCAL_MODULE_TAGS := optional
Change-Id: I292f6297b06f97360c15884677057d624e73fbf6
ndroid.mk
smPrinter/Android.mk
isassembler/Android.mk
argetInfo/Android.mk
|
| df55fea807835bc23a2879fbf7f7a8bd53de8256 |
16-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Spill R4 if it's going to be used to restore SP from FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123567 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| a0f720f500222c43e3f9905eddda2e6e6bcd300e |
15-Jan-2011 |
Eric Christopher <echristo@apple.com> |
80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123505 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ca3f06963c21ee34c7454be807c4d72af3b0f3ad |
15-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123497 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
|
| 41262da6cc8e61d7ae5e021a41964d50c964e390 |
15-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Fix 80-cols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123494 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f3eb3bba1614a7935b44fc963a805088d71267f3 |
14-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123424 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 0c9f250d54ed59108fffe5ce2f7df7bc8448915c |
13-Jan-2011 |
Owen Anderson <resistor@mac.com> |
Recognize alternative register names like ip -> r12.
Fixes <rdar://problem/8857982>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123409 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f7ca976e74eafeeab0e9097f0fb07d6bb447415b |
13-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a few more places that should use MBB::getLastNonDebugInstr().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123408 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| e4e5e2aae7e1e0e84877061432e7b981a360a77d |
13-Jan-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.
With this, we can properly pretty-print and encode assembly like:
mrc p15, #0, r3, c13, c0, #3
Fixes <rdar://problem/8857858>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123404 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 4f28c1c71450c711e96aa283de53739d8b4504cd |
13-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach frame lowering to ignore debug values after the terminators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123399 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
humb1FrameLowering.cpp
|
| 422578547e0e3464af7ae23305c54dd71a8bd9e9 |
13-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Tidy comments, indentation, and 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123397 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 67b212e03b77e921e2b9780059681125a45d15a7 |
13-Jan-2011 |
Kevin Enderby <enderby@apple.com> |
Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target and
directional local labels like 1f and 2b.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123393 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5f3e2be7c941b26ac865fa00c3f314bcd1e6cec8 |
13-Jan-2011 |
Jim Grosbach <grosbach@apple.com> |
When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly
set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123387 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 7597212abced110723f2fee985a7d60557c092ec |
13-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
RMMCExpr.cpp
RMMCExpr.h
RMMCInstLower.cpp
smParser/ARMAsmParser.cpp
MakeLists.txt
|
| fef9ff492206330ff0a5b94cec5ac1455b28df88 |
13-Jan-2011 |
Kevin Enderby <enderby@apple.com> |
Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 or
.code 32 if the TargetMachine's isThumb() boolean does not match. The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123353 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8a8696db6b6f6e735bb9de630876af83946b45f9 |
13-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Change call to Error() to assert()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123350 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8dc602d24590206571836f31b8fead56cb51318c |
13-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Added clarifying comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123341 91177308-0d34-0410-b5e6-96231b3b80d8
RMFixupKinds.h
|
| 650b7d76afbc7db2dd1a4590149d50a162bb25d8 |
13-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
JimG sez: "The value-kinds look like masks, but they're not consistently used
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."
So I am reverting this bit until a more opportune time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123340 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7caebff83d90a59aa74876ff887e822387f479e0 |
12-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Sort the register list based on the *actual* register numbers rather than the
enum values we give to them. <rdar://problem/8823730>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5f8a917b6558f8fdf31b4a6fa591b396e16b9ff2 |
12-Jan-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Mostly undo r123297, but move the default case in EvaluateAsPCRel to the top
of the switch block to appease GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123317 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| e45f2dfde651c01aafa73e7708ebd76881427690 |
12-Jan-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add another note taken from the gcc bugzilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123315 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 676943b31aaa5c298a978b0acd7aa00015c22482 |
12-Jan-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Prefer llvm_unreachable to assert(0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123297 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 86a97f2e4d0cde5e992f52ac287da0de687e0110 |
12-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 9081b4b4cf89a161246e037f4817c69de2fcdf82 |
12-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Workaround for bug 8721.
.s Test added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b72d2a92b75daa9cbac7338aff0cd8ae04c2b4bd |
11-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM subtarget code by using Triple ADT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123276 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFrameLowering.cpp
RMHazardRecognizer.cpp
RMSubtarget.cpp
RMSubtarget.h
smParser/ARMAsmParser.cpp
|
| eb9f3f91c03c29f020ee3c25cfefe7ae2b496526 |
11-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Fill in GetMnemonicAcceptInfo().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123253 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6c562f69fe7aa5550e7b6594ee4e861f767471b3 |
11-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment: We now have intrinsics for vcvtr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123246 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 3771dd041f6a68bef08b6f685a41d1d54f4e8b9d |
11-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Sketch some logic for determining when to add carry set and predication code operands based on the "canonical mnemonic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123239 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 352e148cbe6498a6dd31b7fc71df7cd23c4b4d10 |
11-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 94bb7b561c16878ae442adeb13dd42140b55d027 |
11-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Even if we don't have 7 bytes of stack space we may need to save and
restore the stack pointer from the frame pointer on thumbv6.
Fixes rdar://8819685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123196 91177308-0d34-0410-b5e6-96231b3b80d8
humb1FrameLowering.cpp
|
| 4dd312f2334a215cfc7961518823ef36884b4c95 |
11-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Expand on the safeness of restoring the sp from the fp a bit more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123193 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameLowering.cpp
|
| 8ab1112bdc30b8675bb12431d8b5b270da42f1b5 |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Flush out hard coded known non-predicated mnemonic list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8d66b7852afec301a1a667069f8c497da2eec964 |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Mark some T2 ...s instructions as codegen only, they aren't real
instructions but are restricted pseudo forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123177 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 238100aaa7952d754fe33c0b29423fd5f0044a04 |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
ARM/MC: Mark several '...S' instructions as codegen only, they aren't real
instructions but are restricted pseudo forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6a5c22ed89c8bb73034a70105340acf6539dc58b |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM/AsmParser: Minor nitty fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123175 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7af6fad0a73f33a6782166676d48073ce8565c47 |
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Update CMake stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123171 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMExpandPseudoInsts.cpp
RMFrameInfo.cpp
RMFrameInfo.h
RMFrameLowering.cpp
RMFrameLowering.h
RMISelLowering.cpp
RMRegisterInfo.cpp
RMTargetMachine.cpp
RMTargetMachine.h
humb1FrameInfo.cpp
humb1FrameInfo.h
humb1FrameLowering.cpp
humb1FrameLowering.h
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| badbd2fde9b8debd6265e8ece511fb01123d1d5f |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM/AsmParser: Split out SplitMnemonicAndCC().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123169 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c9df025e33ac435adb3b3318d237c36ca7cec659 |
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
|
| 55d42003368c57d3a41c5f464d39b8440050d558 |
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| c36b7069b42bece963b7e6adf020353ce990ef76 |
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 70f85730b199839891166b2a0acff126d1cc7c12 |
08-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add an explanatory message for an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123042 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 697970286ac61ff5bf4659d51a2cf9e0a2b7800d |
07-Jan-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Eliminate variable only used in debug builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123040 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 11a1dfffc8b6bbe0c0936c2c70681bc74bb5cd56 |
07-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Lower some BUILD_VECTORS using VEXT+shuffle.
Patch by Tim Northover.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123035 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 5e8b833707e6d59576d91b23a2c24e596eace60e |
07-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.
The test changes are needed to keep those spill-q tests from testing aligned
spills and restores. If the only aligned stack objects are spill slots, we
no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 6819dbb6f86f519130edf22ac3a30fa53b01fa45 |
06-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
PR8921: LDM/POP do not support interworking prior to v5t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122970 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
RMLoadStoreOptimizer.cpp
|
| 28f1015e3665cae34fc8337ec8e03ad903d30a33 |
06-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Remove extra whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122969 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| 0fef58465cb3a54922b65da01b69bec98f43e36f |
06-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122968 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0521928ae7cc492f3f45ef0e0cedc349102489c5 |
06-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 54c6d6f42d096f8144ac636ec6ae0d3362ead43e |
05-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
fix some -Wself-assign warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122893 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6018deefe823598a3bbe03de9af354d269ae2130 |
04-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Fix the ARM IIC_iCMPsi itinerary and add an important assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
RMSubtarget.cpp
|
| 2c502f915f52aab994fce7d3e78d1d021321d7a5 |
04-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Formatting changes. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122789 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
|
| 4d7286083537833880901953d29786cf831affc4 |
01-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Model operand restrictions of mul-like instructions on ARMv5 via
earlyclobber stuff. This should fix PRs 2313 and 8157.
Unfortunately, no testcase, since it'd be dependent on register
assignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122663 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMAsmPrinter.h
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 7d63a2c2e8da75eeb2d36dd93adf33f7658d0083 |
29-Dec-2010 |
NAKAMURA Takumi <geek4civic@gmail.com> |
CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122623 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
isassembler/CMakeLists.txt
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMHazardRecognizer.cpp
RMHazardRecognizer.h
RMSubtarget.cpp
RMSubtarget.h
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| f12eee75d1f8a3e276d03cc0fda95d18097fb08e |
24-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Use a StringSwitch<> instead of a manually constructed string matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122530 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
|
| b0ad9cf935b0fff60ea2bc43cb944255f1bad61a |
24-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122524 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 940c8e5494c17529f96f5e1915ad89e488bdd69e |
24-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Recognize a few more documented register name aliases for ARM in the asm lexer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
|
| 3c904694fc769ce9e12455b43b94144a99325110 |
23-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 036609bd7d42ed1f57865969e059eb7d1eb6c392 |
23-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Flag -> Glue, the ongoing saga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 9584bd83e6042484da11ab592c9b1eb04c61b014 |
23-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122456 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
|
| 316009054ef25fd12f95d97ac9282dede2392e1a |
21-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register. Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up. Radar 8755338.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c19aadb8b0219462ff55f4bdc8106cebc1245bb6 |
21-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Arm and thumb call instructions are also in different orders.
Fixes rdar://8782223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122313 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 6e90ce21cc2b0627ee9219e3fb0cf808f2b73328 |
21-Dec-2010 |
Eric Christopher <echristo@apple.com> |
If we're not using reg+reg offset we're using reg+imm, set the opcode
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.
Fixes part of rdar://8782207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122307 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| a519d577251c2a1207b466a4659d9eff37a989e1 |
21-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122303 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 9a4d2e40a02b6e5fab5ccf1c768a52c76f3aec6a |
21-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122302 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1ec5bd31fe491e610839ea448bd99fd171785837 |
18-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MCObjectFormat class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| bff66a86e6e44dc7424cd2d7719ac80630b3a5f8 |
18-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move some data to the TargetWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122134 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a68a4fdf37676794ce69624d1fd4e4627c377902 |
18-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122131 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| cd080249fc249a51d8b0021a651d8b9d4a4977e0 |
18-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
RemoveUnusedCPEntries can change things. Track it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122129 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 094dd80ecc6758543f088539a96ea9fad8ad858a |
18-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rearrange some Neon multiclasses. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3deb45149a2eaecfc9453db2a7e840531b930cc6 |
18-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix result type of Neon floating-point comparisons against zero.
The result vector elements are always integers. Radar 8782191.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122112 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3a75b9bc8fed6c7f3f30470d3f3e28ac83df9d40 |
18-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add some missing entries in ARMTargetLowering::getTargetNodeName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122111 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 976ef86689ed065361a748f81c44ca3510af2202 |
18-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
During local stack slot allocation, the materializeFrameBaseRegister function
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 9bb43e167576d464637c480eccc5696e01e1887c |
18-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Avoid report_fatal_error in ARM's PrintAsmOperand method.
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122100 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a3dbd3a2444f2531763ba05b64a30932542a631f |
17-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with
a partial value. rdar://8782954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122078 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| f0db261e97f9c199e584b2a73095a7e36f4eb3cc |
17-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122076 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6ec6eeb692fa11b569af8b69b2bb11cc84f04926 |
17-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle 2 and 4 byte data blob fixup values for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122075 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 6024c97ffa15766bc0f200ffd309d9e017ae0d4b |
17-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Stub out explicit MCELFObjectTargetWriter interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122067 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 285b3e5b61af15f11e59a7700375aefa2a326bd8 |
17-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move createELFObjectWriter to its own header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122064 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 1139d5090ab96e24342f12a6a6817d5898358e1e |
17-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Use aggressive symbol folding (important for jump tables, for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122044 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 7b62afac0a6f967e7466e60ceb26bfdcff2e59f4 |
17-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
superceded and was effectively dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a1f544b62e5d9eae0311dfb3a0b0e72f25e041d4 |
17-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use PairDRegs to implement ConcatVectors. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3efad8fad41f6ba8141befcc3fc6662246b663ad |
16-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121990 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrThumb.td
|
| 5d05d9769ec98cdee359fd934a56c9455e21232b |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121981 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| ae5abd595f5442767313a4c8a24008ad19323ceb |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121973 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| aa4b7dd13ba83152473950d7014a29686dc7eef6 |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121971 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 2761fc427082215c2affcc9d8db8491400bc9e5d |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| 656b3d22f70c2d1c8a5286f7270cb380df862565 |
16-Dec-2010 |
Matt Beaumont-Gay <matthewbg@google.com> |
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
(see PR4579).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121939 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 6baf46dbeab86dd7a35a9737bbdc5c67bee0bf69 |
16-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
it. I.e., it was always an immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 5a54516adf2b15fa337445d327ec3ad9bd1e3648 |
16-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| dedec2b89dd05891d0e22093887b190462d5b82a |
16-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for Thumb1 Spill and Restore pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 3e333637f172c30adf5c8333b592fbde17ff9f78 |
16-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrThumb.td
humb1RegisterInfo.cpp
|
| 836c6245ad7e8f2b9f72c2a9e4cb1df101eaf2c7 |
16-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Don't handle -arm-long-calls in fast isel for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| 7a905a82f7425d1a10b828c8bb3365b2ebc15833 |
16-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
If we're changing the frame register to a physical register other than SP, we
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121915 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
humb1RegisterInfo.cpp
|
| dc3813750e4400a02099b047c3ebe5a182585ac3 |
16-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Whitespace cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121914 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0406356cd4cb7b689e2472faa8dfb7d721f9d274 |
15-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrNEON.td
|
| d481110ef753902447d6b42e09d0ad0718e417cc |
15-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak a few pseudo-inst pattern base classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 41b1d4e4725b34ccf646c706757d8a557ab376e7 |
15-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 47dbd429daefa9b3f19347194ddfb6f69642465e |
15-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Implement cleanups suggested by Daniel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 22447ae54bcb8ca94ed994cad103074a24e66781 |
15-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add fixups for Thumb LDR/STR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| bc4224bc6bc078b249b030c54f532215f61935c5 |
15-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Reapply r121808 now that the missing patterns have been supplied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 415af3452ea85f544761f8947426e4431706a165 |
15-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add some missing patterns now that tLDRB and tLDRH are split into reg and
immediate versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7d1d8db54a8257bc6d954ff73f35171d757beafc |
15-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r121808 until I can fix the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9d04dc52a5848a3311e08e65e0e10a07864e5e57 |
15-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
thumb adr fixup needs alignment just like the t2 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 345cdb647506c36caa5efa48143a3c2dd4f62c65 |
15-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Comments and cleaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 2af0fd3fee1f65f11ff6ca003c51ac9c640328a4 |
15-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0]
and not
ldr r2, [r3, r0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d40963c4065432ec7e47879d3ca665a54ee903b6 |
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| ee2b350d835231aaf96e4b83dca48326b20dcc42 |
14-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
RMFixupKinds.h
|
| b6faf6521543186e6cd305594f60841b7ae66cfe |
14-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Multiclassify the LDR/STR encoding patterns. The only functionality difference
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 8d6d7d6e30f3c90f92c5a12522d1500ca92299bf |
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
RMFixupKinds.h
|
| 40edf73a62bf025eba4391e806fb1ddada662355 |
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor a bit for legibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 00f25fa43e5e36912a3302756a77585b810859bd |
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| eb61272150574ab6f51c9c84db119b53b92bb4df |
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure to propagate the predicate operands for LEApcrel to ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 86abd48fd01080f08eec1b46f92c90308b03bfd4 |
14-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| abfbac52df836460392186a61619fe266b40fa8c |
14-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| e8eb1ea6acd54538b42491b95d8fc6281d4b5710 |
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 971321bb70d3f0fc622bda75d876e5c7d2b33e56 |
14-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the integer scheduling intrinsic for integer loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| f4caf69720d807573c50d41aa06bcec1c99bdbbd |
14-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrThumb.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef |
14-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a838a25d59838adfa91463f6a918ae3adeb352c1 |
14-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 4711d5cda37fc4a756f83fc1090e85ec9302c52f |
14-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 0e6d540d1745ea00042ca6d56d6e5929e7c8e5ca |
14-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Simplify N2VSPat, removing some unnecessary type arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6b8719fd7dc527e4c1910ae49ebee61d90907c08 |
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121721, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFixupKinds.h
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| e8d02539d7981c07d301d91a6a5b6ad34099b510 |
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMFixupKinds.h
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 4dedddce93ffb4476fb269caddb10da60a0a8d84 |
13-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Delete a line that I forgot to revert previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121719 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1e6f59608bf5becb3c560dd5c38c7b37c0edcbdb |
13-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 3a6756cb1c87908f5d04660b6ed7d464b56f78f6 |
13-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for 2-register Neon instructions for scalar FP.
Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 6dbcea1f8e557a5374714338f9b5116ae139ef32 |
13-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused instruction class arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121715 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 30fb13f97a197823f66da4df98625a9b3585ece9 |
13-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Generalize BFI isel lowering a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c266600bec4b5ba0ee93ffdfeaafcab8f1295145 |
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 56a2535474dd4482c432b3c75c3dab4b2f3dd1e2 |
13-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Use 32-bit types for 32-bit values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121709 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 7e294cfcf97cd7b94bf5c4de0f214480ec13adad |
13-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121708 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a9688c4b5769be7a6a89350888b3173c97fe87ed |
11-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| 092e2cd5693114a4f1d93eb5b72f3e194de27236 |
11-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121598 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 63ee22065dc4e8af7f4bf99c25b82da132700267 |
11-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to get Thumb2 branch fixups working properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121593 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| 5fd873d8e83e485aef79c1f5fa1704748500ca8b |
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix merge error in my last fix to Thumb2 vldr fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121588 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| e2e0f58809374265bd75edeefae8817e7ade62b4 |
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121587 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| 1591b293d6b31ae52a7d5ec16b8117d033204f44 |
10-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The MCFixupKindInfo table needs to be in the order that the enums were
declared. Add a note specifying this and spruce up the list a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121586 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| ac00e9627388e31a5704bc3e3430ffd0631bb1fe |
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121585 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 746fa17d59000be7f642a0b6c5223f29c5e10f00 |
10-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121583 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 20d5515aa503ef0cfe1fa8545c18c3b4d3f4473b |
10-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121582 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0f4b60d43a289671082deee3bd56a3a055afb16a |
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb1 LDRB and STRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| 7bf4c02789f97e32225fc248dff6622b994a15ee |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121580 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 808c7d1482bafdcf1e6b2d759ae98946074b95e2 |
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 encodings of STREX and LDREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121579 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0be099da7937c13794e148ebcafa7880c01ed11a |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121525 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 90cc533fda9742f5c67203f97e69e5efd270c676 |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121524 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 683fc3e9afeda5178ab0644f4ba299715f53a7c8 |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
More trivial cleanup. No need to define the EncoderMethod property type. Can
just assign to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121523 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 04da9bf9f133a3e5233d10885a38e1d14199549c |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121522 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a79bd0e1e0df2358bd8d1d1d5bf30bdfc0141f67 |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121521 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a92bac64cb75853c65a6146e015c2bf60c710869 |
10-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed. Add tests for this, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121506 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 568f528c997505706d3d02a31517338ef7dc2d17 |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR
instructions to restore a single register rather than an LDM instruction.
rdar://8754999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121498 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| e246717c3a36a913fd4200776ed621649bb2b624 |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb unconditional branch binary encoding. rdar://8754994
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| 01086451393ef33e82b6fad623989dd97dd70edf |
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb conditional branch binary encodings. rdar://8745367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| 44a9e8f869dd9d04a04eb556ff0ff4a1039d371f |
10-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Fix the leak from r121401 of the Operands erased in the list but not deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121450 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 272df516d7a9b1f0f69174276abaa759816ee456 |
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| fe7fac74b4edaf9cc04460fc21aa949e5533aea2 |
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
but it gets many more of them correct than it did previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121414 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| 05018c2f2872a05b1a2fff1a9934621ba1f38084 |
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121408 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| b492a7c2134d3886f545f1b5ea55115d71529a10 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename CB/CBZ specific fixup accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121404 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 193c3acbe5cdb60767d114016970e898c7502d7a |
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add support for parsing ARM arithmetic instructions that update or don't update
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 027d6e8d1ca04e4096fb3a27579b861d861466c5 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename the encoder method for t_cbtarget to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121399 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| cf6220a9de15d8a2a431f2672ebab3ffb0048c78 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb needs a few different encoding schemes for branch targets. Rename
t_brtarget to be more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121398 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c6f9261711ac6666db5d99715531a41c1b1d98ed |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM stm/ldm instructions require more than one register in the register list.
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121391 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
RMFrameInfo.h
|
| bfd0daa6a67f838679d09c9a80df0dfa860fc255 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121371 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| 2a4f0986ac2d43cd20b78df9e0aded0e67151770 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121370 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| 6b0fa635d5bfd80940e667cec1662e611f5d270f |
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix encoding of the immediate operands on post-indexed LDR and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121354 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1a48c032bd7c240fc4c52aee6dad57f8043a77d9 |
09-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Fix up some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121351 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| d7b3f5870d9d04351d9cd363d9d6af01482a2eb8 |
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 fixups for ldr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121350 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 766a63d20e89ad5a8b19aba2df0128c1f73174b3 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a textual message to the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121349 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 9702e6075c3e4cd508fd787e3bf6b3e64eb029ab |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
referencing the stack pointer as they say they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121347 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| cde31293d45f14ddff482d385429d256bd4e0820 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
When using multiple instructions to reference a frame index, make sure to
update the opcode when necessary as well as the source register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121346 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a0e23c5e95978565b9e5a0cd38f4a0f26555d9be |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The add/sub SP instructions are really pseudos. The assembler should ignore
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121345 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0a29c270b53f15723811783c572d06b9500a7e8f |
09-Dec-2010 |
Matt Beaumont-Gay <matthewbg@google.com> |
Remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121343 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 8f0794331765661f92cf074f638acb1ea927bb5d |
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix typo in Thumb2 branch fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121342 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 2fe813af23e682b418ecd477144fe070be325419 |
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove extraneous semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121338 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 797b7aab35d815a48f58ce7f7b0b8d0fe06c92af |
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Attempt to make the bit-twiddling readable resulted in the binary value being
overwritten.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121337 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 09aa3f0ef35d9241c92439d74b8d5e9a81d814c2 |
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The BLX instruction is encoded differently than the BL, because why not? In
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| fb20d890756b75d6ccfa7ab17f170a877d425dc6 |
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 BCC encoding and fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121329 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 045869c12ac5af2b1dd97a0dcbedab8db01fe765 |
09-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Style nit and whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121317 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 60fc2ed2bb7e031c95fabaae581583110af8b831 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME
for more thorough cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121315 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 20e0fa698d734f5c1b2c96ff5b266e393c82c0b9 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121314 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0062db8b4f388308f8838805f160259a48a2882e |
09-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Removed dead comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121313 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| a0871e79270b2a05f93c9df73bbe24c587faa94e |
09-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
ARM/MC/ELF TPsoft is now a proper pseudo inst.
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121312 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| 7685ff84ada08d63c8b67618d54ab7eb1fcae365 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121311 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 37474e6d68b42b0d1f4299c8588893bfaa3d0d09 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121310 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 07e9b26371c1045a5b1dde55fcaa8e2753eb0377 |
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121309 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| dff2f7151f695b86db8c4b0c6604463bdb8a63ea |
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Support the "target" encodings for the CB[N]Z instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| 5d9e0160256b7d5e19072f89006157ab6d28a698 |
09-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious cut-n-paste error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121307 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| b76dfe06d9eb42a4b7ffbb02997a2a8eead4faa1 |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding for Thumb2 addw SP + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121305 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7c6d85a98102add1994b612a707a379b8123c34b |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize opcode encoding bits for Thumb2 extended precision integer
multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121301 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 520820489905c3c9ed268a1c27416f2a726cb66e |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121297 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 86386923625c7ae59e8e3d6ceaf9fdd3b33f7718 |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify T2 operand assignment notation a bit. No need to specify a bit range
for the source field when it's the whole thing that's being referenced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121291 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0c2c217244573cdfb4be8b7fa62670412b4c1e71 |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM fixup value adjustments for Thumb to better handle the half-word
ordering of thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 6b1207267f01877ff9b351786c902cb2ecd354c0 |
08-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Generalize PostRAHazardRecognizer so it can be used in any pass for
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121274 91177308-0d34-0410-b5e6-96231b3b80d8
RMHazardRecognizer.cpp
RMHazardRecognizer.h
|
| cc78f5c09c451dd84ef5c4abdfcdadd4270a4942 |
08-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Improve comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121272 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 022ab3779c4280f41daf8621257c41cb028c6efe |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add initializer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121262 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 275bf631157ec5b2f0c29b3273f008f1bbbdc7f0 |
08-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121238 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| b8958b031ec5163261f490f131780c5dc3d823d6 |
08-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for loading from a constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| 5be6d2af38c29e3653998978345220974cc40c01 |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Let target asm backends see assembler flags as they go by. Use that to handle
thumb vs. arm mode differences in WriteNopData().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 255eafbd498e7d41ceef45ee0ad13bfde573ff82 |
08-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Simplify the byte reordering logic slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121216 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| d8e351b96f5fd7007fbdd636acaa1fc9f6e18f3c |
08-Dec-2010 |
Owen Anderson <resistor@mac.com> |
VLDR fixups need special handling under Thumb. While the encoding is the same,
the order of the bytes in the data stream is flipped around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 2bf315f0871a65061d8fd9c867587cfe02adefc7 |
08-Dec-2010 |
Matt Beaumont-Gay <matthewbg@google.com> |
Fix a warning about a variable which is only used in an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| d832fa053b86f42a5bc1e55e979b61c1115a8053 |
08-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Cleanup in the Darwin end. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121198 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 06d65f515638dc996a4ecaf2a9692475aa4b46e3 |
08-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}
vpush and vpop do not allow gaps in the register list.
rdar://8728956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121197 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
RMFrameInfo.h
|
| 52e635ea3512cfcd03587201b20100074e5b6ac9 |
08-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No
functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121195 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| d967cd096ae87accf2f1df86b2dfac969d9c9da2 |
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Binary encoding for ARM tLDRspi and tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| bdf714450b70509538aa5a8a676034418ce827b6 |
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 encoding of the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 97a884d602538705644e296a57a039959cdb6f6e |
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
possible. They were duplicates for everything exception the source pattern
before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| 52f21e35e83d9c644aa40d557816ea647288c99d |
07-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up; no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121176 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| 9801b5c822bf475e859e3fe18b87dbb308b0e22c |
07-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up; no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121172 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
|
| 5169220624b73c8792f06d91292ed8d57ec444f8 |
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the literal field for tCMPzi instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121153 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 6aa49435994c33257b7588cac24671785d17fa6e |
07-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add parens to pacify gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 40f8f6264d5af2c38e797e0dc59827cd231e8ff7 |
07-Dec-2010 |
Jay Foad <jay.foad@gmail.com> |
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| eb6779c5b98383e33542207f062102e79263df16 |
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMInstrThumb2.td
RMMCCodeEmitter.cpp
isassembler/ARMDisassembler.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
humb2SizeReduction.cpp
|
| 662a816e89a9d77bf75e1328b09cf9235b4682aa |
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add fixup for Thumb1 BL/BLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrThumb.td
RMMCCodeEmitter.cpp
|
| 179821ac1f282ef6f8d24d5ea346028aee8ba4c7 |
06-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the instruction fragment to data fragment lowering since it was causing
freed data to be read. I will open a bug to track it being reenabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| c76c59840b7a4491afdcd2f35483f8d6e5ab533a |
06-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121021, which broke the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrThumb2.td
|
| ba3368ceae8d3e3f1653de4aa24f168eae8f083b |
06-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 4c386fc75488cf8663acf9527e335bbca1fbc0ac |
06-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrThumb2.td
|
| 04f74942f2994a7c1d8e62c207c4005ed4652b6a |
06-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
the instruction is predicated, reg0 otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d67641b6f804110505a69aaed5479f446bbbb34e |
06-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
not an immediate. It stores either ARM::CPSR or reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
|
| 04e2b639c13a73ac91686d484628325ee536e9cc |
06-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unneeded #include's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120971 91177308-0d34-0410-b5e6-96231b3b80d8
LxExpansionPass.cpp
|
| 714e07f75dc5b08bec391a3c93cd2ba397911e09 |
06-Dec-2010 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120966 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 167be80ee7763c5939f2d73de2c15efd703931f7 |
06-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120965 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| f79ed109ec4ead50216bbed3d80d1ccd5ad94061 |
06-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120964 91177308-0d34-0410-b5e6-96231b3b80d8
LxExpansionPass.cpp
|
| 48575f6ea7d5cd21ab29ca370f58fcf9ca31400b |
05-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMHazardRecognizer.cpp
RMHazardRecognizer.h
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
MakeLists.txt
LxExpansionPass.cpp
humb2HazardRecognizer.cpp
humb2HazardRecognizer.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 7389b98289f7fb09c1641e07044ff816a56f4eba |
05-Dec-2010 |
Shih-wei Liao <sliao@google.com> |
Fix Android.mk's
Change-Id: I4de9583db7f8d47bdda444804aecaeb71c5dfcb8
isassembler/Android.mk
|
| c24130bade8c348d0d437644b01ebdd3c65e6681 |
04-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
The Thumb tADDrSPi instruction is not valid when the destination is SP.
Check for that and try narrowing it to tADDspi instead. Radar 8724703.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| ceab50198ee0d1aa2468d868111e3cf7c0c56ebd |
04-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode condition code for Thumb1 conditional branch instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| ed09087dd30c3150a228b14fb224a3491dd6af62 |
04-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| fb62d550de4e4f17072ac1dc76e7dfebe6ba0c05 |
04-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Use correct variable names to match the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120857 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 1b555d9f960e54e9e685585435daf63d89c88a56 |
04-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Match pattern operand names to expected encoding field names. This corrects the
operand encoding ordering of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120852 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 4fa102b84e6e0ec889e99ef7ab3c05885a3e4cb1 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect BL target encoding (it's similar to, but not the same as the
ARM instruction). Add encoding of bits 13 and 11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120849 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d91f4e40e6312304c60c83c3dd93f769a39a9772 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
halfword being emitted to the stream first. rdar://8728174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 41ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
32-bit wide version by adding the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
|
| b3a04d46e8bb635727024a0ca9a8a0c4699f2080 |
03-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120836 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 6e572981270cd6485973f3d493e5403514206a57 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Reduce t2 ldr/str instructions to the correct t1 versions when there's an
immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 2ccf148fbaaf9ea15233d7ef09e31ca0fa6ee3be |
03-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120832 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 0b951ceb02c43c157022f284881da7d2f7daf58d |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
No need to declare EncoderMethod property anymore; just assign to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120831 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d253545c17d5ed70fa134c02bfca9c3f85402473 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120824 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 2c971ab9d9a52b3402d708e9a83586f04116a6ac |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 278b6e81c85a2c003282024656c11dab19900c4f |
03-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't overwrite the opcode passed into the T1Special pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120782 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 534a5e43051cc02c3139c03633189d916029096a |
03-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add Thumb encoding for some more instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120780 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0bdf0c05b990b4f2d29719b34f4ce44f16176f09 |
03-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The tLDR instruction wasn't encoded properly:
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>
Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 7721e7f279c4c01b29583011eaff48250ec6cdd9 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120748 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1ab4b211ea5165445b791277507d58dcf1e46688 |
02-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,
not thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120711 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| ce4fadf884a63527942882be449d5ea75593740f |
02-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix copy/pasto in vmin.f32 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120709 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| dff84b03258514463ede477af38f1246b95b0cd0 |
02-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for binary encoding of ARM 'adr' instructions referencing constant
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMFixupKinds.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 1bf891ae6e174ac92c1091be0c62891f4676beb8 |
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix and re-enable tail call optimization of expanded libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0c628c2617a2c25cabea6d1cb8bd13b79b3cb15a |
01-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
fixing style nit: move class static to global static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120619 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| cf590263cd5c24ccf1d08cef612738d99cd980d9 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a post encoder method to the VFP instructions to convert them to the Thumb2
encoding if we're in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 5177f79c378b47e38bed5ac05ba4b597f31b864e |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Use the correct fixup type for ARM VLDR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 5d14f9be7ba64162c7b996f36d419b11d8cdbe9a |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 9d63d90de5e57ad96f467b270544443a9284eb2b |
01-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrFormats.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
isassembler/ARMDisassembler.cpp
|
| 1920d82f75c365a72e0925fb6d4e6977ffb888c9 |
01-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
kill trailing space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120586 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 3990d8f89f130f200b367be2248dbf6a6a16e8e9 |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
10 bits, not 12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 887c0e4cbf7c80f0b6e0cdc3b18bad54c30b9d30 |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Elaborate on FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120552 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| baf120fbe8056ef68fc91b16465590fdf2311c27 |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Move the ARMAsmPrinter class defintiion into a header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMAsmPrinter.h
RMMCInstLower.cpp
|
| ff25116a097230f6fff309a73a9b0610631282a6 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove "comparison of integers of different signs" warning by making the
variable unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120541 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 43f7b2d3703987fe964985846f8a6829a66b5d69 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
General cleanups of comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120536 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 85fed5e0c5bc010f967948a4af6b425a5a2f2bd0 |
01-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
ARM/MC/ELF relocation "hello world" for movw/movt.
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
refactor ELFObjectWriter::RecordRelocation more.
Possibly share more code with Darwin?
Lots more relocations...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120534 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 0480e28fb2a7d4e140d56c39e9705c922456585c |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Formatting. It's all the rage!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120533 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 1d045ee8841a08df534b4f1c3053a49d0c15d8d2 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
More refactoring. This time the T1pI pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120532 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 564857f776084a85b6b4bf0c896fd60c69d0c521 |
01-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Refactor load/store handling again. Simplify and make some room for
reg+reg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120526 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a63bf704b4ebdc109f1514bed82fdad7ad3eb70b |
01-Dec-2010 |
Jan Wen Voung <jvoung@google.com> |
Initialize an ARMConstantPoolValue field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120525 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 40062fb7479487e3bd44944b2be0b055b9ea6269 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
s/T1pIEncode/T1pILdStEncode/g
s/T1pIEncodeImm/T1pILdStEncodeImm/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120524 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 0b424dc6b734fc5538887d1ebbd843c3a8d3d49d |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Renaming variables to coincide with documentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120522 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 76f4e1038878e1944bb3e32e8183ce8b973bc61b |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor T1sI and T1sIt encodings into helper classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| a5a42d9b3cd4bae306c2b67ede512420f70dadb3 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120512 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| ca6945e5e2ead38c99a76d69a4649965caf52eca |
01-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Use by-name rather than by-order matching for NEON operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3d2125c9dbac695c93f42c0f59fd040e413fd711 |
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable sibling call optimization of libcalls which are expanded during
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 3f8c110dc643847363686d543a56c23c41353ab0 |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename operands to match ARM documentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120500 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| b0708d292bbe04cfcfe0c5cb5e27d8a872c9839a |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120499 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| d309b413a5a246e006a63f61aa9052effd8b4c7e |
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120497 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| 61db62990b4bae51c5434b1a494a7ee30fd2af26 |
01-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Thanks to JimG for catching this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120494 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 2cbc9fe83741f9239aaf99c5b71bf3635f9af9da |
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Inline classes that were used in only one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120488 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 1fd374e9c1c074c1681336bef31e65f0170b0f7e |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrThumb.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
|
| 80dd3e06129e2b570cbd65cba850571981df693a |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMMCCodeEmitter.cpp
isassembler/ARMDisassembler.cpp
isassembler/ThumbDisassemblerCore.h
|
| 97dd28fb89dc4c4caa3c60890335dc99489981a6 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix handling of ARM negative pc-relative fixups for loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120480 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| c7373f8158c162509ce7aef932ccf01aa9419de7 |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for a few miscellaneous instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120455 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c02ba66d4140ff18b3b93b237fccfc0903213225 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120451 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609 |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add encoding support for Thumb2 PLD and PLI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 06a86da3238d9f2234cb7eb7ca6bdc73b65bc408 |
30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Noticed this on inspection, fix and update some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120447 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2e812e1635422d0ec71cb4bda3f4d654857913f1 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize ARM MOVPCRX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120442 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| eb05a8d250fb4da51279efc59e99a54eaf5b60ed |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide encodings for a few more load/store variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120439 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a0d2c8a40f890345237abfa9cece16c517e1e280 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
rdar://8685712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120438 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrFormats.td
RMInstrInfo.td
|
| ef4a68badbde372faac9ca47efb9001def57a43d |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
|
| 0e45a5a9016ce36675409fb358c3e801b7a1d12d |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor cleanups. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120372 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 6e46d84eea97792a66c0bb64f26aad3976a23365 |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.h
isassembler/ARMDisassemblerCore.cpp
|
| 647fea57fd56b7c0e24f98e01f2a70fd265cc461 |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
able to match this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120369 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 532c2f1d503a42c5e8e0c5c9a513c459fed73d25 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction
and which are pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| 67077419c63d7714f8254cca12489e7a13e8684f |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add some encoding for the adr instruction. Labels still need to be finished.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120365 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 6af50f7dd12d82f0a80f3158102180eee4c921aa |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Correct Thumb2 encodings for a much wider range of loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 5c86a0a2b5005a37c791c75882b5b3185c61ecb1 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Make a few more ARM pseudo instructions actually use the PseudoInst base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120362 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8ca2fd6665dd9ba5d527fb4c78de4861842e2411 |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Predicate encoding should be withing {}s. And general cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120361 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 194271a76e5b41ed2765449abf55ff85e092da68 |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Predicate encoding should be withing {}s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120360 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 8e0c7b52877983b4838e54e233449912fc1a2325 |
30-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix the encoding of VLD4-dup alignment.
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| 173fb1421ac03999561e365d8413e8983189dab3 |
30-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename VLDnDUP instructions with double-spaced registers
in an attempt to make things a little more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120357 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6c4c982f83eea655e0f14610d2689fad722aeb7d |
30-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD3-dup instructions.
The encoding for alignment in VLD4-dup instructions is still a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| e76473d9ba1222cb38958d5b05204417e8c2f469 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120354 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6e4221153bf0f2b6acda93f08b08155e3628bf4c |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize ARMPseudoInst size property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120353 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 00a257af5b62df1921e3df3ee2fa4adc2ccbd297 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a few missing initializers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120350 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 03f44a04e63ff77af12df33e10ffdc473609dfe2 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120344 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cd3c7cb9159bf80e6847c6d3c182ee4ae5e02281 |
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a FIXME. No need to be fancier here, as ARM handles constant pools
locations and formatting specially. rdar://7353441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120343 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 75579f739fbc99a92a15f3ce75bbd7628ba00f8c |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for basic loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 1e0eab122b6981d7180337aef2856851616c1183 |
29-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark Darwin call instructions as using "r7" to prevent the frame-register
assignment instructions from being moved below / above calls.
rdar://8690640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| a0bb25311925079117de74e2e5a5fba8be4e91b4 |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke dead isCodeGenOnly annotation and extraneous comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120338 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fbf0cb18cbf74ef551c6e9f1cd8bd2c6541d7171 |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120335 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9b0e92ca5b65eb20ee51e67fedeac8288a1eccde |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Thumb encodings for conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120334 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 5ca66696e734f963b613de51e3df3684395daf1c |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
instructions. This simplifies instruction printing and disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| a46a493c026cb60eec461f40318ce7ca7574f1b5 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor some of the "disassembly-only" instructions into a base class. This
reduces some code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120326 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7bb5996e474806eee2fde0f446400ecbab59e4ae |
29-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Update fastisel for the changes in r120272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120324 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d092a87ba3f905a6801a0bdf816267329cf0391c |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
|
| 5404c2b36e7f4451c29d1a070fb090c59aee552a |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Improving the factoring of several instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120317 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 86c6d80a7a20fa7decc3e914be5d1cb0f7f29a6f |
29-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD3-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 2fcda63763ef010c57f6e7f250868e355075f6cf |
29-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix copy-and-paste errors in VLD2-dup scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120311 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
|
| f1aa47dc1aed018e2f70ffe7d32dba51e2ac45fe |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Pseudo-ize tBR_JTr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
nstPrinter/ARMInstPrinter.h
|
| 00a035f74f85e2f05dd641cf7a0eb1d466a270cd |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Thumb2 encodings for MSR and MRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120309 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d18a9c9b9d7136c50daee7e5b43dd69da1c0aa52 |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Thumb2 encodings for system instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120307 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 05bf595122154b45dfc4e23b459878a4b5224559 |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Thumb2 encodings for branches and IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120306 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 11fbff8085850a112ec50a6ba5c3bb4de37b432b |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to
get the pretty-printer. That's handled explicityly by the MC lowering now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120305 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3cc52ea33c0b96d1682f14fc45c45b57df0f39b6 |
29-Nov-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
I swear I did a make clean and make before committing all this...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120304 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 2dc7768d73c9afa3a23b86ee7827bc8de426f459 |
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrFormats.td
RMInstrInfo.td
|
| 2f17bf2a4406d89b5e127306cbd0fc862e0a6bd5 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 5cbbf68e35a053c904548564da13d4a8596f988b |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
More Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120278 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d19ac0c75a019273e03922e2252ed262578a43d1 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add Thumb encodings for REV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 849f2e381e4e83dc4f60e4a1fe6e6bb47bde8248 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120272 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| b1dfa7a8e0c1972231bee636afd5239b009ba4da |
28-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD2-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| f3d2f9d4be5beaf4c37b071373592da55fb44d1d |
28-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Another minor refactoring for VLD1DUP instructions.
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 364a72a8e5810561613491bef0de6f301ee4925c |
28-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add entry in getTargetNodeName() for ARMISD::VBICIMM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 94c5ae08750f314bc3cf1bf882b686244a3927d9 |
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move more PEI-related hooks to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameInfo.cpp
RMFrameInfo.h
|
| cd775ceff0b25a0b026f643a7990c2924bd310a3 |
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move callee-saved regs spills / reloads to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMFrameInfo.cpp
RMFrameInfo.h
humb1FrameInfo.cpp
humb1FrameInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| bce55776af16b70408e2ae2e6d91f8ac1e43f6a7 |
27-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor. Set alignment bit in VLD1-dup instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120197 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2a0e97431ecef2aa6a24a16ced207d5b53fcfc2d |
27-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VLD1-dup instructions (load 1 element to all lanes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 8d412946643f048daa9d76b4f021a172341ea045 |
27-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
|
| 36d76a8dbc87b62de82a4a8c0d7cb4bb2a202934 |
27-Nov-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Switch to using MachOFormat.h.
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| fd46797d0da4970a40f8b5648b8f9b186ce5adb9 |
26-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the unused TheTarget member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 13534672deffb571d90f2c2f0a237c67d5aa0594 |
23-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Move the ARM reloc constants to Support/ELF.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120035 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
RMELFWriterInfo.h
|
| 626613d5e8805db1f40e956faf47c87bea3aee44 |
23-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
We need to check if the individual vector elements are sign/zero-extended
values. For now this only handles constants values. Radar 8687140.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
|
| ab5c703fdb0b07c6d89271519fd1cca7105b3eae |
22-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix epilogue codegen to avoid leaving the stack pointer in an invalid
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMFrameInfo.cpp
humb1FrameInfo.cpp
|
| 3d93893895e5ae86e7c32da4329a8c0ec1a6ceb1 |
22-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Fix a compiler warning about Kind being used uninitialized
when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 9d89311df8e188ce55faad3e49842c7f8d6a0818 |
22-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Pseudos default to 4byte size, let the instruction size field notice
that branch tables are special.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dcf0a47b765567596957db407d5388864d41e635 |
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
More Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119940 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| af2b573614c7d853879ff24eb9a86d1c36acc198 |
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for ARM "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9717fa9f29696bca45ddfdf206b1c382c8b40b78 |
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The "trap" instruction is one of this which doesn't have a condition code. Hack
the code to not add a "condition code" if it's trap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7d0affdf02f5bbdda5f6ee067c5003f87e9ccc39 |
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
- Give "trap" the correct encoding, at least according to Darwin's assembler.
- Add comments saying where the encodings for other instructions came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119936 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| aa54524a44a5c1a0a3f4a85f113fc4f510566aa1 |
21-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Use by-name rather than by-order operand matching for some NEON encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119923 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0eb49c57f0163d590567bb6ac13e4bd307bfd1d7 |
21-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119918 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5cc88a205dc8c3009cd7f2b8165c2757082871a5 |
20-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
A few more thumb instruction MC encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119913 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 827656dab4931a512d6d994d9c61d280a2651dd4 |
20-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite address handling to use a structure with all the possible address
mode variables. Handle frame indexes in load/store and allocas again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119912 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 13df1a0baca2af78e24919e6a52b452f4d45f32f |
20-Nov-2010 |
Eric Christopher <echristo@apple.com> |
STRH only needs the additional operand, not t2STRH. Also invert conditional
to match the one from the load emitter above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 82f58740c76b42af8370247b23677a0318f6dde8 |
20-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move some more hooks to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameInfo.cpp
RMFrameInfo.h
|
| a09cc2b42938db39301cf1ebe159491ff2f16581 |
20-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb add instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119883 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 95a6d1759d7b1ad144703046eaf30ab579aa9d71 |
20-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add Thumb encodings for some add instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119882 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 6179c31e0745eb872d78df17a72255d840fa486a |
20-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more encodings for Thumb instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119881 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 20272a7c5a0ecb02364fb03ccde5a0d4533cb3d7 |
20-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
value that the one in ARMMCCodeEmitter.cpp does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 078e239f6948d4a942e16db3868908e503a51efb |
20-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM LDR* post-indexed operand encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1228038ed93504b0a34878dc659cca98092a1f2d |
20-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encodings for the compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119868 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| b16926940e8857438d38556b288f149ebcc1b18a |
20-Nov-2010 |
Owen Anderson <resistor@mac.com> |
The Vm and Vn register fields must be the same for a register-register vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119867 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ff96b63d6fb0b6e6eccdabcbdc4eeeb69e54c648 |
20-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a cut-n-paste-error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119866 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7b6ab402fe201598dd38d9338078d74c4d0783c7 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Operand names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119864 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a30a51b16a002dc51e206ea467f2c4ab7ca18a77 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119863 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| b37165808359c71b20291de51368f9efb65e7108 |
19-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Don't need to save piecemeal now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119862 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2d630d7bc9ae746d353211c3532dfa8e4f0ce9d5 |
19-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119861 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0ae28e44479595ccea9b1a43a152c01224b625bb |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for some of the thumb ADD instructions. Tests will come once the
asm parser can handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119860 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 88de86b550a1fd19dd968cafac48e810f1da5254 |
19-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119859 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| efaeb41aec9bc54467e7c6d24ed628666e7d3aca |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Clarify operand names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119858 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0d58122e1221665d421a53741ef638505ecbe745 |
19-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Refactor address mode handling into a single struct (ala x86), this
should give allow a wider range of addressing modes.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119856 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6571101cb727740951a452d667479cea3f17bc3b |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding for ARM MLS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119855 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2aeb6121a19aca7c317619f7ec37d7a770e9f03b |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| a1b4175b8e2d8f95498a8148586734c4e44f342b |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Shuffle things around a bit to keep like things together. Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119851 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ba46dc06e68cf6b3708cf41b737cb485152f31be |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119850 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| a898166d3863b163ee87d69a4e4a487a5a92af43 |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Change long binary encodings to use hex instead. It's more readable. Also
initialize missing bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119849 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 953557f445ba749e0ec95e43bc5143849d1fd99b |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119846 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| e2d54af47f67f3a868f96a4d9856042c71244814 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Delete another dead class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119844 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| fc0cb4b90673eedfa36024bfee21ef6af3d50101 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
whitespace tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119843 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 9ef65cbbc6f23ee8c44b065d3a4feea11c471a2f |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119841 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 9558b4cdc4d12079250fe1d6302b954c7dfc0010 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119840 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 9cb15b5be51b7e36f3fe0c9ee256eb9c99b9d796 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM binary encoding information for the rest of the indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119821 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 0c2283a910fef6347ddc46196cf37b4ff7e87fb6 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119815 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| f1ce7cc1d19309e5cb086739471f4dc04728117b |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 3ea4daaf5043ba2d4745f43c5dc2e44c0305ca00 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove hard tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119810 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7a08864860d68af2fdd70496601378e5e1b1c15d |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7920d96964d707a3af85332c98d95b2fabc3d5c9 |
19-Nov-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Avoid release build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119804 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
humb1RegisterInfo.cpp
|
| 8b8640a9647ecbd461e20ec8ac823c7e5271835f |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fix decoding ambiguities of stdrex and ldrex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1f190c8bdf1d74c029c85b0865c983f3f9cafb31 |
19-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
These instructions are thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119793 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e8e67e13d49219bc0acd73961f3b2dd2ccb90cf4 |
19-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119792 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 602890dd8ef53c6e8d60a2752b97940f7a58de1a |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119774 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| cb21d1c9fd1cf53f063183f7eb28af7fa4052ef0 |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use array_pod_sort because the list is contiguous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119769 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 91a7c59134fa331a8a5560ea0a96dd4ca50fea5b |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for strex and ldrex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 817c1a6dddadb4664738777d224bc7eae6e62cf3 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Minor cleanups to a few llvm_unreachable() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| d1fadd8c5d6a4e953323690860ba90e63d04cd2c |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
An 'unreachable' shouldn't have a '0 &&' prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119762 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 50d0f5894448aff6eb02ad63da55ecf26b54aeb8 |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for parsing the writeback ("!") token.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 837caa9313e1f9480721f232f89f5c7b1b9c9d09 |
19-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMELFWriterInfo.cpp
RMFixupKinds.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 71c11825bf1673baad44274ff71e8df1be938f5e |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 75b7b879c078366d3e7d90360f01a6e7c0a75b68 |
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Encoding information for UXTAH and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9684a7c1281e7d7f6d7ab7c3f8484fe2138f39bc |
18-Nov-2010 |
Tanya Lattner <tonic@nondot.org> |
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 24d22d27640e9de954a5ac26f51a45cc96bb9135 |
18-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't allocate the SmallVector of Registers. It gets messy figuring out who
should delete what when the object gets copied around. It's also making valgrind
upset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119747 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8ee9779658d61a426e52a2010522ec8914b8efdd |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119744 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c884aff5f4d431b31b5f85ce8a208dba30bd72df |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for LDRH post-increment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119743 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMExpandPseudoInsts.cpp
RMFrameInfo.cpp
RMFrameInfo.h
RMISelLowering.cpp
humb1FrameInfo.cpp
humb1FrameInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| d5448bb6e845bd6c2dcb98156f49a73842759ab0 |
18-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Split up ARM LowerShift function.
This function was being called from two different places for completely
unrelated reasons. During type legalization, it was called to expand 64-bit
shift operations. During operation legalization, it was called to handle
Neon vector shifts. The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function. I don't have a particular testcase for this; I just noticed it
by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119738 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 612fb5b9a6472f8e1cea8a4f771238840f4eaa1c |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119737 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 821752e2e601b2e4c0bb83cb341892c853f16d0a |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out the set of Thumb2 multiplication operator encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 707120047e0107cb15dd4bbb31613df129b13c7a |
18-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Missed the _RET versions of LDMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119726 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 8b3ca6216d62bf3f729c2e122dcfeb7c4d7500dc |
18-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite stack callee saved spills and restores to use push/pop instructions.
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.
Adjust all testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.h
RMFrameInfo.cpp
|
| 056ab107ff8e818258c39b1f1e318b2aa1a417fc |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARMPseudoInst instructions should default to being considered a single 4-byte
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119713 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 5c71c7a13715ed6f5bfdd5497172ddec316b68b0 |
18-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119610 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1251e1a8df29099332294b99f68a6b27dfcf0271 |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119608 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 99594eb1dec2ddccbfbc995d828ce37ad829ec87 |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
the operand to the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119607 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 1b4886dd00578038c0ca70b3bab97382b89def26 |
18-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119604 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c6961f140ad9bb4da6554c12a4a6af4cd2dab54a |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119603 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 53694265a9e571aa53087ed0d5b770fdede12394 |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
just pretend to be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119602 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 35141a9ba3ce92281cdbe1ccd0f6b5a42398249c |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Try again at providing Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119601 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 160f8f0e6779b76c7713036c8580ae25c5aad586 |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor a few ARM load instructions to better parameterize things and re-use
common encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119598 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 424216453fe2d16379fbb6c3310004b997d3771d |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119593 while I figure out my testing disagrees with the buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119597 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 18333616cd824bee3abecd607d3aa432b5cf507d |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119593 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 85eb54cf0cfb0f328669080c45cf8cc298aa2868 |
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
it as such. Add some encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| 2f7aed39a3082a3e0bb35475e8ed0cb782fef4b5 |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at correct encodings for Thumb2 bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0129be281eea2c22a925873f2e1cd5cc978ae87c |
17-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 05646099a0b7ebd97571354d658a142e4e4c94c7 |
17-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARMGlobalMerge to keep BSS globals in separate pools.
This completes the fixes for Radar 8673120.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119566 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 619a3726177c63a14e2822a80e6bc897be2e5a91 |
17-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARMGlobalMerge pass to check if globals are entirely within range.
It is generally not sufficient to check if the starting offset is in range
of the maximum offset that can be efficiently used for the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119565 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 72831dc905c2354fc08762dbfd5f1b20fbd5b18b |
17-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change the symbol for merged globals from "merged" to "_MergedGlobals".
This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119564 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| edf046716ce7d0da9479c37a5bbb6dd33ce6d390 |
17-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes.
It was mistakenly looking at the pointer type when checking for the size of
global variables. This is a partial fix for Radar 8673120.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119563 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| f8dabac6041b2a38307a5ab0beb330ededb7514b |
17-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
in the MC lowering process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 6b19491468e44249a35d869642e7302aaacb220b |
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119558 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5aba9f694fbfb78df2aa2a228e85ba4c27f3037b |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119551, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119555 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 23465a06f4f4fa098f99cf91e81ed8f26f962f3f |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119551 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c4af4638dfdab0dc3b6257276cfad2ee45053060 |
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| f2dc4aa562e2478a73fe5aeeeec16b1e496a0642 |
17-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
make isVirtualSection a virtual method on MCSection. Chris' suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 46c478e80255bb1475e712ebb119808a9d0b9e12 |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| df8d94da01ccae58c93b03a5fb93fa1f05799c2f |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add missing opcodes now that this function's used in more than one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119539 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 89e14c7579d9351da2e39a85703882bac3a83980 |
17-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM encoding bits. LDRH now encodes properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| baa45f7298c266f0f89b17e50e9d98709dde84d7 |
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert r119109 for now. It's breaking 176.gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119492 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3642e64c114e636548888c72c21ae023ee0121a7 |
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Simplify code that toggle optional operand to ARM::CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119484 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b75c651e22a63907b727664f044283bf9c9fb885 |
17-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119462 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMTargetMachine.cpp
|
| 2567eec4233d58a2a0cbdcafca9420452689b395 |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The machine instruction no longer encodes the submode as a separate operand. We
should get the submode from the load/store multiple instruction's opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMCodeEmitter.cpp
RMLoadStoreOptimizer.cpp
|
| 0f6307561359fac4425a0b9e512931cf96c1ec5b |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
smParser/ARMAsmParser.cpp
|
| 6bc105a7b9282a0b5beb9d06267b31a3054fb3fa |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add binary emission stuff for VLDM/VSTM. This reuses the
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119435 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 3380f6a4d0f88fa27ac7112ffe0ad9b55f589828 |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the correct variable names so that the encodings will be correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 7911916cf7a819c2a303ca143f7c28b0c0f99d12 |
16-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM conditional mov encoding fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119354 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1eeb2806cbfb27db6a842f586d498ef12a933608 |
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
L_bit doesn't work here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119325 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7b71878d9f490dbdccd39a7f8e813cab58fe8503 |
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
- Remove dead patterns.
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
|
| 73c57e149cc96abc74d6c67f9a09f14d687101c9 |
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
vldm and vstm are mnemonics for vldmia and vstmia resp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 73fe34a3ee866867d5028f4a9afa2c3b8efebcba |
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMExpandPseudoInsts.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
nstPrinter/ARMInstPrinter.cpp
humb2SizeReduction.cpp
|
| 27ead00b8a99ce29e9e5d7d6268da5995d56895e |
16-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for mov and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c56dcbf641f1675579e23064b1c7db1c73ca712b |
16-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for mov and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e1b76d67dc649ab1c558d39946460a2752ba2332 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide encodings for some miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119187 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| da663f7b51acdc076eb40cbaf197816ca26ff64c |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide encodings for some miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119187 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8c5826be10ecf5eca355a0c9110b4f1d0865d5f5 |
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. The peephole pass should be the one updating the instruction
iterator, not TII->OptimizeCompareInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| eb96a2f6c03c0ec97c56a3493ac38024afacc774 |
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. The peephole pass should be the one updating the instruction
iterator, not TII->OptimizeCompareInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| f5cc5f76333b67656c47de5a9cd593ce7bba2fed |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for sxtb and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2c4c45deb6a7a8521f6039e3da9688be4cac09d2 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for sxtb and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d6b12afee3fa4ecccf9ea1841acfaf31515bb101 |
15-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Recommit this change and remove the failing part of the test - it didn't
pass in the first place and was masked by earlier failures not warning
and aborting the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119184 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 76dda7ec1d8d0ee65a103b6710ab75c2a9e012d1 |
15-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Recommit this change and remove the failing part of the test - it didn't
pass in the first place and was masked by earlier failures not warning
and aborting the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119184 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1e30624e0cd61521c7d2c784c85460f6cc0c45c6 |
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 99f53d13efc259b47c93dc0d90a5db763cbe371a |
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 7cec86017183390b04b054007a56ab4b2c0b0de2 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for comparison and shift operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| bb6315d1e48f24e0eefa98b0f572fda8dbb3251f |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for comparison and shift operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| eb4a8e300d3ada654787254a9fc43f1bad8c3fdc |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for mvn and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a99e778ed894402a4468ad0b695716226471d726 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for mvn and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4e95530f2396a9c2fed16a27aafe87cf01bcdc93 |
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119167 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 11bbeecdf1dd07599e644577bd56ea89294d0d04 |
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119167 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a2cb4d2d388088ab0bef7adf3e12bc3bec7ed2b9 |
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke redundant encoding bit set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 17e967eac2dec4ab0b7d3ce7ce6b348d6a275cb9 |
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke redundant encoding bit set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e29edfe062b2e073da8ed6aa123ccddf74838340 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 2ac190238e88b21e716e2853900b5076c9013410 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| e2831db8d962cfecf9820a384aa2aca4368c9728 |
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119109 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| fbc8c67992d8c8b0f4ea07b29cf31a4f0c1b28fe |
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119109 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3240bd8146a525e65fe2f132773736cb186fc4ea |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
silence a ton of warnings from clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119102 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
|
| 65a0adb5978d44c791d047cb44792785abf71e4b |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
silence a ton of warnings from clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119102 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
|
| 972882d91a6041801fab51ba56c6be498e1cfc24 |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Attempt to unbreak cmake-based builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a460e4a1427260bd46171e674d0a4c41cdd6313f |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Attempt to unbreak cmake-based builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| b87e6afa1369ea12e485b1037184f78e42dc73df |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameInfo.cpp
RMFrameInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
humb1FrameInfo.cpp
humb1FrameInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 33464912237efaa0ed7060829e66b59055bdd48b |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMFrameInfo.cpp
RMFrameInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
humb1FrameInfo.cpp
humb1FrameInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 88fda4d8db965a8ec3ba87cadf92cc922ad7ec30 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119075 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| 77ec256be694d3df4604e7fbdf4d6e9cc0fcda33 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119075 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| eb4a44aff329512abf114ac5b3a32784f271ce03 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMMCInstLower.cpp
|
| 30e2cc254be72601b11383dda01f495741ffd56c |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMMCInstLower.cpp
|
| 43dbf1b574add946fabc3fa4009fb9dd35195b3b |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
even more simplifications. ARM MCInstLowering is now just
a single function instead of a class. It doesn't need the
complexity that X86 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMMCInstLower.cpp
RMMCInstLower.h
|
| 1612a619f18cbb328df5b2d8d268dd5e02a4a483 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
even more simplifications. ARM MCInstLowering is now just
a single function instead of a class. It doesn't need the
complexity that X86 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMMCInstLower.cpp
RMMCInstLower.h
|
| 163c75f642bcf00432738fd45f723cfd7b972a5e |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
more shrinkification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
RMMCInstLower.h
|
| b16ddb1fb3de22f4bad48d0cbc00e8b067463a64 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
more shrinkification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
RMMCInstLower.h
|
| 32af12c9d5c71429cfd622f687625bcf0562ef82 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
more simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
RMMCInstLower.h
|
| de36af4c157b0df6fd089b8fe965904761c2b5e1 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
more simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
RMMCInstLower.h
|
| 83a6356bad383147afd5219dfa5e9cc0f11b7dca |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
simplify and tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMCInstLower.cpp
RMMCInstLower.h
|
| 112f2390e19774a54c2dd50391b99fb617da0973 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
simplify and tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMCInstLower.cpp
RMMCInstLower.h
|
| 2a9137b38c78cff810ce7265b75fddd65332edef |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
stub out a powerpc MCInstPrinter implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.h
|
| 60d5b5fdeec64b69c92db60242d3d90b3f978e69 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
stub out a powerpc MCInstPrinter implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.h
|
| b2b0ec48661a6e5f1956da4317dc17a6d4bd3039 |
14-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at providing correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 83da6cd5e2d84a7d247f7f8af745763f550c1af5 |
14-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at providing correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b098011b0927011f9f51a24f5b66f18f4ed3f350 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment out the defms until they're activated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| c93989a0606daff0e96c34790e603b1dd5ca966e |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment out the defms until they're activated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5c45266c4c183b9d8c2bbf07f2ec89c703d4e0f0 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| ddc918b379d448d8fc8f249459eee5f3772e07e9 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| b249e75ec90c83f1bd052c3a9eb32d0d6b9fb62a |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Convert the modes to lower case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 1f4abcfa5cf2a2d929d95714078ac16ebacba7d8 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Convert the modes to lower case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 9b19707e6bcd2c38bf845a460c6c0038e36b9469 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor cleanups:
- Get the opcode once.
- Add a ParserMatchClass to reglist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
|
| 04863d06fb3f2972355c990b29edcab1d9a85b41 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor cleanups:
- Get the opcode once.
- Add a ParserMatchClass to reglist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
|
| 8fb906e1a45a1ae59d118faa2b8d745eb885ccae |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 6c470b806fe8eefae1b7bf180f269a4b120173a4 |
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| b43be3dc3e0f90a3110ef8a23d05ed62c67a557a |
13-Nov-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Simplify Mach-O and ELF object writer implementations.
- What was I thinking?????
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118992 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 115a3dd066c277c5417f4d9b9f642b732b76f4e7 |
13-Nov-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Simplify Mach-O and ELF object writer implementations.
- What was I thinking?????
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118992 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| cb52334ecbb99bd4807329534ec251a88acd4265 |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Conditional moves are slightly more expensive than moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| c47f7d643eee54c087bbe4c9964aa4d5afb7f6fe |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Conditional moves are slightly more expensive than moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| eb1d6de0bb40ca19640943b7b03bfa31fa333df5 |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional move of large immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 63f3544a7f6ca09e7515d6b0e1bf9e8e884131e2 |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional move of large immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 08cd8844e4e878229a5bd85636c47fe6ae971e99 |
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Swap multiclass operand order for consistency with other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| df7e0f8d5de7feb82923f627062c774e31e74e48 |
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Swap multiclass operand order for consistency with other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e4e1d9829cf9632ed0155bfe32edc1ba96dbe4d8 |
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0f6e33b0c83eb6db0a059dd9d16798d919725b94 |
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8018d300c149a2a58375ddba9d90df71180db34c |
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
flag for the LDRT/STRT family instructions as a side effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 9e0bfb58298cab01625e56c49bac23f52bf782c3 |
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
flag for the LDRT/STRT family instructions as a side effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| a3c5f6178a4eb3786bb09a063606a95a28a234fc |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious typo which inverted an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e5e0ef180ea1d0d7b482f998db12defde96cbf4f |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious typo which inverted an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 91b85c341624502e148b32b31960e554ceffcde7 |
13-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Temporarily revert this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118946 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 84e86c0156a6562bba87a0484ef24c2de4f641d7 |
13-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Temporarily revert this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118946 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 50b3ab9ea7cdb9dc1c51556991bce9d0cdd06519 |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 11c11f8ab0e97150998db2a44cec9d334b0bd154 |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 7b1de199d6356e539078c2407cfff5158811d2c2 |
13-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r118939 while I work out why it broke some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118942 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b9a643e2cdfe0ee9f99e1e32ccdbfd3ddf13a46f |
13-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r118939 while I work out why it broke some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118942 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6a2528802c7daa7efe033af61c9a3950a73966af |
13-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attemt to provide correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7a6b810dcb3f25634f46462914b3d22985b8559f |
13-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attemt to provide correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7bda3adcb509f837b10f418d94707498a388ff9b |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMExpandPseudoInsts.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
|
| 893d7fe2098cc81ba1b4ce0ed71f6f614843961f |
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMExpandPseudoInsts.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
|
| 64536716fe2343fe0e12fde5a687c2e8e44cd602 |
12-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Make this happen for ARM like x86. Don't entirely bail out when
an address is in a different block, get it into a register and go
from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118936 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| c0394c0b8cee513a624566ce1db100bd66d4da57 |
12-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Make this happen for ARM like x86. Don't entirely bail out when
an address is in a different block, get it into a register and go
from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118936 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 506743bc02133fe51a0302779dbf88a7d38ef67b |
12-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional mvn instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 875a6ac09a2a4ae2d83dfe262a81d6eb33c24022 |
12-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional mvn instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 40338cce58d9e3176a9a48f01c888b1d277cb5dc |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Zap a copy/paste-o bit of dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e1634e935123d7e6de540baf8510618cf58afe3b |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Zap a copy/paste-o bit of dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ff7260bdc99e53152288b49c56a28fbf7afcde11 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 2716e25c2cee61e95bec3d17b49ca37a48b4cfab |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 0d5d833eaee85389cee84daae39691c75faf728e |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
First stab at providing correct Thumb2 encodings, start with adc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| 5de6d841a5116152793dcab35a2e534a6a9aaa7a |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
First stab at providing correct Thumb2 encodings, start with adc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrThumb2.td
RMMCCodeEmitter.cpp
|
| ab1df1f1da3becba7956c79c4002f2f6355f0550 |
12-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrVFP.td
|
| 529916ca4ab83ec472a2d7039a05007c4d40553a |
12-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrVFP.td
|
| 9750f91a399a256d2664e2cca5d7bd3d25faa69e |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Kill more unused stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| b39e6488eef7a5ff8b4e6acf0d42d096f5be853b |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Kill more unused stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 8f3f214fd780375c90217adc8ba848282e30e2f0 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a0a6a47c02d360e8a167a6a28f03a3b453c38fbb |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 75fe9b9c0156dad0ebf0021ee7e0f2b5a515f5b2 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fill in the default predication bits for ARM unconditional branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d75c3f136b2f7496d177b868956a4489d4b980b9 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fill in the default predication bits for ARM unconditional branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3e7f4a4567b387c01e47f9429e752724755da667 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 80f9e6724fa98b5af0bb43f58002c1ac3e9cb30b |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 776f92fcb090ed2ea379ba7d75a8560633181f13 |
12-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Fix up a few more spots of addrmode2 (or not) changes that were
missed. Update some comments accordingly.
Fixes rdar://8652289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d0c82a683e965f326e36a2bcaa85c00e917f8282 |
12-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Fix up a few more spots of addrmode2 (or not) changes that were
missed. Update some comments accordingly.
Fixes rdar://8652289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2ff865a92f1c29619b38e894f4a724db38a56f40 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Start of support for binary emit of 16-it Thumb instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| e50e6bcd901ebb1cfc42fe9ca0796ae303d7f1a1 |
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Start of support for binary emit of 16-it Thumb instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| b2adc06c2e963ca9af94c1b0c154c599496b7a0e |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out support for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 8f143913141991baaa535ca0da7c8a81606d6392 |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out support for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 42d0aa8e8035a3899bb8a652f6f7786791c86565 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 57dac88f775c1191a98cff89abd1f7ad33df5e29 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| a33b491422896729f0f46fac929d890fe47fff00 |
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Revert the accidental commit I made reverting the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 79ab2fe01a39a2fffe4e901ef3c96b6b943412a0 |
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Revert the accidental commit I made reverting the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 927caad7ee747d9cba1c4ba8534c0b8c2b6db522 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM fixup encoding for direct call instructions (BL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d1d5a39cada320949353e8b2c59b6a160a67f7bf |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM fixup encoding for direct call instructions (BL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fa0ce020983c9302473dcf656152b6cbb2d9dd5d |
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Revert this temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMTargetMachine.cpp
|
| 6c50119ba33bf22885d2229726c809539a85c247 |
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Revert this temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMTargetMachine.cpp
|
| 01b88edadb7526af91d5db570ea41f01a287244f |
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Change the prologue and epilogue to use push/pop for the low ARM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 391f228e7e00f62b79ad483b801f5f58f046b7ea |
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Change the prologue and epilogue to use push/pop for the low ARM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 79ecaa7de5ede4475ffdd30c48093c885397ffe9 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| c7139a6f0d3acd198ab9eb536ea1ec52e61ff130 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 43bcc3ab69a55bf0cf8c11f4b702092676ecca17 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding of destination fixup for ARM branch and conditional branch
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| c466b937dbdbaabeef0097fe340de1b8f49a3508 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding of destination fixup for ARM branch and conditional branch
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMCodeEmitter.cpp
RMFixupKinds.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 219358c134c3539f4a7cc110355633f4004dda39 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSH_POST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 7eab97f260ba0f56d1d4a82f3a4eb2c979452011 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSH_POST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| f05ba339c1ec78d6476cbe0f0ea0cbf4e9805837 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 928f3325a70384ee91af5768f628cf0748879b11 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 9b0387a3ec5a35a18cf53c1826f435bff1c33549 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding of Ra register for ARM smla* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d507d1f616be89b2327ebcd420a42075e59695b0 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding of Ra register for ARM smla* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2dbf8f4ff196eddb21ebc59095c21547372f759e |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 570a9226913ebe1af04832b8fb3273c70b4ee152 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 734aac12ee1334397dd2b9f7a070b93f5f78d58b |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Move LDM predicate operand encoding into base clase. Add STM missing STM
encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 954ffff79bf2f48ac6fd8b4406fe51e3d19440e3 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Move LDM predicate operand encoding into base clase. Add STM missing STM
encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 64a300e4ac281fe84470fb10e56c4f3f7edba1f1 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM encoding for the mode (ia, ib, da, db) operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 5d5eb9e3817a2765297e6dd5649ecb9b8b03e334 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM encoding for the mode (ia, ib, da, db) operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| c5d5f9cd53ba6054c36a7437679a332ad6421ea6 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM encoding of non-return LDM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| c1235e2a4eff7ce61ab15375f6686238c39ab304 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM encoding of non-return LDM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| dbb532831985861ebcda6ce79f7de1a3a1ca5f04 |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM encoding of LDM+Return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 866aa394ca72ca015e65fff55043bc1120b3b58d |
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM encoding of LDM+Return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 24ed1da6ab61b7fd404160879e2180626e40ab31 |
10-Nov-2010 |
Nate Begeman <natebegeman@mac.com> |
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bf5be2654ee396710e28d83d2afebd6f22720c52 |
10-Nov-2010 |
Nate Begeman <natebegeman@mac.com> |
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 943948dbf8c94f7fffeabee4ffa26b5f192c960d |
10-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7c7ddb21c3cc65ea08de8f90bb97cbdead3173f8 |
10-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| df17944721c87c09f55750761c9ccce10a5e55a2 |
10-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2c4d5125c708bb35140fc2a40b02beb1add101db |
10-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d4c610f4dd6945d2e718fdf21e8259e49fe700fd |
10-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Emit a '!' if this is a "writeback" register or memory address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8ea974039a8811ff83ad2c45ec1037ac78e5afab |
10-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Emit a '!' if this is a "writeback" register or memory address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3a7a8d6a32d2cb9438ad4d6fecfa9a711e47a651 |
10-Nov-2010 |
Matt Beaumont-Gay <matthewbg@google.com> |
Rename a parameter to avoid confusion with a local variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389d |
10-Nov-2010 |
Matt Beaumont-Gay <matthewbg@google.com> |
Rename a parameter to avoid confusion with a local variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| afea8497c88d19080f4ef844ad0b898bfd96f534 |
10-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Emit the warning about the register list not being in ascending order only once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8e8b18bcfa87ff919f127b1270a6891db1c9021f |
10-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Emit the warning about the register list not being in ascending order only once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d66b32f4234cc1d76b99079ced4fc7129329208c |
10-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
s/std::vector/SmallVector/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5fa22a19750c082ff161db1702ebe96dd2a787e7 |
10-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
s/std::vector/SmallVector/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 415373106fbe372caa4ae8fd548113344992eb66 |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Delete the allocated vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c3236753d6bb69d20003a7da441e9a42707ed714 |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Delete the allocated vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cdc0212337a79b9470fe55631a51d12340b4b03a |
09-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Define the subtarget feature for the architecture version,
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 66f6c79450a93d979128d8702c83841c8f715dc8 |
09-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Define the subtarget feature for the architecture version,
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 646f35a6145ba4c6feba57ebefa6ef7c70c4cd16 |
09-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Do not use MEMBARRIER_MCR for any Thumb code.
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 54f92563806e87f47acd04fd71e4189d35d11005 |
09-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Do not use MEMBARRIER_MCR for any Thumb code.
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0fa77dc899b53c0aa4230b41024c71e66513640b |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Two types of instructions have register lists:
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7729e06c128be01fc564870d5ea3d22d236dddb5 |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Two types of instructions have register lists:
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 11c1894d007e83af904aa79c6226ef79206b4acb |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the ARMConstantPoolValue modifier string to an enumeration. This will
help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
|
| 3a2429a86c50a89c3321c741b85fa7d1fe668b38 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the ARMConstantPoolValue modifier string to an enumeration. This will
help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
|
| 782ff938d82a3560923682c34851cd290e250404 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle ARM constant pool values that need an explicit reference to the '.'
pseudo-label. (TLS stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c9962aca8f2f2c51794996ac1e2b7731d1d1d497 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle ARM constant pool values that need an explicit reference to the '.'
pseudo-label. (TLS stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 56f9c1e73b86dc5a85fc8c15475228d67f7f482c |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 16cb3763c5a1dad7d6bcbf0fffdfc58c84b46f89 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 654d9ac45b96bde52852e564e68bb4108d4e8d8a |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Further MCize ARM constant pool values. This allows basic PIC references for
object file emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5df08d8f55f47aafc671c358d971dbcc10dfdeef |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Further MCize ARM constant pool values. This allows basic PIC references for
object file emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 3b01d74c7a56165855866afbddaa31ed7b45224c |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e0ee08e367b6af33ef005bb1c6389c65453518b3 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bc26159885d080dd66386a17dc7113e7d0ad12af |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| d92354c5742ea72abd3039cda5be37cc757d47d2 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 84b3b02c888bfe9abb2920c04610c43208a995b3 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM .word data fixups don't need an adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a9a0dde8720d94f96c4e2888801c04c88cdb05cf |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM .word data fixups don't need an adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 68291b0f3a96a589794b405196d237834bee4bf9 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoder method for ARM load/store shifted register offset operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 54fea632b161f98e96ec7275922e35102bcecc5d |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoder method for ARM load/store shifted register offset operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| f57da9342c48d3f09b86a62c1159e2eb955e31e4 |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| 679cbd3b215b1769a6035e334f9009aeeb940ddd |
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMMCCodeEmitter.cpp
|
| 05c1e0cdbac50d55253182fe9a3f22110ce5ad4f |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r118457 and r118458. These won't hold for GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 5e559a22c18166508a01fbd65471ec4e752726f9 |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r118457 and r118458. These won't hold for GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 0278827f2c43b6dd17426a3c1b482a1a90c601ee |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Get the register and count from the register list operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 4b97c55648a228305e28b4164dae9dcdebccdc8f |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Get the register and count from the register list operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| ee5c435340414c3368baeea3e1bcff7632a43974 |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
reglist has two operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3734ef3fb478cbae7baedfe009519a51db3b095e |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
reglist has two operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0285e65384d6868160f0602305fbdccaa9f9bfce |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The "addRegListOperands()" function returns the start register and the total
number of registers in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 87f4f9a946549ad93046990a364ac5190333a7eb |
09-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The "addRegListOperands()" function returns the start register and the total
number of registers in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a031d8a072e7915a5823b5bbe2b4510adf6de254 |
09-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for ARM's specialized vector-compare-against-zero instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| c24cb3551ed66830b53362f593269873cb53a0c4 |
09-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for ARM's specialized vector-compare-against-zero instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| ae6e0c887b8dc864753f0791e8a9ef9535ecae95 |
08-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add "write back" bit encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 85c3f24da311ecb00d708bc95d52e4b48c9ecf84 |
08-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add "write back" bit encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 8b58c3a84e7e12df8b62831f1b2fe46eb8d48ffc |
08-Nov-2010 |
Dale Johannesen <dalej@apple.com> |
Revert 118422 in search of bot verdancy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 7179d1e5c0acfbb0980eaf85f266cd8981dbd12d |
08-Nov-2010 |
Dale Johannesen <dalej@apple.com> |
Revert 118422 in search of bot verdancy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 77c739945cd3ba53362864c55f0a0446bf6bb5f3 |
08-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 69ad7138b7f8a884e0fb2ebf103c47d786ada8c7 |
08-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 0d1c920a1f09c088ec029a0f08755afb76eee7bc |
08-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Complete listing of ARM/MC/ELF relocation enums
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.h
|
| 6cecceb2f6900fa1197acce4c086a5c58dc21392 |
08-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Complete listing of ARM/MC/ELF relocation enums
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.h
|
| 286e89d08fa990df4faab15ab573f6e7d3ba0669 |
08-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Make RegList an ASM operand so that TableGen will generate code for it. This is
an initial implementation and may change once reglists are fully fleshed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5991487c10faa5f1c0cc815381d745150582a309 |
08-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Make RegList an ASM operand so that TableGen will generate code for it. This is
an initial implementation and may change once reglists are fully fleshed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8a76af6a9fe09099f2cb56eabd6f41f031c0aaad |
08-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b32e7844e9f79d2bd4ff34a1d19aba347f999abc |
08-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 391e949571b02bea54e082c8020d8d93616fde7e |
07-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
In this context, a reglist is a reg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e8399c6e01f5d53ddda361a5eb5952147bb25f94 |
07-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
In this context, a reglist is a reg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2f4760ebde80318c01def9f9b7640d82cd7e2970 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for parsing register lists. We can't use a bitfield to keep track of
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e717610f53e0465cde198536561a3c00ce29d59f |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for parsing register lists. We can't use a bitfield to keep track of
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ed0216bdad6919e5480c3abf038fdd136105676b |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Return the base register of a register list for the "getReg()" method. This is
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8155e5b753aca42973cf317727f3805faddcaf90 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Return the base register of a register list for the "getReg()" method. This is
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cda0350636a876dab8186aca1ccb8056da475afd |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
General cleanup:
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 146018fc6414eb2a1e67b2d8798a42a2f55ec96c |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
General cleanup:
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f41329ef997d9e000b48537f47ab446908f69030 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d79b12cd176dd5f05559770b71ad3fd7e7b8e9f3 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 12f40e9a6305fe7553ebce19346cb55874073fc7 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f88785ad0d60c11d68ebf8e33f441451aabeb22f |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a60f157b7c6fb60b33598fa5143ed8cb91aa5107 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 54a49c15d0c66ab57fe4b53fc6fb664996685268 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
MatchRegisterName() returns 0 if it can't match the register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d68fd9c79eeb30980c18dc3f74b2da839bb259f3 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
MatchRegisterName() returns 0 if it can't match the register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| bba89fe20c43653b51833e09ae4c7f85725830e3 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
while the latter doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1d6a26507bfd75758f5c8a29bccf577784ead751 |
06-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
while the latter doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a65c81e50c67504c740ab90e8f3caa81f7fefbd4 |
06-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Make sure we have movw on the target before using it.
Fixes 8559.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118333 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5e262bc94342b4ce277206cb739b98b80b8b0d2b |
06-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Make sure we have movw on the target before using it.
Fixes 8559.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118333 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e745b1374ab8a9bc8e477a19927c2db578188bfb |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Hook up the '.code {16|32}' directive to the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118310 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2a301704ea76535f0485d5c3b75664b323249bdb |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Hook up the '.code {16|32}' directive to the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118310 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| eb1a4ca9168820d466a290657384d5f620eddf84 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Hook up the '.thumb_func' directive to the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118307 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 642fc9c24ba7c43a4a962c6c05cfffce713d7de7 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Hook up the '.thumb_func' directive to the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118307 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 38b40a962f4b843fd57e828d3d314190e146c0a8 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix past-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118304 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 83c4018fcca18fe9c281c3943fc58a17621636c4 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix past-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118304 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c74e86be08dc9b31392d1dd57555d51df6cdc3fd |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
MC'ize the '.code 16' and '.thumb_func' ARM directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118301 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ce79299f78bb04e76e1860ab119b85d69f3a19c7 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
MC'ize the '.code 16' and '.thumb_func' ARM directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118301 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c3e911ee314e6a33634fc5e646ecda96cded9fca |
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 36fa3ea566c66b42e4dd7b4394be2f1e071647b8 |
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 04be6cbe163fbbc6dff7c99650040ff8a0084241 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
MC'ize simple ARMConstantValue entry emission (with a FIXME).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118295 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8da0a5785ce4f4b891fbe272177c6be14019bcc7 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
MC'ize simple ARMConstantValue entry emission (with a FIXME).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118295 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| aa03b79b6c46cbc9fcfafb016c35ad8b7587f8a7 |
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add codegen and encoding support for the immediate form of vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 080c09229739ec2b13f7bccc361994a8d26b4ed2 |
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add codegen and encoding support for the immediate form of vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 8b08f587372c756d2084c448cf259f0711fbfd38 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
(relocations, e.g.), but this will allow simple things to flow through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118289 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a55661b6bdb4a635c37cb3acfbf3bb09e1645de2 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
(relocations, e.g.), but this will allow simple things to flow through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118289 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| c148d4f949316acad6dad0f8a3ccdfe9bd1ba355 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow targets to specify the MachO CPUType/CPUSubtype information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118288 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| c9d1439051d130cfb947ef9ab4a95737c41e2fd1 |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow targets to specify the MachO CPUType/CPUSubtype information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118288 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 3dcb461d1e721afdd2b90b24b8882f13da0dac2c |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6d87bca865eef4d08828029d973d844a6e992dff |
05-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 05b343ad87802070ad17ed8a1c72ce521714ccbe |
04-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMFastISel.cpp
|
| 1e96bab329eb23e4ce8a0dc3cc6b33a3f03d15bf |
04-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMFastISel.cpp
|
| 4c4a48e7f8a68674552e761d5750e6bc48e58d9c |
04-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 416941d50fec5ebdc4ae3b113a0db1320c3b2a87 |
04-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| c3f42e42a6b87d24db56c596250a0b4d0739035f |
04-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM fixup info for load/store label references. Probably will need a bit of
tweaking when we start using it for object file emission or JIT, but it's a
start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| 70933266ae73c891d9d1c2f0de72ecd1db8f86df |
04-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM fixup info for load/store label references. Probably will need a bit of
tweaking when we start using it for object file emission or JIT, but it's a
start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
RMFixupKinds.h
RMMCCodeEmitter.cpp
|
| da542e4619f687ec9d18571a5b569d670384edc4 |
04-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 2f46f1f59c17040f7a2c970342f2f1dcc9b78319 |
04-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 5a4535cbcd5b2186a1e79b7937c2555ffc17f3d9 |
04-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach ARM Target to use the tblgen support for generating an MC'ized
CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
MakeLists.txt
akefile
|
| 806e80ef42bdb416f409142a1ff1d4e8752baac8 |
04-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach ARM Target to use the tblgen support for generating an MC'ized
CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
MakeLists.txt
akefile
|
| 37719467d6f6fd22d931496f5e61822af8cc2488 |
04-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 60f4870c221d0496254c78c6e61bc00e4540fc1b |
04-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bc47beeb26cd1d56b42bb7e33f82cada92ebcff6 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| d966817f3cb87897cbec29c967b974924fe939ba |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 9abfdcd75b21df5a856feb931028c3a772497de1 |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 35b2de012d9404e3e9e4373e45f41711f752dd3a |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 1fc7fee3274fee338f3340adbe3074452576a1cd |
03-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Optimize generated code for integer materialization a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e5b13cfdd0fc6529f8e2b3704ccaf20369aec486 |
03-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Optimize generated code for integer materialization a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0ea841035daa0c15a4c17836c6bcaaa67b1effe9 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 7a25825033a53925f6039b77c4cb0b975026b4e1 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 50f5f6b7ddd9dafaa17f69a370d897613298247e |
03-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen patterns for VST1-lane instructions. Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d168cef6647c3a02e5b22d8d651e344af6b96fe2 |
03-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen patterns for VST1-lane instructions. Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3fb89287dea2a6f61038d3e64dac94c54ecb1030 |
03-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Check for extractelement with a variable operand for the element number.
For NEON we had been assuming this was always an immediate constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3468c2ee20e26ded1a5182edcc72e36fb09c909b |
03-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Check for extractelement with a variable operand for the element number.
For NEON we had been assuming this was always an immediate constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 465b5af7980d8ee7cdf82694791b2fb9748b4684 |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| cdfad36b401be6fc709ea4051f9de58e1a30bcc9 |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 08903968f7100c2693a113b25b86d2ff39f81b5a |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMFastISel.cpp
|
| 1440e8b918d7116c3587cb95f4f7ac7a0a0b65ad |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMFastISel.cpp
|
| a1f6e33543f44e6c03a704ee6b650bfa6bd2ca89 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMSubtarget.cpp
RMSubtarget.h
|
| dfed19fe2c34c1209108afa58e8ab014ffd894e2 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMSubtarget.cpp
RMSubtarget.h
|
| 8ea60bc4c322910d48ce1b1a1cf416e90268cc98 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
isassembler/ThumbDisassemblerCore.h
|
| bc7deb0f758d2544fc4c36433668340cbf4835cf |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassembler.cpp
isassembler/ThumbDisassemblerCore.h
|
| 6611dcc3423a34a8602c282684e6d418b96c3a9e |
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Put the PC encoding in the correct bit position.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| cdbbec43a837532d6a19e95320361c4b7c215a02 |
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Put the PC encoding in the correct bit position.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 25487d9df40fc3bd9cfecfe114e4246fd46ab324 |
03-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Invert these branches by default, it makes assembly comparisons a little
easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 000cf708effc247ff1e609d0703324b21585a4af |
03-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Invert these branches by default, it makes assembly comparisons a little
easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5a7b47f6e8f8f9ed702ad23497fa0123c722271d |
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrVFP.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 92b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4 |
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrVFP.td
RMMCCodeEmitter.cpp
smParser/ARMAsmParser.cpp
nstPrinter/ARMInstPrinter.cpp
|
| c8436f7fbf40ea841d5f43ba94f3cf48d391a46e |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 2915eb44301f1943df870efe37c424a6e8bdacfe |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 391ab2bde46e3f1542dedac9ce71d6c887f7da6e |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove the no longer used 'Modifier' optional operand to the ARM
printOperand() asm printer helper functions. rdar://8425198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 0a2287b909634991a8e8aa7a93f81f09375227b1 |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove the no longer used 'Modifier' optional operand to the ARM
printOperand() asm printer helper functions. rdar://8425198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 5e3d24588bcca470142e76f4d14918c92347bda2 |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 496e2b2908820348163e2271708c40e8e398315c |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 2cdfb732ae0708ee86b78da051e7abda10982dd3 |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| e6913600c723a10ab1f06a43c93d82ee8e26c71c |
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 6c35fb1a67dd7e4c71d1a3da6406908ab323577a |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 51d074eb705869afc6a0aa27a39f7c43c86efe47 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Modify scheduling itineraries to correct instruction latencies (not operand
latencies) of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
|
| 41957f6eb2271e5f1981b32a873d1b58217c6411 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Modify scheduling itineraries to correct instruction latencies (not operand
latencies) of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
|
| e862bb16d8ae4f796caa544a2b0e60ba089c6fca |
03-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Make sure we're only storing a single bit here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4c914125c4d1746dd2436cb5b1620efd6182f1db |
03-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Make sure we're only storing a single bit here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5a41e328034d22336dc079d46f3457228d6573a4 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r118097 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| f431edae5c0c79077451adb6fb0f406f7c7e5368 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r118097 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| d9f1faac9a76d2c18b01ff718cddde6c1042935e |
03-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Completely reject instructions that have an operand in their
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| a1ca91af4e01b413cd1d1b3fa9d8d24fa99d9293 |
03-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Completely reject instructions that have an operand in their
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 6d4872f4dc11e8e0c46337eeaac07133ce3b6392 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Obsessive formatting changes. No functionality impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118103 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 0800ce71896ccd7f49b37861a8cfbc21b6b10022 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Obsessive formatting changes. No functionality impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118103 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| c559f0fb03cab01eb7ef24e208cde5dee9431b3d |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Omit unused parameter name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118099 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| d3a124db4dac3186148aaa4dc60161d30dcfce4c |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Omit unused parameter name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118099 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 0ba4accc5a694014fabd225aac0f460b4e71160b |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Simplify the EncodeInstruction method now that a lot of the special case stuff
is handled with the MC encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118098 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 7292e0a6564bb24707eff1c49da9044dd5eaec78 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Simplify the EncodeInstruction method now that a lot of the special case stuff
is handled with the MC encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118098 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 0bd06085cca33a63b2ca9ef431cac21f6a5f100f |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118097 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 1ba6064437f7cae1d2cd1aa9c8dd50a78e8657e3 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118097 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 620a4c21e78c9e6616f911b42a2af8b08f5ffa47 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrVFP.td
RMMCCodeEmitter.cpp
|
| 5df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0ad |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrVFP.td
RMMCCodeEmitter.cpp
|
| b203fb2303fc4f88a4d2fc34d12fcb6fe6f4ddbf |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Rename encoder methods to match naming convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| a2b50b300ec32dc223a82a256a3d93b8eaf41662 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Rename encoder methods to match naming convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 1fafa35c9c842bee1a2ad7e738aa44b393c6afde |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the remaining vst variants that we currently generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b20594fce621a0b80132a575113c15ad33afc5e9 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the remaining vst variants that we currently generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 091a07af417de8b6c693780bf45ac8c7ffda4c58 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Tentative encodings for the "single element from one lane" variant of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118084 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e95c946aebbdf42bc637709bfa6899cf275cbe39 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Tentative encodings for the "single element from one lane" variant of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118084 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| cc41dc0ebd6cef8c8d2a11baea42d33d726d1375 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for basic variants for vst3 and vst4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a1a45fd25471e1121887b45ddc50f611f3c5f0aa |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for basic variants for vst3 and vst4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b6e22f527bff9c53edb6397e2e0769a837633d4e |
02-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118069 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| d0c6bc220433fab06bc1507f963ea5883fdc4f69 |
02-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118069 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 51374b8d2438ae0bf20b21928a52a37cbf6b5455 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic variants for vst2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d2f3794e4dba7a397eaae62114fffe46213c7d41 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic variants for vst2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f4d678aae53f3e67e6b23e82e8f068ec50a0386b |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic form of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| cfebe3a8b1b5b4654761953a9b695901a1b8eaec |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic form of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b59ec6ca7f74d32744636e0498a406317f1fff3b |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Factor out a common encoding class for loads and stores with a lane parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118055 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| d138d7034e8dcfbb55683116a854a1e42d6879a4 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Factor out a common encoding class for loads and stores with a lane parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118055 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 7ff4fb9c15e492018ea578cb55df8faeabfa636a |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the rest of the vld instructions that we generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| f0ea0f2b1575868cd238391868d8f51370041303 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the rest of the vld instructions that we generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| 979d96c2dc28c448b0fa371dcffc7fc29eec6291 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Sort bit assignments. Cosmetic change only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118029 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 28b108250d302cca8e71d13f2fe5d954c1d6c33a |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Sort bit assignments. Cosmetic change only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118029 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 97f1ad08bad32690f482382201fba21040ec54e9 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMMachineFunctionInfo.h
humb1RegisterInfo.cpp
|
| ab3d00e5350fd4c097e2a5b077da7584692029a7 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMMachineFunctionInfo.h
humb1RegisterInfo.cpp
|
| 1ecf448d79815235fc8d5ba8838a2ced577ebd96 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| cf667be17b479fe276fd606b8fd72ccfa3065bb8 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| 849220554f8011978d22de887d18650395d91e27 |
02-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Remove an assert - it's possible to be hit, and we just want to avoid
handling those cases for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117996 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4053e63a4b2f54446e29ef5bdad64e43b3bf52d6 |
02-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Remove an assert - it's possible to be hit, and we just want to avoid
handling those cases for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117996 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b62cd2bd322a2bd8290860514ea896e08ff89d99 |
02-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Whitespeace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117995 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 61d69da051f5e45ebca4b78f3cec21370de25061 |
02-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Whitespeace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117995 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 24c58bc0e2000c7304d3b5e3d27e95ec7e375e3c |
02-Nov-2010 |
Eric Christopher <echristo@apple.com> |
No really, no thumb1 for arm fast isel. Also add an informative comment as
to what someone would need to do to support thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117994 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| aaa8df4cad59e41bebba47ce2b4c74c1f0a23c77 |
02-Nov-2010 |
Eric Christopher <echristo@apple.com> |
No really, no thumb1 for arm fast isel. Also add an informative comment as
to what someone would need to do to support thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117994 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7a5e5e37c2d70b111072ab1c47d4536513996675 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
since we can neither generate nor parse them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117988 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e85bd773e64e5e6e33a3c9b57129c4c4703ba82f |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
since we can neither generate nor parse them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117988 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 58932668cea35e2d94e4675ef7d503a85afafcc6 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add aesthetic break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117986 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| b552174a8c784299c476c3235c56a1eca88e2a23 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add aesthetic break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117986 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 92ccf4e164683b68c5dfb8b66fb619a6c571ac86 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| 75c6ac64ad47d9bcfc923623c7be3211499d9886 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
for handling the fixup necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117978 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 9af3d1c0dc2250793ada1ca6cfa98e9f1253f7f9 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
for handling the fixup necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117978 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| be127d05f5580698d478a5b686532199023edc9e |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117977 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| a502423d1e4db0376ab3e1e45a7e9df79cc43952 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117977 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 8ba606daa503d4af7688d37eea00d5c847bcaab6 |
02-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 665814b6be3e44fdb84bcf1b7e5c933b60fbf280 |
02-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| f4eec5031ee9ccba75b159217cbe901249f8df5e |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Missed reverting this bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117971 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| cd944a424cbc15f9a83137a08f14c96bfe268bc5 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Missed reverting this bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117971 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 6e61c624543627a3c4597ff1478f9d1517213877 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117969 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 160accad6b0c466fe7d9e18ea1eb63d4b26e0106 |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117969 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7a5bb4807c5570753a80a7f1ff15b05a507b0dc1 |
01-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| b796bbb6de19872c0c1921b8b3f05206dd33c97d |
01-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 28f7f4d40dd4b765dd9c77f2f4c0f8ca874d3a1c |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Move the machine operand MC encoding patterns to the parent classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| c2bf50245f86805e95d01a243e7de3641c5ab7a8 |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Move the machine operand MC encoding patterns to the parent classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 53b2e23459e1c21c51bf220e7a548baf69217dfd |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 40a5eb18b031fa1a5e9697e21e251e613d441cc5 |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0b76671fa0cc53d874ca88b382e3bd1cb5831be4 |
01-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
NEON does not support truncating vector stores. Radar 8598391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 24645a1a6d317acfc16303237704f32364fb2f0f |
01-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
NEON does not support truncating vector stores. Radar 8598391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 56cadba21ed7d2fb1459a85f0b76ce9cdba264b5 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 469ebbe148b18a78963e8bc3fa7ae8e5700d8d27 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b86829a9a21a937381103bb9cc5cb842ffe49fbf |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 6797f89815d9e26ae6b6856273e6a96ff5e135ea |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 6898286c29fe741d57c1d2b93cf5b457bc761e4d |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 833c93c7958dbbd9d648f331091fbfbeabf342e6 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| c0fa459df9069566c3ce1a646333a89e0a7d3a8b |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d4462a5a4feae0293ca14376ff25d8bb72dd12a9 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3dd1cbe73ac70920e1580715618a596941411a85 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
patterns as such
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9729d2e9989f970724776c3e947cc7244ae45f90 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
patterns as such
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| abc59f047ea072c84adc1fa6f701f2261312c877 |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 69661191ce9f4e8a2fa00391a0708905caccf52c |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| d5630c0c279382a70fc95c2ce97d28e5dd6d2c6c |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
reject instructions that contain a \n in their asmstring. Mark
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 4d1189f3857c627a5e771207e486b00cb22c36be |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
reject instructions that contain a \n in their asmstring. Mark
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 19634b2d42b66e6e5e9718f8adbaa9d6984642bc |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 150d20e8fcadda6600bbb2e188c17a35b8ec7cbd |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| f258fc2d6781c945b366838e0012f5bf20b7213f |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| a4a3a5e3c212e7b4ac84fec94c9a140f120f3ff6 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| db58982dcf4a5525ccb0542a6eac8213db785cdc |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 39ee036f407bd0c94cb993cf9b97348843cfafa4 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 3bf6befe61f238194ab53c0b460d31d24ebd92b2 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
revert r117858 while I check out a failure I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 8b2f0822f3e9e5727b2188872a9db76bc6b87cc6 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
revert r117858 while I check out a failure I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 7a5bb18d0fee8c1ce32a0d161856337505962614 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| efa53760feb23935c29176a94e937f02c3aa5683 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| cd6d92367bd2a08e6455c6cd8713ba679b6c0fcc |
30-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Make sure we have a legal type (and simple) before continuing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 76d61478dff97d10ed01ae071f9fff1a24001009 |
30-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Make sure we have a legal type (and simple) before continuing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9307dcddf8b61a3cd161ef3c2b40a6079014c505 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7644971232f21a5d5e232b72bc815ef26163e06d |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| b0fc3893740e5de4ba7342d102f0b9a501370100 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4aaf59d8ed5e565632314a1eeb7cf5a1fe1fdbe0 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e54264ce81ab1f28a3a8c40a0a93cc1e0c860c5f |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
simplify this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| dba34d874d0ac8c334f03d770b80c6ee2f12808a |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
simplify this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 74a33b27463eefdf57e65ac2f7a60dad2b3fe4f7 |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e5658fa15ebb733e0786a96c1852c7cf590d5b24 |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b94eff0d0f262e753e122687d215feb7c227474c |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 4b5236c9660784ef09d355e0e4523d8b05fd14b1 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 81daf43d4cdb0f276efe03b615e77ee41d3e69d6 |
30-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| f74a4298163a7d0b500c7f7a818829c153dc942e |
30-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 8e744e3ebcd112345c2abe72a28d308bf5e55d96 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the register list operands for ARM mode LDM/STM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 6b5252db2db5eeeadec4602329ac56beb6dea54a |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the register list operands for ARM mode LDM/STM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 62799ffc207b9f9054ce261ff9d8b211807462ef |
30-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 52925b60f1cd4cf810524ca05b00a207a926ab9f |
30-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2513dceb8c4a135b9dd9f24f5a439640f060cdd5 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove hard tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f38bfd1918aa3d9397e501d5f4a5bd0434fa2742 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove hard tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4ad47e374eb0ee8e3de2fd752fb06bbcd26243f6 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| c4bc2111a75dc1ba2383a7021dc95750b3398efe |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d8f6e42e51b99cddc618965c4c5ec46924bdb0cf |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| d8a11c25fa64c152628cfcf5f9d36eb60242b302 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 9bfe04956edacefd08e23c130d623b4dcdd15ac4 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
encoder functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 0d2d2e92461781d11a8a055720e7ddfa4c8eee28 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
encoder functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 51c1d4a748e88f79417e0976b53c1701d7f49b35 |
30-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix fpscr <-> GPR latency info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMScheduleA8.td
RMScheduleA9.td
|
| e09206d4d7683e2a421104c5cb83f7808ba4b06e |
30-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix fpscr <-> GPR latency info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMScheduleA8.td
RMScheduleA9.td
|
| 8c7dc4348d7fb9745f998a806bfdc53d33191018 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3df518e67edaf358154af394cc99d21435b7b118 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 222da5d31f0a1423ec94d6252a1d36236cd26ba8 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMExpandPseudoInsts.cpp
RMInstrInfo.cpp
RMInstrInfo.td
|
| 8e0a3eb95784c76f3a73abf815a0143613068f72 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMExpandPseudoInsts.cpp
RMInstrInfo.cpp
RMInstrInfo.td
|
| 82575e011ca82b1a4a89860a48c0f49d20a75000 |
29-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle comparison values we already have - this fixes the consumer-typeset
failure for llvm-gcc on arm fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0e6233bfd75a12b9e56507086a37816240ca877a |
29-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle comparison values we already have - this fixes the consumer-typeset
failure for llvm-gcc on arm fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 64da73d968671c9c6f9df67342cd16f64ef01d04 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
handle it in the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a3c1629ff58812250de8848c42bfd3dbb5098436 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
handle it in the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 64e19824c18ae7fa4e3c497ed859afa19f25126b |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e317b13a2d3c2ae6eb462f7c7ecfc45663750116 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3507570425e390334c876c634250920f5648e42c |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| f32ecc69e51b45bd5c0ec93b393aee535f43c66a |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| aa4b1bfd5615a0186faabd8f6b7eda2b8e6e68bb |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode LDREX*/STREX* binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 86875a2463be6c0ac4df121c3319e3e1f73dcdda |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode LDREX*/STREX* binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| e8e0b0722a5492cb8436dcb8d57849e9411d08c6 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding information for ARM conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117687 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 27e900888e3ce05233eceef995ed8847353f6109 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding information for ARM conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117687 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d9818d9f3d989f528a4ae03fa3f3a826a066c9b7 |
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 089751535d6e9adf65842e2ca5867bf9a70e1e95 |
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2bf1ccefc98fa5a0aed0b997fa18ad5eeaf0aa1c |
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
- Compute CopyToReg use operand latency correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d7e473c629a5e4fb1584fb5c5c1b0c1e142fdc8f |
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
- Compute CopyToReg use operand latency correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a0f84fa67baf067119047380157293165f09417c |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle ARM addrmode5 instructions with an offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117672 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 80eb233a3ce1a6f2e6c0847cb3e456d735e37569 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle ARM addrmode5 instructions with an offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117672 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| baaadc0c041f03553dd0a1b3327395480c3dd7c7 |
29-Oct-2010 |
John Thompson <john.thompson.jtsoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 44ab89eb376af838d1123293a79975aede501464 |
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 57c3f4fc5dc37ddb8ba0026db0db6eed4a5dc536 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Revert 117660. Apparently it's not as trivial as that...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117663 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d8d716fad3eefce98fac5a76a70250d89fcf9a20 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Revert 117660. Apparently it's not as trivial as that...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117663 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7394cfa8dbb4b5eceb1e38ff56d18a7a7a227561 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117660 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| da54c6dd4f4e54d654722390311bdab502badc3a |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117660 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e6ab23f37a074b658eb0962d6329bf8a610b0b59 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117651 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 16c7425cff6ac3d0a4a9c56779bdfa91b2e8e863 |
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117651 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 20f45f07f15886725d4e89c77ff947a3a9d8b538 |
29-Oct-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARMAsmParser: Plug a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117648 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 61a4d56a03c051834ee25d8248fa9f434e7e8c19 |
29-Oct-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARMAsmParser: Plug a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117648 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ebc772c2d549bc596c3553990b51d3060c0b7411 |
29-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add an unreachable to silence warning - the switch is actually
fully enumerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117647 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c223e2b10b4753a63dfe7e6980c650b179139983 |
29-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add an unreachable to silence warning - the switch is actually
fully enumerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117647 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5fb3b7fca47d8e6b9d94af56a9b8d546f0b8569a |
29-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add simple support for addrmode5 operands, allowing
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| 14b93851cc7611ae6c2000f1c162592ead954420 |
29-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add simple support for addrmode5 operands, allowing
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smParser/ARMAsmParser.cpp
|
| ca209b7e9d30d9c0065c94675444234335ac8095 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
give better error diagnostics, for example:
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e73d4f8ec7af68fc0f67811e4e004562ab538014 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
give better error diagnostics, for example:
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 8aee3f10dd8cfec46d0beb1581e63b86b4310621 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 6274ec48b3a3e1fbaf3a359868d53a76f20a4245 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| ff341a00bd32474f3d5f00e05c3bba0a7c9cfd57 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move a method out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117605 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fa42fad8bf7b0058ba031a275e1e8ce53b2cb1ad |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move a method out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117605 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 75a503f2b099b45ab991976436f974862fe871d3 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
remove the rest of hte owningptr's, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117603 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 550276ee5bb3e115d4d81156dceffb9d3d78823a |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
remove the rest of hte owningptr's, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117603 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ae56607709f815c0b4b305ebcaf51497f07055e2 |
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
|
| ab682a2090f795d0b67f29889622da0a74cd97c3 |
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 3a8e9696997a8e15fecb2fe88a098d5acd8eb0c6 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
rearrange ParseRegisterList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c0ddfaa134fe60c09686906b3a8f489531653453 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
rearrange ParseRegisterList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d07f95acf87b7b1ea2ab557ad67f31f48a5f4a06 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
refactor some code to simplify it, eliminating some owningptr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3a69756e392942bc522193f38d7f33958ed3b131 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
refactor some code to simplify it, eliminating some owningptr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1c84f66defee7f096924b517f08b401a6d88054d |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMScheduleA9.td
|
| 7e2fe9150f905167f6685c9730911c2abc08293c |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMScheduleA9.td
|
| 9c25d0a6067d2770fb86a0a0ffeb4ac57a2f6c1d |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMScheduleA9.td
|
| 9e08ee5d16b596078e20787f0b5f36121f099333 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMScheduleA9.td
|
| 9b76f895552a9beaf5227722ba0fc581da1607b1 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMScheduleA9.td
|
| 0104d9de04f5620ad9f837efbd3d82f31c6ff451 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMScheduleA9.td
|
| 12f17ed2f11df462996a2aec58ff194931c77c99 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vtbl and vtbx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| cfd0e1f3ae97ac20b92649b4a6c75930b1f8b19e |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vtbl and vtbx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ffb791d782f639b2c54cd72e61fbb388d93c9406 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3eff4af42ddbac97807348eadd292ff5f276fe69 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 759896d89df9f554538ec7bd94787380da7356b2 |
28-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix compiler warnings about signed/unsigned comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1fa9d301a83569e8b0f4224097e0869c8a06f879 |
28-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix compiler warnings about signed/unsigned comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 33c79277a205027b67c0f615d3025e5e6392fb62 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| f40deed62f4f0126459ed7bfd1799f4e09b1aaa7 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| f9ea7dde3e92919ea1716e38c1ad3aac7bb7a9bb |
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMFastISel.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
|
| 7e3383c007f53b3a00675af225e428cb66ddf404 |
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMFastISel.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
|
| 16a78721a9a60678667fbada8f8d3e4a016f4618 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| 498ec20703c89d0c2890b0967791f0f5f2b59a2f |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrNEON.td
RMMCCodeEmitter.cpp
|
| ea78cafaeb6cc121cbe1a9de384a8556d9b3459b |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6b15639e267575a2c95f89d6b266e0fcd9231d91 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2648baadf69171dcc003aafddc9fede8b23c3d2e |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| d2fbdb7f5c85d2191514953bdba0fae7b788e623 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 86524951ec98dee8f6dd930da6902b6abafde2c6 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
JIT imm12 encoding for constant pool entry references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| ccf72caa92ba03fcaf348f9d8c7d14eb5738a31e |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
JIT imm12 encoding for constant pool entry references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 162cec8eae0dea7c65303386bc0414b5b43f9f55 |
27-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
SelectionDAG shuffle nodes do not allow operands with different numbers of
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f20700ca773acb0d79ce69ad5834e00884ad31f0 |
27-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
SelectionDAG shuffle nodes do not allow operands with different numbers of
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 08db1849b78a233df0b965cb723b8e81e8457d68 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM JIT fix for LDRi12 and company.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| f31430f6ecea74681a53d1e4cb64b0f93635fc58 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM JIT fix for LDRi12 and company.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| 119ab1e696e8598417c180540e2c9a86851d2817 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vdup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| f587a9352a80bc62d9d521d5051c69d1fefecca7 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vdup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 4dcf14aadbfaa68953607b11dc5008f7a0cce1ae |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 093177d5cde06dcb63829320f12195c32485a6d1 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| f9e0bc96b43264280564d36212a35f3c72af4ce9 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsli and vsri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0745c389d903bf9d8a8705ff49bea818a6be6c52 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsli and vsri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 134fc4be37ee4e3d065c741914c54953a639b766 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsra and vrsra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| dd31ed67e67ffa9c7817d96d69e98c0eab8d1e90 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsra and vrsra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| aac41af01f1e73d8fcc86a4fea2006c9f8366a05 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 063efbf569e46776093ddf50099c98fdbb362167 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 20a934901bf3c119dab32c9da3dc6a722c7d08e7 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 77aee8e22c36257716c2df2f275724765704f20c |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 7a6ca274b860b2a4b431cff58592bfe594cebfc2 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| f85dd04bfaba4b7d57833d576127439628cb2931 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 26add5beb46ea01a903e3f2ebce235d452be90da |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFastISel.cpp
RMInstrInfo.cpp
RMInstrInfo.td
|
| c1d30212e911d1e55ff6b25bffefb503708883c3 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMFastISel.cpp
RMInstrInfo.cpp
RMInstrInfo.td
|
| 2964f10a37f43f383d668a28d0ec3f42101b0053 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Since I parameterized this bit, I should probably actually use said parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 28e3fe961f2c4d6ce5317770f660c56cae3d2ec6 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Since I parameterized this bit, I should probably actually use said parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e0575bb95eb09385d756e63241bb5086e92adcd5 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 86ed2324a6d2fa54d22afa96520de9e7c9fba28d |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f39c0c29d39e1b49391b1cf69f026ae330d734a3 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
RMMCCodeEmitter.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 3e5561247202bae994dd259a2d8dc4eff8f799f3 |
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMFastISel.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
RMMCCodeEmitter.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 61fc7978c680b19bfb7d97e6d55d23779de17930 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 632c235a316e38e5d0c6d66498064bc3e391fab1 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 42a946a67108aff039e90e3b0ef78ce2d243c898 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Simplify classes for shift instructions, which are never commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ac92262b61368d32a2435ab7ab17e68c82dfadd1 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Simplify classes for shift instructions, which are never commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 868e1b24881262ae2c33ed236b6c97295b2854c8 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vshl, register and immediate forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 3557d00a388585b8827d3e864cb8cd24ee42368a |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vshl, register and immediate forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| e052f6574c25f9d94e14f84e5a5cc9a6657fbb65 |
26-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 0eb7d06ab12bd66d04ea2329f71ceb2e8022f83a |
26-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 88f689ec95297d17374817f4e66dc528576b8ed8 |
26-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c3baf62800b149bbd966e5dcd11bce498f428b72 |
26-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 746c17a29ba8dd07962eb7f53e390b83a4649c57 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encoding for vpadal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| bc4118bd36d90bf7fba68d6b274afb089f295e98 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encoding for vpadal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b811e9f3ed71b10ed8aa0b5358dcb88dd40d83e9 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| a88ea03bf22ba098f1b7d3471d98f3303dcbd33f |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| b674a439d5771e3e9fd6874261263e3c845e5fe2 |
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use instruction itinerary to determine what instructions are 'cheap'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0ae |
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use instruction itinerary to determine what instructions are 'cheap'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 7014ec913509a830f1f2c3cdc44069d49d6eb208 |
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
NEON vmov's are in Neon domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 0e9996ca94ac84c10aeddfb9b6300b2b89b08fe2 |
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
NEON vmov's are in Neon domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| d5629ba7c887c6af40d56199ae892b0945bd6a0c |
26-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy up redundant check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117331 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
|
| b3a6817d06ab88f410012b5c5cc17fc4f07058c3 |
26-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy up redundant check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117331 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
|
| 549c7a3a26421ab124acb61530d1a9aa8612573b |
26-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce the headers directly in the Finish method. This allows us to use
the existing streamer methods that are endian safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 3336384239e563bdc5f3dbb8affec6c1e9ffbc47 |
26-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce the headers directly in the Finish method. This allows us to use
the existing streamer methods that are endian safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2d88e9b93d3df7e98ad2494c5500637237f8faef |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vabal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5258b619667c54d3f07c12031fa0d75595a25527 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vabal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8b230969f52dad57e5749a4e8cf300296c5c7196 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vaba.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 410aebc670ea1ae0412dc2bbe0b4b79f25e53ce0 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vaba.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 89880a03240e2b76c67f8bb3e220cd50debc0c07 |
25-Oct-2010 |
Shih-wei Liao <sliao@google.com> |
Enabling bcc to do host-side cross-compile. So we can soon do a build-time preopt, similar to dexopt.
Change-Id: I82085a058bfc61a0dfcf6394e59f12986b728c76
isassembler/Android.mk
|
| 1d4b6e31212c9cbdbaa0cb6fc310de178276d438 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 31e6ed890a5336779fa191a98af1fc0513380180 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f65436f35dcdb1d675266d772d6e3457160077ea |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vbsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4110b4325da839e17dae901996b2263a1c672c87 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vbsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 638d1ca07a09c765bd088465d991df39cfdf818f |
25-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
imm12 operands aren't Thumb2 only, so rename the printer helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 458f2dc5d1b0120bd5921582eb1149ea770568bd |
25-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
imm12 operands aren't Thumb2 only, so rename the printer helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 316194f7a2b84dda91624c57fcca3588309c1ded |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 162875a9f3be40bfccc07c29ea4ad19f599b9ee4 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| c95b18e74a6307055622ff0f6adfd52f5b3d8228 |
25-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a virtual destructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4921e2356ef8f3b3f9ebd0c154b091c3d5dd2ce4 |
25-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a virtual destructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 31385c81e48178a332da4738bc7257e989cd1459 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vand, veor, and vorr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 8c71eff59439708a61a2c65919ccf9c2791d1f1b |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vand, veor, and vorr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 2843791b39af563edc3cb12340cd5557022c48cb |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encoding tests for vcgt and vacgt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d0c5b6170f97aff20dbc1e7f24e56a7cfdcb653c |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encoding tests for vcgt and vacgt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9100a0c00cb340fad7a918343373814c60f30ddf |
25-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for emitting ARM file attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| cecbc3d28277ff4916326311cbf87335ed05d106 |
25-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for emitting ARM file attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| ee07255730ce63803c7e76a4a9fbe38dd2fc9a3a |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vcge and vacge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 10c15e5d584d8f9ee44740eca3991a63bb45a90d |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vcge and vacge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1c3451623acf65d36cf937999b8a3d654e1fd5fb |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add a warning about our inability to test the encoding of vceq with immediate zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4fe20bbd668528a82254e4fb9152daa4d30af684 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add a warning about our inability to test the encoding of vceq with immediate zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 84284868627fd84ad2a70828c5423c26f3683e8a |
12-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMRegisterInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| 39571b6c608d92496df41b2cf01cbfd79f645351 |
23-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Move rejection of NEON parameters earlier in fast isel call processing,
note that we can actually handle some f64 arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a4633f5d7458f4d04e4bf89be48d3b14e1fae044 |
23-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Move rejection of NEON parameters earlier in fast isel call processing,
note that we can actually handle some f64 arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a70d37154f528d30af1c320fd2888974e949dac4 |
23-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Move the remaining attribute macros to systematic names based on the attribute
name and prefixed with 'LLVM_'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 19e57025d458d3cb50804fd821fd89b868a819bd |
23-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Move the remaining attribute macros to systematic names based on the attribute
name and prefixed with 'LLVM_'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 61c583f564379ef0dce4ae770450a3ab65c94c74 |
23-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
until other LLVM projects using these are cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 100c267249d1d03c4f96eede9877a4f9f54f2247 |
23-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
until other LLVM projects using these are cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| b0fb18dd0edc43750f124e9c62b7c1a42633b3e2 |
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable ARM fastcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5c2d428f43e83912e8f20e6f917fe11236741bfb |
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable ARM fastcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 39ab4ffb397f1695f74a3f0408476f43cf2db294 |
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Latency between CPSR def and branch is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| dd9dd6f857604abdeb5213648ffe50c10ccc59b9 |
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Latency between CPSR def and branch is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| fe28399f15ff797837190cfd008b15b42beabc47 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a9a968d1ef199ba113e63ef0928d266123203fb8 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6c93a37e3d99f220b4261aadc8a1141a954c7604 |
23-Oct-2010 |
Gabor Greif <ggreif@gmail.com> |
fix memory-layout assumption which only holds on little-endian systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 41f31ef28eb10e6938e491987e3c1d74742ea520 |
23-Oct-2010 |
Gabor Greif <ggreif@gmail.com> |
fix memory-layout assumption which only holds on little-endian systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 889a7718ef1a8daf816a0e2d4c6a5ec2113d15b7 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| f8da5f5dfa5e847d76bf20d0ec4940e3ca51d275 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 19694bcf496c44bd130a947ed2dcf4219da590f5 |
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Transfer implicit ops when forming load multiple and return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| b179b46cc558c720d23a066c768bad71f975eb93 |
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Transfer implicit ops when forming load multiple and return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ab95b475706b2cd8d2d65aed14b619d7fcbf30de |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqdmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9b264972734a96b7956d3ff7ad6d7b5dcf5baf39 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqdmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ae04b160aef1c8d7fa8b81af3ad73c83b52a4cb1 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add the encoding information for the rest of the ARM mode multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 385e136dce9f77ad949f54277b33b31c0d1f1588 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add the encoding information for the rest of the ARM mode multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cba865d02ff96797849b5ef6d4afda1e39c9b5d7 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 92205842ca21952929eef1571a9b5b6c758540e0 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 151955782797b345201b84a3bee1a9c5a4c82296 |
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1f8b40d51c0e1bb7fce5a69c2fadc656bfef3092 |
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6249ff562403a21fffe869d7c4777a39bc6091c8 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vmla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 18341e9e31b95ff865530e04662f540e2cdf3382 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vmla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 53895dc78a01908964f0097572cb204dfa0ac922 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 3870b750e6d8af533926138e670f4643a5953e42 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| de6850078d82b519d7063961728815ead281b27f |
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
|
| 76f920d316dc6a9e5e77c8e36f9312d1708e376b |
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
|
| 75bc3537410d8911225a6b115ba9809256243648 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize a bit of ARM encoding information, simplifying some instruction
definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 929a7056d8fa54a45471d2861034e3faa11e232e |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize a bit of ARM encoding information, simplifying some instruction
definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 68706787649a67e1b60fc5221014ef2032e39dbe |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instruction encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 9463d0e400d4bac590960ba5593d7850870f7187 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instruction encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 324a6e60434f1486a273d458801cd2a5bf897710 |
22-Oct-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Making the e_machine configurable by the target backend in ELFObjectWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| eecb858ca86fa949c06f819d6127e2ac68d165c8 |
22-Oct-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Making the e_machine configurable by the target backend in ELFObjectWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 502d3260380621c3f3eefff5c0f6dffdae3cd85d |
22-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add some basic ret instruction support to arm fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4f512efee9198eb38bf190b0c3fe50429a065d15 |
22-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add some basic ret instruction support to arm fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 848c950d0857b4a7c93dbee3669744f002dac9f3 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encoding for some of the multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f50af8b5b87c8f8af0ef5bea17d5c09145e603a7 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encoding for some of the multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 264f3008d8853ec73757a25290af8e0dd0f0b43d |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encodings for MVN variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3686046a2cad2e3d62c7fbee9aadae1bf242fa4a |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encodings for MVN variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d6eaaca5d353ffb9936b7ed95333e5b08f095a53 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Binary encoding information for BFC/BFI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 3fea19105d4929ad694f0b6272de31924c9f9f09 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Binary encoding information for BFC/BFI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 24c792186d46fad9566dced3560e6fddeaa44001 |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
These don't need to be virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1778772d1ba9a434dc98a96cbb1b97028d6cd49c |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
These don't need to be virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 84ee7410380ba441c35ed4bed2ccb4e3a52b2f5f |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Move the encoding logic for Q registers into getMachineOpValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMMCCodeEmitter.cpp
|
| 90d4cf931477b497553a9f2d0ed53377dd5dd88c |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Move the encoding logic for Q registers into getMachineOpValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMMCCodeEmitter.cpp
|
| 4fed4fe9661ad5a924ab5b16ffbbe9af3f74ea72 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMInstrFormats.td
RMInstrNEON.td
|
| d451f888b85d01caa586b0d45bacb41836fd2c31 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMInstrFormats.td
RMInstrNEON.td
|
| f7a1d96e192555ed915694011cf3aedf9ea28009 |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle storing args to the stack for calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5b924809e4a62ddc0221cd355e834ecec22bbf40 |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle storing args to the stack for calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3d27e168afcb40195a43cc6c770908f5dec85b95 |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
More load/store refactoring, call reg+offset simplification from within
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 212ae937bb9b52bb1f27f02cb0c28496c4d1e2b9 |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
More load/store refactoring, call reg+offset simplification from within
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 83134cbec8dc2102211223c1429e507889482f42 |
21-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3ab5658a127d78c4bcf2b4a69fb838f14f833f0a |
21-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 582ec605747376a33a1c0adbbbee0c150f370e80 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vhadd and vrhadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1e93466c3a5556db0bd87755e10e2938c2a43c1f |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vhadd and vrhadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 79b09c92d03e49100aa896926f0d251c1ccce50c |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vaddw.s* and vaddw.u*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9d50559bae511cd75ea61efb7189e4b954ab4175 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vaddw.s* and vaddw.u*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 70f4bb6f4aedebe57c1f342e648d302aa1d1d895 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e0e6dc3f4ec31c98f6860c56cad406d3882db428 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 22032b23faae599c46b70d8074e6e18911791223 |
21-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
The return value of this call is not used, so no point
in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| dbbd99faf1d661f03a9dfc1551d7537c34d64bee |
21-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
The return value of this call is not used, so no point
in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 64e3d440c0311c5f12ad8b286b1db0d8d1f48831 |
21-Oct-2010 |
Andrew Trick <atrick@apple.com> |
putback r116983 and fix simple-fp-encoding.ll tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 5b7a825ec5551fd1dff8c9f280cc203da3fdedd9 |
21-Oct-2010 |
Andrew Trick <atrick@apple.com> |
putback r116983 and fix simple-fp-encoding.ll tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 7eda5e481d44f7f8d32ef0386ed731559cb0e9f3 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| d9707e3d852622197133a73dcb788a7fcd364015 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| adf3ce0c20eef93999643fa0dbacd7f3d214fb69 |
21-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| d6865de2d205d501e20d312ac66463be57dc44a1 |
21-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| a3281b83e2ff2893bc55ab69b3ac69140ce237ae |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Implement correct encodings for NEON vadd, both integer and floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d7795540d0538fb79e70d0519858d463ac4375af |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Implement correct encodings for NEON vadd, both integer and floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 41d387eae8d4204ed77578efe2f729b1c1a9112d |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Custom lower f64 args passed in integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2d8f6fe610fa859370c38cfbe38ff809a3a417de |
21-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Custom lower f64 args passed in integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4da55a384402b2c67a426b7d66d15360ea5b29b4 |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for moving a value between two ARM core registers and a doublework
extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 01aabdac44af241a9a70c3d6ef8d5007e3e80ce1 |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for moving a value between two ARM core registers and a doublework
extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2f37e157aafd3c7495d74e6081e598bc3a19db9e |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for movement between ARM core registers and single-precision
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 7d31a169af3c49f54e8dd59bb3a75b37afad890b |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for movement between ARM core registers and single-precision
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 2af133efaa100bfa78b45517a1c9a422a0b191b0 |
21-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Fix crash introduced in 116852. 8573915.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e4d31593c5b0693480e697d7aeb0a24edcf53870 |
21-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Fix crash introduced in 116852. 8573915.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6586b37895f3b5f81ee931c3c5b6432c4311ff3f |
20-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
#includes in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1cd9708f5cc13995a4e84ef498e4162a47f8b4f5 |
20-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
#includes in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e70edf893e5e61a41db7298c8678c00873f2fb65 |
20-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix a TODO by removing some unnecesary copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116915 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3659ac22c0dcb64d69aa9b80d9979caf0cab2e4f |
20-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix a TODO by removing some unnecesary copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116915 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e55933d0aa8c7d75a8b9ad254fd35cabcb846f70 |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix backwards conditional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| b8e67fc92b0a508e3782b782baa98a6d56d5d7ea |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix backwards conditional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 6978ccafa38030a6ef71e19a4337190656946dc3 |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add dynamic realignment when rematerializing the base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 8b95c3ebfbd492c2ac863df93e40c11fc2e914fd |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add dynamic realignment when rematerializing the base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| a9d3b097b4cca190eda88ea3d7c6db829fd3e6de |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a commented out bit that got missed a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f6d7df6f21abcf15cfa10a6ac7fbb2f7c959093d |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a commented out bit that got missed a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 06c918d2981b0b470eb4e25642150303264381e8 |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
humb1RegisterInfo.cpp
|
| e4ad387a5a88dae20f0f7578e55170bbc8eee2a9 |
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
humb1RegisterInfo.cpp
|
| ebe92ab52810713fe79e53bfdf3ce1869ccc84e3 |
19-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Update comments to remove obsolete references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
|
| 8155ea4c3a656d32b0ddd93de6e7bbca4ace867a |
19-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Update comments to remove obsolete references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
|
| a2aaae34d15fc9e8010bdd69f5f58b7926779f4b |
19-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Enable using vdup for vector constants which are splat of
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 575cd148cedec66af0adc266c5d7ecdbe1641d7e |
19-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Enable using vdup for vector constants which are splat of
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 21e36b85449fb02a67f818137045fb6b919e78c9 |
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 2312842de0c641107dd04d7e056d02491cc781ca |
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 1ea11fd65ecb7650ec9346aa24e1b716af04a59a |
19-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 98694138025fdb0cec0cda5727201ad00ded3d63 |
19-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| ca4762cf48c713cfeda2ca8262853590c25e2a1d |
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 11e8b74a7ae9ecd59b64180a59143e39bc3b9514 |
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 0d9ab2b69eab06125e83e90d49ab4aeaaaa8e2d4 |
19-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Support alignment for NEON vld-lane and vst-lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3454ed9545d10064d84e45ad9a9ea26dddc255ba |
19-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Support alignment for NEON vld-lane and vst-lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 442972471d2bdf42adf6c431c81272654999eb91 |
19-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding information for [SU]SAT* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 70987fbc60a8e6788668f44eba56c34ef17c7672 |
19-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding information for [SU]SAT* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ef22a13c3afc82eeb7cfd0da8c6389cce9aa0a0e |
19-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Revert r116220 - thus turning arm fast isel back on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116762 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6e5367d6a35e7d4cde8ddb8d56b706d5b8dffbd0 |
19-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Revert r116220 - thus turning arm fast isel back on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116762 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 48c2c93170baeb4c25558777774c8bd5eb51ac94 |
18-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't recompute MachineRegisterInfo in the Optimize* method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| b41ee96d76ccf1eec2fd898def4cfd7c16868708 |
18-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't recompute MachineRegisterInfo in the Optimize* method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| ee87fbe536d77d59616e3922a89985248ce176af |
18-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
For Thumb2, try to use frame pointer references for stack slots even when a
base register is available. rdar://8525298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 5c57639c283479a7b1c66e27a745d31b310291c4 |
18-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
For Thumb2, try to use frame pointer references for stack slots even when a
base register is available. rdar://8525298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e1cf4e2d274f45f9fd3a2db61f8ec77828064da3 |
18-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 0f0127f4a686ed55e5b8344d576999259f8c2297 |
18-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 902a96d9d420880a0eb8b99d2c6774c9397c1eee |
18-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e038a206df7df6f799be8e3a308101b77a3414ce |
18-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 960dfa264fbf0ee4de6b5366fc76252ac65674fb |
18-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Remove the check for invalid calling conventions. Testing shows that they're
working just fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4cf34c6c041cebc1d816d178654c6bbb7737cc4e |
18-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Remove the check for invalid calling conventions. Testing shows that they're
working just fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fe9c44207ddc57ef5c25da738f799251b426f932 |
18-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Lift arg promotion from the X86 backend. This should be unified at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fa87d6675212d5ca04725b7e541156f58c4ab40b |
18-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Lift arg promotion from the X86 backend. This should be unified at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 89313fdc6461b1ace33b2d7f10328025e5671e89 |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Now that we handle all allocas via a non-SP reg offset remove all of the
special case handling for ARM::SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 404be0c04f8a984e21f650c2bcd7b277c6fa6a84 |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Now that we handle all allocas via a non-SP reg offset remove all of the
special case handling for ARM::SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bf3066497b14bfcb327122ee22f21a68195cf9f5 |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Allow more load types to be materialized through the allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ec8bf972f5a270c80c7dca05151c9063be646e2b |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Allow more load types to be materialized through the allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 39e561285e94219d97ff1ba23ffd10d153d5f7ad |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Optimize GEP off of intermediate allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d56d61af0190ee8024eb71dd4138ed7861f20adc |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Optimize GEP off of intermediate allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8ef49aa3ce3ff4cffc801154ada968ac93e6cb72 |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7208dbf2d58a8eeff755907494d77af052db207b |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e8e7d0198cdd46ada3d069b6d64a523409c8114e |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Turn on AddOperator folding in GEP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dc0b0ef6cd593a7eb502ca0842fa1f653cb68140 |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Turn on AddOperator folding in GEP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fe6a2943cb3e514642f71bb703320dc36d96ee50 |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the i12 immediate versions of the load instructions - they're handled
more in the post-passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116678 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 45c607134b396ebdb8eb0cefe831e6ab2e37deac |
17-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the i12 immediate versions of the load instructions - they're handled
more in the post-passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116678 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 41bee2a4296949ca0d3dd6e83726efdcf96cf0b1 |
16-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCObjectFormat class so that code common to all targets that use a
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| f230df9af4012f9510de664b6d62b128e26a5861 |
16-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCObjectFormat class so that code common to all targets that use a
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| ad001767b03b71a2b993999244f25932c6e4eefd |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix some funky formatting that got through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 47650ece374315ce4ff5e483f6165ae37752f230 |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix some funky formatting that got through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| aac45b3f7244c975f23f170ea10e8d9d24ec17fa |
16-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
ARMCodeEmitter::emitMiscInstruction is dead. Long live
ARMCodeEmitter::emitMiscInstruction!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 07fda9f9b61c7f072987bbc2731690f6b5d5fd5c |
16-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
ARMCodeEmitter::emitMiscInstruction is dead. Long live
ARMCodeEmitter::emitMiscInstruction!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| a0e37a131229159615bd028fce9b0bb398bc6332 |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Make sure offset is 0 for load/store register to the stack call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| c9a91fdaf99a138e9d0aee648c7bc5d04ac385cd |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Make sure offset is 0 for load/store register to the stack call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 12e4cd62feb46991247f07e40ee4b6653a7613bb |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.h
|
| 00ed59a968f3a41c36c5c01f6b3215f539d679a8 |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.h
|
| 50aa85ad232c366aa1a7f6f7eed974f1f00784ba |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix else if -> if in store machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 315030ca74f7c3cf8bf7f7d29da667ac9fc45bb0 |
16-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix else if -> if in store machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4bdc3ababa80019f0fa14cebd579a3bc9b74fa2e |
15-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Reformatting. No functionalogicality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2695d8edd132b19e6a598e0a784205cdc4c12d09 |
15-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Reformatting. No functionalogicality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 793ab52691dd8800d0ab6bc5865538ab25f1daeb |
15-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Refactor ARM fast-isel reg + offset to be a base + offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a32242564220e66a4f0fea8c173b0094ded2aa5e |
15-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Refactor ARM fast-isel reg + offset to be a base + offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a66e845b571af4ed717626dc04fc3e4137f04cab |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding information for the various ARM saturating add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5ad01c7728b9c1aab2ddca4d6a97ee6693accb9b |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding information for the various ARM saturating add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bac8cadd510bf3fb5b7031cd66e5c8fe9176cac0 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encoding information for RSB and RSC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 84760885e1cb9f8a63243500338907e516b4c9cb |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encoding information for RSB and RSC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d55143b96b0f91c340f046082dfaeba8a65ba264 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't mark argument value stores as immutable, as otherwise the post-RA
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fd52906478a17c1459607a9e458578d4289cdfa6 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't mark argument value stores as immutable, as otherwise the post-RA
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b4f4f6dce6202b925fbb8ba7c5392ac18fa1b849 |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use simple RegState::Define flag instead of getDefRegState(true).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 01b35c25deee3d4cab339e620c12c721e627d609 |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use simple RegState::Define flag instead of getDefRegState(true).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| ac1bd0fe61662071fc7d5adae767ea320670d70a |
15-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Expand GEP handling for constant offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116594 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2896df897cc7d1bd3d211f6a8f47081a1a929bb2 |
15-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Expand GEP handling for constant offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116594 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e8bc8902a5d916361133406be8c7da3eaa7ecadb |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
an explicit def. Make sure to capture that properly. rdar://8556556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 6bdc8ae2916d20740790e0618692df7dac598cd0 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
an explicit def. Make sure to capture that properly. rdar://8556556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 2f751b9419e7522209befd932b4b73360544bdbd |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for UBFX and SBFX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 8abe32af38b66bf4577526b23b6af6ec7eb6c155 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for UBFX and SBFX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 0b1d74325eea1ba67f169a31125c733138f249c2 |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused ARMISD::AND selection DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 1dd5a2f4e127a99914359cf39f19b3a9916d6be1 |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused ARMISD::AND selection DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 29f073ea18c5bc2db06ec872fe5e1656380ef26c |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| cfbece50f602c561c5eac046bcfc9a07c8c006cb |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| eba354614ad3dea9cca53d606473e4ff00d76e8a |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding info for extension instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 197a8df6405511e78265b09b6b313c30e7679094 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding info for extension instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 178db3353b224ac791f08742c7d8386a1746e8af |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add missing Rd encoding for MOVs instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 58456c0b041f47734a990030eff205a4f429f1da |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add missing Rd encoding for MOVs instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9fe3098523d0cb5a8a43e36f78460e6899580134 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| 7032f922b12746b73d6316578b0aea2d812b07b4 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrInfo.td
|
| 7c165e244d6747a51f74568588240dc8eaef5542 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 792e9796b3dc068d4545e9f5ff927b02731e3836 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| fa1f28703d8404689439243a5230b820639b9732 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MOVi16 and MOVT ARM mode encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1de588df69ceb999dd4680679cc3fe519bf9a124 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MOVi16 and MOVT ARM mode encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a3b7637051d177f4244751792b43b1214a50bbb9 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify encoding information and add 'dst' operand info for TAILJMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2d294f564b1eed29682b11d7165ea5800015cfcf |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify encoding information and add 'dst' operand info for TAILJMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0aa96f8072bfce0b29130a3a102f7d632c37df13 |
14-Oct-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 7bd698153db1403cbe8cc7cd8a250d4cd815d603 |
14-Oct-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 5dc9789269709ea6e5d8119d659ad0ba119a8e83 |
14-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle more complex GEP based loads and add a few TODOs to deal with
GEP + alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| eae8439771a9dafd09e32026ca42bb81cceb2af1 |
14-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle more complex GEP based loads and add a few TODOs to deal with
GEP + alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a4776de44edaa3c84035632c60247b97eab08ff2 |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMMCCodeEmitter.cpp
|
| bbbdcd453d22258cb4dd217eddf016668fcebf84 |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMMCCodeEmitter.cpp
|
| 4d2cc190d1bf1881d2e6d87425e22d27e218a791 |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for 'fmstat'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 946a2740a54fe2cd57509999384239101bf5b9df |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for 'fmstat'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 8f81224f2931eec7fdcfbcbb524f0f3601a59860 |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 88cf038436a142611424c895c601731ffa7c993f |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
|
| 5065379300cee7f37baed59f787f941452385f41 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Regenerate. No functional change, just cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
RMPerfectShuffle.h
|
| bd38acfa6ffabac94453eddf37e6e1272feda53b |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Regenerate. No functional change, just cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
RMPerfectShuffle.h
|
| cc38f2c329d4bbf432ffc8d19c4db6c8fa72274f |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Detabify and clean up 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 55561d188246e128e6c452d2e254cfd9fd359f2e |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Detabify and clean up 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 2bb253820d01f955c1bac57db217ca153cbdbe90 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
A few 80 column fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMInstrNEON.td
RMInstrThumb2.td
|
| 95369599c61ab1b35ae3afe349763b886225c5be |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
A few 80 column fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMInstrNEON.td
RMInstrThumb2.td
|
| 75954c8db8c6ddeaadedce4d7429115f77c69b8a |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 3a37866e53c6beb615300e2444e2c1b3a7647f3c |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| f8f6e7c727c42eb923b4331f29f65c9b179788ef |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b4b07b93ea9a107637cc1ab2c6b8cca9caea0590 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| be5e46fb3f83b315669e3f6269443d2abc7303d2 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding bits for SMC and SVC in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 06ef444e5cd85264a4e6eb0059b0c2174e4bbe61 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding bits for SMC and SVC in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 11bd124dad9f3d14ca16d0fc4b36a7ee14982b5a |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More encoding cleanup. Also add register Rd operands for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 832859d062458ebb467209aad10c2a76511be8f6 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More encoding cleanup. Also add register Rd operands for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 50f7ae208dbecdab729df45bc906316948ace7bd |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify some ARM encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a7dbc1ead75c99c16fee398c2b85adedccebffc3 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify some ARM encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8d64d50631b30c75611df69228efac152c692619 |
13-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a9c575110f6a8b1aeadefe5728393bb20697b5c5 |
13-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 90f3e2092c7a0af5bf0751e2eed66a9a15e9a9d8 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME. The ADR instruction is a bit odd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6c354fd3f5321f4afddd90543cce46c0a1bd8404 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME. The ADR instruction is a bit odd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cab2a3b65c595425cf0f2e93260e3f9c954d60e1 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| b3af5de2d97c30355b8109e149326b0664d34085 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
|
| 53b5ced0d44ea1445d7956241f267810504d018d |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 67a704de03b7466c3bd696c3d40780d277134d57 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| cb474728b11ba4dc7f1c90f1e0f24af0201f45dd |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 596307e13325f071bc9709793b58e2d9fd7125cc |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c1f66a5e36e0294300ab3a2478db3eed15f0ea82 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fa7d2cb6803b166ac9f75bb5ae7dcfd84c983854 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 21698a2600710fbd9f80ae90be81295bfbb63085 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| b35ad41fef5d1edd9495f708fb7eae1a0a94ef9d |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| d98b3ea750bd3d93775a07db563ed40c67823166 |
13-Oct-2010 |
Shih-wei Liao <sliao@google.com> |
Fix Bug #3092270. Make clang and llvm agree on v128.
Change-Id: I50deafde09216b09ce6cb8762b31601fb62b6a51
RMTargetMachine.cpp
|
| d859535fb4ca65ec6a664b7c9d97546e9b2ecede |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding for compares. No Rd register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e822f9450992774a2058163d0572538375e74051 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding for compares. No Rd register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 38956c2d2cd2c3e09df68a800e0528d36c82f8e9 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 24989ecc70ad7bbbfc135fe341484ef4fdeabd09 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9383983e5c15188c1673de7642ca23e6dcf8115f |
13-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Start handling more global variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ede42b0a22fdb57eb70d0d8c780dc5d3283397c0 |
13-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Start handling more global variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a71a41e8376ae6c82e285433401bc3c44b22564a |
13-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 14ce175216c452996ce9af04aa5749cb3c2c31dc |
13-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 8f053b42ce6cd046fea17cee9f16be1201ed8348 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 6932643a371b7a6dcc0c2b4f3a38b6b18759da87 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| a56cbbaa9eb434aa4a2eb1975d2a91e9cfbe1d09 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VCVT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 54908dd72b1c6add6f3d074df1b67060e5b57025 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VCVT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| b561a4f1c3b698dcbe637dfcf9bf3603e6fa4aa8 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 89c898f8af3e96db25fe4986b7e7f27663ebe26a |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 97c79342075f6147de07f50a60d9988610b75cf0 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add VCMPZ and VABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 1fc6d8837f03471b815a9312091b9432939b49fc |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add VCMPZ and VABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| c67e1a38f5cb899f005ee58dad75e5b3e0d71aa1 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor VCMP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| cd776862544518e215b5af8a294f5026ee844684 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor VCMP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| e631d79977c636c471178ae9a5f90a96df645dac |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add the rest of the ARM so_reg encoding options (register shifted register)
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| ef324d704425a372aeba5fc91bee4d81635121f3 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add the rest of the ARM so_reg encoding options (register shifted register)
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 40fbeab26c8a18eda1017cd503ad79aede9e4a36 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNMUL[SD].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 5a1fd8cf68a120e0f4a1e71773422a7d5a284a50 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNMUL[SD].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| da32e820dce9b67f3c018bc06883d0e400ae64b3 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VDIV and VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| caa3d467ab849ebf671441f3adf1ecda715e98fe |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VDIV and VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 24ad3be2dbdf34a342afe90a17a4ec846a2c16de |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Move the ARM so_imm encoding into a custom operand encoder and remove the
explicit handling of the instructions referencing it from the MC code
emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 2a6a93d5425b38546de2b6674719d52f565171d8 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Move the ARM so_imm encoding into a custom operand encoder and remove the
explicit handling of the instructions referencing it from the MC code
emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| aa6b803399296d49ef4aa01cc01ded63271a9b9a |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor some of the encoding logic into a base class. This keeps us from having
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 52061f83e77cc6ad6c3d9afec7749b899585308b |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor some of the encoding logic into a base class. This keeps us from having
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2b80f415f24e44b5c8859b7ddf3939bdf657a64c |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 08bd54987f4ae482de13436e7254ff08b23f825f |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMMCCodeEmitter.cpp
|
| 34c2b09f9dac7f8d16b2d6872a3df9eff68c48ff |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| dd3bc112e6545634d9700c777c975f072128a51b |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| c61b506b71447e1abb7a63a57ba75b4b066617af |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 174777bb2b0a1896afb5dc5ff96a91d162d00149 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 402e7837014eb9c664ed6fb0442b031da0711752 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Split out the "size" field from the encoding. The newer documentation has it as
a separate bit in the coding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a0c14ef8f6a41184c65a7904e70efa268ab241f9 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Split out the "size" field from the encoding. The newer documentation has it as
a separate bit in the coding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a7dc0ed7f42e88d9f258b5bc76675890598b9fc0 |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix thinko in arm fast isel alloca rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 558cf007b5ed92324156b29861a0acbf95442278 |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix thinko in arm fast isel alloca rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| edf21333934799675b2762c312f610cdce2e5a20 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM-mode VADD.F32 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 499e886fe6c0ad02e0079734733dd7dde03d2940 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM-mode VADD.F32 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 96d02f96f26f3230c288cb6858c7e07601821dae |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MOVi ARM encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| f59818b81ad75e43727bf8143b64386c82b77fe9 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MOVi ARM encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 2aa6740ece4aa0a89674cd530bb9c7c240051abc |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke unused wrapper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 8e157302f4991b08a625b05238e01d12c82a2976 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke unused wrapper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| fc21fbe8a9a13089b60ab00839c74c27f4808282 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoding information for the remainder of the generic arithmetic
ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 0de6ab3c43ed2143d661115dddf1480545236c91 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoding information for the remainder of the generic arithmetic
ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| d369c9a38dfba58dcec49c53236eb951d3733286 |
12-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMRegisterInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| 77f42b52781b6923924a93b8ab338d183887a592 |
12-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMRegisterInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| 7a0a1d517870d6eeca1350107b162fef97f8b11d |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Rework alloca handling so that we can load or store from casted
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 15418779419923dc9222cd804d409c1878b5e3b1 |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Rework alloca handling so that we can load or store from casted
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 454c4dcd8d4557d37c748bf0e586a2d8b608b587 |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle a wider arrangement of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5532433a574043b516aec26a4dd4b6c8d7fc551e |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Handle a wider arrangement of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 95bf689428749685464fc127aed50633bb8e5427 |
12-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
More ARM scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 08cec1ef27d4f27320f871cf17fd742196465232 |
12-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
More ARM scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 5763060a005b28bc6f8946ffd28ad17de728433a |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MC machine encoding for simple aritmetic instructions that use a shifted
register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 42fac8ee3bc02e18a5887800e812af762b45b9eb |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MC machine encoding for simple aritmetic instructions that use a shifted
register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.h
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 7fbd5ff30035a562c6c7731ade9ad766345a3c64 |
12-Oct-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Second set of ARM/MC/ELF changes.
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| 17b443df4368acfad853d09858c033c45c468d5c |
12-Oct-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Second set of ARM/MC/ELF changes.
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| 9b468318b87b52ff393ddaa9ba2defc70cba97e2 |
12-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Proper VST scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 60ff87914fcafd82fb123f03b17827ab7b2c3ab3 |
12-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Proper VST scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 9906ead3d25adb55167fee0f4c7dc9a1c5db4383 |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use a sane mechanism for that assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5f9e8b971bc4cf1f34901389ef9fe3b6344a0a9c |
12-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use a sane mechanism for that assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a879c9b1ca41a7780ca8ad9501428ecb2d3ef12e |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
We're not going to handle dynamic allocas anywhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 050d16c2a978eda86a5b6dc56d6f0cea10963b9c |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
We're not going to handle dynamic allocas anywhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5208a656d2d6be52684aed2e9951ac763f5d0bde |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Make sure that the call stack adjustments have default operands. Also
leave custom lowerings for later.
Fixes some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fb0b892f7ebee68760645dd220f88bd9177cf2e4 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Make sure that the call stack adjustments have default operands. Also
leave custom lowerings for later.
Fixes some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8480a5d4505148aeedec17a21843ee72dc70051d |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Found a bug turning this on by default. Disable again for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8ff9a9da0a2efc7e901c79e62689b49a38454063 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Found a bug turning this on by default. Disable again for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 97b641d25151519c33adeb7fb1e1bac870a5a5d4 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix help text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fa6b29dacdb268301d8e3f58356071c998b2b8a5 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix help text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b59f37a31f76c53064c2b46c966783e25257ce6a |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Change flag from Enable to Disable since we're enabled by default.
Also don't use fast-isel on non-darwin since it's untested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| feadddd6b6c029bc77d6c11a7a637689d15cc7b4 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Change flag from Enable to Disable since we're enabled by default.
Also don't use fast-isel on non-darwin since it's untested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 34e67a7429900b00fbec1e4c1c462281fc359fe6 |
11-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More binary encoding stuff, taking advantage of the new "by name" operand
matching in tblgen to do the predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 62547267f088a060d7c1084a40d740645efe86d1 |
11-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More binary encoding stuff, taking advantage of the new "by name" operand
matching in tblgen to do the predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 7b94d0052ab50d5144bf6befb18605f880c523c8 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Turn on arm fast isel by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a2efc5ff6ecc7dfca66b51030510afd004732217 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Turn on arm fast isel by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a64c092761e7ffb9c920283a8396df43943e5c89 |
11-Oct-2010 |
Francois Pichet <pichet2000@gmail.com> |
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/CMakeLists.txt
|
| 12657762432211d97b8c6831666d93c8fd7c903e |
11-Oct-2010 |
Francois Pichet <pichet2000@gmail.com> |
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/CMakeLists.txt
|
| 098ca99ad1de07ef2117d8fe0f4bfad3cb9d4301 |
10-Oct-2010 |
Zonr Chang <zonr@google.com> |
Fix VFP register encoding.
A VFP register in Rd/Rn/Rm is encoded as (Vd:D)/(Vn:N)/(Vm:M) if it's a
single-precision register, (D:Vd)/(N:Vn)/(M:Vn) if it's a double-precision
register.
Change-Id: Ib6c2ea23328b5e71012ea8b1375c38700100c96b
RMCodeEmitter.cpp
|
| 6035b159275db5e56c2e7ad0d8ef847ca207da0e |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Copy and pasteo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a1640d9ed9e0e9860614944f79a40ae66ecf56fc |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Copy and pasteo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5f973ec92e00ddfce13bc28c63fed4f98945747f |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Whitespace cleanup in ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dccd2c3c4346dd6625b80fcac9caa1be99731c9c |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Whitespace cleanup in ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 19294cd7de39df380eb74053e96b2c43c7567666 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add srem libcall support to ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6a880d6ba8e489fc85d18cfbc5f8f6187d438630 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add srem libcall support to ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 35f730b219fd4d1e064c8d13a6e41320c3e14ae7 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add i8 sdiv support for ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7bdc4de4e71e3c9c8d82504b99d03bbec3c06ec3 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Add i8 sdiv support for ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ed8242af5b9ff73811f79f9d39b9f245ce5e68e1 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Implement select handling for ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3bbd396853c7645791417bc795bab4662235ec10 |
11-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Implement select handling for ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ed4fc768a36d1b39c79f8ceb0948181557143bcf |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add VLD4 scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 10dc63feeb7847f867a6f35179312f4079981ad3 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add VLD4 scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 2af3d163beb659492fbb69ea5a591f2666a8f48c |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Finish vld3 and vld4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 84f69e8436d522cb3a772766ba67a1d7658dfdf5 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Finish vld3 and vld4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| ec35db65470411f371135ad2c5213981e6ea66a8 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Complete vld2 instruction itineries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
|
| 40bb6836f64ca5c60f759896805fcc163e305a4d |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Complete vld2 instruction itineries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
|
| 60461c143c37b84ca2f4d1528163986aa1fb1492 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
|
| 8ae6ffacdd115c096213332928441ff3776704a4 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
|
| 2977595ff379b14b2e03622bbb237abaf384d766 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correct some load / store instruction itinerary mistakes:
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| d2ca8135496ff7945e8a708dccb26b482e563a63 |
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correct some load / store instruction itinerary mistakes:
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 6e7c85e3896d8089c195d46e3eca8148f5c7a64c |
09-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Check to make sure that the iterator isn't at the beginning of the basic block
before decrementing. <rdar://problem/8529919>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0aa38b9381a5be42abd4f5ca5baa8c2930d148d3 |
09-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Check to make sure that the iterator isn't at the beginning of the basic block
before decrementing. <rdar://problem/8529919>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 311ed85ec58a80fcb4617951a103909279bf40c6 |
09-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix the store part of this as well. Fixes smg2000.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116123 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e93417bcc8940191396d7fa977e2c8d713bd85f6 |
09-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix the store part of this as well. Fixes smg2000.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116123 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5a899b38b0b69f6600fb9687e484f99eac214be5 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement a few more binary encoding bits. Still very early stage proof-of-
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 56ac907c57fcfddfd650238f03c856a9d55987e5 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement a few more binary encoding bits. Still very early stage proof-of-
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMCCodeEmitter.cpp
|
| 6a153f291b60c7afbc8ce9f96c5468476474addf |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Reapply 116059, this time without the fatfingered pasto at the top.
''const'ify getMachineOpValue() and associated helpers.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| 3e09413c2cec4552532e0ab5006ca80f86897905 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Reapply 116059, this time without the fatfingered pasto at the top.
''const'ify getMachineOpValue() and associated helpers.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| e2c730c6288b85f7017358078cd5e8d8b3e977f0 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Reverting 116059. Bots are unhappy with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| 2cee75a2543395b6b4bd89173bedb1d1520b26f9 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Reverting 116059. Bots are unhappy with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| 34ddd8145c4c02d31e11d3eace357e87d8ea51c7 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
'const'ify getMachineOpValue() and associated helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| 461caba214ae577e05c3ce55b568cf09533617bb |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
'const'ify getMachineOpValue() and associated helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| 5dfdc1f818cc0cbf2570dc5f396629ab7a8dc310 |
08-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change register allocation order for ARM VFP and NEON registers to put the
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 7d24705f6538688937f571961d41c7bb2985c7e3 |
08-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change register allocation order for ARM VFP and NEON registers to put the
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| fa6eeaf22c4bd93c5b78354409660c9ee2868efd |
08-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Move to thumb2 loads, fixes a problem with incoming registers
as thumb1.
Fixes lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7a56f33583a331bd1d6de57af3fa03085889ecfb |
08-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Move to thumb2 loads, fixes a problem with incoming registers
as thumb1.
Fixes lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| baeb93832017e185982e72c60de76df848379fb4 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable binary encoding of some simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 58f38bfa2457d4729a5bdacde193dc7c7d25ac9e |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable binary encoding of some simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 251fa75c98f1f716d36929d3b29872aad7c2d52c |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| bade37bb8b83deefa166776b1b5185c237a42e71 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMMCCodeEmitter.cpp
|
| d4980995131997af5179c527ff134960185ca9e2 |
08-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 344d9db97062736cd66da6c07baa9108b6cfa419 |
08-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| a270576d6da83e2a5dd4636828d1323c21366957 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trivial MC code emitter shell. No instruction forms actually handled yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| d6d4b42ba473657b6d30242962f0d0fb23fe126e |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Trivial MC code emitter shell. No instruction forms actually handled yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 19e2c510219b024c748054675ed16fab587ac02c |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Include the auto-generated bits for machine encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 9af82ba42b53905f580f8c4270626946e3548654 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Include the auto-generated bits for machine encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| e03ff9903a65f2a76c99956a0a4bf761d8991272 |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Remember to promote load/store types for stack to register size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| df1f5a924e89fc2f744681677ca03c68aae5bc34 |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Remember to promote load/store types for stack to register size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 13a418ceeced0e5aa09f5cf47728902b3a467ece |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM instruction don't have instruction prefixes, so remove the helper functions
for them from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| ae93ed1dd7fdb92239bbf255017e0d2ae82d434a |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM instruction don't have instruction prefixes, so remove the helper functions
for them from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 2b9e155bad4e1418b124cd240597b1861c447515 |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the correct register class for load instructions - fixes
compilation of MultiSource/Benchmarks/Bullet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ee56ea62431081a2333eb47df3fa4dfcd425cb54 |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the correct register class for load instructions - fixes
compilation of MultiSource/Benchmarks/Bullet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9814e7d444f8ddd69983101abe02e6f97528ffac |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the correct register class here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5d18d92aad587381b5d9ecf0aeb3c2eb1530ee61 |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the correct register class here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7ed7b7e9bd1d8fc40b95004ee859478a06b05dbc |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the thumb2 conditional move instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 338c253d7ebfff4495697911e07cf6ee1724015f |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Use the thumb2 conditional move instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 66d5959b0f565868ba87f0fdfdc0c30d595d4f1d |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Remove in-progress assertion, add TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1107734e223a140962e220ba64ea62227ffcbe20 |
07-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Remove in-progress assertion, add TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f8910dbd30406c3856931522b09fa87aeb515549 |
07-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMInstrVFP.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 5a50ceeaea980962c1982ad535226c7ab06c971c |
07-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMInstrVFP.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| fc7f62afd73adbb065e190e9d638af6ab9c2910c |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| a4257162be84d9d606a42e9db5ce2163426949e3 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 5492a1d971627bede4f228880a18aaae5d8c75f7 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 3bbdcea49abddea69d124e7ef055c9fdaa8d12f6 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 60fd09674ee9adab2203726a41da52aba8784007 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| fa7fb64fad0e46e7329e4ba84a1edec5e979c31a |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 301ea92b5d9757fd7793551f46b289c8a01bf8bf |
07-Oct-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
First in a sequence of ARM/MC/*ELF* specific work.
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| def9ac48b779a4cb0b1d1486286cda157a2fe86e |
07-Oct-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
First in a sequence of ARM/MC/*ELF* specific work.
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBuildAttrs.h
|
| 26a3a018bef3647a14b5a37f0e30ba1805260144 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 3c38f96af2a5443d9f72fd078c2c98dd08746e51 |
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 5f4935560852f9d569a37b0904542eabdaa2e251 |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
nstPrinter/ARMInstPrinter.cpp
|
| 1d6111c5ac97c321782637b2cd72e2c3e4d3d694 |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
nstPrinter/ARMInstPrinter.cpp
|
| a9afe6a57c38fb10677711fdc387c0f287d0f7e8 |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 35636281c7ab6eb128b4ced6bf7ae0b6b8458dd2 |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
nstPrinter/ARMInstPrinter.cpp
|
| 58b821ea848c832e62237de80f2195c6c347397c |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| 65dc30340cf874307eae11ec1195a1cd6d27fb13 |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrNEON.td
|
| f63de95cc76ce3c5235263555941f7cf515c3f2f |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a 'pattern' arg to the ARM PseudoNeonI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 7cd2729d2a2ded13ba35f85575b64383f198f976 |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a 'pattern' arg to the ARM PseudoNeonI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 5a3d6058fbb3c011f6b16f938ce811882546f11a |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
target operand flag values aren't a bitmask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4dea941c8de1b40717f5b788c993c325e9f7540c |
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
target operand flag values aren't a bitmask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5cb06cba2dffe2a72ba3fcc947b0c265232355c8 |
06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| a0792de66c8364d47b0a688c7f408efb7b10f31b |
06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| ceeb10aad381af39671a41f58ff163aaae34d3ce |
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
replace stuff like:
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 78caacc2266e504eca315844203b3f727c27fbd0 |
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
replace stuff like:
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 19dc10866650192e3f9bf7b3ee68e2e0beb08718 |
06-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Comment out fastisel debugging message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115717 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e540a6f94a4011e6ecefe9e21c3f2b3b581fd6c1 |
06-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Comment out fastisel debugging message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115717 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f9684587d83ae39d21171b0e185e6a59b1bdc75e |
06-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Random cleanup and make the intermediate register in fptosi a
32-bit fp reg, not 64-bit.
Fixes SingleSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115711 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 022b7fb045973531a1b05f4f0dae28fd836c9890 |
06-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Random cleanup and make the intermediate register in fptosi a
32-bit fp reg, not 64-bit.
Fixes SingleSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115711 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 80d9232d209e00abb1a0fc1c04d384734e10dcb5 |
05-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Increase the number of bits used internally by the ARM target to represent the
addressing mode from four to five.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
|
| d86609fca46ac9e186557d2d7b12f029febecf0e |
05-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Increase the number of bits used internally by the ARM target to represent the
addressing mode from four to five.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
|
| 48f77fe80fdca3f5a11e15acc958c1183af063c9 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
fix MSVC 2010 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f000a7a212590bfd45e23c05bff5e1b683d25dd6 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
fix MSVC 2010 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ffe08f1b5115ac20ca8bcf06c92bcaaeab8feb59 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Cleanup Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115593 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2bbb76909126db5bed6bde84b16d94ab5de4d372 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Cleanup Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115593 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 4727ac53eaffedf69630a630c10dbd9fceaefa64 |
03-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| 0febc4657b0edbf16b55ca5365d2b6aab45be7c5 |
03-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| b563f3ea5b22b6b0aaf6d1c34424813e03b032e9 |
03-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Cortex-A9 itinerary.
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115457 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| ec45f60cab671b0e7e2c1768395310bed7c74525 |
03-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Cortex-A9 itinerary.
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115457 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| fcc5063bcc917ffe13c085e0e1cb7a06812c9f5a |
02-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Start on lowering global addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115390 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 890dbbec5773fb4d3823e3102d403d79900b08bc |
02-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Start on lowering global addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115390 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 73b55ea192583f82c54ba3f6b8ae99422da478a8 |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
PrintSpecial() can go away now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115376 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.h
|
| 443e625d8a2198c1793833fa1754f78e2492f4c3 |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
PrintSpecial() can go away now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115376 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/ARMInstPrinter.h
|
| b5c35d50da767a1f37896a024a1b1a8d331b77ae |
02-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Stub out constant GV handling, fixes C++ eh tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115375 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| c9932f6f60827e31395d5254fda73f03257963ae |
02-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Stub out constant GV handling, fixes C++ eh tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115375 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e3260ba1f26845dda20ab0c8637934e47f1983fd |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke the rest of the :comment references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 78890f41f404fad3663408edd4adf2e13c1e13b5 |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke the rest of the :comment references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 76cea02299a10bb041c38215dee4f88355106e2b |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a bunch of no-longer-needed comment-only asm strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115370 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| adde5da63895d9c68c07c53c25083f6e4e9e8a65 |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a bunch of no-longer-needed comment-only asm strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115370 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4c66d6599df041744cde788827658bffd700f7da |
02-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r115332: correctly model AGU / NEON mux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115365 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 055028215d53759a46fcc61fe95cda4a4bdf3a35 |
02-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r115332: correctly model AGU / NEON mux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115365 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 97d3291809ac35f2551f8d71bd7ff190ac4f45a2 |
02-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| e3cc84a43d6a4bb6c50f58f3dd8e60e28787509e |
02-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 3ec104aa69da2d9677e2268e8b4ac2a4d882a0ba |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename the AsmPrinter directory to InstPrinter for those targets that have
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
smPrinter/CMakeLists.txt
smPrinter/Makefile
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
nstPrinter/CMakeLists.txt
nstPrinter/Makefile
akefile
|
| 7ac1609a3b81504d269bf967060241c309771f23 |
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename the AsmPrinter directory to InstPrinter for those targets that have
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
smPrinter/CMakeLists.txt
smPrinter/Makefile
nstPrinter/ARMInstPrinter.cpp
nstPrinter/ARMInstPrinter.h
nstPrinter/CMakeLists.txt
nstPrinter/Makefile
akefile
|
| 5fd189c81a2df52a0cbfaf30c21c52b88301434e |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115354 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMScheduleA8.td
|
| ef0ccad72559e51cca878590c40aed06d286dc54 |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115354 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMScheduleA8.td
|
| f2e515d314d3651199a4f90d5ce39e52fd79fa40 |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add operand cycles for vldr / vstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
|
| df9da6a0336e40ef78da2cb467d2ea0015a01db8 |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add operand cycles for vldr / vstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
|
| 50ed1bbd11e637b0a0ddbd939748d570d7a436d5 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Direct calls only for arm fast isel for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115350 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e6ca6771e330a0590d529d94f72201c05d0cf6f8 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Direct calls only for arm fast isel for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115350 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 14d61a579b356441eedef8ceaef025afa1dd23fd |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| cae6a12a999ef9434f110950d453814ab41d2156 |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| fb3dade3906887cde4e14399796964baddb24569 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix thinko on store instructions. Fixes test_indvars failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115342 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 45547b844d6a1cd69d6f71ec304948896c89bf43 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Fix thinko on store instructions. Fixes test_indvars failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115342 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bd3e51a313193f11126b098d2a444528192d9b1b |
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115341 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 00d4f48168eae664e1f8fefc17a912c05b878513 |
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115341 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 90bf97bb79885e0ead7ccfece4d7dcb325ba9400 |
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide an option to restore old-style if-conversion heuristics for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| aa9f0a57d03b1eef5a58c48b05f6657d2a5a0d0a |
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide an option to restore old-style if-conversion heuristics for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| f4bf950374787eae2d778e48dcb3abc4c995d553 |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115332 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 7c3423f4138fde8c38e87894e72f6658cee8cc7b |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115332 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 56e513b9786d85d01d551e6744c8be8adedb4036 |
01-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115314 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| bffa1a5cf3de7d46c71fea93835c6e84f33674e3 |
01-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115314 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 76c25b039aba3d31a8f7b4ae03334bac585baa51 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Implement double return values in calls. Fixes
SingleSource/Regression/C/casts.c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115246 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 14df88282bf897403db6ac1dc20ad01a0ae79835 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Implement double return values in calls. Fixes
SingleSource/Regression/C/casts.c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115246 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 038e3a35b69cc1591ebcb1f384b3a9bb672e5ba8 |
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Temporarily add a flag to make it easier to compare the new-style ARM if
conversion heuristics to the old-style ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115239 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b3c04ec956247a984b3113a01cfbfad91e5ca5b3 |
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Temporarily add a flag to make it easier to compare the new-style ARM if
conversion heuristics to the old-style ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115239 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7f7e8331e9c81dd001e81a8f9ab2b362191c2c2f |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Movement and cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115225 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 086378597df590e6401abf90d0b5edb09bbaa297 |
01-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Movement and cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115225 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 006b8284a3ebe6c5860c05c615505ef3c0fc460e |
30-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Start of generalized call support for ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115203 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f9764fa14fc6e168956bd53e696e8aa4e7b5d42e |
30-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Start of generalized call support for ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115203 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f380e252b7c91150e3d1b991c01d733f9e34a267 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a few more unused asm strings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| a3fbadfcd882f9f15bda7c1213b5ff52d6582a10 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke a few more unused asm strings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| a29700f5e904147b19152401e14fe090c922448d |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Move getPointerSize() to the base class since it's not dependent on MachO
vs. ELF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115180 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 3787a40e038d6444a1b0e93f1cdc55fb006a5392 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Move getPointerSize() to the base class since it's not dependent on MachO
vs. ELF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115180 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| af5eab57945e5ada32b01b82928bba4d8c265222 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove extraneous ';'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115176 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| af2a8b21f1a172f1d8156c502bc59f9d1335168f |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove extraneous ';'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115176 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a1eada6425624de8f74f5a64b25daee5c1a2c81e |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
The asm strings are never used at all, so just nuke 'em entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 71d933a49ef10508f8117a58bab63cb1bb7bdc00 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
The asm strings are never used at all, so just nuke 'em entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| a31eb15fec5b7897e67254ab17aa1b8faac1bee0 |
30-Sep-2010 |
Kevin Enderby <enderby@apple.com> |
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 8ebf66236e1a0a3f6796abcbf6be83eb6a55e3fa |
30-Sep-2010 |
Kevin Enderby <enderby@apple.com> |
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 6a566e9d951ef68d6fdc3e1c5ad90e672e8cd00f |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115149 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2f24c4ece09f1157c5cb29357d91d2a0d77eb57c |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115149 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 542a0940a9f259cda1901c416e8c8688d23d5085 |
30-Sep-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Fix two tiny issues (ARM does not need COFF) and comment sanity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115147 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| a4c27248b5ddba8c821889abf8c222950b3426ef |
30-Sep-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Fix two tiny issues (ARM does not need COFF) and comment sanity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115147 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 4fed2a8336f26d84851fea2cb1ae165b1e80148e |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115136 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| f73fd7278f2bebd435c84c55a79db8ccb07d3534 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115136 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 48cac28aed85f0d54885ba396fa4bbb626396dd2 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove misplaced ';'. Make buildbots happy, hopefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115135 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 87dc3aa2d87871f1affc6f3f2fa587c7b6725d83 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove misplaced ';'. Make buildbots happy, hopefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115135 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmBackend.cpp
|
| 34990b4f9cdf3ae85e86932bc06f2be736af6de0 |
30-Sep-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115133 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| afd1cc25786f68ca56a63d29ea2bd297990e9f81 |
30-Sep-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115133 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 973b31a55125174f29e6cc5b317de17831bab38d |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Go ahead and jump!
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 7ebc863c156c5ccd127045ddb8d663c3b49ac5f3 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Go ahead and jump!
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5e8145d8fe5a8a5ed2f9ccb59d389a6eef6cf653 |
30-Sep-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
I added a new file ARMAsmBackend which stubs out in similar ways to
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115129 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmBackend.cpp
RMTargetMachine.cpp
MakeLists.txt
|
| d4d4f4f488d46a9743a0c494b42b22a1b15e0e7d |
30-Sep-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
I added a new file ARMAsmBackend which stubs out in similar ways to
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115129 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmBackend.cpp
RMTargetMachine.cpp
MakeLists.txt
|
| 4c07ed51a71943f07d6ef00615f399389d2e72e7 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that the pseudos that needed this are all custom lowered, we can go back
to an empty PrintSpecial()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115128 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| a4e97de71d7dd890eb9f705710bd094f0fa7ac49 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that the pseudos that needed this are all custom lowered, we can go back
to an empty PrintSpecial()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115128 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 8a8e5fe14352aaeb0ccc1c9cda5698d004dac093 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke it from orbit. It's the only way to be sure.
(Kill the dead non-MC asm printer for the ARM target.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115127 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 2317e40539aac11da00bd587b5f0def04d989769 |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke it from orbit. It's the only way to be sure.
(Kill the dead non-MC asm printer for the ARM target.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115127 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| e5ae8136455a0d920c957629e9a5e2c496a2f33c |
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM instruction itinerary fixes:
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 0e55fd61ae9ab88cf76b30f7e69d168bd7be87d0 |
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM instruction itinerary fixes:
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 4b7451800f06c328e1cd33b96d9aa79ed33bae82 |
30-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Refactor arm fast isel libcall handling so that pieces can be used
for generic call handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115105 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a9a7a1a9a557cc03d1fed6cba3f27520be5274c0 |
30-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Refactor arm fast isel libcall handling so that pieces can be used
for generic call handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115105 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3ace4f36ced9f788c7e06afd1bc76a41fad8539e |
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 3881cb7a5d54c0011b40997adcd742e1c7b91abd |
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| b71f561c52dc16e823fef3f5a2801abbec594bd7 |
30-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add a convenience variable so I'm not chasing all over looking for
a context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115094 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8cf6c60710c7924bcd0235f37e4d613f9abf7dc6 |
30-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add a convenience variable so I'm not chasing all over looking for
a context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115094 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 326c3ac04b4344149c2cab663c0e27e342146727 |
29-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add specializations of addrmode2 that allow differentiating those forms
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115066 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 828916203a731c5031fbe440f1fc6cdf82b2e711 |
29-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add specializations of addrmode2 that allow differentiating those forms
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115066 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 1bcb1b4fc19f798f3922f9d6eed4b709845b91e7 |
29-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMSubtarget.h
|
| 7122ba7efb5430d724ed3a0ac86fa7f7185b43ba |
29-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMSubtarget.h
|
| 16981f3fcf2eda510393df72581b4eab042e7f20 |
29-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add braces for legibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| be91232900776c23d4b327be7bc3f03f711d11a8 |
29-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add braces for legibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6c6005eccd76a66ed897310fccf8aa1b90f2937b |
29-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
One Printer to rule them all, One Printer to find them,
One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115038 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b454cdaebc6e4543099955ce043258c3903b1a0e |
29-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
One Printer to rule them all, One Printer to find them,
One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115038 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 123c7e86b555dae59adb497c43e04b4301d3b386 |
29-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
added some doxygen on the way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 05642a3eba3f35aa8fdf6aa16d87561560e60af3 |
29-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
added some doxygen on the way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 3918081b73d24896b8ec4e0f17d27e1bc18ed1b2 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8456378 and PR7557 - support for the fstsw,
an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7c51a3172cf5104ebeaef22f1366fa634ca00d85 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8456378 and PR7557 - support for the fstsw,
an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c575a6ad74eadff19e5e632faf241ab24dcbf0ee |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change the protocol TargetAsmPArser::MatchInstruction method to take an
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7036f8be4df8a1a830ca01afe9497b035a5647d6 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change the protocol TargetAsmPArser::MatchInstruction method to take an
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 98cd9c0e3f4a221ec699de66f6c6a327f4ba64d6 |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework comparison handling to set a register on true/false. This avoids
problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115013 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 229207aa2edaeb872e9f987ad8df3a67455f240c |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework comparison handling to set a register on true/false. This avoids
problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115013 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 629d060ad46c6a512fcd120985e07a410b15b649 |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Remove unnecessary set ahead of time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115011 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f8476e6742d22f97932409e79b59a693df6b5947 |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Remove unnecessary set ahead of time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115011 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1e11b96bdd475390ef783145107b29caa62640b4 |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 5d42c567c901508e80ab10ddba1bb30a5007d742 |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 98d3af863f5d21f782bc8518d4a59137ba46e315 |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Remove assert, add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115009 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 98de5b46039984759f236cf991b0eebd179e9411 |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Remove assert, add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115009 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8a80e302b07346c988ef58e7501a6d907284f80b |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 7e1bf305cfecbaee859405468b769650efe68f1a |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 03248d8bf693d3d865e4fd8c2110887ec4433e26 |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 63d66eed16a6ee4e838f2f7a4c8299def0722c20 |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 973fcf845fcbdf77e166eb49b16d358c30359d77 |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
32-bit constant ints only for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115001 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 744c7c8e1b9bf166ded2b4e0b57638a004a44f8d |
29-Sep-2010 |
Eric Christopher <echristo@apple.com> |
32-bit constant ints only for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115001 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 335edd1b5f4d10458376cf20cda536fc291f5a10 |
29-Sep-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Removed a bunch of unnecessary target_link_libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 3609eb0de2f786ca6917d0388c37c23873dbd247 |
29-Sep-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Removed a bunch of unnecessary target_link_libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 864e65a8b1191b8f92fd68dd28feef50ef163c43 |
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 654d5440a477b1f6c89b051107e041a331f78e27 |
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| fda713abc03c74dab3ff16b7739494061481c82f |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Integer materialization needed the same thinko change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114994 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fd60980eb248f44927ea55c1f8d11fa019d318a6 |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Integer materialization needed the same thinko change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114994 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5633d7d7981397593da2839256668dd437af9dbc |
28-Sep-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Resolve this GCC warning:
ARMTargetMachine.cpp:53: error: control reaches end of non-void function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114992 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| a6136b7156fb8ed9b5ed3fc27296096ea0d5c99e |
28-Sep-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Resolve this GCC warning:
ARMTargetMachine.cpp:53: error: control reaches end of non-void function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114992 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8a92d8523b69c492e788c6b83f52307bb9e2750f |
28-Sep-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
User proper libcall names & condcodes while compiling for ARM EABI.
Patch by Evzen Muller!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4f922f2cca58d794671afedc22f82d96aeb46afa |
28-Sep-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
User proper libcall names & condcodes while compiling for ARM EABI.
Patch by Evzen Muller!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e527996e6891f18196ca628be56aa31beff2e593 |
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| b20b85168c0e9819e6545f08281e9b83c82108f0 |
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 9bc2306405d3c8c38ed949579e388272246227a7 |
28-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Factor out dbg_value comment printing and teach MC asm printing to use it.
This should make the arm-linux self-host buildbot happy again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114964 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2d0f53bd6348be3b28ffa53c37e3079bb33dd170 |
28-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Factor out dbg_value comment printing and teach MC asm printing to use it.
This should make the arm-linux self-host buildbot happy again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114964 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8c68f5d6edb01207d27c57325eba1cb04dfced6a |
28-Sep-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Add ARM Disassembler to the CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114949 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
isassembler/ARMDisassembler.cpp
isassembler/CMakeLists.txt
|
| 38e1390c29c024d5bbff3063c2a86bceb7bd3e60 |
28-Sep-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Add ARM Disassembler to the CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114949 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
isassembler/ARMDisassembler.cpp
isassembler/CMakeLists.txt
|
| 053e08ef7627a2edc3ee52f75897b437ca300c7d |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
80-col fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114943 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMELFWriterInfo.cpp
RMGlobalMerge.cpp
|
| a99c3e9acd95f5fbfb611e3f807240cd74001142 |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
80-col fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114943 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMELFWriterInfo.cpp
RMGlobalMerge.cpp
|
| 60b668c67a68ae36db5a8f1676c4baa8babfa294 |
28-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it. Radar 8465431.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 02aba73a9ec04d0de9424422249af3948ca9573a |
28-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it. Radar 8465431.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 72b926bb743135098e1727804c3750279e63b37e |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework builtin handling and call setup. The builtin handling
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114934 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7ed8ec94d96cc87e768fd5ebe4ddeb04dd56e8ab |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework builtin handling and call setup. The builtin handling
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114934 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e387baadc1716e1b0be54d270f708f25cc4c32c3 |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114931 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 5371cabfc26ced514069de95cd04f6311f782716 |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114931 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7194838a9d1f7770c9bf905ea1fa3eef49adcf99 |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix fp constant loads to have a destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114930 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f5732c4ee5af93bddeb8f4612441bfdf19237ea3 |
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix fp constant loads to have a destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114930 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9f9d21646c876bcc3ca886a9b2b917d4cc4da4ad |
28-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114915 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 385cc5eede9f81717b03121baf47b7aa185b5128 |
28-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114915 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d5f2300f8566f801e9704ba67b7ecbc2a278e0de |
27-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM-mode eh.sjlj.longjmp MC lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114896 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5acb3de8b7cfd5a104722526b731a3c87bb1a46e |
27-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM-mode eh.sjlj.longjmp MC lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114896 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 66d3b4bc7c47b6fafe795ecff0d3e80858ed627e |
27-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114892 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 376ce97baca2bcf97ab420313a876214cde7f9df |
27-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114892 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 08506221e493316521016e800c0de1fb45d46d59 |
27-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Hard to imagine there are still people using inferior compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114862 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
RMTargetMachine.h
|
| 3b9569e70db0b5a0d1389384a07fecbea8dc7dc2 |
27-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Hard to imagine there are still people using inferior compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114862 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
RMTargetMachine.h
|
| 426313624725c39521868263a2a9487abf6a8a70 |
27-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Odd additional stub framework for the ARM MC ELF emission.
llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114856 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
RMELFWriterInfo.h
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
MakeLists.txt
|
| fd9493d74e5429eab44638cd9badbad9090cd713 |
27-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Odd additional stub framework for the ARM MC ELF emission.
llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114856 91177308-0d34-0410-b5e6-96231b3b80d8
RMELFWriterInfo.cpp
RMELFWriterInfo.h
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
MakeLists.txt
|
| b59abc868b75fdd4310c93603cb71089a7587a92 |
27-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Insert missing coherency in comment. Add a quick check for hardware
divide support also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114813 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1127c720ede18f8ffaae4d7d6209569803c24720 |
27-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Insert missing coherency in comment. Add a quick check for hardware
divide support also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114813 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7802e5e2d2d62b32697a6953746e60e2202700d3 |
27-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Mass rename for Jim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114812 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 43b62beb4cac4337a080c2d3fb8f218a7ffb59c3 |
27-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Mass rename for Jim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114812 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e96a4b04467e75ca151de180d43c34b2b05487e2 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix IIC_iEXTAr itinerary class of Cortex-A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 5981fc67883bfa74ac13625b05442b54ea7f6a1f |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix IIC_iEXTAr itinerary class of Cortex-A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 1fb3657d51ef470589d7a7a5361fd6c14029cf2f |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a unused instruction itinerary class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 27fdcd1c95fb1ded32d5e3876fed3c0f0641ab30 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a unused instruction itinerary class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| e459ad4380c5eed48471d4dac025f732c909f6d3 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix zero and sign extension instructions scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 576a3968a2c1607d0ca0d87b28f8509b633e4bf0 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix zero and sign extension instructions scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| ccba3a6a1ddb723aa799044d9b1c3c5392d0b22d |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
More pseudo instruction scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| bd30ce4311e158f1bfc6c95987ffbbad2193fef3 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
More pseudo instruction scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 6b530794d75c306471eeb68594209c71072f7a29 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 5be39223216298009799d4a51ed8669934685d58 |
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 0793c9ffeea806dbf81fd3b3a8066b435728e9f0 |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114758 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 433a5785cc8201a8a384f0a5648d3dbac87f9fbc |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114758 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5884f8942ef5602d7f29bfec1731b2e7e2d211a4 |
24-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable code placement optimization pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fff606d7b2d65495050360056acc65ec667a93b5 |
24-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable code placement optimization pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b2a7dae5aecf58c776dbcf760df734c68bbf50b7 |
24-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a potential null dereference bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| de0e11c8f3f9ad60844c210bf68111db6e25f9a9 |
24-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a potential null dereference bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 325fc0b687d114113f2cb557248677be8817ebf0 |
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| f523e476c2e199220306b367b7bd834978fb93d6 |
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 85a5c32287005113b019b2bb105f66a70ccd8c73 |
24-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Set alignment operand for NEON VST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 2a6e6161422154ea44f9e653e2d0bbfc3942af2b |
24-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Set alignment operand for NEON VST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 53748dfadb43e5be17e2b3572ea1f172f88019ae |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 453900814e5245fd823b2b24ee9da9b5e8b4bfc4 |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6c5ab7e1bfc83a4b9b267f4cd8e69042b1f4799f |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
#+4 --> #4 for consistency with other asm output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b327e1374025f877f323d47b812e543e350c9885 |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
#+4 --> #4 for consistency with other asm output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4c228fedc212271c3f6842614b5c7621a859bfeb |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix formatting of output .s code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 45d6c1777ceb7102db5907fed0e4899a0b006afe |
24-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix formatting of output .s code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f8d2879879cfaf559732c749ce26f3a91c6b55cf |
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add isConditionalMove bits to X86 and ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 71e416ac3aeccfadec2a57150b4f4a243ed6e461 |
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add isConditionalMove bits to X86 and ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5aaa41eb610f9a75bfdd6f8cf339661fa0e07f49 |
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Set alignment operand for NEON VLD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 40ff01a0305403541353ac83f9f498ab67ebe944 |
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Set alignment operand for NEON VLD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1c4637a4c3d7d4e4eda87ca1afde63569bf3f97d |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
never mind. I can't read, apparently
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b2dda4bd346fe9a2795f83f659c0e60191b2e6a0 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
never mind. I can't read, apparently
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8b9a36b52679b633fee66f5d358969513c491218 |
23-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 676e258366dd17a0b4ee6ac66914237ce181202e |
23-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1706da4737f6ed7b5d3fd37e747e24980b862e59 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
constant. Hopefully the non-Darwin bots will like it...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 24e6f2f802e43af0e3c72ed17fa73e3bc101dc9e |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
constant. Hopefully the non-Darwin bots will like it...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 57394d076cb1b7c080dbe0cced4d30980f2d5c7c |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
explicit 'unsigned long' on constant value. Hopefully make bots happier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5c49b6960967be165cdf5877832772da048e9690 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
explicit 'unsigned long' on constant value. Hopefully make bots happier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2f37999b5b22d74980ef282c7fca4267ea4b7c43 |
23-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Unbreak build. Jim, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c8ab9eb066f6d35880e3a24436baf21236c921ca |
23-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Unbreak build. Jim, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 9ed10a8c494c6bbe77525ad676d9739ffed01b81 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| 2e6ae13bf6e09d844b76b0a12861d25be0842b03 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| d4d16f04baaf4ff6369630c3090f0a6188a4a3ed |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
nuke unused var
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.h
|
| 16c9a64c287dba4c58404b92b3fa9a9089e649f7 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
nuke unused var
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.h
|
| d64d18815e1b650b7f547fd9da766c151f3bd6ef |
23-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
If there are multiple unconditional branches terminating a block, eliminate all
but the first one. Those will never be executed. There was logic to do this
but it was faulty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 108c8724663354050dc09bb1262c3e4511adf82f |
23-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
If there are multiple unconditional branches terminating a block, eliminate all
but the first one. Those will never be executed. There was logic to do this
but it was faulty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 6ccb0331c5a446f4e10e4361adb8e99412a30291 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for ELF PLT references for ARM MC asm printing. Adding a
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMISelLowering.cpp
RMMCInstLower.cpp
RMMCInstLower.h
|
| 637d89fe0eca4fa2b9c95f6c15eb69a99bae83bc |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for ELF PLT references for ARM MC asm printing. Adding a
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
RMISelLowering.cpp
RMMCInstLower.cpp
RMMCInstLower.h
|
| 8cbf3867a659527d2c5b1a66ff4f3cc01c4a9913 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable a few additional asserts in MC instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| b6ec8cae3cf437ea4e3d39ad209a0687df4686c3 |
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable a few additional asserts in MC instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| f0064aed8b3ab56508e32549da63bca5eb6ee224 |
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VDUPLANE DAG combiner to just return the result instead of calling
CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b68987e4bff7cd269e0cb40b30851e9c2195db99 |
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VDUPLANE DAG combiner to just return the result instead of calling
CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7f60fbdd23156b2d873e9fcf52ccf6bd449d0f95 |
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0b8ccb82527616d0fabe5083e69a05e1950caff2 |
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e804549cef90325d3e835a35b717f3e49fe4bea8 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f0633e48eb9d70d5db31a7498736ba21a9ee410c |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d2799e6b8038234bfb577080d49aa4f460f52d42 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove a few commented out bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| bfbe1875934f046eb5cdb107fb5eccd6d86f7db5 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove a few commented out bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| e5a72558a47713fb4dd9776bfe3df25a9508605b |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add PrintSpecial() handling for in ARM MC instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 00d01f1a427c34f444f1935911529becfbf1d51e |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add PrintSpecial() handling for in ARM MC instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| e92e926046a03d1a30ab93411016aa8482780fe1 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MC instruction printer support for ARM and Thumb1 jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a2244cb38781e596110023399c7902b5ee5087fe |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MC instruction printer support for ARM and Thumb1 jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7bdff5a29be0e30e5b480f2d644cec89c1f2fa18 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 205a5fa8e4233cdcdc71152c0f8c4334ea9ce2eb |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5a941003c464d59aa0e5ead0be73c45340518454 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 1b935a3d2e2619c7de2488163fc1501285b53fa3 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| bf7eb36976d6e715fee5da407beea6ac3a10ca28 |
22-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 691e64a54ce899409abe7c131d15ed75e3c1fef5 |
22-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 27b1a4a11cbaddd5d4a7227427d7e3caca501550 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add start of support for MC instruction printer of ARM jump tables. Filling in
the rest of it is next up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 882ef2b76a09cdc39d38756fca71cf6cf25ae590 |
22-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add start of support for MC instruction printer of ARM jump tables. Filling in
the rest of it is next up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 289b962fae94a50f636ecfac924c78bb4b797e8c |
22-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 861416757246f7e2d42cc465137d520105f569ab |
22-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ed3e0638525f4e5bc39d3ecc5d6282b7638ada94 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 6dc99a966d7f72d627750142b8e69e08f967bb3b |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert a couple more places to use the new getStore()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fc448ff89b4fb7721de9da0b96fd00c13160c4c7 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert a couple more places to use the new getStore()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| daa44a53c9445429820033b1f74f00d5ac6a338f |
21-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
and store intrinsics are represented with MemIntrinsicSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 65ffec49f73d1f8856211b107712c58cc9636b78 |
21-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
and store intrinsics are represented with MemIntrinsicSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 6d301553cf248f79299e4ef0ad68fc30a57f12b6 |
21-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix errant printing of [v]ldm instructions that aren't a pop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 532baa5d537e6cbfd0642f6f4f10ad9f8571fa85 |
21-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix errant printing of [v]ldm instructions that aren't a pop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4e852d5f6d7491b267ff418fb6587fe6212bc889 |
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Fix buglet when the TST instruction directly uses the AND result.
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 8ff9bb189ce188452e6cae6ed65cb2745814126c |
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Fix buglet when the TST instruction directly uses the AND result.
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 3b65acae5390d2c798806fbbb0080f2530771c14 |
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Move the search for the appropriate AND instruction
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 04ac81d5db058a3a9492e1aff1f398a8643bfda9 |
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Move the search for the appropriate AND instruction
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 1450c4d3c59001b5b0dd7d2983cc9ba88a949417 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d1c24ed81c43635d00ff099844a9d0614021a72b |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c515938bc6c609b156fbf3609a2849091489282d |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
|
| e72f2027e9116c55a5b39ac72732df8d6c45d37c |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
|
| b1605b16eee965667b57e2799065399b8a45dad4 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 62c323479764f3d64349de86327d4dce8f999f14 |
20-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMMachineFunctionInfo.h
humb1RegisterInfo.cpp
|
| 1dc335a79f5e899aacc6710dfe08ef20abb6a6c0 |
20-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMMachineFunctionInfo.h
humb1RegisterInfo.cpp
|
| a1b373fcaec068186b994f537df0956fc366b7d6 |
18-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 895dda6fb541a4c56b58dafaaa767b980b27b0c6 |
18-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCCodeEmitter.cpp
|
| 50e30a6ab5a4d2c5b9c2227e0a3086444810df56 |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Thumb opcodes for thumb calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| c109556a0a7f0dca78f60967c3560fcaa27097a0 |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Thumb opcodes for thumb calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 163da40c4ff7ac029534094dfe4e2cf654d6289c |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add addrmode5 fp load support. Swap float/thumb operand adding to handle
thumb with floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6dab137b889d1fafdeee9c70c2b59d549d59163a |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add addrmode5 fp load support. Swap float/thumb operand adding to handle
thumb with floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4d394ff9839e1891d27ffa0b1b2acf785805fed1 |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Floating point stores have a 3rd addressing mode type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b74558ad3e1822f90e363c400bd6c06e94c200e1 |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Floating point stores have a 3rd addressing mode type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dc6cbaabe08c076fc37e6805a70721ddff9dd08e |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
factor out a simple helper function to create a label for PC-relative
instructions (PICADD, PICLDR, et.al.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 988ce097b7774ebc935ea539f3d88c2dcc3405b2 |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
factor out a simple helper function to create a label for PC-relative
instructions (PICADD, PICLDR, et.al.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b0e7f46c5102f9f58f036c3bcae36c99ec727959 |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
PC-relative pseudo instructions are lowered and printed directly. Any encounter
with one in the generic printing code is an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| d30cfde935cf5a8649285b6c47abb5e0f6669590 |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
PC-relative pseudo instructions are lowered and printed directly. Any encounter
with one in the generic printing code is an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 6906f3cffe762a39d8617cefb3a8a0f97a14b533 |
18-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 92aa1f71230f086ddb3aaf67e18cea6f3d1f3afe |
18-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| f5091ab8b8a390ff957eb6385929fa2ba2a65487 |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MC-inst handling for tPICADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| fbd1873041783f388de1c36c5d46c82a9ad46ef3 |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add MC-inst handling for tPICADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| d63697e529cad2142619425de8bca0251c6b0511 |
18-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 75f0288b7dff1fcb24d9d61ea3e9547ba21382e4 |
18-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5e0d04ec4c7a3750f470de9fe91d5ed50fca1c10 |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
and shift instructions on ARM. Update the tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| e6be85e9ff6bd28c599421a120a8491257c13ebd |
18-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
and shift instructions on ARM. Update the tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| b20590fa87bdb3b8fb18939a79b80d0f375bf842 |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework arm fast isel branch and compare code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a5b1e6810769bef9a1fd98c69877bdfd75d7b106 |
18-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework arm fast isel branch and compare code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b3bfad0830b03ebf41d18f894c34fbef312dba72 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Hook up verbose asm comment printing for SOImm operands in MC printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 74d7e6c64e955f89e6d3d4023d36fd481da4cfc1 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Hook up verbose asm comment printing for SOImm operands in MC printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 7c08660fcd4e5e6c331f2a40b60fc6632aa669c3 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.h
|
| 196b48b708af4bba14f9e3afb6682c0f0098919b |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.h
|
| ffb8845ff5344095c7cf4fffb95fc7428e9d47ce |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMMCCodeEmitter.cpp
MakeLists.txt
|
| 568eeedea72c274abbba1310c18a31eef78e14a4 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMMCCodeEmitter.cpp
MakeLists.txt
|
| edd3d51c636e04a4abf32323a66864df311581ff |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
handle the upper16/lower16 target operand flags on symbol references for MC
instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInfo.h
RMBaseInstrInfo.h
RMMCInstLower.cpp
RMMCInstLower.h
|
| c686e33d12f84e1e1f5c96eadef851d078bab043 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
handle the upper16/lower16 target operand flags on symbol references for MC
instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInfo.h
RMBaseInstrInfo.h
RMMCInstLower.cpp
RMMCInstLower.h
|
| 0d1220608d9c2f9db00dcd3cc028b4ce91e0c409 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a28abbe24568d39414be7ccb7a1f659f40e487e2 |
17-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5c858c88cc35391d076280f8f9227b212467d822 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
MC-ization of the PICLDR pseudo. Next up, adding the other variants
(PICLDRB, et. al.) and PICSTR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| b74ca9d63104c94b800f2763a654d19f3eb30304 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
MC-ization of the PICLDR pseudo. Next up, adding the other variants
(PICLDRB, et. al.) and PICSTR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 8de878701f9be58b71998f3813656d2ba90d1893 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure to promote single precision floats to double before extracting them
from the APFloat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| 1d51c41a457b99d646e3a9b9fae1e913f7a60dc0 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure to promote single precision floats to double before extracting them
from the APFloat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| 2b95a073a2f93f1babe63e250a73dffb031a745e |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove support for "dregpair" operand modifier, now that it is no longer being
used for anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| de0ae8f83dd8eabc831b0631c20ffa3b53a774f2 |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove support for "dregpair" operand modifier, now that it is no longer being
used for anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 3c2fd42d51214e00fba89d51bd13a15f1d0746c4 |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
When expanding ARM pseudo registers, copy the existing predicate operands
instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 823611bfba4fb2c1abbba2e59d68432c6d0a9e9a |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
When expanding ARM pseudo registers, copy the existing predicate operands
instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| ff8761794ce06ad45a3b5af0ede8aa02aa649e2a |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
unnecessary dtor for MCOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
smPrinter/ARMInstPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| a8e47b3319db56675f8e80f4bb015c163110b902 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
unnecessary dtor for MCOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
smPrinter/ARMInstPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 2ec9d0c827545a92087078b8b8df1b6afa12f9b1 |
16-Sep-2010 |
Shih-wei Liao <sliao@google.com> |
To get address mode's S-bit, we should use ">=" instead of "!=".
This is in order to prevent missing S bit in ARM code generation.
Change-Id: Ieac28c6a2409c1c0d2d0c46a2b01a34c47841970
RMCodeEmitter.cpp
|
| e8ec223e344c3c4db95dcee42c46a829d04f8cee |
16-Sep-2010 |
Shih-wei Liao <sliao@google.com> |
1. Better support for access constant entry (add emitLEApcrelInstruction)
2. Add suppport to emit ConstantVector and ConstantArray
3. emitLEApcrelInstruction uses PC relative mode add/sub and the offset
need to be encoded in so_imm (A5.2.4 Modified immediate
constants in ARM instructions)
Change-Id: Id7a933dddbd7e80289bf5befa48a054dc765a644
RMCodeEmitter.cpp
RMJITInfo.cpp
RMRelocations.h
|
| c326abc2ddc24585c016f0732222c2a3f46e0963 |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| ea606bb76b9922f67b678ea48645cdc9bfa0305b |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 0929cf1df88bf678acdaa9b0a1946800e15057bb |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrFormats.td
RMInstrNEON.td
|
| 9d4ebc0eb80c770aab5b51ca459748a6ac8f1699 |
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMInstrFormats.td
RMInstrNEON.td
|
| 73691a61b221513b5d25d351c754fea47e7fdd19 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for the 'lane' modifier on vdup operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 765c4d947791c6d92532ff81b6d9649e237b2084 |
16-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for the 'lane' modifier on vdup operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| e44257bbd4dac8656e797671f7ace48f8217c0b5 |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remember VLDMQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 06f264e504d75f0426eea55b9f9e36c780d8a4fc |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remember VLDMQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 8c1999bc98b1bc3dd64dfab4282da9b8fe2bc970 |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 31bbc51ac9245bc82c933c9db8358ca9bb558ac5 |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| bfc7bfe49a01b987cdde4ff7b9c0a4afe6528712 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 60396975bea44c8d233eb11df2eb7599d2f5fa90 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| dc3c93266cd023dd0c8015626ef412b2d35d04bd |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
|
| a4c3c8f28d9465dc7c42eb43c2377530f1821574 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMBaseInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
|
| aaa834a043890412e66cbac70891be85d7b60abe |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
merge the common cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| f1c3eb37ae96572e1df34bf980b9ecd149b5ee33 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
merge the common cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 088e712ab59477951bfb3e890bb2a96705e4d1f8 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
if the register is a member of the SPR register class directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 7e2c04fd05c08d46ecb304938767b4b21cdb9325 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
if the register is a member of the SPR register class directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 6491bdbcd95a1af6341cbf257ad2c526a8c1d344 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Reduce dependencies in the ARM MC instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| d8be410d4b1bb2cc5e6917ad15de24bbe7b56d78 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Reduce dependencies in the ARM MC instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| dd13e93dfe62ee787c6b2698f0af5175989cb418 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix spelling typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114008 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
|
| 8b7fa198c352993c406b756c84531e33fe1b49eb |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix spelling typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114008 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInfo.h
|
| ea62e37056cc77e3229e1e09c22f396304b09963 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Factor out basic enums and hleper functions from ARM.h for cleaner sharing
between the compiler back end and the MC libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114007 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInfo.h
|
| 754578b56518d57c28cd439a6dab2b75865e6746 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Factor out basic enums and hleper functions from ARM.h for cleaner sharing
between the compiler back end and the MC libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114007 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInfo.h
|
| 7555705c8a0a80849e0543c57f5bd797ad27ec53 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for floating point immediates to MC instruction printing. ARM
VFP instructions use it for loading some constants, so implement that
handling.
Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
smPrinter/ARMInstPrinter.cpp
|
| 26edbcb8d5da5fb65816a97f740c9868fa798df4 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for floating point immediates to MC instruction printing. ARM
VFP instructions use it for loading some constants, so implement that
handling.
Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
smPrinter/ARMInstPrinter.cpp
|
| 7aca1fbae3c9c394d8edea8342e6adcc5df13926 |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d64816a8d04e5b20b7a0628bc1f22607c07e8f69 |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d7a0af3daf6a87f8edcfbc978e6f8e821f0ec57b |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 3a951829fef6a2cfca87611e94cf48e0136f81d5 |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0b69506f17cca325303c86462b9d3fbc2345bd6f |
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
the darwin9-powerpc buildbot keeps consistently crashing,
backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7602993f2dc0a33d04cf5582cdf0cf515896ea7c |
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
the darwin9-powerpc buildbot keeps consistently crashing,
backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d882b01de69f8135c08983450888d2738295bf45 |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 34327856d92d027733524b9418bd188a9e8db5db |
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 641df469bb6e66172284a3200494150598935c80 |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Spelling fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 064312de8641043b084603aa9a6b409bc794eed2 |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Spelling fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| dfb447f481583ea8d0cead056d9a04367a3e93f3 |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and
storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113918 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 168f382dc67e5940cabdb28dc933c4f91cdd3137 |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and
storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113918 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| c7a331ca4ffaba39818d72131c9a55bfcf133242 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Reapply r113875 with additional cleanups.
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMInstPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 05ae0c6026c15cc934ef2117a7a75ae57c55067d |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Reapply r113875 with additional cleanups.
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMInstPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 5a9a4fa0521c0e6935c4a25c038e28fe0711a252 |
15-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Emit libcalls for SDIV, this requires some call infrastructure
that needs to be shared a bit more widely around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113886 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bb3e5dad6685dd54625edae789d1a703f4107a69 |
15-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Emit libcalls for SDIV, this requires some call infrastructure
that needs to be shared a bit more widely around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113886 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 5eeaf26c4d2b001102b8b788b7f458d854772381 |
15-Sep-2010 |
Shih-wei Liao <sliao@google.com> |
Merge commit 'refs/changes/82/67782/1' of ssh://android-git.corp.google.com:29418/platform/external/llvm into update_llvm
|
| 4442d11d55edac0a6b678003983caf6e56852690 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
revert 113875 momentarilly. Need to fix the MC disassembler to handle the
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 684193928c6b6680df42c8d2598bb403e28f3de1 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
revert 113875 momentarilly. Need to fix the MC disassembler to handle the
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 51de8f34be5f5ea6534806c2bc48897a66709e55 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 15d78984d57378c3600ea26c37e1be05863644ea |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 70c4b84d344a60c6c89cebf5dd09234043c8972e |
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113876 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 308f64a7c847821a4260da673089e7b4af74e56c |
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113876 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2d5d0d2960b91a40e8a1a95b341d48dfdb1b9018 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113875 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| fe125557dd8ef191b572edb4b6fd4b2a4a2f2f9e |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113875 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 164de2283a29c8fdcd25eb1bc116d4cfb84bb7ef |
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
set isCompare for another three Thumb1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113867 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| f7d10f5c129f31bf4c97424b2c9786db6ee9c5cf |
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
set isCompare for another three Thumb1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113867 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c3452d99cc450e44fb0dc472521ad48521bb5309 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add predicate and 's' bit operands to PICADD instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5b46d62c4459dbfd56bb6ac650a271cd02365092 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add predicate and 's' bit operands to PICADD instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 04a067cd7178e1c40c69cff1722afa4500b1c0b9 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Avoid warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113857 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| fe3ac088ee0a536f60b3c30ad97703d5d6cd2167 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Avoid warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113857 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 0d6fe6e871255b498a463124d15d5aeacb4031f9 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
fix comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113856 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f3f09527e6484143fcdef2ddfef0b2f016881e36 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
fix comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113856 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f23bd5f6779a6f463675b39ec1bc5232e1a16c08 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Make NEON ld/st pseudo instruction classes take the instruction itinerary as
an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4). Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113854 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9d84fb3c9139f650e0252c1ed1a3b6e169cb13fb |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Make NEON ld/st pseudo instruction classes take the instruction itinerary as
an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4). Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113854 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ee3dba3ec25633e7e13a9cefafe276159cb04932 |
14-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
set comparable for a bunch of Thumb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113849 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 007248b478e0c39faa8719b562c2ae47bfc2251e |
14-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
set comparable for a bunch of Thumb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113849 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 2147b5fa3c0d04747834ba9247eae7f2b17df2f3 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't ignore the CPSR implicit def when lowering a MachineInstruction to an MCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113847 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| 1685caffedd0d0b351e0ec475d2529d90efec2fd |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't ignore the CPSR implicit def when lowering a MachineInstruction to an MCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113847 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
|
| dfeaebd8f9b8622ab0e1531c39e7278cb74006f3 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Clarify comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113846 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 9854f197f3385713c77df8cea0e39a231b91a650 |
14-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Clarify comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113846 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 7a4150705ccd171c0e75ad85d305a7e5e91e7998 |
14-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Eliminate a 'tst' that immediately follows an 'and'
by morphing the 'and' to its recording form 'andS'.
This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.
I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113839 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| de90bfd14af1a850ec43438d9cfffeb83f50a5a1 |
14-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Eliminate a 'tst' that immediately follows an 'and'
by morphing the 'and' to its recording form 'andS'.
This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.
I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113839 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a283da5bedc75b4f90f05900f124594002ad1189 |
14-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix QOpcode assignment to Opc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113837 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 23da0b23a3f01d9a46e54a4ba6fc6e4b42eda7c1 |
14-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix QOpcode assignment to Opc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113837 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f318164d18455fe44fcc9e03329036917f303edc |
14-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113819 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
smPrinter/CMakeLists.txt
MakeLists.txt
|
| 3a210e2d302758101ac06946e86027b327c7d0f3 |
14-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113819 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
smPrinter/CMakeLists.txt
MakeLists.txt
|
| b035d820c57792a3772c5192331eb6c989b775d0 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
RMTargetMachine.cpp
MakeLists.txt
EONPreAllocPass.cpp
|
| bd916c54b7989ddbab373c61eb1ed2556ca44d27 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
RMTargetMachine.cpp
MakeLists.txt
EONPreAllocPass.cpp
|
| 65ff3622f02d8d48c52f90cef0d910da66f1e319 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Switch all the NEON vld-lane and vst-lane instructions over to the new
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113812 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 8466fa1842ad4f2d6fadcf5c23c15319ae96b972 |
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Switch all the NEON vld-lane and vst-lane instructions over to the new
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113812 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| f6d6fee473408227eb8e7c00619f0fa037f8c141 |
13-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113768 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
RMMCInstLower.h
|
| fc16a8950c671b9434e60702ba31224c39ee133f |
13-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113768 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCInstLower.cpp
RMMCInstLower.h
|
| e1e63e8abb587eb6094fc47569b3a9b4516efb21 |
13-Sep-2010 |
Shih-wei Liao <sliao@google.com> |
Potential fix for b/2988615.
Change-Id: Ia15a1f5e25360dac4ca4bfecc35cb1aa6b6db1b8
RMCodeEmitter.cpp
|
| a95f589c757c8c857096a07e0d376ca9aaec6c2c |
11-Sep-2010 |
Shih-wei Liao <sliao@google.com> |
Apply changes on LLVM r112364 after merge.
Change-Id: I9688675d46dca0d564206616c40b005669269010
RMAsmPrinter.cpp
ndroid.mk
smPrinter/ARMAsmPrinter.cpp
smPrinter/Android.mk
|
| 9edc31c101ba6efd4b653db935810308f659c560 |
11-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix the asmparser so that the target is responsible for skipping to
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113688 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cbf8a98c7c652e96967623c80cb945fef001b090 |
11-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix the asmparser so that the target is responsible for skipping to
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113688 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| da61c1662bd86ea1f7fad601e9966f1b700636c1 |
11-Sep-2010 |
Shih-wei Liao <sliao@google.com> |
Merge commit '69494cf8102cf872e9cb76662e9960be7c112112' into HEAD
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/Target/ARM/ARMCodeEmitter.cpp
lib/Target/ARM/ARMJITInfo.cpp
lib/Target/ARM/ARMRelocations.h
lib/Transforms/IPO/MergeFunctions.cpp
Change-Id: I23d40983717e072fa49334c1fa54f2cf961476c7
|
| 5d7db1fa13488aa726bf61a1c7f544661cb01ef4 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename ConvertToSetZeroFlag to something more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| a65568676d0d9d53dd4aae8f1c58271bb4cfff10 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename ConvertToSetZeroFlag to something more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| df43da9e50014e1f89626bf9bd3868d90586b3c9 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
No need to recompute the SrcReg and CmpValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 3665661a5708c8adc2727be38b56d1d87ddeb661 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
No need to recompute the SrcReg and CmpValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| f93cebaf113032a711b2f434bf2c37e1bc6a4cee |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Move some of the decision logic for converting an instruction into one that sets
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 92ad57f066e9f256e4e3d72febf152e68caa80c7 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Move some of the decision logic for converting an instruction into one that sets
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 154909222cb004dbff875cdcc3d33df30cc0c5ec |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Start sketching out ARM fast-isel calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113662 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d10cd7b31464a73e3a19b9fada80b9567b04d314 |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Start sketching out ARM fast-isel calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113662 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2f730643475e1f7167d802d23ac96b79fdabaab8 |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
For consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113659 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 44bff903e20574e7ae6b23c7c3f244db39e0a035 |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
For consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113659 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 06660e8720c8474da451942c2b6c48b181e275ff |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Newline at end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113654 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
|
| 09b2171d7e78de240c4b510dd9808010a5e2efdd |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Newline at end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113654 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
|
| 4eea118bb3b9912bfec7c3beee92f3df447fa5b8 |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Split out some of the calling convention bits so that they can be
used for fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMISelLowering.cpp
|
| 6f2ccefdc069b6bd2e8f8b110fc3205b821a17a7 |
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Split out some of the calling convention bits so that they can be
used for fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.h
RMISelLowering.cpp
|
| c9c9de1260bf0fd85b9628c614cb7289f30ffb9a |
10-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Modify the comparison optimizations in the peephole optimizer to update the
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 220e240bdf3235252c2a1fc8fcc5d4b8e8117918 |
10-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Modify the comparison optimizations in the peephole optimizer to update the
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 3373a6638c29cbd68ec2da2089f4fc58213c124c |
10-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113637 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 51f5b67395780b8421f4aa6ee998ed51b23dae9d |
10-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113637 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 338c97baad1444a4158a7d99162e0e654f058c43 |
10-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
smPrinter/CMakeLists.txt
MakeLists.txt
|
| 4e9c939312ff73bd0c6a6485fd5f97012f5910fa |
10-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
smPrinter/CMakeLists.txt
MakeLists.txt
|
| af4c6f5182f510aeecbb82b52299e5f352d3b03e |
10-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Calculate the number of VLDM/VSTM registers by subtracting the number of
fixed operands from the total number of operands (including the variadic ones).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113597 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 979927ab26a1832ee2ecd1edb17d50184756f474 |
10-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Calculate the number of VLDM/VSTM registers by subtracting the number of
fixed operands from the total number of operands (including the variadic ones).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113597 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| daf207e732174aee86493581752036aa5a3fd58a |
10-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Reword since this may not be a bug but intended behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113584 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c8714bb144928f0b45826617ca701805093ffe36 |
10-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Reword since this may not be a bug but intended behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113584 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bd9c766fa67f718f225e461ed69c3d11cfe7068c |
10-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| efe7d9a12f441a256d67c4e4da494dcefca678a5 |
10-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 0cf9a820e435a74ef93930dcaf8917323f2f99be |
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.h
humb2HazardRecognizer.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.h
humb2HazardRecognizer.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 3288f13270360d667bf13f6393435cfa4e282c2c |
10-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113566 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 920a2089d9b737820631bc6de4c4fb9fa9ad1e07 |
10-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Fix build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113566 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 845b079c1e7d65839cc8bc853fae082d7adfc909 |
10-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Update comments, reorganize some code, rename variables to be
more clear. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113565 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| db12b2ba9c602fc9bedcf0a9b2e72e23e29005d8 |
10-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Update comments, reorganize some code, rename variables to be
more clear. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113565 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 203c5c75385c3d582ec4385e111f12a11189d1d6 |
10-Sep-2010 |
Eric Christopher <echristo@apple.com> |
64-bit fp loads can come straight out of the constant pool, not as
bad as I'd thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113561 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 238bb162514afac2cfb7221a0f102456de09f581 |
10-Sep-2010 |
Eric Christopher <echristo@apple.com> |
64-bit fp loads can come straight out of the constant pool, not as
bad as I'd thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113561 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3512654d327720193714d6c002379ccec3bade50 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move
some data around and implement a couple of move routines to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113546 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9ee4ce2f91250ef44fea427392c8dad369df8972 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move
some data around and implement a couple of move routines to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113546 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dfeb4f6b8b412b1071c720e32f41266f80b40ad4 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
New "move to fp reg" routine. Use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113537 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| aa3ace10c1b90e07114e60700c8c1f8e6b4f3e84 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
New "move to fp reg" routine. Use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113537 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d5eda142f2094bc34449d4e1a457c0e10b96684b |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
"Strike that, reverse it." -- Mr. Wonka.
Truncate when truncating, extend when extending.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113536 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ef2fdd21418e0cdc5df963a063b0f940964fa208 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
"Strike that, reverse it." -- Mr. Wonka.
Truncate when truncating, extend when extending.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113536 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| db4fc6a604fa96fa24061b11a8585c51ea432bf3 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add FPTrunc, fix some bugs where I forgot to update the value map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113533 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ce07b5458d87d5f5ad306a1d86785537e9a3ce0c |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add FPTrunc, fix some bugs where I forgot to update the value map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113533 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9c78dcf6c5652931ad268986544333eed0c8eeac |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Basic FP->Int, Int->FP conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113523 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9a040492f7ed084e12a19d56995855c9b5b1d3aa |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Basic FP->Int, Int->FP conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113523 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9a374dfaa80634a7eae85e7e7ba8cd9fb2aadca7 |
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrThumb.td
RMSchedule.td
RMScheduleV6.td
|
| 5f54ce347368105260be2cec497b6a4199dc5789 |
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrThumb.td
RMSchedule.td
RMScheduleV6.td
|
| e0af855b8fbbff064d3a01478d2103f861903be7 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113473 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0f1e9457a578cbc2073107f4d3d7529cbac7e5c3 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113473 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a092554e777ed9217a97e3fb6a3263ea3d4479db |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Nuke whitespace and fix some indenting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113463 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ac1a19e18ad73198ae54cc4bc08000523031f84a |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Nuke whitespace and fix some indenting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113463 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 46c6754580411c95b9278102b3cb6484a754b522 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Handle 64-bit floating point binops as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113461 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bd6bf0848ee651a3cf4ea868b7a7605e37b4e028 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Handle 64-bit floating point binops as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113461 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ff5fe9ba7671ecd4de42429a2a0ac392adf12809 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Basic 32-bit FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113459 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| bc39b829f2a1f1f0ce3cfe7f9dd99c3402ad2e62 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Basic 32-bit FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113459 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 328ca4d2403cfd24e0a9b724a4d5c8d4d09cae11 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113456 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 19d644d5a9cd6699e5f9f1999deb3c77b2bbdca4 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113456 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| c84676c9cbe72a7d1fe925a695b970cdf3c68de9 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Handle float->double extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113455 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4620360842bd8cddc5b1bad7f2f04214c91ac9cb |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Handle float->double extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113455 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 6fc6204d5e8f76a28a03debf74f2af592d7b3743 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite TargetMaterializeConstant splitting it out into two functions
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113453 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9ed58dff86f09699946641ba87f6c4f04a3773c8 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite TargetMaterializeConstant splitting it out into two functions
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113453 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e05e4524511d947fb0f35e6a4366f0dcf14da9b0 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Simplify copying over operands from pseudo NEON load/store instructions.
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113452 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 63569c99ec944210d0edc687d7411b5c687e97a7 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Simplify copying over operands from pseudo NEON load/store instructions.
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113452 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| ca4a9af750cbec8aaad073322b16feb74a766bb8 |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113442 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 656edcf138563068a2e7d52fb35f8de1375bad9a |
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113442 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 80498c669bd685f5c2329963bca0c93a9244594a |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Very basic compare support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113440 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d43393ae34ba7e39239d593742eb63086b68f29a |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Very basic compare support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113440 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b6c0d47d76c5ef1f3fc70b9517fa6ae98e23a277 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113436 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a88d8577e696e35bf72bbc2e5ab1f7e2002b8cc4 |
09-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113436 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8949da81805e3dfe51b4cafca248c0bd0feab69a |
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix LDM_RET schedule itinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| 7602acbf3b90af995606e199d68510b856c8e7e7 |
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix LDM_RET schedule itinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
|
| f12c667508110edd3a9588523640cd3a711a7149 |
08-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Make the loads/stores match the type we really want to store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113417 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 30b663339e4e76981a2fc4dee84959298c0a1dc8 |
08-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Make the loads/stores match the type we really want to store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113417 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 91d06604bcb3ec5d94f78d8b70ca0e9d408c8f27 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
Re-running some nightly testers w/ it enabled to verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113399 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d0bd76b0fb27830f18e15e3d73f2e383ff1c59f1 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
Re-running some nightly testers w/ it enabled to verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113399 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ce2393133083f31481ea41b592896a1bb8825e90 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix errant fall-throughs causing the base pointer to be used when the frame
pointer was intended. rdar://8401980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113394 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 951f699afb0872bec605a3d0e84c41cddcadf7b4 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix errant fall-throughs causing the base pointer to be used when the frame
pointer was intended. rdar://8401980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113394 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 9f5c4a94c34e93a0f8c48c777e610362565a3b4d |
08-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite TargetMaterializeConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113387 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 845c5757ed40f23595b89cc0ba1db05e2c3d0099 |
08-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite TargetMaterializeConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113387 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 23e844b1487b8ed50e9b6e706908cb536e0db6e5 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Be more careful about when to do dynamic stack realignment. Since we have an
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113366 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 30c93e1cd3e43e174994834900325fcff3322288 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Be more careful about when to do dynamic stack realignment. Since we have an
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113366 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d2e97313dfd812658a8b205072a3de714c969b94 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add missing assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113365 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6b53834d5fe1c51f3012f23ed9cbec267959e6bd |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add missing assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113365 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b263834aca54d14cc2f82718c2d833b8ec4349aa |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change the MC "ParseInstruction" interface to make it the
implementation's job to check for and lex the EndOfStatement
marker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113347 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 34e53140c2cc02ce4c9d060e48302576d3962e1c |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change the MC "ParseInstruction" interface to make it the
implementation's job to check for and lex the EndOfStatement
marker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113347 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ee0672f2ad43a5c328d11471f99f5024c6fc89a5 |
08-Sep-2010 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113345 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 186acea74646c9f3909b1968920bed8c7ab6148b |
08-Sep-2010 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113345 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| e4c62fbcab1d602b850c9aaad41929d22eb05c43 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113338 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4725ca746ae815f68627657fc4135a285670a4a4 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113338 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 12be250ead1809e9548823d9f2a89a5a391505ee |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
remove obsolete comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113337 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 707fb648d2b7ac8d206a20c9f02d631647e3b0ed |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
remove obsolete comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113337 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f583892fb61256727316c14441b17bf8d99dcf24 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
disable for the moment while tracking down a few Thumb2-O0 failure that look
related. (attempt deux, complete w/ test update this time)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113333 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e1e6d187863ad7ca2e5331f496f27d480cb39734 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
disable for the moment while tracking down a few Thumb2-O0 failure that look
related. (attempt deux, complete w/ test update this time)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113333 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 1504ddc6061a71ec24dd3bca79ffc909386107fd |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
woops. need to update a test along with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113332 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8b95dfe2b6c2c77b65bc35ce0db64d5a19617f29 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
woops. need to update a test along with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113332 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 65c4e8eb6fbd55934e76a7bb3fee3a70adf2895d |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
disable temporarily while sorting out a few test failures in Thumb2-O0 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113331 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8a076eb79db5f82729436938681e4787ebc4a305 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
disable temporarily while sorting out a few test failures in Thumb2-O0 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113331 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f8811af9818cdb74e5e8d9d82463a91bf193ea78 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
correct spill code to properly determine if dynamic stack realignment is
present in the function and thus whether aligned load/store instructions can
be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113323 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0cfcf93c95af91e809ef740eb0ab368477226b40 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
correct spill code to properly determine if dynamic stack realignment is
present in the function and thus whether aligned load/store instructions can
be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113323 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 4e51f4400ace464e9b9d90f374a7facb98927eba |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
VFP/NEON load/store multiple instructions are addrmode4, not 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113322 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 72db18243839860019ab93e7c30e86228f017ea7 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
VFP/NEON load/store multiple instructions are addrmode4, not 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113322 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 3d537195129f746767062caf8fe9158c2d25b5e5 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).
rdar://8394087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113297 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 447e7ac913181ec3eae7c56a73c059df5382c029 |
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).
rdar://8394087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113297 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 5c05cbcd0008e5254068a05f531ba35163b73c33 |
07-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113289 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| e2f70d1724a8336f5dd455fea7ec3d71592a2fa7 |
07-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113289 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 99d29915f3dc5a5d0cc3740e1046668967e584ec |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
hopefully fix a problem building on cygwin-1.5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113255 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.h
|
| 6cd5db41f7ed2446c9db0fd7bba4bb8591fe567e |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
hopefully fix a problem building on cygwin-1.5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113255 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.h
|
| f0fd95999d46181785cf9e6c88c46afa21be7b1f |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
in the case where an instruction only has one implementation
of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113178 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| ce4a3355d96971e7edcbff3c1975f83e1ddcb8f2 |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
in the case where an instruction only has one implementation
of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113178 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 13d589767eb08a0c90a69dddd7c1cc113229a7f2 |
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change MatchInstructionImpl to return an enum instead of bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113165 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 79ed3f77e8b87615b80054ca6e4e3ba5e07445bd |
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change MatchInstructionImpl to return an enum instead of bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113165 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 57c1257bbbc00c6663bd2a0a634d45101553c160 |
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
have AsmMatcherEmitter.cpp produce the hunk of code that gets included
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113163 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0692ee676f8cdad25ad09a868bf597af4115c9d9 |
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
have AsmMatcherEmitter.cpp produce the hunk of code that gets included
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113163 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b56dfd1bb914c709c45fe7ea11e5dded9f4ab7b4 |
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
remove some dead code. t2addrmode_imm8s4 is never used in a
pattern, so there is no need to define a matching function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 979b0618192cd99058a7a21c04341c47801dd688 |
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
remove some dead code. t2addrmode_imm8s4 is never used in a
pattern, so there is no need to define a matching function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| fc96d7800752892cdb73a3b0d22424ce20da755b |
05-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113119 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 252b491875c544335406fb461be0fed8649e3814 |
05-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113119 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 81760863d144656b1d9753cbedb4d97927429b81 |
04-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 17aa68055beed6faa48ca3a995c5b6fdf5092fd4 |
04-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 67c7268341659d6a1a29faff3ecd6bd171d9a486 |
03-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."
r112986 fixed a latent bug exposed by the above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
|
| 65482b1bb873dd820f54a24a2f34bd65f2669e5c |
03-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."
r112986 fixed a latent bug exposed by the above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
|
| 7db850bd856d3c1e2586a6f6c6397b020dbb5d42 |
03-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Check the local frame alignment for determining whether dynamic stack
alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112986 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| fc633002339439339e94f83eca9a012c6fc51e50 |
03-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Check the local frame alignment for determining whether dynamic stack
alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112986 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 856eafb9481b280ea46b940c4e2d3149375f4026 |
03-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| f572191fe43025bd85ab5d398a5b53305fdc6b8b |
03-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 6d3d52b9bfd823d49cf3ea77f94ab6145aa1d997 |
03-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
|
| 6a8700301ca6f8f2f5f787c8d1f5206a7dfceed6 |
03-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
|
| 21fb5c8b0480e12f9e439cd835341725ea1b1ad5 |
03-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| eb0c3d372906df9c61a31651a0ba278034447e94 |
03-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| d4e976a5e075cf86c76f5ad8a38169523967e10b |
03-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Simple branch instruction support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112923 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e5734105daf799dea671666059f7ecab6abb389f |
03-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Simple branch instruction support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112923 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7d46263237a74033dc41bf768d71ea907035eaaa |
03-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add basic support for materializing constants (including fp) and
stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112912 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 56d2b72884f98001cefdf8de61d6d7fc00d3df90 |
03-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add basic support for materializing constants (including fp) and
stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112912 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 28a11c52796c4506d5a72ca9e71de3a517e56aae |
03-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.
rdar://7352504
rdar://8374540
rdar://8355680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
|
| 1755b3964f931bdd6fa9b4c0138f666ccfa12aca |
03-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.
rdar://7352504
rdar://8374540
rdar://8355680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
|
| c5218ea0315c26313217aa3edab56bb35da1736d |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112852 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 5c33f5bf67f61e3a1addda6de735d28d550dd0eb |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112852 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e2e8eeac79224e6899e32f1675fb5a5945b7b549 |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that register allocation properly considers reserved regs, simplify the
ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| e7c14162631d845ff3c465bfe2c6bdf2f59dba70 |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that register allocation properly considers reserved regs, simplify the
ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| dcab47a6effbf4a03747b01c64e4fbbea1b52243 |
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fill in a missing comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 82a9c8480ecd41a1351274569f8d4e4de2723cf6 |
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fill in a missing comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 9550ea48f891d97a611b62d807dd1657b377a73a |
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| ffde080ae615906545eb33dab30e7bc47c2ac838 |
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| d7795a2ed7fec29211353ba0b422d554b02685a3 |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Clang's -ccc-host-triple was ignoring the arch specifier on my triple,
I don't need to implement this quite yet - and not for ConstantInt anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112798 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1f58741aabd00545468f4ecf29db3dba8e0bd6ac |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Clang's -ccc-host-triple was ignoring the arch specifier on my triple,
I don't need to implement this quite yet - and not for ConstantInt anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112798 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7abec8920f41b5d1d9ec8d5f06c39d40b01cd10e |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
This should be TargetMaterializeConstant instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112795 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1b61ef4b22c8ae0ef82685637142246a245f9ecb |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
This should be TargetMaterializeConstant instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112795 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f96e527cfdb1c05c73da2958b6163805ff906e8c |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
One definition of isThumb is plenty, thanks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112793 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| eaa204b2f8414a2ac5764a753c119c8cd40bade3 |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
One definition of isThumb is plenty, thanks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112793 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 35448158e8ca2f657a9e3ef65858833fdf87ea0d |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112790 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b0739b78332275906cd5ace2ae0d65a29135667b |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112790 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0cea67e33308c0e6a7db75c2ab16b08956d306c0 |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework arm fast-isel load and store handling. Move offset computation
into the "address selection" routine and handle constant materialization
for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112788 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 318b6eec8d72ad6dad887abde3fed484bd8d86ef |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Rework arm fast-isel load and store handling. Move offset computation
into the "address selection" routine and handle constant materialization
for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112788 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b2064cfed9823f83b9dda9ee2ef70c215967beee |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trivial cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 7af3a345a9aa1772d723c7e2c3a059dfdfba028d |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
trivial cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 6647ba4e23d7f995c5d9a0f9b4547546f61adec4 |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify the tGPR register class now that the register allocators know not
to try to allocate reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 352f23529c47486d35662de031403de9428c309b |
02-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify the tGPR register class now that the register allocators know not
to try to allocate reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 8d16b413cb261383d69adb86d0ba6451eabfc21b |
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| d0b69cf1198dadbb7bdfc385334b67f60f756539 |
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| fd6c6e603102d56c48f5d43507687182733750c8 |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Some basic store support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112752 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 543cf05b9cb98f50a22cf05137d97bb3bb61f94a |
02-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Some basic store support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112752 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e667ceafa490f762f2bbe876f4e5d40db0edb282 |
01-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add some more load types in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112721 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 4e68c7cca44d33771d376f1668d687ce9d8f11d3 |
01-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Add some more load types in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112721 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 49071048d8cafc11ab950cde1207424ed5324cf0 |
01-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112712 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 14ab39e43f151d833e74534c87b670b767ff0d5d |
01-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112712 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 79476545f88f0ce8be5ac7a32bf793ee3bad6b0f |
01-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 5bcb8a6112eca5fb72b39b6b4e608ab1b41e94de |
01-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| b9875480df977bb738490ff9a33740c816a7f190 |
01-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
We have a chance for an optimization. Consider this code:
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 43a6c5e2fccadb299c35cb3147d112f706922acd |
01-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
We have a chance for an optimization. Consider this code:
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 9fce9b6dec5deec32d0f70fb323ffdec9c6b71b1 |
01-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
And ANDS pattern to match the t2ANDS pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112654 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2d811d38d43479995d5b4c97b7a777b0f8984325 |
01-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
And ANDS pattern to match the t2ANDS pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112654 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b93fd8d23bef3c063e8a2bfd7636253326d2d1b2 |
31-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
SP relative offsets need to be adjusted by the local allocation size when
determining if they're likely to be in range of the SP when resolving
frame references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112624 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c1dc78de762e8a65fe1edd0cced13d94ab5a971f |
31-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
SP relative offsets need to be adjusted by the local allocation size when
determining if they're likely to be in range of the SP when resolving
frame references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112624 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b920f48fd81356229c82ff0645a27af6c7e2bd77 |
31-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
this assert should just be a condition, since this function is just asking if
the offset is legally encodable, not actually trying to do the encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112622 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d4511e947ee1e89a4f199bfac0d401976930ccfe |
31-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
this assert should just be a condition, since this function is just asking if
the offset is legally encodable, not actually trying to do the encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112622 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 7fd6f7361639c2cc05dbbcd8206d63fca14a40a3 |
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
- Cleanup some whitespaces.
- Convert {0,1} and friends into 0b01, which is identical and more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112593 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| da2ae63206bcf6856f9d717862508b94213c2336 |
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
- Cleanup some whitespaces.
- Convert {0,1} and friends into 0b01, which is identical and more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112593 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 09d3cce43ab4f7af166ec7ccdfc137abe20be98c |
31-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite slightly so we can expand for floating point types easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112568 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dc90804a402b9d617c154625e04a74ebd7fe3599 |
31-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite slightly so we can expand for floating point types easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112568 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 197dfa9acaeb6ea16767126861b6638f01d5579c |
31-Aug-2010 |
Eric Christopher <echristo@apple.com> |
If we have an unhandled type then assert, we shouldn't get here for
things we can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112559 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 548d1bb97e6510d1e16299058a4bacb068ede13a |
31-Aug-2010 |
Eric Christopher <echristo@apple.com> |
If we have an unhandled type then assert, we shouldn't get here for
things we can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112559 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fedf918b16a0f20347796a8e19c2fded1fd12ff0 |
31-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand MOVi32imm in ARM mode after regalloc. This provides
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 6d1e29d2f203093e3e03f15173c0f36637d3afe3 |
31-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand MOVi32imm in ARM mode after regalloc. This provides
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| a710318ed065b392bf6174433dd719fb538f4f0b |
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 55c134a26188291f60c44d027a837f05d797194f |
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 68322e5d81e982ca050362917555bc572c9a36ad |
30-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remember to clear the shadow kill flag at the same time as clearing the real
kill flag.
This could cause duplicate kill flags when the same register was used twice in a
continuous sequence of STRs.
There is no small test case. <rdar://problem/8218046>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112534 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 253627967454246d347a5038ec971f6738f77f07 |
30-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remember to clear the shadow kill flag at the same time as clearing the real
kill flag.
This could cause duplicate kill flags when the same register was used twice in a
continuous sequence of STRs.
There is no small test case. <rdar://problem/8218046>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112534 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 0f8fd69a7d9e323019b59270341855d0976f1c5a |
30-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
Auto-upgrade the old intrinsic and update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 973a074345add36c046c0f0bfea0156a532ab479 |
30-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
Auto-upgrade the old intrinsic and update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 800263cd08fe1943a1d14eabe40f80f82ffafccb |
30-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 663e339e208a9d54d3731618cb484e8a07c33335 |
30-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 366fd5ebfb62c0a45510d6cbcac2db501bb7429a |
30-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
When expanding NEON VST pseudo instructions, if the original super-register
operand is killed, add it to the expanded instruction as an implicit kill
operand instead of marking the individual subregs with kill flags. This
should work better in general and also handles the case for VST3 where one
of the subregs was not referenced in the expanded instruction and so was
not marked killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112494 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 7e701979ad20796bc930b21de3888ccfa0d8b33d |
30-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
When expanding NEON VST pseudo instructions, if the original super-register
operand is killed, add it to the expanded instruction as an implicit kill
operand instead of marking the individual subregs with kill flags. This
should work better in general and also handles the case for VST3 where one
of the subregs was not referenced in the expanded instruction and so was
not marked killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112494 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 34b4817b4079a750d00397447b986d29245b199c |
30-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 4822bce4aa395e3e96215e18f5c926c78d4a0e64 |
30-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| e88c8a67b11820af86cbd9d46a84772ddb7337d8 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix whitespaces. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112421 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 10ce7f311694aed3bbdd4ba7c5260c05597a2f22 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix whitespaces. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112421 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dc73ae1268b84720a7e62c82bd943f30c6df9170 |
29-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 04d6c289ab28114af5471c4dc38cbf7b7127d3c3 |
29-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 11a4400a9e355f0086646c391c9cce42b2ba66c7 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add a parameter to T2I_bin_irs for those patterns which set the S bit.
- Create T2I_bin_sw_irs to be like T2I_bin_w_irs, but that it sets the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112399 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1f7bf0e1f5748a1f8486ebc62fd556eccbe76e1c |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add a parameter to T2I_bin_irs for those patterns which set the S bit.
- Create T2I_bin_sw_irs to be like T2I_bin_w_irs, but that it sets the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112399 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3f1594c9b1e0a4b199718b227d711c92320b51d7 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Name ANDflag to ANDS, which is less stupid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112395 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2c4b30ebca87b4578fcf7a45a0bb9dbe956f1ec0 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Name ANDflag to ANDS, which is less stupid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112395 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ee4049d2a2fdd07b97570448934674af1cded60c |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
File missing from last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112394 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ac3b93536227d7bc71f8c1cac429201131705d67 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
File missing from last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112394 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 64f2e2acdc30017773ef58eb46f1a1be2a8cdb41 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but
it sets the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrThumb2.td
|
| 0b4aa7d11b9a55d602b7398da4495a3b6eba5018 |
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but
it sets the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrThumb2.td
|
| 5f5dbccb8f5dc31e95d3705b4aab25ca20ade911 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST1 and VST2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| e5ce4f68c786696a96acf1f1aa5431652abb6ce7 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST1 and VST2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 76b3870ecc86c541a8ea5a8a720ba2415e9b3db2 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
We don't need to custom-select VLDMQ and VSTMQ anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112336 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| fd7fd940c33ee48265cb8947d99f21a6711bd9d6 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
We don't need to custom-select VLDMQ and VSTMQ anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112336 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 7bfaf805bce188e658b51c0842a9845b73754098 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
When merging Thumb2 loads/stores, do not give up when the offset is one of
the special values that for ARM would be used with IB or DA modes. Fall
through and consider materializing a new base address is it would be
profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112329 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 14805e2afd5aa754e13fd5bb99365ffe972e9696 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
When merging Thumb2 loads/stores, do not give up when the offset is one of
the special values that for ARM would be used with IB or DA modes. Fall
through and consider materializing a new base address is it would be
profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112329 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 1e68cc1f1f9540f01e2aad5eb0c2a8710ca4a054 |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMInstPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| d4bfd54ec2947e73ab152c3c548e4dd4beb700ba |
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMAsmPrinter.cpp
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMInstPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 161330d66149d8ffb25f3e13003f1b7c26fc4940 |
27-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Unsigned value cannot be < 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112300 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3d38e8364a542abab6ca3d3aed658cf60d3112b4 |
27-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Unsigned value cannot be < 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112300 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 32b4e13e59e23f2354f6c3ecc45df8e43a989b0f |
27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a |
27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| ae4da43c7e09c17e962d1619f3ed0714dbe782d2 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up a bit. no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 1ab3f16f06698596716593a30545799688acccd7 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up a bit. no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 4659ad5ea0571106af47acb0305e52cf0135337a |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Turn off the scavenging based frame reg reuse briefly to measure whether it's
still having a significant effect. It shouldn't be now that the pre-RA
virtual base reg stuff is in. Assuming that's valididated by the nightly
testers, we can simplify a lot of the PEI frame index code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112220 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b0fa9932ccf9760e7b20ab4233799b4f9f5e0ba5 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Turn off the scavenging based frame reg reuse briefly to measure whether it's
still having a significant effect. It shouldn't be now that the pre-RA
virtual base reg stuff is in. Assuming that's valididated by the nightly
testers, we can simplify a lot of the PEI frame index code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112220 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 3e22f9cee290c1c1e74a762b6892b17f55200aef |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112208 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 01ba461af7eafc9d181a5c349487691f2e801438 |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112208 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 877732be562940cfe7532f26f27691473ab210e4 |
26-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Reapply r112176 without removing the other CMN patterns (that was unintentional).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112206 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6165e87824621902370d4f258063a1029326b881 |
26-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Reapply r112176 without removing the other CMN patterns (that was unintentional).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112206 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9fcf879633dbfa171d84b94bfffb76329e095559 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Restrict the register to tGPR to make sure the str instruction will be
encodable as a 16-bit wide instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112195 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9f134b571310f5591015cb85bbe182890191f837 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Restrict the register to tGPR to make sure the str instruction will be
encodable as a 16-bit wide instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112195 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 575146a0c167c6a84c421bbb3fcf863723732d1f |
26-Aug-2010 |
Dan Gohman <gohman@apple.com> |
Revert r112176; it broke test/CodeGen/Thumb2/thumb2-cmn.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112191 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4b7dff9a793f3258936c990c8f6a991366d4f55b |
26-Aug-2010 |
Dan Gohman <gohman@apple.com> |
Revert r112176; it broke test/CodeGen/Thumb2/thumb2-cmn.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112191 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8319e7f7b76c82046b34655bd33e364a4827a451 |
26-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
There seems to be a (potential) hardware bug with the CMN instruction and
comparison with 0. These two pieces of code should give identical results:
rsbs r1, r1, 0
cmp r0, r1
mov r0, #0
it ls
mov r0, #1
and:
cmn r0, r1
mov r0, #0
it ls
mov r0, #1
However, the CMN gives the *opposite* result when r1 is 0. This is because the
carry flag is set in the CMP case but not in the CMN case. In short, the CMP
instruction doesn't perform a truncate of the (logical) NOT of 0 plus the value
of r0 and the carry bit (because the "carry bit" parameter to AddWithCarry is
defined as 1 in this case, the carry flag will always be set when r0 >= 0). The
CMN instruction doesn't perform a NOT of 0 so there is never a "carry" when this
AddWithCarry is performed (because the "carry bit" parameter to AddWithCarry is
defined as 0).
The AddWithCarry in the CMP case seems to be relying upon the identity:
~x + 1 = -x
However when x is 0 and unsigned, this doesn't hold:
x = 0
~x = 0xFFFF FFFF
~x + 1 = 0x1 0000 0000
(-x = 0) != (0x1 0000 0000 = ~x + 1)
Therefore, we should disable *all* versions of CMN, especially when comparing
against zero, until we can limit when the CMN instruction is used (when we know
that the RHS is not 0) or when we have a hardware fix for this.
(See the ARM docs for the "AddWithCarry" pseudo-code.)
This is related to <rdar://problem/7569620>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 01b1e1c958d50b79acdf90824f36f7cb8a5be884 |
26-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
There seems to be a (potential) hardware bug with the CMN instruction and
comparison with 0. These two pieces of code should give identical results:
rsbs r1, r1, 0
cmp r0, r1
mov r0, #0
it ls
mov r0, #1
and:
cmn r0, r1
mov r0, #0
it ls
mov r0, #1
However, the CMN gives the *opposite* result when r1 is 0. This is because the
carry flag is set in the CMP case but not in the CMN case. In short, the CMP
instruction doesn't perform a truncate of the (logical) NOT of 0 plus the value
of r0 and the carry bit (because the "carry bit" parameter to AddWithCarry is
defined as 1 in this case, the carry flag will always be set when r0 >= 0). The
CMN instruction doesn't perform a NOT of 0 so there is never a "carry" when this
AddWithCarry is performed (because the "carry bit" parameter to AddWithCarry is
defined as 0).
The AddWithCarry in the CMP case seems to be relying upon the identity:
~x + 1 = -x
However when x is 0 and unsigned, this doesn't hold:
x = 0
~x = 0xFFFF FFFF
~x + 1 = 0x1 0000 0000
(-x = 0) != (0x1 0000 0000 = ~x + 1)
Therefore, we should disable *all* versions of CMN, especially when comparing
against zero, until we can limit when the CMN instruction is used (when we know
that the RHS is not 0) or when we have a hardware fix for this.
(See the ARM docs for the "AddWithCarry" pseudo-code.)
This is related to <rdar://problem/7569620>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112176 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8d1f30a7b84941f0777010f15ce810d2091934fe |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST1d64Q.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 70e48b23a3455e4689ee24cec4eb153d67223e86 |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST1d64Q.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 8cc452394c07881b37238aa8faaa1e5393927da4 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable pre-RA virtual frame base register allocation. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ae47c6d69e2e34bc558a302586cbc3f27a6d7334 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable pre-RA virtual frame base register allocation. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8b3107390815cc5e85ab8563a65f06305e38895a |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert svn 107892 (with changes to work with trunk). It caused a crash if
a VLD result was not used (Radar 8355607). It should also fix pr7988, but
I haven't verified that yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 2ac124c561c6c6687ce0a4f7709586010b6c80c4 |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert svn 107892 (with changes to work with trunk). It caused a crash if
a VLD result was not used (Radar 8355607). It should also fix pr7988, but
I haven't verified that yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| c13e856c93813acc4dc5670e07eec01e2fe4912c |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 709d59255a3100c7d440c93069efa1f726677a27 |
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
EONPreAllocPass.cpp
|
| b91b721f3ec0f36ce312501faddbf58d0b47a326 |
25-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't override the var from the enclosing scope.
When doing copy/paste/modify, it's apparently rather important to remember
the 'modify' bit...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112075 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f78ee6316bc755779920ac207edc27a89c0bd2f9 |
25-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't override the var from the enclosing scope.
When doing copy/paste/modify, it's apparently rather important to remember
the 'modify' bit...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112075 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ba3fb74d7619aae96996136279d5c60d2c9f51e4 |
25-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
comparison that would overflow.
- The other under/overflow cases can't actually happen because the immediates
which would trigger them are legal (so we don't enter this code), but
adjusted the style to make it clear the transform is always valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3cc3283fcbb90924196cc38ee5977b35c4ee28b5 |
25-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
comparison that would overflow.
- The other under/overflow cases can't actually happen because the immediates
which would trigger them are legal (so we don't enter this code), but
adjusted the style to make it clear the transform is always valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3bdc53a822cf2c94a64f49ade806db66d5838f2a |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Do type checks before we bother to do everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112039 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 61c3f9ae0624281a7feb0027b8bb87874fadbcd4 |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Do type checks before we bother to do everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112039 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| fc4959c13dc6b2f9039d12d235d7a58d4e50018f |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Reorganize load mechanisms. Handle types in a little less fixed way.
Fix some todos. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112031 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| b1cc848d1a9a831e8058fad546e41b21d955fd88 |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Reorganize load mechanisms. Handle types in a little less fixed way.
Fix some todos. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112031 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3c1d4d8887ea5327165b82d2b794dbeaf64cee55 |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix predicate and add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111981 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 992ea38e0e35f3700a76f49443fb134e7fcb46be |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix predicate and add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111981 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 3c1fada9859db2493b63b1b3854b803b6871165a |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Rework braindead conditionals I put in yesterday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| e24d66f525825a96ee76508076696936451902be |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Rework braindead conditionals I put in yesterday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ba1b277fd74478b9f5c9149281ea46a452af8337 |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix thumb2 mode loads to have the correct operand ordering. Add a todo
to fix this in the port.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 9f782d4dcf580ae508cc83f412884cd3c5f9207d |
25-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix thumb2 mode loads to have the correct operand ordering. Add a todo
to fix this in the port.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 734d432236e7dd52c2026e105bd22e7537ebcaaa |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 3197380143cdc18837722129ac888528b9fbfc2b |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| d7ac185d7a151148cecab8162ff8cfaa1e6a956a |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| a273442891ae20fd8192526132e3819ea9e5eda9 |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 721b89a710574b339374ef2640c46afaf3377c5b |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
add ARM cmd line option to force always using virtual base regs when possible.
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8c |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
add ARM cmd line option to force always using virtual base regs when possible.
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 74f2552c772d1ffbd05bcb69501e1d974edbcbd4 |
24-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add comments for what the condition code symbols mean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 5e7044bd0e3921c166d3604d12695e10782913c4 |
24-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add comments for what the condition code symbols mean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 4bd7340a2d997bf06788ea4a7331720ac2a5ae0f |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 882d62e2db7a82e4fd8fc401545ce3db46eadd82 |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 740df227906eba62add166420a55a5fb9ba3d324 |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix the opcode and the operands for the load instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2012c7bb7be28c163a4b8034e961ace51f6a7224 |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix the opcode and the operands for the load instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 534dc2d1b1e89191b95aa1eb11df85d2bf23b15c |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add register class hack that needs to go away, but makes it more obvious
that it needs to go away. Use loadRegFromStackSlot where possible.
Also, remember to update the value map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f06f309002f00e7927347502997f2df5756f4d9c |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add register class hack that needs to go away, but makes it more obvious
that it needs to go away. Use loadRegFromStackSlot where possible.
Also, remember to update the value map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 2c3a0818023da213c18423766aa3f7ed2c9ee62d |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add some more debugging code, make it more obvious that RegOffset is
getting an address for an object and select some default values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| cb0b04ba6fc847574f592d1a80ff3b60c0d4228c |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add some more debugging code, make it more obvious that RegOffset is
getting an address for an object and select some default values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 01db9cab563659c8014cedaa4a5442fc5846bc2a |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Don't need the extra register here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1dfb4d31e068855c594d157d5a9a207daf473426 |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Don't need the extra register here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| c31428e6f3456fc6bdce342d98a2cfd9788d7ffc |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add some more "get address into register" code and a more TODOs/FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8654c71e56cd1f21f71bfce7eecb7373242663ff |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add some more "get address into register" code and a more TODOs/FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 00aa20a98c019c0950b4993d3bf7d9ee9d1cf6be |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add an ARMFunctionInfo member and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 7fe55b739c1bc319da9c81bcfd9d3e5d5030721b |
24-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add an ARMFunctionInfo member and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| dbb80464e3fe15360d1ee8db564d5c2cc1c0c4d7 |
23-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Start getting ARM loads/address computation going.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8300712c1e73dc106242f0007e0e0e4dd9ea38ce |
23-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Start getting ARM loads/address computation going.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| a88844b6a2e62840e510b5cced8fe03dc17276d2 |
20-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
zero-extend operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| b31a11b466281b7e01cfde007b2041eefa2341e4 |
20-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
zero-extend operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 28c238c9ded0b5c91e122c94b5a02d76a5245c11 |
20-Aug-2010 |
Ying Wang <wangying@google.com> |
Fix sim build.
Note that this only makes the sim build green, but the built images won't work for sure:
No libbcc.so, which depends on something else that can not build in sim mode.
No x86 bitcode is generated as well, I believe.
Change-Id: Idca8378427196622ac77cd56a38c6a160f03ba22
ndroid.mk
smParser/Android.mk
smPrinter/Android.mk
isassembler/Android.mk
argetInfo/Android.mk
|
| 21805df06264c2875849034c01bf4cdbcfecbc2d |
20-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| f762fbe4fa421c91e20044ee009ddb57e25dd135 |
20-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| d5178cd12fbb1fed250e8b9fa6995e0dff454963 |
20-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add a couple of random comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| cb59229a4a60abaee9ef060c515dbd3513865afd |
20-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add a couple of random comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 8a242004e2fbb8631bef004a62a5d6a3ca98d52b |
20-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Better handling of offsets on frame index references. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| e2f556933e1a19cddf6d4f370e2770c0f763b025 |
20-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Better handling of offsets on frame index references. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| b211dfb0547305b4dd399dd712b9d324def2ea8d |
19-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb1 support for virtual frame indices.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 74d7b0af58951dce2f874c600a6a48a2454b4914 |
19-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb1 support for virtual frame indices.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| e0837196c0fa42f06e3906419e2c91e3c6048334 |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 979e0a141487a4cd8538dffbe09eca544acf14c7 |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0f9dc31d179babce2cb59eb53068598ff9599500 |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add an AddOptionalDefs method and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111489 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 456144eb14b377166af1d9439cee6fad86fcdb1b |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Add an AddOptionalDefs method and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111489 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 838d0c71b9538c3eced88f47368bca45df4a2680 |
19-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the "isCompare" attribute to the defm instead of each individual instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f0e132c385fa0196e1c9a744ee0aaceec527bc91 |
19-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the "isCompare" attribute to the defm instead of each individual instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 86cec0707c4de85b3a3ca9ce760ce516b1102652 |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Remove extra header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111456 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| d96b02b3d6dfede96b6259f737720cc10330c84b |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Remove extra header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111456 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 931ad7afbae7e7edbf514e24c482183b6138c422 |
19-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable ARM base register reuse to local stack slot allocation. Whenever a new
frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111443 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 2b1e202e1c2137b03f7c6ecc18668e40819fa22f |
19-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable ARM base register reuse to local stack slot allocation. Whenever a new
frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111443 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 811c60b698ce5f4ad304cb6394426de7dc0ee2e6 |
18-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor simplification. Gets rid of a needless temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111430 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ad422718f9b3224234f52e84d28d8a57a4e89987 |
18-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor simplification. Gets rid of a needless temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111430 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0bcf23f115608757b1d704e2f70a1148132551db |
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook for re-using virtual base registers for local stack slot access.
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.
ongoing saga of rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 74d803a58c7935c067397bb19afc05ec464d8159 |
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook for re-using virtual base registers for local stack slot access.
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.
ongoing saga of rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 4e18f31e27dd8b7b725bb4acae8be8240d23bbe0 |
18-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Expand ZERO_EXTEND operations for NEON vector types.
Testcase from Nick Lewycky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2003bcfbd243716e5599f65705b515c2a229c7d3 |
18-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Expand ZERO_EXTEND operations for NEON vector types.
Testcase from Nick Lewycky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0db154b121c5929e8be95ffafc007f128e31be19 |
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add materialization of virtual base registers for frame indices allocated into
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.
Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| dc140c6e7b8350ca51aa1d408c10e25a27826e2c |
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add materialization of virtual base registers for frame indices allocated into
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.
Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 373707e4c4b55e7ec34f792a99387b837567468c |
17-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't call tablegen'ed Predicate_* functions in the ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 00d3dda86f825f32277eba8c4206f48fbfc9f584 |
17-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't call tablegen'ed Predicate_* functions in the ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 1e26304589fae0b648b779cc23aece264e7405b3 |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
|
| c5ed0134a782f16e343892ef7d2faf368fce1ab6 |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
|
| 64a2ed70ddd5d095eb7ebb0b1ac342f5a4732847 |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook to examine an instruction referencing a frame index to determine
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.
In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 8708ead5a46f4ec8f2d5f832be23381924d72b8d |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook to examine an instruction referencing a frame index to determine
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.
In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 936ea41c5926db650b5fc577f18914d04d1fe899 |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
explicitly handle no-op cases for clarity. Fixes clang warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111260 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 3edb90492727f60683181672201fd811101ea0d7 |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
explicitly handle no-op cases for clarity. Fixes clang warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111260 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| fec03d6365fe3d8a86bd9bb82e6274bbf567b914 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| f955f290c949ff0df7d23cec055efcc4ffeb35d1 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 03a159cc0b456eb87b97d056d3dd2db6a6388bca |
17-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix emacs language spec's, patch by Edmund Grimley-Evans!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCallingConv.td
RMRegisterInfo.td
|
| 23e70ebf352ff4938210711464c68b5a6e46e61c |
17-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix emacs language spec's, patch by Edmund Grimley-Evans!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCallingConv.td
RMRegisterInfo.td
|
| d085fbd245d4cc6f4620b656b058024257421824 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow more cases of undef shuffle indices and add tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7aaf5bf3db44c94bd630e07d63c3a4a1d92e44f4 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow more cases of undef shuffle indices and add tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 75212ed9fa54e7383a30fddf128ee35036d4e7f2 |
17-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Copy over some overridden MI wrappers for ARM fast-isel. This is where
we're adding predicates and optional defs to the MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111222 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0fe7d54732491126c26e7e1ec60274ff2b02b849 |
17-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Copy over some overridden MI wrappers for ARM fast-isel. This is where
we're adding predicates and optional defs to the MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111222 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| ed477833e7e42b30e473b8cdeadd76a93d0d9193 |
17-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Make arm fast-isel possible to enable via command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111219 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 038fea5e30faaf37e597f8a4627e1e3141fb59ba |
17-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Make arm fast-isel possible to enable via command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111219 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 54984dc0510fc3baa1fec8174059cd887587a0e2 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111208 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ca5e47d3f84dcf3dfbc6706bf1041e7029f3ce0a |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111208 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 947300beef202bd763dc6df6e193e56d8efb6957 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
that the high halfword is zero. The shift need not be exactly 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| dc66edaced5dacb56f06f52723dd340d5cfe4eab |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
that the high halfword is zero. The shift need not be exactly 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 255974d9ffbe398eb7bd1765ec0b1bb0ce6ca25c |
16-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename sat_shift operand to shift_imm, in preparation for using it for other
instructions besides saturate instructions. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 22f5dc79c05d69391b17e14ed912aa8e98a63027 |
16-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename sat_shift operand to shift_imm, in preparation for using it for other
instructions besides saturate instructions. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| bd001e29c82e85cdf88c0da668a20a357ae77015 |
16-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111154 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 45cdd7fd612df94f92e7b7c5b0a03d078afb490c |
16-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111154 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 256a47bb64119aee251d3ba7658d8fb937d92602 |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 136e4912806a2182a41e3011e86830a9c77160f0 |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 616d081f189e70a1277f6534f6a2c7d621c1685a |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 20d8e4e7aa5645450f3eaedd9f9dbb70423f8ccc |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a5142538b3506d24c90018f185f8f1f36165fd5f |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily disable tail calls on ARM to work around some linker problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 703af3ab128addcd061e0761b059a919da2a4066 |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily disable tail calls on ARM to work around some linker problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 83447724884122e84541b83a315189eb8ce34c30 |
13-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the Thumb2 SSAT and USAT optional shift operator out of the
instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| 38aa2871fc7a37f7a6854744e71fc366ba12888a |
13-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the Thumb2 SSAT and USAT optional shift operator out of the
instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
isassembler/ThumbDisassemblerCore.h
|
| 99a5ff08a4e3ba7d8ff8652b4a12d16d4ecbf12a |
13-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor the code for disassembling Thumb2 saturate instructions along the
same lines as the change I made for ARM saturate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111029 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 6daf2a254b89bc039f9d58c38e2158a1896d4695 |
13-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor the code for disassembling Thumb2 saturate instructions along the
same lines as the change I made for ARM saturate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111029 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 232f400541c7710767234dfa95df16bca4fc72dd |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMInstrInfo.td
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassemblerCore.cpp
|
| 1adc40cac314b0a77b790b094bca146a3a868452 |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMInstrInfo.td
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassemblerCore.cpp
|
| 34923bcdbacdce7500ceef304b130ea6bb411be0 |
12-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 719510a178a910feb1db707140011c32a30992c4 |
12-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 82c8b83b35f2255127bd06180390db44dcefc23a |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 270159fcc21e06c67aa571d10d2b22d41d9a751a |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 2ae71c9eabb91083ac98f49da2e3a4561a5b219c |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
instructions onto the target specific parser, which can do a better job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f1e29d4c21d15f9e1e3a64f3b92b1aa9908e4f63 |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
instructions onto the target specific parser, which can do a better job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 049a7528a0bbafcc9c7ef844cea64d27dbc95f98 |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
target specific parsers can adapt the TargetAsmParser to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4f98f834593f0a107268d19a557b63f0da33a751 |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
target specific parsers can adapt the TargetAsmParser to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7fe6c8acfd41e32d895a60170b040509096fa063 |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 7def14f40f0b47551e2d66ec2f140a18b5bbbea4 |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 6aed5ee28d0ef1b624ea5367409c497b4ab4a36a |
12-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMInstrInfo.td
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
|
| eaf1c98a7c38444d41d1c6dc2074736eec7d452f |
12-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMInstrInfo.td
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
|
| f0f1a33b427ca5ac25b1fefbd18906e263a884cc |
11-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| fcba5e6b645df89ae6b93911fe0f80b08fa6b44c |
11-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 962e99e5a6f6e6a6ccefa2ccca411263e68ff99d |
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Consider this code snippet:
float t1(int argc) {
return (argc == 1123) ? 1.234f : 2.38213f;
}
We would generate truly awful code on ARM (those with a weak stomach should look
away):
_t1:
movw r1, #1123
movs r2, #1
movs r3, #0
cmp r0, r1
mov.w r0, #0
it eq
moveq r0, r2
movs r1, #4
cmp r0, #0
it ne
movne r3, r1
adr r0, #LCPI1_0
ldr r0, [r0, r3]
bx lr
The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".
I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.
Now we generate this, which looks optimal to me:
_t1:
movw r1, #1123
movs r2, #0
cmp r0, r1
adr r0, #LCPI0_0
it eq
moveq r2, #4
ldr r0, [r0, r2]
bx lr
.align 2
LCPI0_0:
.long 1075344593 @ float 2.382130e+00
.long 1067316150 @ float 1.234000e+00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| de2b151dbf125af49717807b9cfc1f6f7a5b9ea6 |
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Consider this code snippet:
float t1(int argc) {
return (argc == 1123) ? 1.234f : 2.38213f;
}
We would generate truly awful code on ARM (those with a weak stomach should look
away):
_t1:
movw r1, #1123
movs r2, #1
movs r3, #0
cmp r0, r1
mov.w r0, #0
it eq
moveq r0, r2
movs r1, #4
cmp r0, #0
it ne
movne r3, r1
adr r0, #LCPI1_0
ldr r0, [r0, r3]
bx lr
The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".
I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.
Now we generate this, which looks optimal to me:
_t1:
movw r1, #1123
movs r2, #0
cmp r0, r1
adr r0, #LCPI0_0
it eq
moveq r2, #4
ldr r0, [r0, r2]
bx lr
.align 2
LCPI0_0:
.long 1075344593 @ float 2.382130e+00
.long 1067316150 @ float 1.234000e+00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 8c4ded47fbbde07e851fe428b8f2dbb7802c834f |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 7b4d31176efe6894bcfaa05257dd5783acda5ddc |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 7c896f25f5e2da16dd955f6eaf0c4fdbdc710ce8 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
ArchV7M implies HW division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 8d62e713ea8c1597cc81da029a79925cbb125f4c |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
ArchV7M implies HW division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| aeeb5e9a9c7e090b61096a2c33eaf2a5611fbb6d |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| cb5ce6e62bcc15add9f0d1a79392c0cbb00ba861 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| c39216fea2b853d1a539d45703486e9dae8f1e4a |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| d6b463225674c10511b00f8f631a89b6da5afc54 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 092c0eaf089faf01fc68406e28b6ac18dc2475aa |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 345a9a6269318c96f333c0492b23733e29d952df |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0e55d907262e8d6e4c8ba7b2412f1fd0294ec386 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Split mnemonic on '.' characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5747b13af801d5af7cd5827c07c6a59e981bdb1a |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Split mnemonic on '.' characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 43ba789b65eb806be0e03c0bb5b44062a374694c |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Fill in ARMOperand::dump a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| fa315de8f44ddb318a7c6ff913e80d71d7c68859 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Fill in ARMOperand::dump a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 20f4ff12b48aec8ecb2a25ffbf14a24dc35ef63a |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MCAsmParser: Add dump() hook to MCParsedAsmOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b3cb6967949493a2e1b10d015ac08b746736764e |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MCAsmParser: Add dump() hook to MCParsedAsmOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5239aab3b92aa9fc8eb3b596287a73e8898d4992 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Add an ARMOperand class for condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
|
| 8462b30548fb5969250858036638c73c16b65b43 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Add an ARMOperand class for condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
smParser/ARMAsmParser.cpp
|
| 65ecbb09616d844f87d6976fca8494dcdf7b1b27 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Really control isel of barrier instructions with cpu feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| ee34987fd58ed98c6987ed46979ccb46e7420919 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Really control isel of barrier instructions with cpu feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 4efe9cdd80635a480bcd5db4b4ed25e2dc0bee51 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| c7569ed4e43a25aa52cf3b5580f1ee00d7d5db96 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 1d2eb4554167be32d72cc959a11b7b60b2edf153 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
isassembler/ARMDisassemblerCore.cpp
|
| 11db068721d44fd5f9b0c2a3a4c90f813d2eae9c |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
isassembler/ARMDisassemblerCore.cpp
|
| 561f6e2a38588d62c8769b752f1a7951066f339f |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Switch to using the generated match functions instead of stub implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 3483acabf012b847b13b969ebd9ce5c4d16d9eb7 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Switch to using the generated match functions instead of stub implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1ec885e7738b487683dc1d370763c2d341f7510b |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
|
| a7ac688d55210487052dcd809ed2643d6016315c |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
|
| feea73bb726c75c27696ce788c1086fe78030fb9 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 3bcd9f7902aa1c61b868fd57da5c18f201280ca4 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 6f1df8609dcd102e316e2ac07daf2c7f3d84412b |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM: Quote $p in an asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9db683b06ccdc4e1274257d1458711e0fa2d9b58 |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM: Quote $p in an asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f56a8513b923b01717f7079914cffb1f380bd117 |
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 38ae997e63e3e1bb2c8679e01ea74cf8fd0be893 |
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cabfc706966bc0db095b0e2f7a30c774fb0e0dbc |
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Mark ARM compare instructions as isCompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0cce3dd3267e8416a34ef59ac72351dc9e1e30eb |
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Mark ARM compare instructions as isCompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 118b4dea46da0da74c3ef4a1c6e7581b404d59bc |
11-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 9a1c189d9e7472f336f3c6d61be76bc46b25749e |
11-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 2957defe6ebad79f5bc3b503daf96a7b0403e6bc |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
CBZ and CBNZ are implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3611d9e25d8cf79f1d0a608fb5affd6bf2d41598 |
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
CBZ and CBNZ are implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3e5165a7cc01d28b680a5f409eda72788cb451d3 |
10-Aug-2010 |
Shih-wei Liao <sliao@google.com> |
Make resolveRelocDestAddr handle the right relocation set. Otherwise, assertion failures "Can't handle this machine constant pool entry yet!" may occur.
Change-Id: I3235610163e6ce762f0493a1eaf5036805346c09
RMJITInfo.cpp
|
| 6d7069e367f247469f3292d1262a1bbf5e97ca81 |
10-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Turn optimize compares back on with fix. We needed to test that a machine op was
a register before checking if it was defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 75486dbf4e9611f2070bf13b874f78a5587ed7ff |
10-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Turn optimize compares back on with fix. We needed to test that a machine op was
a register before checking if it was defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a55247d0ed62d64a776b7bacb2195ad87b3713d1 |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete some unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb.td
RMInstrThumb2.td
|
| 5818032521e9e76873ec82104a7c22ffb9d9b277 |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete some unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb.td
RMInstrThumb2.td
|
| 5e4330c1f16540fb1ddd1252ed18cd8ab0e5e0c5 |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.td
humb1RegisterInfo.cpp
|
| ac096808a3accc516ae7c193c9a2c1392bf3301a |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.td
humb1RegisterInfo.cpp
|
| 2fe97c4cbba4d55547fafcb0e8087dac4aa02a1b |
10-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.td
humb1RegisterInfo.cpp
|
| 4bd828f78139b9bab561102c5b9c40133ad375ca |
10-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.td
humb1RegisterInfo.cpp
|
| ab507e020eeaaf1cf18125281dfaf5a743bc4438 |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.
This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.td
humb1RegisterInfo.cpp
|
| c9aed19747608b7688a64f2f382a008889f8e57d |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.
This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.td
humb1RegisterInfo.cpp
|
| 97bca3642164e5e7b735914fb5bfeb5a163c0885 |
10-Aug-2010 |
Shih-wei Liao <sliao@google.com> |
Make emitConstPoolAddress use reloc_arm_so_imm...
Change-Id: I4856d1e8b958156624b4b72aec8466342ce05f5d
RMCodeEmitter.cpp
|
| c4cb277fdfdbbf959c2500f0b7a0d1235e559b91 |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARMBaseRegisterInfo::hasFP() has been broken for a while now. :-(
This will always be false before PEI:
(DisableFramePointerElim(MF) && MFI->adjustsStack())
Which means it's going to make r11 available as a general purpose register even
if -disable-fp-elim is specified. It's working on Darwin only because r7 is
always reserved. But it's obviously broken for other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110614 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b000d683c822bab7bed608937048b24b4b6db551 |
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARMBaseRegisterInfo::hasFP() has been broken for a while now. :-(
This will always be false before PEI:
(DisableFramePointerElim(MF) && MFI->adjustsStack())
Which means it's going to make r11 available as a general purpose register even
if -disable-fp-elim is specified. It's working on Darwin only because r7 is
always reserved. But it's obviously broken for other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110614 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 4527913ba9c81601d3d3420a5f444dc99c84e1ea |
09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Explicitly initialize SlowFPBrcc and Pref32BitThumb to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110587 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 9de1ac267e197d40cec7a14041f2bf69498536c9 |
09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Explicitly initialize SlowFPBrcc and Pref32BitThumb to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110587 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 8bab3a6bad22c95fd8f4ef3dc6ff4400eef03e61 |
09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110584 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMConstantIslandPass.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| e44be6381609d31b2d8879dbd5107e01404fa475 |
09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110584 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMConstantIslandPass.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| dc9312bb08e590a4dbc04c98c418653daa7e6ebd |
09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an option to disable 32 -> 16-bit Thumb2 size reduction pass for experimentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110579 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| e8846feaa1713fa6ba32b4d1e3901284daf7927f |
09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an option to disable 32 -> 16-bit Thumb2 size reduction pass for experimentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110579 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 7f80b0a9af7a6618516fb29324c83b26189a7372 |
09-Aug-2010 |
Shih-wei Liao <sliao@google.com> |
Handle load effective address (pc relative).
Change-Id: I060d0f6b7983aacacf03c40ee7b0a8a0bcee053c
RMCodeEmitter.cpp
RMJITInfo.cpp
RMRelocations.h
|
| b38c700c87bd03e5271a8e2e86b7fb5b3060b55e |
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the "isCompare" machine instruction attribute instead of calling the
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrThumb2.td
|
| c98af3370f899a0d1570b1dff01a2e36632f884f |
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the "isCompare" machine instruction attribute instead of calling the
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrThumb2.td
|
| 7569322765651f19eea0609fb082e6b267d5d2b5 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMGlobalMerge.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 90c579de5a383cee278acc3f7e7b9d0a656e6a35 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMGlobalMerge.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 9d40857d4b77e1d6af7a777d5f0f648769e0bfec |
06-Aug-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix eabi calling convention when a 64 bit value shadows r3.
Without this what was happening was:
* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110446 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 55e958746901ef8c04f370e746a7538137d0bcf8 |
06-Aug-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix eabi calling convention when a 64 bit value shadows r3.
Without this what was happening was:
* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110446 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 49fbac55a4aceae06fdfad7d5e24c513363c7cf8 |
06-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the Optimize Compares pass (disabled by default).
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:
sub r1, 1
cmp r1, 0
bz L1
and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| e4ddbdfd3cf031034020671d03626f0373fbd5ca |
06-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the Optimize Compares pass (disabled by default).
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:
sub r1, 1
cmp r1, 0
bz L1
and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 619acdc63ab0a47d125dca0591285c8ac4c9ed20 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMGlobalMerge.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 1f74590e9d1b9cf0f1f81a156efea73f76546e05 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMGlobalMerge.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 0e63653ab0d25d579ad99948db606d8723d271dd |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMGlobalMerge.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 9ccaf53ada99c63737547c0235baeb8454b04e80 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMGlobalMerge.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 270aad1e410fb4ee87bdcae4805ac25ee193676a |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
For local variables in functions with a frame pointer, use FP as a base
register for local access when it's closer to the stack slot being refererenced
than the stack pointer. Make sure to take into account any argument frame
SP adjustments that are in affect at the time.
rdar://8256090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110366 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09 |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
For local variables in functions with a frame pointer, use FP as a base
register for local access when it's closer to the stack slot being refererenced
than the stack pointer. Make sure to take into account any argument frame
SP adjustments that are in affect at the time.
rdar://8256090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110366 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 25d5ad459ca3e783b439d3f5b77fd3fb64aeed70 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110363 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 751aaf8ac586860df8f22c3707905d1a8005f1ba |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110363 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 82cd29430e7d0f0186e6736f13251cf194fe0d52 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM RSCrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a1d410d51265516584bf62c4e48874488dd2cba4 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM RSCrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dc0b5bf3da25c359250c6bd03d084a7a71ec8409 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM RSBrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cff71788446f17fa691a2768d8c11f46ae3206a2 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM RSBrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 987e0672357f9646191b2150f1088a622ab56d78 |
05-Aug-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Silence a GCC warning about && and || without explicit parentheses. This
preserves the existing behavior, as it seems a concious choice to allow RS to
be null and BigStack marked true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110307 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a7da3ac14ab1ca6da52547baf572d29c066559cc |
05-Aug-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Silence a GCC warning about && and || without explicit parentheses. This
preserves the existing behavior, as it seems a concious choice to allow RS to
be null and BigStack marked true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110307 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6d79da8d33e0eb1f2c7b4bce7f85bdde82d29705 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM "rrx" shift operands do not have an immediate. PR7790.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 1d9125a6ff192f1346d2b08bbf6ecc9c9e44103d |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM "rrx" shift operands do not have an immediate. PR7790.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 62393bcbf164da6e87fcb3446f792f0028e43222 |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
and back in. false alarm on the tests from another unrelated local change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110269 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| abf7bdffd67689781a5104b13fa806b92f3e96e1 |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
and back in. false alarm on the tests from another unrelated local change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110269 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c7d396c8a787c1270820ec8d86dd799d09410595 |
05-Aug-2010 |
Devang Patel <dpatel@apple.com> |
Implement target specific getDebugValueLocation().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110267 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 59135f49e1699daec9a43fc2d15715d55b910f54 |
05-Aug-2010 |
Devang Patel <dpatel@apple.com> |
Implement target specific getDebugValueLocation().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110267 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c0e52a00d7784d4082a5f9ad524498de18e8d95b |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
oops. revert for a moment to clean up tests first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110259 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 87c0175cce653ee1d69d1efce77e7531c3066dac |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
oops. revert for a moment to clean up tests first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110259 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c674e7016a1993e8d3bf3ea9715b509ccb34c07e |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Reserve a stack slot if the function adjusts the stack but doesn't
simplify the call frame pseudo instructions. In that situation, the
calculations for estimating the stack size will be way off, leading to
not having an emergency spill slot when we need one. It should be possible
to be more precise about tracking the adjustment values, but not really
necessary for correctness. Upcoming cleanups for PEI in general will
render that moot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110258 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 936ed5424cc55a01cb6afdf687a82b134356ddc8 |
05-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Reserve a stack slot if the function adjusts the stack but doesn't
simplify the call frame pseudo instructions. In that situation, the
calculations for estimating the stack size will be way off, leading to
not having an emergency spill slot when we need one. It should be possible
to be more precise about tracking the adjustment values, but not really
necessary for correctness. Upcoming cleanups for PEI in general will
render that moot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110258 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 44339ce617e33a1f273d77d22eb5716faa75544b |
04-Aug-2010 |
Dale Johannesen <dalej@apple.com> |
Remove switch for disabling ARM tail calls. They
seem to be working correctly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110226 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a54db0c48597d68e54528d0ae129f1f1ea4c0b50 |
04-Aug-2010 |
Dale Johannesen <dalej@apple.com> |
Remove switch for disabling ARM tail calls. They
seem to be working correctly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110226 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c91d5cdfe124447b07c6db932a4f95ba857b8daa |
04-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA
(absolute difference with accumulate) intrinsics. Radar 8228576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110170 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 67b453b0d1ed7ab42a9408a6eb00131e160eb421 |
04-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA
(absolute difference with accumulate) intrinsics. Radar 8228576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110170 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 37f991ab49d0df3356ff446a763c21e66477b1c0 |
03-Aug-2010 |
Nate Begeman <natebegeman@mac.com> |
Add support for getting & setting the FPSCR application register on ARM when VFP is enabled.
Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110152 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
|
| d1fb583128c6682bb8a7c74eafa810a9270cc8df |
03-Aug-2010 |
Nate Begeman <natebegeman@mac.com> |
Add support for getting & setting the FPSCR application register on ARM when VFP is enabled.
Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110152 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
|
| 40776ed24fd56548cf7dca4dafd598377195057d |
31-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Silence some -Asserts uninitialized variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 425f634917542d7f09c189e2eb130752c6a12d2c |
31-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Silence some -Asserts uninitialized variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8b13b96d1b3d1577e4a52706170d8079ec52e88a |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move newlines before inline jumptables from the asm strings in .td files to
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109948 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| d4d188e5029801ef2a76ee756dcba49f313004f0 |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move newlines before inline jumptables from the asm strings in .td files to
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109948 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 78da5814dee4bebdee493ef06d786492bdc9bbfa |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for disassembling VMVN (immediate) instructions. PR7747.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 98e1479575c87fcd16d2087c99b8e07e6722ac36 |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for disassembling VMVN (immediate) instructions. PR7747.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 95b8251c55f7cf21b13d7755dacb7077b80490ee |
31-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109934 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a2c519bd0bdb19d4bb1f2377fcf429653af95960 |
31-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109934 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d87ca843cc99e7c04a47a7923562574ed0c1d443 |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a check in the ARM disassembler for NEON instructions that would
reference registers past the end of the NEON register file, and report them
as invalid instead of asserting when trying to print them. PR7746.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109933 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 70a4e3c532ea1985278f85bf51296dcd0da65ead |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a check in the ARM disassembler for NEON instructions that would
reference registers past the end of the NEON register file, and report them
as invalid instead of asserting when trying to print them. PR7746.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109933 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 227246a9b5449d73019e5cb0af5e3eacad32751a |
30-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add the __TEXT,__StaticInit section to the list of sections emitted at the
beginning on ARM Darwin assembly files so that it won't be placed after
debug sections. Radar 8252813.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109879 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 63db594559dc8eac666204c7907bae664f5234da |
30-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add the __TEXT,__StaticInit section to the list of sections emitted at the
beginning on ARM Darwin assembly files so that it won't be placed after
debug sections. Radar 8252813.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109879 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 50b97e1e4e26f88e328947cad91379acf10407d4 |
30-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb2.td
RMRegisterInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
humb2InstrInfo.cpp
|
| 6ccfc507dc1f7ad8c8964193a2407264ca644f0d |
30-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb2.td
RMRegisterInfo.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
humb2InstrInfo.cpp
|
| 3f03afad2ef1c3d2a73aba32638bf903c8eaf1b5 |
30-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 0e0a20eb3859affe4626ee75bd5cb32c033d73fb |
30-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 3752043a5819f3118e790c3b96bfd5780aad43f6 |
29-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor ARM-specific DAG combining in preparation for adding some more
transformations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109800 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3d5792a5aaa735c35e5cb66b615ada9f7b6fa052 |
29-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor ARM-specific DAG combining in preparation for adding some more
transformations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109800 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b2fb2538ce959973624f134f1821763bb1170d32 |
29-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Implement vector constants which are splat of
integers with mov + vdup. 8003375. This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f630c712b17cae45e8cf9bc670c8b1695c37c3c6 |
29-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Implement vector constants which are splat of
integers with mov + vdup. 8003375. This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fba1dca1bcddc6c0bf2b1764a40b982a867e0600 |
29-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Don't assert on an unrecognized BrMiscFrm instruction.
PR7745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109788 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| fb13b95162f645260cf6a5511318abd55f124f5e |
29-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Don't assert on an unrecognized BrMiscFrm instruction.
PR7745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109788 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 9c98cd8fa49d3a6ada76f963e2ae31700bf28429 |
29-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 692433bc2d3be9c3bb2fd67ab688eda073bafca2 |
29-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 41a304000bf27999542b6003de98f49aa44f6e83 |
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109696 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 542f642684db2b5f5124f8276793324a62e45dd6 |
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109696 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b53035ab15a8be32908d53d1ccf1543567077ad3 |
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109693 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7946494ceb506f995f2f11f4ba7390c4481ddeb1 |
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109693 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9b0b3a205a9b3aa06210666d75b6684bdc4d830d |
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove dead prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| f0d7e366914068991ded69b72a88958851b11bbf |
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove dead prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 67a3862c3f6880084e4fb6f196734e560d49e335 |
27-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
And a bit more non-ASCII stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109458 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a10213e9341963e47008a697d9fb2f901e17f4dc |
27-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
And a bit more non-ASCII stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109458 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 98f2e3df1bb05b6983e69457a67374827dac03bf |
27-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Drop some non-ascii stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109456 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4e084e93a73ea1f63d919700ed0b2315357941c4 |
27-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Drop some non-ascii stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109456 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 03cf9787359fba41d31af9a1e5dacdf1f68a194f |
26-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109448 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 25a6ab0144f5e206729cb38da654c256d1672aac |
26-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109448 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| db5b01e33c23489e894691ddeb23880c9e112fa3 |
26-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Currently EH lowering code expects typeinfo to be global only.
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109423 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| b5a0ef99f8e2bd48f2fb2a3221d296d48f1d5940 |
26-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Currently EH lowering code expects typeinfo to be global only.
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109423 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| a4fa8cba39113b38d7d467dd0fc269c5fb3dc419 |
26-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM fastisel isn't ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109421 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 0944795b8c84612303e9de00bc7e9ea362441227 |
26-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM fastisel isn't ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109421 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
|
| 1629958afd9b094b67ba29b9b2549c2a806382d4 |
25-Jul-2010 |
Douglas Gregor <doug.gregor@gmail.com> |
Remove extraneous semicolon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109373 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 037b5e41285c325d8ce706db7d653087df80b8ca |
25-Jul-2010 |
Douglas Gregor <dgregor@apple.com> |
Remove extraneous semicolon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109373 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| f6cd23ed59112a4d2c10c1b8a14861cdc9052cb7 |
25-Jul-2010 |
Douglas Gregor <doug.gregor@gmail.com> |
Unbreak CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109372 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 1984d98376c1cb8a55f062f0e33308beb222b23a |
25-Jul-2010 |
Douglas Gregor <dgregor@apple.com> |
Unbreak CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109372 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 6cd461f358b227a0dce4d8ef6d872aa3a192f367 |
24-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hook in GlobalMerge pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMGlobalMerge.cpp
RMISelLowering.cpp
RMISelLowering.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| cec36f4c1118dc8388910d4753fe7cbf88d2d793 |
24-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hook in GlobalMerge pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMGlobalMerge.cpp
RMISelLowering.cpp
RMISelLowering.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| 884326e35446070e70dc3e685a174e6b382ef2ac |
24-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Use the appropriate register class for an i32 when adding ARM::LR to the
function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109293 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c2723a57f35dd69bd261faaa71ee7aa05f40a87d |
24-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Use the appropriate register class for an i32 when adding ARM::LR to the
function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109293 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a5a4fe7353ad29c689a88a64efc07ce5ed653fad |
24-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Revert 109076. It is wrong and was causing regressions. Add some
comments explaining why it was wrong. 8225024.
Fix the real problem in 8213383: the code that splits very large
blocks when no other place to put constants can be found was not
considering the case that the block contained a Thumb tablejump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109282 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 8086d5800dbe8cc392ce217adccfaca915858aed |
24-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Revert 109076. It is wrong and was causing regressions. Add some
comments explaining why it was wrong. 8225024.
Fix the real problem in 8213383: the code that splits very large
blocks when no other place to put constants can be found was not
considering the case that the block contained a Thumb tablejump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109282 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 922a4d36f7218b00baed5994960e79f7e977ec56 |
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 3144687df78731ac4ddbc716a24b951678a73f57 |
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 657d57f6e9b901063b609757eb027514f3aa1fc5 |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMConstantIslandPass.cpp
|
| 2062875a7d8f7dd94a20d9e3a298e9e216efb4b5 |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMConstantIslandPass.cpp
|
| bd0548064a7cd12ab260d0f993c16aa6197efa7c |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
switch a private implementation of GetFunctionSizeInBytes.
This is probably not the best way to implement "Force LR to
be spilled if the Thumb function size is > 2048." do this,
it should use the branch shortening infrastructure, but I'm
just preserving functionality here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109165 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 1c55386dae428d076bd7d054ed8bbb59c4ba954e |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
switch a private implementation of GetFunctionSizeInBytes.
This is probably not the best way to implement "Force LR to
be spilled if the Thumb function size is > 2048." do this,
it should use the branch shortening infrastructure, but I'm
just preserving functionality here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109165 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ab4095eeebd2d0ed2f1c3baccaae7674700d9995 |
22-Jul-2010 |
Xerxes Ranby <xerxes@zafena.se> |
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109125 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
|
| 99ccffe87e7b2bdc8e5a477f8c1e9087758daf56 |
22-Jul-2010 |
Xerxes Ranby <xerxes@zafena.se> |
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109125 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
|
| 8d20b5ae0ae3c61a87f002cd11e98cb1f0fa16f2 |
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Mark an assert-only variable as used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109091 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 30d35b8720cb148eb4cc417b3710e0d66ce5ec95 |
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Mark an assert-only variable as used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109091 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7bf9a01870f9fd87898dbfc76ecfc5cd57a72afb |
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Fix the generated file name for CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109090 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 986569ac9a7d90180cec515b5f101ced94ae794c |
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Fix the generated file name for CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109090 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 38dfb28983f7e48fef4aa58a3c4faa83dbb6b856 |
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Attempt to fix linking issues with CMake. Please review other CMake users,
especially on other platforms. Is there a better way to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109084 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 8a89a6ae9c3fb524cda60768e094ba481ac17be1 |
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Attempt to fix linking issues with CMake. Please review other CMake users,
especially on other platforms. Is there a better way to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109084 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| f2feafd516681c14d2249fd38e1528a7925ec136 |
22-Jul-2010 |
Owen Anderson <resistor@mac.com> |
Update CMake files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109081 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 214e46eac77bcea2b57d0d454a2dda1d97e979fb |
22-Jul-2010 |
Owen Anderson <resistor@mac.com> |
Update CMake files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109081 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| d2346d858026392706e54d00ed32f1d375da3fe0 |
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix constant island pass's handling of tBR_JTr. The offset of the instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into:
mov pc, r1
.align 2
LJTI0_0_0:
.long LBB0_14
This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109076 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b1c857bb7b3d7bc187de4e97439eb212a8604bf0 |
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix constant island pass's handling of tBR_JTr. The offset of the instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into:
mov pc, r1
.align 2
LJTI0_0_0:
.long LBB0_14
This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109076 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 2408253b0680ef77feed50de7e6743881ccfef6e |
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4a863e2c75145432fd660ee65e61b578c5e90ac9 |
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 30ea00a73f82df33ce1a38628fbff1b56a778f4c |
22-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
rdar://8202967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109057 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 917290043f87b8efa6ba540bec5963013c517912 |
22-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
rdar://8202967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109057 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a8fd2b42c0723bfa6a3bf4549a70b37dbc7f52ec |
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Baby steps towards ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
MakeLists.txt
akefile
|
| ab695889c67fb499bd902e8a969d0ff02ce66788 |
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Baby steps towards ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
RMFastISel.cpp
RMISelLowering.cpp
RMISelLowering.h
MakeLists.txt
akefile
|
| 2653313bfbae107be3742909cf8c99165c64e511 |
21-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix calling convention on ARM if vfp2+ is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bc565014357a89c91a46a647714cb0d256186cc9 |
21-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix calling convention on ARM if vfp2+ is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 83bd3e6df5274f42bbae9f5f611b373ac61c945c |
21-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 4f6b4674be5473319ac5e70c76fd5cb964da2128 |
21-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 944625143da8d16c561de79a1f4af849e0b1d302 |
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108929 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.h
RMExpandPseudoInsts.cpp
isassembler/ARMDisassemblerCore.h
|
| 4dbbe3433f7339ed277af55037ff6847f484e5ab |
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108929 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.h
RMExpandPseudoInsts.cpp
isassembler/ARMDisassemblerCore.h
|
| eebaf5a5b0a4ab8c8e6cbc49c82aab1e5deea5af |
20-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Using BIC for immediates needs an extra bump for its complexity to get
instruction selection to prefer it when possible. rdar://7903972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108844 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f084a5e81d7a0552dca2a144624812bb4547efd2 |
20-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Using BIC for immediates needs an extra bump for its complexity to get
instruction selection to prefer it when possible. rdar://7903972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108844 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8514cfa4210cbda710e87bb7a6e4354dc6abd416 |
20-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Removed un-used code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108841 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 26ede6834e8a435bd7a6670cb34f64d3f8e2599d |
20-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Removed un-used code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108841 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c045005458f070655bc119d0a1f26bac7efc8b04 |
20-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Constify some arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 72852a8cfb605056d87b644d2e36b1346051413d |
20-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Constify some arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 448a71eda23a82cc14d14566436525561a5d63b7 |
20-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Update CMake files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108787 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
MakeLists.txt
|
| 7b81a0ef1789439024c3788cf136f9520f83dd96 |
20-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Update CMake files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108787 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
MakeLists.txt
|
| aba25af8891408590193d9f2bce42e69e2240384 |
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
sink the arm implementations of ASmPrinter and MCInstLower
out of the AsmPrinter directory into libarm. Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108783 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMCInstLower.cpp
RMMCInstLower.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| f447a5f1446d3f3ccd7f342a54f565ab02a087c8 |
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
sink the arm implementations of ASmPrinter and MCInstLower
out of the AsmPrinter directory into libarm. Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108783 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMCInstLower.cpp
RMMCInstLower.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| fe8ff14a3de380455d0aca6de3893bc40b170cdc |
20-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d70f57b254114841892425a40944268d38ae0bcd |
20-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 3945a5d26b16d48e3a0016e66ca272ee8904b1c2 |
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108730 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e1102caf86c8e09387ac7ee83aae4e69d2d35fc4 |
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108730 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b878c2dbd526cac108882518efce4b845ecbac72 |
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
revert so I can get the right PR# in the log message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108727 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 350afb16ecab216d5ea887b93112b24ba87ececb |
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
revert so I can get the right PR# in the log message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108727 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| bea96646c67c0c8b6f47c525f1d4d1f1acbfd548 |
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108722 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 0bb9895a78368a75a3bfe2cb54ac6953b990515a |
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108722 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| a3692dad3ef77c2a5e846f2324927e3ee0afee78 |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Target: Give the TargetAsmParser access to the TargetMachine.
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d73ada7d24832bc2a4c3965b8f00ffd951341acf |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Target: Give the TargetAsmParser access to the TargetMachine.
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 533bae363191f5f441ed4d88d762e3d98506d3e0 |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
EADME.txt
|
| 5423856e44a7e4b173af211b0fb0675c44945a58 |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
EADME.txt
|
| a4c200546479ac059d89c0cb25370a0b757b06ac |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
add BFI to getTargetNodeName()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108603 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dd7d28a17b19d03115592de74e8291e47afbcc72 |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
add BFI to getTargetNodeName()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108603 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f0889c8c17ac0feedc40db91bf5233454cd2eb0a |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix logic think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108601 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 15a2f2eff80485e0f02a01300fde04d0b2f84a91 |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix logic think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108601 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| af37a7c752ca00280d86bfb58ffd411fbef72865 |
17-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Remove unnecessary check that was subsumed into canRealignStack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108588 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 697cba8ec2b3f5160175fd5b4a641dbd48606e17 |
17-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Remove unnecessary check that was subsumed into canRealignStack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108588 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 0e640c32d682f44098af4d60b4b9577bdd8eef49 |
17-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Make more explicit and add some currently disabled error messages for
stack realignment on ARM.
Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108582 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d4c36cec1db81b4ee48cd4ab462262615d78f22c |
17-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Make more explicit and add some currently disabled error messages for
stack realignment on ARM.
Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108582 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 7e792d59d7e5c12129b672b27dc80977e99a8eb1 |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 469bbdb597f27d6900c95b6d8ae20a45b79ce91b |
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 805f0c5b16c2b545eb39bec4e5d029a0b270e64e |
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 354b464f7174846b94dfe54ac6435570ec51fbb6 |
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a small local function for a single remaining late isMoveInstr call in
Thumb2ITBlockPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108564 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| c66756ba16a3df8b6426aee4ffd9c308f38bea57 |
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a small local function for a single remaining late isMoveInstr call in
Thumb2ITBlockPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108564 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| a02effc0bdeef3db3c148485564cab5ab6a7294a |
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
|
| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
|
| ddc0a8b9568a49c9b26f8c35d5ed777bc91c116d |
16-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 60108e96bbc5432f4fe06ba313e64448e97a0e15 |
16-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| a88b0db5e5a5dc6f79987157d3ae978ad4cb27bd |
15-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Random note about bswap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108396 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4baa8ebc930407affeeba452ff75d20da73bf7f2 |
15-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Random note about bswap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108396 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9676c5f0a3404d52eee60f18c336e7e971c85e7e |
15-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove restriction on NEON alignment values. Some of the NEON ld/st
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 273ff31e134d48c8247e981d30e214e82568ff86 |
15-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove restriction on NEON alignment values. Some of the NEON ld/st
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 4cf6e73f51b33e252cdad17bc03f487f17418941 |
15-Jul-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't pass StringRef by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 38e59891ee4417a9be2f8146ce0ba3269e38ac21 |
15-Jul-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't pass StringRef by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 2719050a2879d62c2f46a002a60145a96180649d |
14-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 502e0aa62833a1648d66c8f7edf5d21cf96c2f56 |
14-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 2e623e3ffdd8ca0bac3dd1c598758bd5da1bb267 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing address register update to t2LDM_RET instruction.
Patch by Brian Lucas. PR7636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fed76ffa569444596b4e15e2681298c8d7b6be83 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing address register update to t2LDM_RET instruction.
Patch by Brian Lucas. PR7636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d0645cb23c0363e8ce5d7f90209a7b5f8ea02cc8 |
14-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
A couple potential optimizations inspired by comment 4 in PR6773.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108328 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 54cc0e12dadd710e1b27d69c47ba30457e621d51 |
14-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
A couple potential optimizations inspired by comment 4 in PR6773.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108328 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d7144b2eb13eb08bb6529851ca84995c90de7c64 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 7e3f0d26908b82bc6a3699251e0d38821610bca7 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 7689cc824ce7b21aa0b60429c23ee80800cc9773 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
of the value of the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108323 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 046afdb50b4884470a93f1ff0c68a24dad110062 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
of the value of the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108323 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d4db5b1afb179ad3fe1b9f10fee79615feff8ebc |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9e82bf12a03117bfce78217662d5cf8e74aef357 |
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c97f96261679ee23a1ca8456915cba4b4ec00571 |
13-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
NEON VMOV-immediate instructions. This simplifies some things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| cba270d042862bca213b812656a2181b0de0578e |
13-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
NEON VMOV-immediate instructions. This simplifies some things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| e06bb790215bc2d8e9661078aa8fa2391638f11b |
13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 218977b53eb215e5534db2f727d109ab18817cc1 |
13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| f0a3d352dd3aeaf610458f778052342dbb11c0e6 |
13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 7a415999625f9791a8a7eea2027e628e29de15c0 |
13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 766d996c6f80d6e05032fc4eaa73201825fde6f4 |
13-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
avoid replicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 6dce00ced45b5bd1b7f34fe6f2d70c50fc090664 |
13-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
avoid replicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 5ebdbf3ac210861f340a4153a42b047eeb850bd7 |
12-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove some code that doesn't appear to do anything. All the ARM call
instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c7a797b82bc44b0aace62033d7e1ac7058ef45c6 |
12-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove some code that doesn't appear to do anything. All the ARM call
instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c2d3eee936fe8da7e8e257cb45580149421190bb |
12-Jul-2010 |
Duncan Sands <baldrick@free.fr> |
Convert some tab stops into spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
smPrinter/ARMAsmPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| 3472766f9eb7d66f234c390ce1b3a8b76f0ee9ce |
12-Jul-2010 |
Duncan Sands <baldrick@free.fr> |
Convert some tab stops into spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
smPrinter/ARMAsmPrinter.cpp
isassembler/ARMDisassemblerCore.cpp
|
| f39a984209597675643a69bc056402f571f4705a |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 600f171486708734e2b9c9c617528cfc51c16850 |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 1d416d406a947eb15d8f2a59497583763c78de1c |
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| d6d7abaf4ebbabb850aa9c20e1617f897608fe62 |
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 7322ec9f1735595cdc32fb18ef1dd816a14961db |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| ac2736670034e8942939b9fccf8e4618a0bda908 |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| deaae440ab24bb0531c2e23bde4f64300291e832 |
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cbeeae23c31d32b833c9c7c3e8984e4cbcf22f45 |
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bdf207628dff7c02ba5435744226605f906c886a |
10-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Add parentheses yet again to satisfy GCC's warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 68eec39bca280f98bef1256a5e89531ac1a77d1a |
10-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Add parentheses yet again to satisfy GCC's warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b4737986ba62ecb5647e3bd01bb7a14fbc610f8e |
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1f32340d95ac480bfc74bcfd00fd5cffbe078652 |
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 6b3f5c9a78dbe591c5b2514fe01536c5469c84dd |
09-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6c7d3a16b3321c527e35322e869c73d47dba719d |
09-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| bd0018eda94328833ea24fa39b9b9848685471ba |
09-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a0148c360e9bb4badabf1a2397cfd70907618f87 |
09-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e839d46632093c38330966474f2ab017c036ea19 |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Check for FiniteOnlyFPMath as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5d115a0ff9634149ef021ec9335a47c52aaaafb0 |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Check for FiniteOnlyFPMath as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b41ee4c1c7124f3901219a487fa922b01e1514f6 |
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 1425c6a92747acd904dfbb9c537e444e15b1ebdf |
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 8a7e4c4381057a31fe342e578eb1e7e25783dd9e |
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 8190173350f4e4d916d2307278955b133fba8a00 |
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7110f4eafc823fbbeb782baf495f6b8b0613334a |
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107882 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 8af4c54af1ee55d5e22a76a9201dd351acf3cb5e |
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107882 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 4dc8a1eda314b03118daf8dbd1e2c237c8082eea |
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 0bc25f40402f48ba42fc45403f635b20d90fabb3 |
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 6f1a01b5591c98e0bfb427d53c471655ee028aa3 |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4ff7ab612c66fb7ecf547242d6906be6ec3fa604 |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ab54f36cf8fff98ea20a5f2575282741aed76c2c |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 515fe3a58877c745a922252a4492e866a2f1e42e |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b7d735372bd03b1afbc23f182503757a6fda6a57 |
08-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMInstrInfo.td
|
| 7835f1fcdbb58093377c9e3476f45a2638565762 |
08-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMInstrInfo.td
|
| f9340efbd7e65a62da55ab23b8d79deb8aa5a85c |
08-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107831 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 03e2d44722c1ebd3953007db0579147b46efba18 |
08-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107831 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9f6fe14da01027a5d3c785cc8401f144f2a4b607 |
08-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle cases where the post-RA scheduler may move instructions between the
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107830 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| c7937ae025194cb62ffcd592785c3ad97e7882ce |
08-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle cases where the post-RA scheduler may move instructions between the
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107830 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 41482e09ea07ec0120994dd43a6aa0f4ef66a391 |
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar and trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107811 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 26b8ef53ff2ff1ffd72d140b5be264e32dee0195 |
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
grammar and trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107811 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f53e8cd8b1639a358a97deaea7ee5abae7c560ad |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c1c0833f5c20e2558f5767735b60fdae654f8fe2 |
07-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Also use REG_SEQUENCE for VTBX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 78dfbc380d685c59b9321e43c10677a179850e29 |
07-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Also use REG_SEQUENCE for VTBX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| ebb6efb9531854b8daa1eeb24255753db2a225ae |
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
they've been tested to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e97f968a69d90ee61fbe16d1740ab7f7ea18d1bf |
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
they've been tested to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fb695a291ec7ad5be9f4c13eb7df14c903d4ad15 |
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c66e150b2cb1f2f8e2f4eb124b9177ffc6ef3a74 |
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e633a7a766d71736c91b0558eecb0dbf0d929d26 |
07-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
allocated to consecutive registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| d491d6ecd2debd444451f07e6e947685d1e02217 |
07-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
allocated to consecutive registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| a274fde9cf6f3b82414c343f581251b477ec4fc7 |
07-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Track defs for all aliases in NEONMoveFix.
This means that an instruction defining an S register will affect the domain of
the parent D register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107725 91177308-0d34-0410-b5e6-96231b3b80d8
EONMoveFix.cpp
|
| fca3a25fed9950f7ca39c86a3f2b72a1966f7896 |
07-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Track defs for all aliases in NEONMoveFix.
This means that an instruction defining an S register will affect the domain of
the parent D register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107725 91177308-0d34-0410-b5e6-96231b3b80d8
EONMoveFix.cpp
|
| de09e922a6a82ff48d31328606f691591ae8fa19 |
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 30377a614c8d671f0da10e59416afbe2a282a2ff |
06-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Represent NEON load/store alignments in bytes, not bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| f967ca0eaf30325cabe3c1971bf0dba16cf1b027 |
06-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Represent NEON load/store alignments in bytes, not bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 3dd527d9807fa0c5f81fbbf92858e0362226b327 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2241e6cd892d48716c7823683b21184f3395a013 |
06-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a5e82a5748763eba327176def083eec688eb4d6b |
06-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 17ce26121c7897de51b0206bf012c32e2f2cc53a |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 56f3378de6b873302cbf2f69582b29811cfd919b |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b81c771c0d9ab5a980caf3383932b051eafd1a39 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9ff54089b59fb811a3530cf96ebb5c946cbb140f |
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a8487ca33322438f1fd20f2334439ec831b3251e |
02-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove early IT block formation. It's not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
humb2ITBlockPass.cpp
|
| dca653951c693edf47437cf0a10d0d0dbb57276d |
02-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove early IT block formation. It's not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
humb2ITBlockPass.cpp
|
| 3477c87be5b32ca1348a53666e688b3d249eabd3 |
02-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| e45f72c833a23602399605148c76b6debb3fabd2 |
02-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 7a3f4a976d6542b3da87ef7d947147c452689ca6 |
02-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM function alignments were off by a power of two. svn 83242 changed
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b5b5057a709a6dc8e99c6e57bdea89c2b53dd4de |
02-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM function alignments were off by a power of two. svn 83242 changed
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ffdc17bec626bae590717b8af59e4ba1de216bb4 |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding VDUP (ARM core register) instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 21773e716f72babacfcf98cb5a90fc1a62a8254d |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding VDUP (ARM core register) instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| bdd93b262fd7700fa141f937925842b901e8d382 |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding NEON VMOV (from core register to scalar) instructions.
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d5a563de07b7479c6c69b35a81d48bb8002580fb |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding NEON VMOV (from core register to scalar) instructions.
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 4645ae684ad7a66e2c4542a251037682ac2b85b3 |
29-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
skip dbg_value instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 077f1bfa91953eb2378fca9b5ae91b08a2fc17bd |
29-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
skip dbg_value instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 54ccceb347a1c09768588483fa891e1187f8ec8b |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 1ab38469dfa8050724a8443d7b7ef2885e11e1db |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| dd68477a2b0c937054dce377a953e161d4db7b5f |
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d31f972bd33de85071c716f69bf5c6d735f730f2 |
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| fc7f22f577eaac4342fdaf41d9c3176feb634eda |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove pointless variable LastDef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 31a3a3ebaf9c28fcfd82b1494a47fb11cc00759b |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove pointless variable LastDef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 06d55e1575fc6a25fc7c0afd652642de640c3650 |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove unused variable Loc and pointless variables unified_syntax
and thumb_mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 58c86910b31c569a5709466c82e2fabae2014a56 |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove unused variable Loc and pointless variables unified_syntax
and thumb_mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 0f4c7e269467d70dba619e721a5b376c6e9df1ab |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove an unused and a pointless variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 978189e090e809c1a6efcf2677e785a06f71029e |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove an unused and a pointless variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b375499e2d56fed3125a7d797ef21e03fe220176 |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove initialized but otherwise unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 90c64f4aac95ebfcdeb8ad78a373fdb9e61b002c |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove initialized but otherwise unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2aa4e7c23ca30bf42eb424419ed231f81a8a4cd7 |
29-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c36b5b97308f098beb6c0bdd754bceb39675b049 |
29-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f00173992ff82419767f47900f11b71beaff7c13 |
29-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-cvt options to something that actually as useable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| c170f66742f84367e9922e5dd1953d696788a8be |
29-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-cvt options to something that actually as useable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 1791cdc133e01a06970c51005621845f77210e99 |
29-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
When no memoperands are present, assume unaligned, volatile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 628a79771ba6d293ba7b6f2615f022e1ae9c7c49 |
29-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
When no memoperands are present, assume unaligned, volatile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 113efc8485d586656ff7c7966e35dc34ea982dab |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
the same as ARM except that the condition code field is always set to ARMCC::AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5cdede43e92a370130fddde2ff071c74ea463448 |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
the same as ARM except that the condition code field is always set to ARMCC::AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| b9103199ac28a1462150439f024e615b36bef093 |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
of the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 62d24a4b92df6f367b82eb232961c27421d8abfa |
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
of the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 64082f40bb36661b3f585f870b4e332b3e764618 |
28-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up style. no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
humb2HazardRecognizer.cpp
|
| e89c5e57cc5c525d7875032a125e37bd404448c2 |
28-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up style. no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
humb2HazardRecognizer.cpp
|
| f48bd3b93d62085766f1ec01e8a2243f68ebe0ce |
28-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor encoding function for NEON 1-register with modified immediate format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 08baddbc0708d6965b72b40aa3c1f40b56a31835 |
28-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor encoding function for NEON 1-register with modified immediate format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 86bd22b53945cda14f934591a587a2dd80dfcbe7 |
28-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Support Thumb mode encoding of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d896a97dc7c14675c08520847b45a60a200b8cf5 |
28-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Support Thumb mode encoding of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| bc6517d2ada0a1cbac8e0682aef95b026609b9eb |
28-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
humb2ITBlockPass.cpp
|
| e9e3f20ffbb20ebae6c48c3499c9b069f28e28fc |
28-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA8.td
RMScheduleA9.td
humb2ITBlockPass.cpp
|
| 06a2798498b807185f64d16352c77c028bb4e246 |
26-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a2c6f457a4954d8e38b4c2c69b011cdfa123ad02 |
26-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4c5c79d288a17ed7be2d8e9155188a3d26a8515d |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding NEON VMOV (from scalar to core register) instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 52e4a0a074b758ad3dbf6841b249aaf3baf08f28 |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding NEON VMOV (from scalar to core register) instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| ce0e66f1ee93efa564eee248dcbedeac82d68d0b |
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
It's now possible to run code placement pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f6799394d5a656fa5adec4619d60c5f79fdb43f5 |
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
It's now possible to run code placement pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c1bffa7b33791ff818ac443b3b879f1136b25028 |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Renumber NEON instruction formats to be consecutive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 80d9bc0336821ca2a94a7afe2daac6e8bc689ef7 |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Renumber NEON instruction formats to be consecutive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 9f1aa33dab8eabb08e383cdef3204fa1e6c8e77f |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
"N..." instead of "NEON..." for consistency with the other NEON format names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 184723d9be17fa0d136b564b2dca44c5216044d6 |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
"N..." instead of "NEON..." for consistency with the other NEON format names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 1a071f68b23b4fbf696b1f7d207565393984774f |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
Renumber MiscFrm to 25.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 26532631653be91f9ccc99fca3bfb8027da7c70b |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
Renumber MiscFrm to 25.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
isassembler/ARMDisassemblerCore.cpp
|
| 6b9223fcf67da4c1983ee73bbfbc952bb6adb001 |
26-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| e39e06af38281bb8923d28b554a11a74e4eb67b7 |
26-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 09f725277d18268655bf3e5e261061a54bfa1d14 |
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 13151432edace19ee867a93b5c14573df4f75d24 |
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 383e846e3abbfb4e09bd7e020a9d46c424755e34 |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding 3-register NEON instructions, and fix
emitNEON2RegInstruction's handling of 2-address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5e7b607f725e5c07aacd1d0cfe5fefb6b3900ae2 |
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding 3-register NEON instructions, and fix
emitNEON2RegInstruction's handling of 2-address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| a7ba9cda87adafd4fcb30902120010c21888e8f4 |
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| f1672483d8ff3d19e647cc959edefc853902012d |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding 2-register NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 583a2a06152de7796967488f3689e109ba6c5364 |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for encoding 2-register NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 40763e060ed493a2b2e3f9bd7cbfc85a1fd4b5ca |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8c605c601da54a09c14c1a9a59e75dbb24df2a43 |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4d27e7b766c2d13bfc849a54feb39493a8d6defa |
25-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
IT instructions are considered to be scheduling hazards, but are scheduled
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 57bb3948034436a458f5ef857eb2e831a47e7401 |
25-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
IT instructions are considered to be scheduling hazards, but are scheduled
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| bea33f596ec9065a282d81c3279f8a05a0892cab |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing ARM and Thumb data layout info for vector types.
Radar 8128745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| ade57fa619f9ed750a359c06ae031e3979e915c0 |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing ARM and Thumb data layout info for vector types.
Radar 8128745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 9986b9f068debf39de9fb587fc697cad86cafc71 |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 86fe66db3ad19bc20dbb9803e4bf032aa6cd1924 |
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a800df9065b67bfdae22819f31d25deb4622f7b9 |
24-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Oops. IT block formation pass needs to be run at any optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8acf67672bf53ba9b168a3b11fba42988708b7a0 |
24-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Oops. IT block formation pass needs to be run at any optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8ca0d0011be5bf73750206990ad726c669e870aa |
24-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 761fa7af9e883c81da52b27abd0d6971dadbc923 |
24-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d834d604eca8794261523af0daaae7efdc25c66b |
24-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
form so they can be narrowed to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 789fef987f9c3dd14743731e3a6733f2f90c9778 |
24-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
form so they can be narrowed to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 3d03781d96a1076d8f5dfd3910702a5dd8671499 |
24-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
We are missing opportunites to use ldm. Take code like this:
void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 4b722108e2cf8e77157e0879a23789cd44829933 |
24-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
We are missing opportunites to use ldm. Take code like this:
void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| b09e66eb68648b8d544ae1f6337e5f8bfcd218f8 |
23-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Do not do tail calls to external symbols. If the
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e39fdbe1187b74f8c415adb9f807fa56f1e055aa |
23-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Do not do tail calls to external symbols. If the
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c4c46f871e5d8603c9af6fc163c0bf39365fd422 |
23-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
When using libcall expansions for the atomic intrinsics, the explicit
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5def57aaf477e3383cbd1b925233098a54273146 |
23-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
When using libcall expansions for the atomic intrinsics, the explicit
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 69a4c0861855d688bc0832e90759fb3786db118d |
23-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
Radar 8031193.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| a3a204664db165f7b58a45e2239127513b207e8f |
23-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
Radar 8031193.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 559d513348a11936bc90b64aad75e2540b26c6a4 |
22-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Use pre-increment instead of post-increment when the result is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| fe60104ac97f3a8736dcfbfdf9547c7b7cc7b951 |
22-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Use pre-increment instead of post-increment when the result is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| 8bed85099fd6ea5f408e5dbaa7c1e60dade7e159 |
22-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855 |
22-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 4962539ccfd20df4f062134f4313de24a832b7df |
21-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
Radar 8104310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 56a1a69a35ca2ee0d1249d705de8936096c6f008 |
21-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
Radar 8104310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 20f2e6efb0e121f11de954f7fe4e7d3ce84baf28 |
21-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| a967d1121a87dfb6b65eb7e3433c041efd881483 |
21-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 548e6e14ba7ecf78071037dd71500ee078a76a5d |
21-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| d95ea2da28901ca6e81645e444e528d66350d781 |
21-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3d63f8a10a0cc52ad504c09a9ddf068f0e93982d |
21-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Fix PR 7433. Silly typo in non-Darwin ARM tail call
handling, plus correct R9 handling in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.td
|
| b0ccb757b3ece5897e61643e055c30df407c0fc6 |
21-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Fix PR 7433. Silly typo in non-Darwin ARM tail call
handling, plus correct R9 handling in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.td
|
| c69a904599265192740373d5d58eb243650eeb42 |
21-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
early exit for dbg_value instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9cfcfeb24bf7182d40d8e8a54e350451b67a1136 |
21-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
early exit for dbg_value instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 23a5d6753ba766a754e5cb37deef19a2a6c82e82 |
20-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a crash caused by dereference of MBB.end(). rdar://8110842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 859df5e9f9a71213dd7e017683d359131ec2d263 |
20-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix a crash caused by dereference of MBB.end(). rdar://8110842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| dbe1ce39595800f1976e70bda0fc386bdec1d406 |
19-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove a fixme comment that is no longer relevant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 31ef8e6663d41bc166b9061c4e9b0472889d49e8 |
19-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove a fixme comment that is no longer relevant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5f85e6378998a1d3120738c9136907ddf4873c00 |
19-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix error message to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dc076da4d25a447982c0629da91e322eda511cbf |
19-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix error message to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7a8db740bf72f2534bc2a2bb6683fce0539cfbc5 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Ignore dbg_value's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
humb2HazardRecognizer.cpp
|
| 02ba9e19c7f537904d02b5df9a12ac5f895c4c0c |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Ignore dbg_value's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
humb2HazardRecognizer.cpp
|
| 609ecbec1ed7352caa2e4e4e1516564545129886 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0110ac66ebd1e59e6ac163e13670f36d091084f6 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2bcb7065b47c2a8eb8d18398731be4bdc5100010 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Indentation and remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6523d2ff7f3c583995b018ecc09391c26b37fce4 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Indentation and remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6d21b6e06548bfd5b4df53d6f87c2d9216dfbb5c |
19-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 9559e3b99af79da0e97027992345b74db2f7f6a2 |
19-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| a529d78106a6145221da33d002df4640aa06a874 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Move ARM if-conversion before post-ra scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 96c3da64363ef8c0fddf4dbba7576332ef868780 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Move ARM if-conversion before post-ra scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| f2573901bb4ccbf3a1c3f4e637505f73200e7b66 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Update cmake list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 3ee608c5aa2954ac2af655b2d73ea6e907465e0e |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Update cmake list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 8fab63a5051350c8b97d940c5be069b3290f3feb |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 hazard recognizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
humb2HazardRecognizer.cpp
humb2HazardRecognizer.h
|
| 886459456c58695fe30dbf5b91954aa36a7a3674 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 hazard recognizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
humb2HazardRecognizer.cpp
humb2HazardRecognizer.h
|
| 24ff056654cd4eae6c6403b81dfceaa46605f395 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrThumb2.td
RMMachineFunctionInfo.h
RMRegisterInfo.td
RMTargetMachine.cpp
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrThumb2.td
RMMachineFunctionInfo.h
RMRegisterInfo.td
RMTargetMachine.cpp
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| dd67159ea024c078f6c9f3c41bc400b1f3f2f6e1 |
19-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ef6eb9c7ab7967790566c5e2d47977d89fc060ee |
19-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4df250458e54135b6af7c19132b8f29d2751ed9a |
19-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable Expand handling of atomics for subtargets that can't do them inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 68741be5e6a4a0e633928e4d86eea38aa07a2ca0 |
19-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable Expand handling of atomics for subtargets that can't do them inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7a7f12d06b652a70dc597c490c46672575bb3458 |
18-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rewrite chained if's as switches and replace assertions with llvm_unreachable
(as suggested in radar 8104405).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ebe99b2c198ec08c5e4a032ec0afb0345c747706 |
18-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rewrite chained if's as switches and replace assertions with llvm_unreachable
(as suggested in radar 8104405).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 248a97be8c83f228ca62f82b750ac3ad183dd2cc |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Fix ARM/Thumb reversal in previous attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 51bd47edbc6112212291f4e82502c8b33ff799f1 |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Fix ARM/Thumb reversal in previous attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8e241b80bc33222e22da8f5060c2224b22c1817f |
18-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 52c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7 |
18-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 967a639933a223c03154115afb3977f771b37919 |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
An attempt to fix the problem Anton reported with
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMInstrInfo.td
|
| 10416803c1370fe1e52a7f1c431fe506be9c1ef5 |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
An attempt to fix the problem Anton reported with
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMInstrInfo.td
|
| f78836334612e03afa79b8b6c1b94ffd1236f44b |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Enable tail calls on ARM by default, with some
basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c66cdf74a9f1ee12cb9bff39cbd6bc518fbc2d3e |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Enable tail calls on ARM by default, with some
basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 05bf7d1642fe2553cc94fd2c27da62357560ab8d |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| a606d955de3b0f777131d74162eb6f11b5f95d75 |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| f8df119403b59c66c2886c26be2146edac74566e |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Last round of changes for ARM tail calls.
Not turning them on yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| df50d7e238c4802eb2de04646b8f7ff7327730a0 |
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Last round of changes for ARM tail calls.
Not turning them on yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| 2edb384bae37fa5f99fe42882a05fad4d8f8842f |
18-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0d8ba3303b40a150f70ff63f04f57160984492c1 |
18-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bcc946d7409ba0d8918f4d0256090ff1a8b90392 |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate unnecessary uses of getZExtValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e368b460a206fafa0d31d5d059b1779b94f7df8c |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate unnecessary uses of getZExtValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9fa5e3347d0fcd2a4626807dc2d8f7ceedf48ffd |
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 828feb68940e33608f14c3d7183fe41ae0464a1b |
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7072cf62a52787c461e3371ad36e1754e8a0dc97 |
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 96b81269d6484b1b8587294de7a47ffdfea67d91 |
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
simplify code a bit and add a more explanatory assert for cases that
previously would result in 'cannot yet select' errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c73993b67815c96bb270034bdc7b7e8edc16d614 |
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
simplify code a bit and add a more explanatory assert for cases that
previously would result in 'cannot yet select' errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6190f65b9987a44f09b29efabab78e39d9f2436a |
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
format and 80-column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7616b646f1436d11ce0cb16f52ffa10b5522b0ac |
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
format and 80-column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6b1388e7bc002b965a2472dd7f85e41a71d465c8 |
17-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't attempt preserving conservative kill flags. We were doing it wrong.
This is before LiveVariables anyway, where these kill flags are recalculated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| a2846b4bee819c02094c41d44c4e92e03fc830dd |
17-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't attempt preserving conservative kill flags. We were doing it wrong.
This is before LiveVariables anyway, where these kill flags are recalculated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 3f0cad3dbf6e69208cfcb8dcc713bdb6b46e8aa3 |
16-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
EONPreAllocPass.cpp
|
| 07f6e805b1e832a2c34a83862cec27736bb471bf |
16-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
EONPreAllocPass.cpp
|
| 160f30cd4ff881f768384f38f1b9d7694faa0b40 |
16-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetMachine.cpp
|
| 46df4eb46e784036cf895db271fe29e1cf2a975a |
16-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetMachine.cpp
|
| b332030af5d914aa9815669fe5ff1d814fd12a64 |
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Add file missing from previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 38d5f0441cb0e78a1ba89d46489ec27a31f0cec5 |
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Add file missing from previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 192119a1cea4cf5a149bc3ed77306060c689095d |
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMRegisterInfo.td
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 6470a116f17b70aba0c2e7ee751551a5ac9797f6 |
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMRegisterInfo.td
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 52f4ff720cb1747339abafc668550f7b4094b0fc |
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add basic support for NEON modified immediates besides VMOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 827b2106fe39c4195f5f5393b6bab70cc297657d |
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add basic support for NEON modified immediates besides VMOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 3cae8c16381853de40154818a76d6f0ef735a86e |
15-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| f4a7bf4ec3faf80a9c890408d574a3d2e7ed1e1e |
15-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 4c5ba5264f5e636c896f7535d1316f6bbea8198f |
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 14f1d4e74bd52b044a2c2bb6dd8df20b0480e633 |
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| bb8a0a630475339df6375468255da8157e9c9e0b |
15-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure to skip dbg_value instructions when finding an insertion point for
the combined load/store instruction. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 400c95fe3802821815c69077e48c8fd276ec6494 |
15-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure to skip dbg_value instructions when finding an insertion point for
the combined load/store instruction. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| a70a91b9867f7e8fc3af65e14e2c4e0f30c2d55d |
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename functions referring to VMOV immediates to refer to NEON "modified
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| d3c4284849ccfbc501483ec3c0810d1d9ef853b6 |
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename functions referring to VMOV immediates to refer to NEON "modified
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| a394cd6dac8c0187bb25028649fabc77fe781aa1 |
12-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a missing bitcast. This code used to only handle conversions between
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1114f568bc35cf13064c864df44194630449bec5 |
12-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a missing bitcast. This code used to only handle conversions between
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 73e9f2e91b86c25a1b908e7dc9a65c2d84339e81 |
11-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction encoding for the Neon VMOV immediate instruction. This changes
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMISelLowering.cpp
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassemblerCore.cpp
|
| 1a913ed17875d1a0fb490e1266b74c057c76a94b |
11-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction encoding for the Neon VMOV immediate instruction. This changes
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMISelLowering.cpp
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassemblerCore.cpp
|
| b50cf05f6bb9106ee625baa08e5c196cb977315f |
10-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete code that's not safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105774 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| aa4b5429ef0c174dbff52b6e67b78c0a68f2025e |
10-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete code that's not safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105774 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 3a208ae6a713461313e373c8e486b74e143829c9 |
10-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| db03adb34615331c6ef55ebbd80d8bc750deefe0 |
10-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 88287d63dcf967e22d0e235765743e4f09e3ce5d |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 68fc2daf8fa446be04d2ed2b3cbb1b00c382458f |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| ac722a52bc3c3d52557f6bfbba7d2ad07ee332fe |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 34aa4238142371d35d3774435b21cb966b2a2c28 |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8bf0e4870680e0e6043b8696b22b82eaf93cfd6c |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
humb2ITBlockPass.cpp
|
| d84712421121744797210a7814aafce8c5377d92 |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
humb2ITBlockPass.cpp
|
| c6afe24569131e628add7653391bad92ced2c25c |
09-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix copy/paste/modify think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 6335ac67b60c69c7314b1fb16721ae4a51043fc0 |
09-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix copy/paste/modify think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| b5e6eed4be00564e022fea3f1bc684533fd38607 |
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassemblerCore.h
|
| 99405df044f2c584242e711cc9023ec90356da82 |
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassemblerCore.h
|
| 351a6ed29ff31726e7cfc8b14827aa46b0c60683 |
08-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105634 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| b84adb3b80c5b17befffd4f1d31ec5331ddcb792 |
08-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105634 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 28188e1c4986d9e4985f0f4a8ce268743eb94631 |
08-Jun-2010 |
Shih-wei Liao <sliao@google.com> |
Git hiccup. Retry....
Change-Id: I5a329137a43f36bab32ea62386ade11da550c0b0
ndroid.mk
smParser/Android.mk
smPrinter/Android.mk
isassembler/Android.mk
argetInfo/Android.mk
|
| c156bc696311928af01132d159b9e307436779bb |
08-Jun-2010 |
Shih-wei Liao <sliao@google.com> |
Fix llvm.mk and the other 49 mk files
Change-Id: I5aa02363c1083297d163a575f5a35c495f950230
ndroid.mk
smParser/Android.mk
smPrinter/Android.mk
isassembler/Android.mk
argetInfo/Android.mk
|
| f4c4adfd7271437b3ba269685d31031a3b73281d |
08-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105591 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| dd726e5bce1d7e612d8de5c4782409858f915b37 |
08-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105591 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 945161acde5b78f7310276c350d44fb825cd9a13 |
08-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Further changes for Neon vector shuffles:
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105586 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 53dd2454d5a38af455a9b23a16b0cca8e691b070 |
08-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Further changes for Neon vector shuffles:
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105586 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 1f4a831994cc33a23be2716f312e0c568791d48b |
07-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105557 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 8077e76f934d575437a55315a0d5fcdcab6d6608 |
07-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105557 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| d6b67b086e22513262254c0f1b5cf056e84ac72e |
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassemblerCore.h
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassemblerCore.h
|
| 2525d7f040971a06e4e36f946dbd6bcbd722c3b5 |
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassemblerCore.h
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
isassembler/ARMDisassemblerCore.h
|
| 0f57ab63e04de9405b02066027aebb898ee3739e |
05-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Improvements to tail call code. No functional effect
unless using -arm-tail-calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cf296fa1629f02e63aa1264a619a65cfc66ef173 |
05-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Improvements to tail call code. No functional effect
unless using -arm-tail-calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8a54f3e1f79c1e57e76a1cc53c6c5697374ea7b5 |
04-Jun-2010 |
Shih-wei Liao <sliao@google.com> |
Initial slang.
Change-Id: I4f84a741e5fbc440cd4c251406d2b611a237f713
ndroid.mk
smPrinter/Android.mk
argetInfo/Android.mk
|
| ed426cc1234231c434523439ef1a8d87a0323e22 |
04-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
More thoroughly disable tails calls by default.
8060143, although this doesn't fix the real problem with tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8fa8e7fe95db6a8c8581ccfe9db2c9faac819f8d |
04-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
More thoroughly disable tails calls by default.
8060143, although this doesn't fix the real problem with tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b858f76cf5c27bed2a81f6982bafa86b51dc9d8b |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Another fix to prevent debug info from affecting codegen. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 8af44b687b0ee552b696361e1ab4b2c178ff6f9e |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Another fix to prevent debug info from affecting codegen. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| c4b03875964b621cfb2dbe0ada3ceb054935d1d2 |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
more dbg_value adjustments so debug info doesn't affect codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 958e4e1967838766d327f1112e5b4900be939275 |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
more dbg_value adjustments so debug info doesn't affect codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 2f61019ceb041eaef447b5b358a4c33aff89a48d |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| d089a7ac70397ea41fe6128639dc54b8e273ed60 |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 4a4ebb84467bc63f5c935ac5269f9c965af11c46 |
04-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 40cbe7d5d41d22d32e8ce773548f510fd1ee0ed9 |
04-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| c038c98ca7c495eaaeeecb9e0b82698891363ef4 |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the ARM load-store optimizer to deal with dbg_value instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3de755bb407f91c494ae675fa6408a29b1954a52 |
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the ARM load-store optimizer to deal with dbg_value instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 4ee77f2e3f64eb92b1c7601a054d033171eacc4e |
03-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 51e28e634880849ed9f7c02e93c08d25dd70291b |
03-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| d2776e0f42e69a90cd99e134481505520973584b |
03-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
|
| 9edf7deb37f0f97664f279040fa15d89f32e23d9 |
03-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
|
| 8ff4917b26a45db09087b5c994b11bd5214789cd |
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMRegisterInfo.td
RMScheduleV6.td
humb1RegisterInfo.h
humb2InstrInfo.cpp
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMRegisterInfo.td
RMScheduleV6.td
humb1RegisterInfo.h
humb2InstrInfo.cpp
|
| 9699a4f87d05daf8809924950a4301a2f93058ad |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the TargetRegisterClass member from CalleeSavedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 42d075c4fb21995265961501cec9ff6e3fb497ce |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the TargetRegisterClass member from CalleeSavedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 89e6290f4307712cdf70249b099f9a9df0b407f5 |
02-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 91a74da036d3a9442953ae1de3e797a50da4ccf0 |
02-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 26c20ff4b09ec5508622be0837408516d2857201 |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Replace ARM's getCalleeSavedRegClasses with a simpler solution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 20fae651816916000c47b78843f22fd259ba4216 |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Replace ARM's getCalleeSavedRegClasses with a simpler solution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| be3e42114d3c7b2ae7396da5fcdb192b5939b5b6 |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some A9 load/store cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 4ed81ecbcd139fe13985a1b962f6cd522b90b79e |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some A9 load/store cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| ad64f2d67f34d25a9cd034202457ff54e47a3bde |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some rough approximations for load/stores on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 8207fce96f44f4e0246781eec909ffbe4fd9ab7f |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some rough approximations for load/stores on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 0ab44bf02562525d04a5eb9970b438c46f46cad7 |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
NEON/VFP stuff can be issued only via Pipe1 on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 1098ef5fa46bf212e49306ec9f6f0c791cab2077 |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
NEON/VFP stuff can be issued only via Pipe1 on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 0d83b588da07f9fe815d2fcd16d954498f517328 |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some integer instruction itineraries for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| 1845a387e104c8b1ad5bb38ccea345f333dcc644 |
29-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some integer instruction itineraries for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleA9.td
|
| c2d375ac4db07e84bec72f589d77647ddfd65a29 |
29-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c10f5434b4ad0758f948c52c18d5740c7f44e8b3 |
29-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 878fa5b3b97b7c3234c67b5b7afe9d98a792cee8 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
correct retattr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bc213209bf3dd5d0b6262464e468fe0d685b24e0 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
correct retattr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 099bac5fc77217992b73be52cc8bd3db010ac2ea |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cosmetic cleanup. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| c9792a3c1ffe9656db85e6a042a6205f27d48793 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cosmetic cleanup. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 04bf1fe000c4b100251fdb3f3dcf2810fa546942 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5caeff5c011d9cff5255748b5a0082bca8426554 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 91a0905536ad0c5ee542b19726aea8244835b247 |
28-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 13ef8408073e00d3ae04067deee79721c62af209 |
28-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1f2914c7abfcd183e1a4bd74d5378c0b4a92b0e6 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Update the saved stack pointer in the sjlj function context following either
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 0798eddd07b8dc827a4e6e9028c4c3a8d9444286 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Update the saved stack pointer in the sjlj function context following either
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5f3b96de192d111dbf648502f7eb6e670f7d57f7 |
28-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use report_fatal_error, not llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 12616727c71721f480f69026d88a58a067d89824 |
28-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use report_fatal_error, not llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ae810412a11fc5c29b2e0c452bccf28d41263528 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
back out 104862/104869. Can reuse stacksave after all. Very cool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| a65850230af7f13d9111450f645886b968dea2a2 |
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
back out 104862/104869. Can reuse stacksave after all. Very cool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c2cb3704c1cfe80a3466f222662c690828a89593 |
28-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 84f60b7359e1aa90794bb19de2bbf4d25dc2f01d |
28-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 314d7ebaee7eccdc0d8ec10fbd13634eb3d8ca14 |
27-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d984eb6073d5445f08fb0cea67a668b1b5e888e0 |
27-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e09ee5c34f29616c2bd649b466551348449c74cf |
27-May-2010 |
Jim Grosbach <grosbach@apple.com> |
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
to update the jmpbuf in the presence of VLAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ad9aaf038e1886013ef7118608182c479c986a97 |
27-May-2010 |
Jim Grosbach <grosbach@apple.com> |
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
to update the jmpbuf in the presence of VLAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 89b515b1412d0e7b1492aeebcd89a0845e01e382 |
27-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Give SubRegIndex names to all ARM subregisters. This will be required by
TableGen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| c8b9f6ce232fcdd38d11c48b51e62fe02d8797ed |
27-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Give SubRegIndex names to all ARM subregisters. This will be required by
TableGen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| cc38a49327e841070b34fe1a92c1191a791887bb |
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 23ff7cff52702a8bff904d8ab4c9ca67cc19d6ca |
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 7b61d2d98875ee7cfd3402215bf85bd23d3343cd |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| ca561ffcf320e9dbfafcac5efcee81471f3259c3 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 37e3887649dc9013835f80283609b9709c2094a5 |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
Coding style change (Adding 1 missing space.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 9f3b6a381a4f70e8af7ddd8ea38981c6795833d4 |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
Coding style change (Adding 1 missing space.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 63ff440fd17c797cebb3c64c7198dad46ef7c90a |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 45469f38b602c8f10ea37dec8d0a4dbb725cf101 |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 7a3d6753afec666711ff4c41ab95a490ba23f37d |
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 54e13eceff09ee79dc6408be990aabdee1a561dc |
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 6befc4388b163a196007644913cfe921d7b5ac26 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| b555609e73f5091bf8180c0875fb1fa6c5ad0e7a |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| dd65ed483487d5c4e6b3f16eaa70a74362864893 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 6a45d681e53a99b4c4f63e0b1664626a596a8151 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| ac79ed164b7f70ab2f16557c7d4eed7e9db3063a |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
Adding the missing implementation of Bitfield's "clear" and "insert".
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 6d37a29588e9a48d81480501f895ac627bf60201 |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
Adding the missing implementation of Bitfield's "clear" and "insert".
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 521a8d4fa73593c22976fc4ad509d46840ef512b |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5170b71143d99a650921cb87223a0b3f46a74fb4 |
26-May-2010 |
Shih-wei Liao <sliao@google.com> |
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5157ceb81fb9497b7dff69b2474bd5e4254fef88 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 4fda9670f0a9cd448d1905ab669421316b8864c5 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 47626de5233ae809b67cab19679c49874d0f2804 |
25-May-2010 |
Zonr Chang <zonr.xchg@gmail.com> |
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| f3c770a2cb39e3293992f017c23539f293286bcc |
25-May-2010 |
Zonr Chang <zonr.xchg@gmail.com> |
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5d392dd93e023f9c14353ea84e2db717792db4bd |
25-May-2010 |
Zonr Chang <zonr.xchg@gmail.com> |
Add support to MOVimm32 using movt/movw for ARM JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMRelocations.h
|
| f86399be0c2cd095ebaa80dcc0180dab45ec263c |
25-May-2010 |
Zonr Chang <zonr.xchg@gmail.com> |
Add support to MOVimm32 using movt/movw for ARM JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMRelocations.h
|
| 1b468abc07f76ea922eea6a7b9a5467c96e50ada |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a85df80ed7ff55595ab7982dd1c0543a8dc56efe |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b86e6e746cb737a404ff899174a9e6aac8850e2e |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4876bdb69e3d857df0647b0e16883f55bebafd9f |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7c56214077521f8bd8b820684dcc3263e81d6fea |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ab3912e3ce5a58a6dbdc2780ae489162faa5452d |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6ce14ee8be65cdbcbaca5e235c3eb28e5ec59170 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use enums instead of literals in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| e00fa64c16f40230d76417be8f09166b7c84c52d |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use enums instead of literals in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 9a8a51545c3e8eeeda47a53e5ba70a79ddd3deaf |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 33276d95ef4191663d8e6b972481f9faf37ce541 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 5ef47c6fc440a8894864248d7583fce03e9967b1 |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c21763fd993f37d02c7a495e96c3e8eb4c0b4015 |
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 43e1f8e1e35a248ba631a1006f68297d8049d109 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Lose the dummies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| f27462eb29667d2327116caec5c2d57653888a0a |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Lose the dummies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 2aadda9d09368ccc1a44b795896f74df647752f8 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 09bc0298650c76db1a06e20ca84c1dcb34071600 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 644f902eacb2c9ac0fd99ebd5e93e298e0aa68d8 |
24-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some extra whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| d303846e162e18e0f1fb02d3826dc4d38244f86a |
24-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some extra whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 1c72147872643779249632583f5abbcc47bdc2c5 |
24-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| bb7ecb2bf514e48b3c37afdc43afc8a8fe3a5011 |
24-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d66243ff34982809bffcf5bb533044f8c64c9ad9 |
24-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
LR is in GPR, not tGPR even in Thumb1 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c7cf10c97ef08dc3dbe917e16908cc9bd3d888e6 |
24-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
LR is in GPR, not tGPR even in Thumb1 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b3a1b9d01cf5eddca16cf2d073070494dbbdbe2f |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a few places that depended on the numeric value of subreg indices.
Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 7bb31e3187c0ba5a076313e5fe9dd869500a6ecf |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a few places that depended on the numeric value of subreg indices.
Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 204c1852a25a6329334caa8ebc0041ef3cbb57d0 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONPreAllocPass.cpp
|
| 558661d2718cf5750907c449d36ff1231924a2d1 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONPreAllocPass.cpp
|
| 74f5e7708bda2936249a57105303b589e4b11827 |
23-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
VDUP doesn't support vectors with 64-bit elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 069e4348685e5e7a472787fc9950a081633bf928 |
23-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
VDUP doesn't support vectors with 64-bit elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 32d1bb9fe7eadcd5088e8048cfd952fc6178604e |
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMISelLowering.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelLowering.cpp
RMISelLowering.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 237b7dd26af11c4e0e8d1acc829cf12bfb50cd1a |
22-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
|
| 5eb195153950bc7ebfc30649494a78b2096b5ef8 |
22-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
|
| 5ca56682f87008da5585a5c27c967e43de279d1d |
22-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| be751cfe9cbcc760e24599a59e5b9699d4d4f9e0 |
22-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f35de8139bfbacae63ae994e461eb7af3c413b10 |
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f7d87ee1584bffe361b39f8cec7a39131c8c4efc |
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5373b294648bf0285621a82281f136578ba70082 |
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 1cc3984148be113c6e5e470f23c9ddbd37679c5f |
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| cd182e19d1886d837407e6811187db30e88aa118 |
20-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 63b8845e786d1204d41952da938518baa3159a97 |
20-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a9d350eb0820423726b445a8b31dfe8b9830f6f3 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 211ffa13519cadfb7f9baf4c8447fa055bf38fe8 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b90ee5d04e44f07f296034e2af58da76d8435e32 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 9085f98b32775aa0190eac221a58350d837ae2c3 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 6744835a83389560a92234d8adc120942eec9999 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 27fa722311f98f3ba55173aebf9bbd8b5acbc1e1 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b8e418ae381cfdd209d75671d21609110fd8da3a |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 5fd1c9be2d6ade68a8cf7b38041ebf79624d315c |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 28006e3787efd57ed3e2b671f1b352881a3a2fc8 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Target instruction selection should copy memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3c3195cbf19030ae3b1c854f3a3cd5fcef520e07 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Target instruction selection should copy memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 05efb04e4d6e6a02ed652ad4667af7c7e9bfeec6 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| ea420b20d4e75af21cfcc1b380a7536c239fb99d |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| e0dbb624960f848bac8e74be2e78cacaaaff5357 |
18-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 28dad2a5caccf579f7430acd3af8fa6e6f8b575e |
18-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 01a9e0f3b686c9ba2aa4d48021e1afeb1ec22419 |
18-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 535af4a320ba169342c87433841dc64fbdcd72b3 |
18-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 84d010929a14d8b4fee5dff78468aa1bc163282c |
17-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
vmov of immediates are trivially re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103982 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 47006be498e256cc8c356a2325c918b825ab2ab7 |
17-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
vmov of immediates are trivially re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103982 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 96a67704edb141ad41fd4609eb49365d401a2cd8 |
17-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
Obvious in retrospect but not fun to debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7f43fd84db4dcb5b948b92ab4a92327c22093556 |
17-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
Obvious in retrospect but not fun to debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 6aa42b0256b14858bf869dcf3d99fed4f2c690ee |
17-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 620612425082ab5d6c6016ae59f8ae9afc6c5776 |
17-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 29afe434bc80b290bced2dbb1bfdca8792f49923 |
17-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
EONMoveFix.cpp
|
| 9c207ac0dc3b2f6af9eac52de488d568a4f96291 |
17-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
EONMoveFix.cpp
|
| 5636a6e84251a36ec051353eb5f1c7c387ce6692 |
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
|
| bd91ea53f823fe71c0b67b9a4552984a8b361820 |
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 45141181198840d6a4df48db6c338a5042692fcb |
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4878b8415fd524489b4bee5f90e969f6ccb253d4 |
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d477a099287ec13a80a64a359a15c9057c12e400 |
16-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model vst lane instructions with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 8f6de385d64922b6d42b91a4d63f862b33ca13e8 |
16-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model vst lane instructions with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c579fc616a92f70dd5b238a9c55bda58618b606a |
15-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a9790d739a7970dd516c57f56d67cf9aa01b9d39 |
15-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4c777120443be13cfab727aacc636e2e7d83b14b |
15-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
"trap" pseudo-op turned out to be apple-local.
Temporary emit it as raw bytes until it will be added to binutils as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 418d1d954daf87965757f5aa5bf8d546d3e40a82 |
15-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
"trap" pseudo-op turned out to be apple-local.
Temporary emit it as raw bytes until it will be added to binutils as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| d5f7e4a4ab736e620110bd58ba859d096ec07f7c |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model 128-bit vld lane with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7189fd03fa66642b58b1e88be385bedeff0ac91d |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model 128-bit vld lane with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4e18478b4beb9e5aa81bb383041d1ec69400e66c |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
v4i64 and v8i64 are only synthesizable when NEON is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4782b1e2caf0030eab1112c12dd4a2ffca688ecd |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
v4i64 and v8i64 are only synthesizable when NEON is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 968b906bd404b338d0f2cfbc817c56fef170e378 |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 06b666c7056376b8aaf40be0dc00b97b2cfceb6c |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 26e7e48dfc4e565cb30c7637ad7cf007ffbc482d |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model 64-bit lane vld with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7092c2bfcb91c367b091e037f0568e249e1b0a57 |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model 64-bit lane vld with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 37f5064fd0e6e9524efc05736649b20d5ba0ec66 |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMRegisterInfo.h
RMRegisterInfo.td
EONPreAllocPass.cpp
|
| b990a2f249196ad3e0cc451d40a45fc2f9278eaf |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMRegisterInfo.h
RMRegisterInfo.td
EONPreAllocPass.cpp
|
| ea089df6e30fb71bcff5403e86ea8bc17f11de0b |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 12c24690c7dc53cf6e6ca8cb062255e82d568edf |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b6d3f2514f08b9451a7b7fb8599c87aba6f0cb7f |
14-May-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b92187a4103dca24c3767c380f63593d1f6161a7 |
14-May-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 40f4ccc80abe01e5b5af3c7a8e278f3429bc6e3b |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
EONPreAllocPass.cpp
|
| 5c6aba2e3ac2239a3de85a77f09cdac9eef68467 |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
EONPreAllocPass.cpp
|
| ee9f5c0a63197e6e3148f09b401f0056cdf1a179 |
14-May-2010 |
Shih-wei Liao <sliao@google.com> |
3 fixes:
1. ubfx (lsb, width and src)
2. vbfx
3. vstm (If Si, NumRegs shouldn't be doubled. If Di, NumRegs *= 2)
Change-Id: Ib5d8f5498f069f597c7af8d2cf1a293d15ddf484
RMCodeEmitter.cpp
|
| 79599dec649aa4fbe90481ab26828f9b5575cacc |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| 22c687b6421d9cc03351ddb0c7fd3d45382bc01a |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| db929f9a1234155ce719299e3ede36a5c05b33bc |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7f687195175f01d820eea70e8a647a61d5b99fce |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1feebb5df60f176a6338d45bef7cdf8b55aa2298 |
14-May-2010 |
Shih-wei Liao <sliao@google.com> |
Add "*2" to vstmia
Change-Id: I95e6eda70555757ca9378d508d0470b5ef0f64b2
RMCodeEmitter.cpp
|
| 520a99752caa9708012ada768303a20591716370 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| c4ca40eb5e632c5700fecc12ca02064429b842b0 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 86d13bed2afb33efa5b9d005e6601784fdffd6cb |
13-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
Do not use those for Thumb1 functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 1190c14b547a1e275e80e43a6ad52178312adbd7 |
13-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
Do not use those for Thumb1 functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f034392cf27727b6f43a5e6e9a35a4090c475660 |
13-May-2010 |
Shih-wei Liao <sliao@google.com> |
Fix vstmia instruction selection/emission problem.
Change-Id: I34137e9a3490fe8859201f727cce6df81ad93173
RMCodeEmitter.cpp
|
| 22ef75746a5a2c499e2da158b62069690aac213f |
13-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 1860e7dcfd98fb4b73c0933573195562978137ef |
13-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| b4593017814e15378b13fb0a693d1fa6a4d0a6c3 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 69b9f9883e10efa266d59a5dd2f4d99de92c6707 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 40562ccfe5586bee876bf26a9b931d0ff337392c |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Expand VMOVQQ into a pair of VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| d929f7773812535271ae6969331f8164c1f7f3b2 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Expand VMOVQQ into a pair of VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| d8e697a06cc6b72c55ad95149abedf8d4713188d |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark some pattern-less instructions as neverHasSideEffects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| 020cc1b4d0551a95b1f46046e4fb7cbd11a8678f |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark some pattern-less instructions as neverHasSideEffects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| b2e4a3f124cdf52c43e918f35e90d2d83ddcc2f7 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 431300797b84600fc9b4eb8ca283277d3e0674eb |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 57d4b224657e81a7a99ed1d4d89b216a533142ad |
12-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a dead fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| a4d73d01c4850dce6a951228b13dcd8e733704b4 |
12-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a dead fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
RMExpandPseudoInsts.cpp
|
| 5fc3053c3a78d6fd90c85c50efa5a28b82c81d5c |
12-May-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for movi32 of global values to the new (MC) asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 18c1021ec108722506125926087b1e5fcfb28046 |
12-May-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for movi32 of global values to the new (MC) asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 43a693338d58381ae977086aedc3cb4f1b1d4f4d |
12-May-2010 |
Shih-wei Liao <sliao@google.com> |
Implement bit field clear/insert. Constant pool fixes
Change-Id: Ie14c0679db2d8fa3a9a6a24d5217c5d9c4e7fd35
RMCodeEmitter.cpp
|
| 36e9f2eff323d79426a87fec5fcaaa771b920250 |
12-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
vst instructions are modeled as this:
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
= VSTxx <addr>, v1025, v1026
The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
= VSTxx <addr>, v1024:5, v1024:6
The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.
As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.
Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 5bdc2aa264b38a4632cf1e4fef1f328b464147a5 |
12-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
vst instructions are modeled as this:
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
= VSTxx <addr>, v1025, v1026
The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
= VSTxx <addr>, v1024:5, v1024:6
The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.
As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.
Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 057000a0279da7b4d63dc02daed2ea4066518dd8 |
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid breaking vstd when reg_sequence is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 9647f3d98159ead48e8e4a2e2c19cde4beb25300 |
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid breaking vstd when reg_sequence is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 87177829e96ec9552c8a426fffd40a3090e515e5 |
11-May-2010 |
Duncan Sands <baldrick@free.fr> |
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.h
|
| 16d8f8bd919b72866e687d99f3aa94a140137c59 |
11-May-2010 |
Duncan Sands <baldrick@free.fr> |
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.h
|
| cfbb32346a7eca19d4dc00fd2c1a0248537b3497 |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| ff7a562751604a9fe13efc75bd59622244b54d35 |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| a39553c3cf2066ec0854fb7c908707695422ce6b |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Remove the TargetLowering::getSubtarget() virtual function, which
was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 419e4f92635cfaa409282691437aff99062e4e0b |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Remove the TargetLowering::getSubtarget() virtual function, which
was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| eae570ed4a2f43ae796772f3b197a8d8311b6918 |
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| fb3611daad2bdf9fd50fe5ef1167fe6a8c950031 |
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| f49da1d2f3e3fff59348bdce0bf17ddcbe3286a2 |
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model some vst3 and vst4 with reg_sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
EONPreAllocPass.cpp
|
| 0ce537a9db2da085ab50b15d2454cb7cac460eb7 |
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model some vst3 and vst4 with reg_sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
EONPreAllocPass.cpp
|
| d98cffb9c2137a94d93966077b39922ff883c97e |
10-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model some vld3 instructions with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
EONPreAllocPass.cpp
|
| e9e2ba05de573f926f1d054add7ddbf15eab178a |
10-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model some vld3 instructions with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
EONPreAllocPass.cpp
|
| a92b2f3024fb3ce131097bbd3704965dc1fbdd6d |
10-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model vld2 / vst2 with reg_sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
EONPreAllocPass.cpp
|
| 603afbfe2ac8ccc21283b149a76a81eb44b956b0 |
10-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model vld2 / vst2 with reg_sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
EONPreAllocPass.cpp
|
| 501b22f305e2fed4379c5d1e9c52194a780fbe4c |
07-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4b77f6a85a206f4a4cd23f8cdf710f2574a5ac42 |
07-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 79ccdd7de9deecafa8a5664ac1b588b90c85246d |
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 435d4991779d6a47cadff4ea670b490d8507d6c4 |
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| aef3d93b3a69284b1ac517e72fcc8b1b11e6653a |
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 07a6d9391c74117ae79f832fd840deacab737b40 |
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b64842b529f761402ff08a19c23393123796d6fe |
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cb |
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 75a44ec07c056f9bcf17368b6643810ecfbe1264 |
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
EONPreAllocPass.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
EONPreAllocPass.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 1f8534d080a425fa232552decf8012a4d6a95419 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| da33451615121df126298b41f4ca17f020090e2e |
06-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a missing break statement to fix unintentional fall-through
(replacing the previous patch for the same issue).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 429009b0f1bef035b8ad1705edb7f1741ddaa427 |
06-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a missing break statement to fix unintentional fall-through
(replacing the previous patch for the same issue).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 82e8f76bc0c1fa402eddf85a25d2533e32376474 |
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d31f00b7f78aff0aaec8322a1a9eccca915b88f4 |
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| fed180e491e87d1b03fd59d9ed3593b90a2baa8b |
06-May-2010 |
Shantonu Sen <ssen@apple.com> |
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| eae216c6d3d29cb9024ddf436a8f2ce222bb9ec8 |
06-May-2010 |
Shantonu Sen <ssen@apple.com> |
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| c867f7384908fb8ec50a8c18c99adcbed4558832 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| b63387afc6b10e88631d1ef232c41ab6c18c8581 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| 54bbf7f44096c0eb2d4b3e759aafe2f4d3e112b7 |
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1ef7c821287cd7734efb148aa3044de3e3e377a7 |
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1613cdd2db71509fbb3319dccd737eadfe3575a1 |
06-May-2010 |
Eric Christopher <echristo@apple.com> |
Revert r103156 since it was breaking the build bots.
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| f865cb5c1f00d5655d981503ed5761b2836fa5a8 |
06-May-2010 |
Eric Christopher <echristo@apple.com> |
Revert r103156 since it was breaking the build bots.
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| af2b353d72cbc2e88ba890526a3c442b2f65efb5 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 9c35ee2099108c43a02aa1f836c3cbf5a0cd6035 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cfde9059e55ea305d6c35ec064f8a382e8b5f99f |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| 4ffc22ae000f207d3c660ebc197d31940025fbfa |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMInstrNEON.td
RMRegisterInfo.h
RMRegisterInfo.td
|
| 2b7b252f31eaef05a706838834cbe01f37873a6e |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d31c5496d7e1580058b5c6fbc8fd537a641ea590 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cb54cf567e234155527605cebb57e6f1a9fe9529 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
storeRegToStackSlot has forgotten about QPR_8 register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7f2f436267cc9684e11878500e017babd1779db0 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
storeRegToStackSlot has forgotten about QPR_8 register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| da0cbe492f73481059759fe92dc79cd7161d664d |
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| 29402132f3e890a2771818f44987ede213297431 |
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| 3cdb17880f02f737348e1d3c6a3782433219ce42 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 676b2dfd2719e03bda4d1d99de67be2a9bdfb124 |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 744b14e0d606e803d484f2c0eb12ff1f1a0fe171 |
05-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| b1dc393bd56365ad8fabb51f22c2f3ace707c39a |
05-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| ad2a1cc8f2c5bb7eda7a5f1cb83d393aa42b45e2 |
05-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| de8aa4ed9c8d3654e08eda3973e0500ddc7ac0fd |
05-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| c96397aefb689bfe7be2262bb7061cdea42628b9 |
04-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 94cc6d3a2b0a424527edcddd1875ed649e8b84f0 |
04-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 33fcfb4abad8cad560ef9de88ad23d8b6addd1fa |
04-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not pre-allocate for registers which form a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 826bdfa603c81d9166fcc6b169585b07f670ae88 |
04-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not pre-allocate for registers which form a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 13a08813d456d9536da574ee549b61b98a36d39f |
04-May-2010 |
Shih-wei Liao <sliao@google.com> |
Added VFP support: Machine code emission of opcodes: ARM::VMRS, ARM::VMSR, ARM::FCONSTD and ARM::FCONSTS
Change-Id: I59050468dabf2bcfbb73604ee31abe588a28c670
RMCodeEmitter.cpp
|
| 452d952c5ca697114235f88dd4ea9f0e83354ac8 |
04-May-2010 |
Jim Grosbach <grosbach@apple.com> |
rdar://7937137 - dbg values not being handled in thumb1 version of
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 6e62b4ef14bf96e84962171dd3f115a7f8c6dc49 |
04-May-2010 |
Jim Grosbach <grosbach@apple.com> |
rdar://7937137 - dbg values not being handled in thumb1 version of
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| ed4dac7caf11058c1a988db9f7102187bd1cc9eb |
02-May-2010 |
Shih-wei Liao <sliao@google.com> |
1. Fix movw. 2. Change to vfp3.
Change-Id: If494e6c62e1d276b78c3d4d4fec5dea3ec7f0816
RMCodeEmitter.cpp
|
| e9198cc2d055953ec847dbcaf55f92dd32b434cc |
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| a59a85f8dd03d52907019f1a4caaf7653b01b7d3 |
29-Apr-2010 |
Shih-wei Liao <sliao@google.com> |
For disassembler
Change-Id: I14e64ec4640cbeb57ac87473775e8ba8a7320b3f
smParser/Android.mk
smPrinter/Android.mk
isassembler/ARMDisassembler.cpp
isassembler/Android.mk
|
| f9c420a62a8bce383b4bb988ff468e36162e8dc9 |
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 2dc4fd904bd7c20984771453e6ab0a4cc3c274c7 |
28-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
rdar://7895451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d100755bab38784703f677b8b8eb174b624b346b |
28-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
rdar://7895451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7abe37e4aee38cc79d91dd069a37d7e91d5bef53 |
28-Apr-2010 |
Shih-wei Liao <sliao@google.com> |
Sync upstream to r102410.
Re-turn on sdk.
Change-Id: I91a890863989a67243b4d2dfd1ae09b843ebaeaf
RM.td
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMMCAsmInfo.cpp
RMMachineFunctionInfo.h
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
RMScheduleV7.td
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
RMTargetObjectFile.cpp
RMTargetObjectFile.h
ndroid.mk
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
smParser/CMakeLists.txt
smParser/Makefile
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
smPrinter/ARMMCInstLower.cpp
smPrinter/Makefile
MakeLists.txt
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.h
akefile
EONPreAllocPass.cpp
EADME.txt
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 24bfa21232573864633b9ac159822a2583730c80 |
27-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle register-to-register copies within the tGPR class.
Radar 7896289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 5dfa87ecc6a8b94096869ca0558c5437006d13b3 |
27-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle register-to-register copies within the tGPR class.
Radar 7896289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 2ecdd06162e06fd6f3bd92794627988a1ef0d465 |
26-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Handle target-specific form of DBG_VALUE in AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3f282aa94b80f4a93ff3cbc37cf3cd4a851c8432 |
26-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Handle target-specific form of DBG_VALUE in AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 359ebdab2682b1eb35c7c36c929cf60af0bfcbe5 |
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM specific emitFrameIndexDebugValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
|
| 62b50656ceb854eb0be265d63b2a1d46e7400d8a |
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM specific emitFrameIndexDebugValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
|
| 5ec7e6b764a28eaf2d952eaf831a3d362f0100e4 |
23-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
extraction. This fixes PR5998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3a1287b470bde29d10e7c6998fb69b74d2265b6c |
23-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
extraction. This fixes PR5998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 044ac58243f2978911cc7f6e910e524db161ca93 |
21-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified some assert() msg strings; no other functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| c048f1d12c129e79c72eb58dea0ec64a23ce9824 |
21-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified some assert() msg strings; no other functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 8898906b56e8cd9ef4cbe04e36f8e9467bd59692 |
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e566763b1915c7a4821ce95937b763724d271fec |
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a06f927cf67607bbe8e48ff587c9574b7842d3da |
21-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Thumb instructions which have reglist operands at the end and predicate operands
before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/ThumbDisassemblerCore.h
|
| 52d2b0ed00d71c8ba0ff1a0b35cad4ffebc81dd5 |
21-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Thumb instructions which have reglist operands at the end and predicate operands
before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/ThumbDisassemblerCore.h
|
| aa811f058026c45a5235df8eb7bcdaa95a512d5a |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| d6b5d72c0fdd0c4717ee6c5357081ad67ca9f350 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| e4276e4a363743280203dabaf35555b4bfb0d287 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| ef37e3abb7fdcdb773163e4e48743b2f7b2141b3 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| deadd54dc48f7ffd890e44b27b0a883afb26f317 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
d==15 is considered illegal. Return false instead of assert().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 3974ade503c14fb7c7db32e0032b77b5c55e6ea4 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
d==15 is considered illegal. Return false instead of assert().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| c42f7a52028574f09556465caecad7c7517553ac |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
More IT instruction error-handling improvements from fuzzing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 6bcf52f00a4fc352e90ff11681a0e69f9757eb37 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
More IT instruction error-handling improvements from fuzzing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 55dcf1347645bfb9ba46fd3cadb1da3a013ae6b5 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error handling of invalid IT mask '0000', instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
|
| d0f3c46d166b5d0ab4573987011cab7bd1ec28e0 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error handling of invalid IT mask '0000', instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
|
| b0573281ad2b6d815f6dd2e7048afa50f5863dd6 |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 22e401f5d4d863e753bc8e5655bac481602d22e6 |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 067388a6d23c4f7a823a407b2545ec8ba23ed29c |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand
instructions should have Rd (Inst{11-8}) != 0b1111.
Ref: A6.3 32-bit Thumb instruction encoding
A6.3.11 Data-processing (shifted register)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| d6cc53cfe4ac1978e591d14867b39744463356c0 |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand
instructions should have Rd (Inst{11-8}) != 0b1111.
Ref: A6.3 32-bit Thumb instruction encoding
A6.3.11 Data-processing (shifted register)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| a10c42a292cd56982ff3013f61a8a5772b9f1d96 |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler did not react to recent changes to the NEON instruction table.
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 4b7df442a8a3cc5eacd2a7bb93ef09b3d3bbe63b |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler did not react to recent changes to the NEON instruction table.
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0054007bf3a7fcafa9598ee725854aefd944041c |
18-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 928eb49cae286c95dceecf4442997dd561c6e3b7 |
18-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV6.td
|
| 2491664d4979d33da2b90fc471cab2287c863e59 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix -Wcast-qual warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 3fb150a9024a38872ec4abbc3300e08a8bfc1812 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix -Wcast-qual warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 443093da0797ffc3b48ef30121243d1a700e63df |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to TargetLoweringObjectFile usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0d805c33d134d88169e3dc4a3272cff9a5713ce7 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to TargetLoweringObjectFile usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| dbb121b1f19bf77e0bef8725d5ee42c1b8761caf |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMTargetMachine.h
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMTargetMachine.h
|
| d80404c4e94e4252c0cb306b3e3fd7ba4dc2535d |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMMachineFunctionInfo.h
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMMachineFunctionInfo.h
|
| f96d8e143dd936173abd66e2061bc06341ffa30a |
17-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9f3f061d74e19543be61e797127c54546668600c |
17-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2cce14d305a9987e2d5d4097f4e7cc7eefc9d68a |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Cast to (uint64_t) instead of relying on the "ul" suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| de0ade493900c0e5c9ebe1f795699b5a9d9f360b |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Cast to (uint64_t) instead of relying on the "ul" suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 8b8dc1cdcf5f34b66c3f929186168102f3149cb1 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add skeleton target-specific SelectionDAGInfo files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
MakeLists.txt
|
| 53c5e42ab9c1a2cce7ad19bb0b4dffe33c9473e6 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add skeleton target-specific SelectionDAGInfo files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
RMSelectionDAGInfo.cpp
RMSelectionDAGInfo.h
MakeLists.txt
|
| 01d31cff930935cd8c8a16ccc1e4315bed5e4f17 |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed logic error. Should check Builder for validity before calling SetSession
on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101563 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| af5b0e851e42d7de1247c4084ba75a76c4497ca6 |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed logic error. Should check Builder for validity before calling SetSession
on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101563 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 6b5e2261f03cd10090e15e29f0cb527298da111f |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassemblerCore.cpp
|
| c7b65914e080b5236078e5f58ded5503226bcb71 |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassemblerCore.cpp
|
| 05af8f4b58d7f69cbbca8334ce41ced530dbe79b |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 16fda6982b8fa366db2632d3b1775d71f1fd4eaa |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| a4a41a75b4c4736d57964a8004eed1e35c026494 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2fb10f17d8e4fc2142e97f4efe653a75177d2363 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| eeff57418ec59658e07e967c7733cf67070caf1a |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" are
considered legal instructions.
Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| d73d187e335c251892eab74fe436ddd701865287 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" are
considered legal instructions.
Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 269b7aa0ccb5565cad0aa3fcd8117b4571bee47f |
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use getAL() rather than a major constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101446 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 47b7b9f228435a7b570ab6fc9f3a9c44ff301ef2 |
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use getAL() rather than a major constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101446 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 884b7e540566b617a0a273494c663a85cdf46028 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
am2offset. Modified the instruction table entry and added a new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1cfa094562457aa0c36818b93b481e4ff454ec92 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
am2offset. Modified the instruction table entry and added a new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 433194a604682fd84a49bc9305cbbd472e31d04e |
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 3a1588a2e38d57de3c4277f071f2316fb3dbc37a |
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| a9b8c2c72967325277821e4a3063eaad68e7b8b6 |
15-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
llvm is generating poor code for dynamic alloca, I'll fix that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 0ea7d219ec5bb45a0b3e96c01070cfc21227291d |
15-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
llvm is generating poor code for dynamic alloca, I'll fix that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a0fd4144c0c1b7860c2c6548e5be4271c77f95dc |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
DEBUG() print out "Unknown format" msg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101382 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| c8866980fe551352a7f9180248f1faa198ddae4e |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
DEBUG() print out "Unknown format" msg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101382 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 0d2e5f562a18139ac0b326c06f6d1ce397e72086 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
ReuseFrameIndexVals is used in multiple files, so it can't be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 8c407d45964fbba19719be555324f247e4fb14e1 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
ReuseFrameIndexVals is used in multiple files, so it can't be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 738422fa501a08e58d1d55ebebdf0ca499059d72 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b35798347ea87b8b6d36155b211016a7769f01ab |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 1eb7a9cc529c07b6dba2a2c205ef3a9b055e1b15 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers for LLVM IR pointers in CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ae541aad5c36cb3e4256514447d1f81e253079c7 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers for LLVM IR pointers in CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| dbb6d1773175fd4945e1127745f66210021b7df3 |
15-Apr-2010 |
Anders Carlsson <andersca@mac.com> |
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101335 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0dbdca5a8594cbc2961faa37e3eadcd6e265fa90 |
15-Apr-2010 |
Anders Carlsson <andersca@mac.com> |
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101335 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 36c56d0353f1a9c4e878f509aff85a62e5087dd4 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMExpandPseudoInsts.cpp
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| f6e1b42c4a0fe4eb7c2784f32cc6822d865ee8f3 |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101329 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 44398693e767f10c1c7edea3578796f12e05af6e |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101329 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| bf3f0fab0ae55b42dc713122d73f14be38120cd6 |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()
function checks whether we have a valid submode for VLDM/VSTM (must be either
"ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101306 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| d1ec11a850843bd7afff1c939b29c9d18527e966 |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()
function checks whether we have a valid submode for VLDM/VSTM (must be either
"ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101306 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 6b39c65f2d4b0097abe957c924b4196449672fae |
15-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Add -arm-long-calls option to force calls to be indirect. This makes the
kernel linker happier when dealing with kexts.
Radar 7805069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101303 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e7b52526d386cd0d3a08b8daa7db67839649bb37 |
15-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Add -arm-long-calls option to force calls to be indirect. This makes the
kernel linker happier when dealing with kexts.
Radar 7805069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101303 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4327798ba572584e7a305335d8babd652f15ebb9 |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
For t2BFI disassembly, apply the same error checking as in r101205.
Change the error msg to read "Encoding error: msb < lsb".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101293 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 2fd100a4cb6c7c013f9bf78fc06b655515b0851c |
15-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
For t2BFI disassembly, apply the same error checking as in r101205.
Change the error msg to read "Encoding error: msb < lsb".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101293 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ThumbDisassemblerCore.h
|
| 882f9f8e14ddb741de2506ef37f22a0b48048400 |
14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.
Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101290 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/ThumbDisassemblerCore.h
|
| d907d2566af966333cf170fae27b3e7847a855a4 |
14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.
Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101290 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/ThumbDisassemblerCore.h
|
| b54145ebf6100d3c5880716d829aacd026fac7f6 |
14-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type. The legalizer does not know how to handle those
nodes. Radar 7854640.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 164cd8b8d305f93a1520fc1354d896acd1d002f4 |
14-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type. The legalizer does not know how to handle those
nodes. Radar 7854640.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9646fe1b20d9265f931b2b20919ebf93683f236a |
14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. Now, when an encoding error occurs
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler
just returns false, instead of assert, to indicate disassembly error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101205 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 6f72ab345de0711aaa5509fd6de38f4eb0ed4070 |
14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. Now, when an encoding error occurs
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler
just returns false, instead of assert, to indicate disassembly error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101205 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| d75e3c7e0b326481fa6c1eaa16a92217678213cd |
14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalid
instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder
instance and the client just returns false to indicate disassembly error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101201 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| efcdac0c41e7f14e81f79762423f30d892792261 |
14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalid
instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder
instance and the client just returns false to indicate disassembly error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101201 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 38df1ce442a5e391ee959999ff7dabdd2e65b97b |
14-Apr-2010 |
Douglas Gregor <doug.gregor@gmail.com> |
Unbreak CMake build by improving the EnhancedDisassembly makefile a
bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101188 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 533ae9b71d88df8d1891c8c653eeb7912b25dbb0 |
14-Apr-2010 |
Douglas Gregor <dgregor@apple.com> |
Unbreak CMake build by improving the EnhancedDisassembly makefile a
bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101188 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 1650fabdd10e3987f6d079e2693d9741267076fc |
14-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle a v2f64 formal parameter that is split between registers and memory
such that the entire second half is in memory. Radar 7855014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6a234f07faf164e62f0799fa87f5742528cc043a |
14-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle a v2f64 formal parameter that is split between registers and memory
such that the entire second half is in memory. Radar 7855014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| eed7cb6cac7dab33af13858e6697d68caab8778f |
13-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a nasty layering violation in the edis source
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
|
| 9899f70a7406d632c82849978bf6981f1ee4ccb5 |
13-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a nasty layering violation in the edis source
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
|
| 831311a36ea23627501023f84918a9d20f67a4a1 |
13-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Changed getSOImmValRotate()'s hunt retry logic to ignore the low order 6 bits,
instead of 7, because we are only looking for even rotate amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101172 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 8a87ffb9252d6d66093dcd96f3b9a496dae4a439 |
13-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Changed getSOImmValRotate()'s hunt retry logic to ignore the low order 6 bits,
instead of 7, because we are only looking for even rotate amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101172 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 2fcbd242b761e0fc22266baec227e210861aab55 |
13-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use MachineBasicBlock::isLiveIn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101144 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| c5e43c958e4a599aef0162cd71f864712b740ab5 |
13-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use MachineBasicBlock::isLiveIn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101144 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 2e34623aa9ecf0590bcd2becd71fd1be93f6f98c |
13-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace r101053 with a fix for getSOImmValRotate() so that it will correctly
recognize all the valid rotated immediates. This fixes the disassembler
issue and will also help codegen for some unusual constant values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101114 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMInstPrinter.cpp
|
| b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8 |
13-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace r101053 with a fix for getSOImmValRotate() so that it will correctly
recognize all the valid rotated immediates. This fixes the disassembler
issue and will also help codegen for some unusual constant values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101114 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMInstPrinter.cpp
|
| 67426ece69205097d45ec5d5a268c115dfafc248 |
12-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMInstPrinter.cpp
|
| bb6e9d8cf7c5a51b2f66568accc489927f0d538e |
12-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMInstPrinter.cpp
|
| 7adb1cf7f970835890b89cdf82dd9951680eb692 |
09-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| ec80e2693ad01262592096d061861e7f1755482e |
09-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| cfe06853d4488b6781a85f36ec2dfb1ecdbc056a |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
delete a forwarding function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100815 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
|
| 287df1bc0309962770b6c176f2d143795dd3cc2f |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
delete a forwarding function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100815 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.cpp
|
| 088d71c31dd9c483998972e3a75fa279a06a6e38 |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove the TargetLoweringObjectFileMachO::getMachoSection
api and update clients to use MCContext instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100808 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 22772214de79aa1c5ca38c4fb1da137d8fb30a05 |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove the TargetLoweringObjectFileMachO::getMachoSection
api and update clients to use MCContext instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100808 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7f42f72a50cf6b5e108f10c94e0c2e529a50497b |
08-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 8f993b8c244bb5ec19d004a070eb9f32c5a29b1a |
08-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 87b9ecfac22af47b7c99193496de6aa0150b788a |
08-Apr-2010 |
Ted Kremenek <kremenek@apple.com> |
Update CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100714 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
|
| 28e830d25f035508c61fd376fa07e390e0bec54b |
08-Apr-2010 |
Ted Kremenek <kremenek@apple.com> |
Update CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100714 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
|
| 8316f2d3810dd37bae0f847bc3efd495432b5893 |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 75361b69f3f327842b9dad69fa7f28ae3b688412 |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 205e4273cf8515ffcd0d5c0d26bd153b65280a7d |
08-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Missed this one line for the previous checkin to fix build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100697 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| b72e59e3615c4f8a8ac272629511814000cde5e0 |
08-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Missed this one line for the previous checkin to fix build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100697 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| 60eb15cb9cb57919bb9a2f1f19d26b26224e8955 |
08-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed warnings pointed out by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100696 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| efd518e1fde69316ae3d860703848f329bd87262 |
08-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed warnings pointed out by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100696 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| d834e29cbb84e0fe5b55e4fb510796231b40e26c |
07-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed warnings pointed out by clang.
Next to work on is ARMDisassemblerCore.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100695 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| 7e4823c51f40d810483a424836710ec6703c204f |
07-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed warnings pointed out by clang.
Next to work on is ARMDisassemblerCore.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100695 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ThumbDisassemblerCore.h
|
| c195a8be9ccb3ecb7ffddaad05511d23329a3bc5 |
07-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed 3 warnings pointed out by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100693 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| c22e2fcf72780b4b66a4262c12208c2d5af2e213 |
07-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed 3 warnings pointed out by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100693 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| d47ae912b9575fa3315d4fc3329b3ea754162a60 |
07-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Makefile
akefile
|
| 3c500e6947ed8db719d87d47572de86e107ec094 |
07-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Makefile
akefile
|
| f3d16ef599d08f6093806e36cc3b88222efb924a |
07-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added an AsmLexer for the ARM target, which uses
a simple mapping of register names to IDs to
identify register tokens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
|
| 90b7097f92f6b4f6b27cd88c7c88a21b777f5795 |
07-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added an AsmLexer for the ARM target, which uses
a simple mapping of register names to IDs to
identify register tokens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmLexer.cpp
smParser/ARMAsmParser.cpp
|
| ac54897bffc47cf30c23cd6432baf3ec764fb88d |
07-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 375be7730a6f3dee7a6dc319ee6c355a11ac99ad |
07-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| e4454320b3cfffe926a487c33fbeb454366de2f8 |
07-Apr-2010 |
Shih-wei Liao <sliao@google.com> |
libbcc
Change-Id: Ieaa3ebd5a38f370752495549f8870b534eeedfc5
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMRelocations.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetObjectFile.h
ndroid.mk
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
EADME.txt
argetInfo/Android.mk
humb1RegisterInfo.cpp
|
| a7a3476e84d08173b6bead2105e07675bc643cb2 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove late ARM codegen optimization pass committed by accident.
It is not ready for public yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMGlobalMerge.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 4b38debf597a22e2db02aafdaa40264d7770c1ad |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove late ARM codegen optimization pass committed by accident.
It is not ready for public yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMGlobalMerge.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| f6b0480857f2e43b7be9f72fdd059f6adbd1a3e0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Split A8/A9 itins - they already were too big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV7.td
|
| e1676011c615e81522278ad09ebb3d57e5e6bb94 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Split A8/A9 itins - they already were too big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleA8.td
RMScheduleA9.td
RMScheduleV7.td
|
| 88797e58d2e6b68cb92ae5d21f2f4966642bbeab |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some crude itin approximation for VFP load / stores on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 895867326ed541a1ada12f45ab8daf72aa2ad3d0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some crude itin approximation for VFP load / stores on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| dd21ccf7216e65b46274cdc857d12310846c05c6 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some crude approximation for neon load/store instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 67867135ec71263295a00db983784ed63e3426c7 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some crude approximation for neon load/store instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| dd71847dd4db1aae097333b3572880b7e57a04da |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some A8-based approximation for instructions with unknown cycle times
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100669 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 9113052a1ff9a78a91d980c3205eb958efe94ae3 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add some A8-based approximation for instructions with unknown cycle times
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100669 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| f69a244eaee851f502dc36659b48b77b9e31f493 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| ebd4cb43c2dd55f261e2515cae764d6552e2f2af |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 72018765fd2cfcd61bc52745eafab5d0be9377c3 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 9ad709b523b2cde67ffe20625fd5e2da9e9e0225 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 2bf942435137563eaee22f36a9e93bf4479ab61a |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix A8 FP NEON MAC itins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100666 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| f3da92b2f27a99bf96939e39c6ec8a9d04d21ba4 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix A8 FP NEON MAC itins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100666 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 57f4726a114d00b43ca1ca583100332d15f6b997 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
A9 NEON FP itins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100665 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 924369d58ea6641419e4e38963ff39afad8098e8 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
A9 NEON FP itins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100665 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 7092bc25507bb277c1cd0c99a040add2bc61051a |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some permute goodness for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| ec69dfa7ca9ccd5b8d13594ad8655909920f9462 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some permute goodness for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 3d45d0552a9cbb0a7427506dba0f2eae20fdcaf7 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More shift itins for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 5ca13c6ee390da552fc0fbf5ba795a1550537413 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More shift itins for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 8d062474d6f2cacc2a8a9842f254e971923b3049 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More fixes for itins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100662 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ecc6406072ece090a434f53916514f854130c10a |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More fixes for itins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100662 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 290319b4c640dcef9216c9d309c9c9f373b96a1a |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix invalid itins for 32-bit varians of VMLAL and friends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100661 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 95102073e8c610b3dbdbdd01a79dc8c0942ab34f |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix invalid itins for 32-bit varians of VMLAL and friends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100661 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 81529e9c8b2eec9df6fc9245871deeb375a628b0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add MAC stuff for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100660 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 7930ac19e74e0836f93c9ad9f0e6e87aa7ba8eb3 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add MAC stuff for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100660 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| d64bb07a350fd21e6a7a4f9b66f358d4ad7e2dab |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix invalid NEON MAC itins on A8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| d76da03e91e5ae31e944bd5e8f0c4a93bc6984e5 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix invalid NEON MAC itins on A8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| ed57ba73a04fb97e3109fd0ca542f46a60a88389 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix itins for VPAL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| dc0bab70cfc0fe2f80e0b4c310581f4cfa57bfe4 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix itins for VPAL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 6928d7c46c4bab79cf3d22f6884dc9d8acc332db |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix itins for VABA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleV7.td
|
| 0a3e2b591c0f5ae5d31aeb2eb794b3c5c38ffa98 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix itins for VABA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleV7.td
|
| ed60a4cca98f8054723c1e398c97bb5000cca532 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Correct VMVN itinerary: operand is read in the second cycle, not in the first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| fc2b08438c485e3c4c9c0328e38d8abb4687076d |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Correct VMVN itinerary: operand is read in the second cycle, not in the first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d36f994b6955365b2f2b6f4a1e1aeb385d1df2b6 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More A9 itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMScheduleV7.td
|
| e715b1e43ae14c07fdb36524a73183c56acb87f0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
More A9 itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMScheduleV7.td
|
| 4f2ada9422ed2e38ac0e53ca49f712e741bdff54 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Correct itinerary class for VPADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100654 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1c03f2493f93ed8fe3c99b39b5b3529771060d9b |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Correct itinerary class for VPADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100654 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 53ab10f9d8a59a95cd8d56dd23e42d782cf0a326 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100653 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4ac0af851f13aa29b4fc5416b90c00025ba05933 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100653 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 10775c13f7c0f589f24719dc3fb81af5b07c5213 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleV7.td
|
| f8b5c636178aa959539d8162c771dcb68a134706 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMSchedule.td
RMScheduleV7.td
|
| 2cea67bb67b99cd41be73108d03cb5a2349ea1ef |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some easy NEON scheduling goodness for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100651 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 268b7446cfc14c35758f1b0b6b00eeaef3a43f5c |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some easy NEON scheduling goodness for A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100651 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 1c05469155761552a82da4ac33647f47e4b45dd7 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleV7.td
|
| a31c6fb65e3741fc195ec7f89dc2ac4761ea298a |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleV7.td
|
| c12ea2987d16220178ec483cd7dbba171daa1690 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100649 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 63401e33cb438edbbae531389a79070026fefe9e |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100649 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 9b84130212977dc63cbe664606b491f9164f9a36 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Proper cycle times for locks, since wbck latency can be larger than fwd latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100648 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| bcc02d13bb268bcd95903c00d5f92ef37a6207e9 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Proper cycle times for locks, since wbck latency can be larger than fwd latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100648 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 783dc90c81525ffbab082d0e68a77c9c913ffbd0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleV7.td
|
| c492e094553bcd64be999f5068eca8d04d872a8a |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleV7.td
|
| f396779d23e585c302178e01cc1d058aa7f8cae4 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleV7.td
|
| 391b3431e2a9049fb1a5d51b6cca1c9a86d636c1 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleV7.td
|
| 71e4e0315bffa9627b96bbb13846c9d3da5779b0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some bits of A9 scheduling: VFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100643 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMScheduleV7.td
|
| 2eeeff83717498be1d7e52e2ef221e8d2f7df42d |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some bits of A9 scheduling: VFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100643 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMScheduleV7.td
|
| 5a998075a8f6fc6375c049ec82337e67402fc4be |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Separate const from non-const stuff during mergeing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100642 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 035b23a0f4320d8397c5eeef0b9d5feecfd205b5 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Separate const from non-const stuff during mergeing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100642 91177308-0d34-0410-b5e6-96231b3b80d8
RMGlobalMerge.cpp
|
| 3e27a4b83f35ac6c5c792c77c3b2b58cfaedd484 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some initial version of global merger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100641 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMGlobalMerge.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 1e7b324fe517583eb093854e17f1619324da4582 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some initial version of global merger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100641 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMGlobalMerge.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 1a85127694bde436b785778d5d28081aae85f9b1 |
07-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Expand SELECT and SELECT_CC for NEON vector types.
Radar 7770501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100568 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d0910c4534d323d101729d796e70805d3c2f0716 |
07-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Expand SELECT and SELECT_CC for NEON vector types.
Radar 7770501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100568 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8d357866cc99a950914087d748152975bb6ff3b6 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
don't use emitlabel in the arm asm printer yet, the order
isn't well specified. ARM really needs to have its instprinter
finished at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100439 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 03335350547b5d3521f9912d301bbb799d7eea31 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
don't use emitlabel in the arm asm printer yet, the order
isn't well specified. ARM really needs to have its instprinter
finished at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100439 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 534cd52347e282750543244d9918fcaf8d46a748 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix a couple problems I introduced handling symbols
with spaces in them. Sym->getName() != OS << *Sym
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100434 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0752cda4de245978e14d806831abba4506272cd0 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix a couple problems I introduced handling symbols
with spaces in them. Sym->getName() != OS << *Sym
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100434 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6d64b1bf6e2ccf3cfdf7bbad7590b6ce47f860dc |
05-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Get rid of traling whitespaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100404 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 7fb053dd45f7754b0a359a9de1a7445aefcca318 |
05-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Get rid of traling whitespaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100404 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| cf23d97c4882e2683452797b455f61722f912874 |
05-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)
to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100403 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 9d563b676cc9f3bcd9a9806ea5e9a791f35e3d70 |
05-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)
to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100403 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
|
| 4f8ea2957aa89b58fe484ab898ece009d2378173 |
05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
|
| fddb7667ca4d8fe83f96b388295849281ddaa5b4 |
05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
|
| 6395b0ac8c233d46d84d3ee9e8e08c1d8ca42760 |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily remove to disable building of ARM disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100380 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Makefile
|
| cb8660942179416e6505e202d0436ae0d58228d7 |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily remove to disable building of ARM disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100380 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Makefile
|
| c477cefe21c994a36294390fc5d4b73df5c81603 |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 100265 but instead disable building of ARM disassembly for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100379 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
akefile
|
| f6232cf8bbb72ac270217455d2a198838566316e |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 100265 but instead disable building of ARM disassembly for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100379 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
akefile
|
| 2b264adfbb8cad0f7b34f7270fbd86b05822680a |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 1b0194d646d67c341a162c580196bb25aee2e12a |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| bec073cea9e938743567789cc5deac473da04506 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
just have all targets create the DwarfWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100377 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 90429c487fe62582241ffe0d3e8acce936f2f8bc |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
just have all targets create the DwarfWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100377 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0e21124a12a70b4f882c3227f711c944523b5698 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
simplify various getAnalysisUsage implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100376 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8e680482c19a2fab185f88a0dea18313e4be70a9 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
simplify various getAnalysisUsage implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100376 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1f850aa77bd5df21936cf59660b16368858e6d32 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the magic AbsoluteDebugSectionOffsets MAI hook,
which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.
Yay for reduction in magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100367 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 3d2251361171b1a41bdb2ac71882e69d48617f49 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the magic AbsoluteDebugSectionOffsets MAI hook,
which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.
Yay for reduction in magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100367 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| cd21b8d590c5930b7bcaf1340cdca2f53c34ec06 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
revert my patch, need to reconsider this and figure out what is really going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100358 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 1d20473c9d920ce7d6aef438ea89544460c56f0f |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
revert my patch, need to reconsider this and figure out what is really going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100358 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 5acb9224102b971807fc6aa25ccacb13ccd4cf73 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix pasto, this is the wrong setting for arm elf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100357 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 416604703098e5c8e044828ebec6bdbf35d5039c |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix pasto, this is the wrong setting for arm elf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100357 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 97c69b7c9f982bd1bd3bf1b67f82cb3778235939 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
clean up the asmprinter header and privatize some stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100342 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3f53c8398d81065736a784469c9dd5afff85673f |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
clean up the asmprinter header and privatize some stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100342 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 017c7f97bb1d77c393f15ebba21c92c31631df9f |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove TargetMachine.h #include, also, TRI isn't used frequently
enough to warrant caching in AsmPrinter, so remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100336 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9d1c1ada213c80135fbdda704175aae689daa6f9 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove TargetMachine.h #include, also, TRI isn't used frequently
enough to warrant caching in AsmPrinter, so remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100336 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3eac1ed5c28f6fd3b670f996e71709c6b16ab9d6 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Momentous day: remove the "O" member from AsmPrinter. Now all
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b23569aff0a6d2b231cb93cc4acd0ac060ba560f |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Momentous day: remove the "O" member from AsmPrinter. Now all
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 82d07b7cf0920fe0c55f948f4577757e01becebb |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
mcize a bunch more stuff, using EmitRawText for things we
don't have mcstreamer support for yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100319 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9d7efd3081ef13b4d1ac7e0ad4854e92e5f132ad |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
mcize a bunch more stuff, using EmitRawText for things we
don't have mcstreamer support for yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100319 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ae18179a38d3ea80e7505a36e35313b9b075cf28 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
convert the non-MCInstPrinter'ized EmitInstruction
implementations to use EmitRawText instead of writing
directly to "O".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100318 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7ad07c46362500f7291a92742569e94fd3538dfd |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
convert the non-MCInstPrinter'ized EmitInstruction
implementations to use EmitRawText instead of writing
directly to "O".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100318 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3eb5dc17a0715f7c67caca590c8349f5599ff657 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix PrintAsmOperand and PrintAsmMemoryOperand to pass down
raw_ostream to print to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100313 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c75c028a15a13786eee585aa634b4faf694dd00a |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix PrintAsmOperand and PrintAsmMemoryOperand to pass down
raw_ostream to print to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100313 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 99fbae7d5b397f285b5e6a9d4da079f79214e1b3 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix an ugly wart in the MCInstPrinter api where the
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| d374087be5360a353a4239a155b1227057145f48 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix an ugly wart in the MCInstPrinter api where the
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 4e972531cf2d719522ab38ce3b5ad1a625579d03 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter. Instead, pass it in explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 35c33bd772b3cfb34fdc6b5c9171f955454d0043 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter. Instead, pass it in explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 483af3c218eaedddcf8873e6af35eba739f593ab |
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 6d718817f982b804ff516e43a47f38aa78d2a4a9 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
asmstreamerize the .size directive for function bodies, force clients
of printOffset to pass in a stream to print to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100296 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0c08d092049c025c9ccf7143e39f39dc4e30d6b4 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
asmstreamerize the .size directive for function bodies, force clients
of printOffset to pass in a stream to print to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100296 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e04b73d1d82f9beac274d11d8a97457fef71865e |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Get rid of the middleman (ARMAlgorithm), which causes more trouble than the
abstraction it brings. And also get rid of the atexit() handler, it does not
belong in the lib directory. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100265 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 7fed809484195c5ae1ab7ab7b706320af2f35cf5 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Get rid of the middleman (ARMAlgorithm), which causes more trouble than the
abstraction it brings. And also get rid of the atexit() handler, it does not
belong in the lib directory. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100265 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| 21c6bcb3f02225544028ce2db38008d55699add8 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100259 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| b7aaed83e2f51769c54d9b0c46fc22cb429881c2 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100259 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
|
| af66e862f426ca84a82ca95b5e376263a1568545 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Register ARMAlgorithm::DoCleanup() to be called on exit to free the memory
occuplied by the cached ARMAlgorithm objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100258 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| b35ae7f7d6fb6bbeb08246922760f0f55b7a8b5d |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Register ARMAlgorithm::DoCleanup() to be called on exit to free the memory
occuplied by the cached ARMAlgorithm objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100258 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
|
| bf51684944f98bbaf7a22c68c326c98121d65d54 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix another build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100251 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.h
|
| a70261550ec464d3ccacd966e72664c997a4cbb7 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix another build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100251 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassemblerCore.h
|
| 3ed7eaf80cf71dbd63fa9903a9412db9b2593252 |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.h
akefile
|
| b68a3ee82a8a34f7bae1d68d76f574e76a5535ef |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.h
akefile
|
| 754058207f2cda84331c448ffcc115debc847bcd |
03-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added support for reporting operand token ranges
to the ARM AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100232 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 762647673379dbcff6bbba6167b0b1b0d658ba9d |
03-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added support for reporting operand token ranges
to the ARM AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100232 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d2c680be1a3161bc53018ae27f6a94628055a3ab |
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| f9f760e09acb520d70f23cdbd6b2d288b9094a46 |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 703dd7c7eda9ffea68170bd9d8cdbc74322825dc |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 139dcd7aa428c188facd672b1c5a0e299b298390 |
02-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 93d6a7e9c21204c52d6efec6c672163e7de79660 |
02-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 58bf0eeec893ce128943d790b1dfd53a26612d06 |
01-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
vml[as] are slow on 1136jf-s also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100066 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 1118b5e490717fc13895e1307a15eb663d3758d1 |
01-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
vml[as] are slow on 1136jf-s also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100066 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| dfd093fd107d0f6047fe646d1ac90ee29c9ea52a |
31-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment the changes for r98218 and friends inside the source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100031 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5e1b55d67288874f8669621b9176814ce449f8f5 |
31-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment the changes for r98218 and friends inside the source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100031 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 76821a73c39a21f7116ef99aa60940b07aedefac |
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 100f090adde26005b9f1eca96871dff52825b27b |
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| f4862b06ca84fae2bb80e4936b3b2e598419c704 |
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 3b197832bf569e331ee057aece06ecd99b13ba2f |
30-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Rip out the 'is temporary' nonsense from the MCContext interface to
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 9b97a73dedf736e14b04a3d1a153f10d25b2507b |
30-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Rip out the 'is temporary' nonsense from the MCContext interface to
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 8d65dc8ff1e323d95527508ee908e0adf02ee93a |
29-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99815 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| f283e40b6a48368a1713bddbb8556797bfec130b |
29-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99815 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 24b8129c8f398e17c779cc87c0861a4158665b8c |
29-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99789 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 79c4d820b46cee1e78ecdef80b3f2ed6373839b7 |
29-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99789 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 0e28e4b5f66ec987dcf33396fa2106ed0936bce4 |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix integer negates to use the proper type for the zero vectors,
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99757 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0a00ed98f1d0734bc5bc699f58852144aa54195a |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix integer negates to use the proper type for the zero vectors,
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99757 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 71c5b64ff9454bba229ee94146d1a3a6e67c7764 |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix vnot matching to explicitly specify the type of the
input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99754 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b26fdcb48bd8dcffa338c98cf9e9c05346f2bb51 |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix vnot matching to explicitly specify the type of the
input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99754 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| acfc7e49a105dba3b409f155e6f516aa245a6678 |
27-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99705 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2cd1a12fe07be753e331a12389aa1ceb49de836b |
27-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99705 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 724df1cf3a37f805adc3064d63d0697860036224 |
27-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99704 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 10bc69c7262d32321b65f21b80a57826b1a90acd |
27-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99704 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 9b2b64f7fe304b8d5700fd321f4a6ef1b8185d52 |
27-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99690 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 897dd0c58859e10afaa36e4175eef9a703b4a794 |
27-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99690 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 408b8036333b3f0e8963497f3bbab1032b16f4cb |
27-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99678 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 9ab042701528bc104053f93135ef7fd1bbb1153b |
27-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99678 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| fe0978b58bb89b23f7d60a9b507ceb11b4a2343a |
27-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9ee9d7d4931ebfb5d16ca401aef96aeb88689d69 |
27-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 633601e00ff4db42bcfed568411852a1bfee5a7b |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99659 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 629c25cda6af43c16ee4d1ef2301c9ff1531d041 |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99659 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| b78241ca7be28a0fb6f76710a6741cac6de530fc |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| c6e704df8d6e96260a463dac4675ed6968e186e6 |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 6c24fc0ed48d4fd0b36f63999deedd1622e29232 |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
vldm/vstm can only do up to 16 double-word registers at a time.
Radar 7797856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 9a52d0c352c852dc9517430442afc54f53e1d4dd |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
vldm/vstm can only do up to 16 double-word registers at a time.
Radar 7797856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| d98e797e5c4e9ec8cf91b549cfe6c1a3f17380b9 |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 575c91cba78332bd9add0949e31a9c228c44cf00 |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 81f9b983bd0dd9d73c89fc42ff39cade9377f25c |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99590 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 0a3dc10eba975195e8b9b028bd21a4969cd6f2de |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99590 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 20d1d65606b107e5f79552612df017f8265a0a53 |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
Re-commit. This time complete with testsuite updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 7ec7a0e96b34fedf11445c1dde27a4fac8e8a1a7 |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
Re-commit. This time complete with testsuite updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 48297ab3e63488b3542546c8749a8234e050fdd9 |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
need to fix 'make check' tests first. revert for a moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 78e496e165e3093f3d7373e50da1c91b9937bc69 |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
need to fix 'make check' tests first. revert for a moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 00f8f55dc6e38a9e05046abedc9e9628ab083c8c |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the flag for using NEON for SP floating point to a subtarget 'feature'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| bd17bc96bf54cc58d91c2d20964c6c5e28bffa57 |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the flag for using NEON for SP floating point to a subtarget 'feature'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| bc4e39eed59cea7dcf004e98d49828841e43cc72 |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Removed instruction class NI from ARMInstrFormats.td.
It doesn't seem to be used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99566 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| da9283cd57843eb21fcd4117833e165017bb9123 |
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Removed instruction class NI from ARMInstrFormats.td.
It doesn't seem to be used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99566 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| dc748c274ac77d5d2b2b56d486d8a29d0cb9bbcd |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the use-vml[as] instructions flag to a subtarget 'feature'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| 6b2e8dc9a0e4ebda645ee4eba95711eb630b4edf |
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the use-vml[as] instructions flag to a subtarget 'feature'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| d2048ff30674b142c716aacda171ac0c726ced40 |
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVDupLnFrm and change NVDupLane class to use that format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99557 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 2d2898e6e99a5a4a16352b86070fa0986b7d1efd |
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVDupLnFrm and change NVDupLane class to use that format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99557 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| cd20f1b53c46d5e3d11a30ad2783aa33b83b2efe |
25-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99549 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 65cef00142c9a187707c56a293ae794765f7463b |
25-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99549 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 16e78bb21e443d10c53c341a852d3361e3d0b997 |
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| fa80bec349b7fff9ec97b5f66795d7bafa72da62 |
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 01f7ec2003f453661eefbe68a5e5be3861f38b73 |
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| e4614f7e84a7219164e9992fff855dee3816a08e |
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| bf83ec6ee76e43bf2c9e92d14b2c2c0114c81f43 |
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 2676737e5ed3e4b5c89b4d06b60d998e9318eb73 |
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 3cc826c09e8ca9b2406934c6e8967073c1a88419 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Trivial formating change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 69631b13275f7f1b35be2df9135632e0671c1a91 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Trivial formating change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 614338f13645d35bf9e01dc708c8781b73d873e4 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
NVCVTFrm will later be used to describe "vcvt with fractional bits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 2fadd6b221893595a7a86eb4b03f5aeadb6088fc |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
NVCVTFrm will later be used to describe "vcvt with fractional bits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 00f055180c03c8dae34718419aec3f38e781b7dd |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Reverted r99376. The disassembler will deal with the 2-reg format of these two
N3VX instructions using special case code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 7d85ac09f864bd0756c2a5be781e14b41b7521e6 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Reverted r99376. The disassembler will deal with the 2-reg format of these two
N3VX instructions using special case code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c4a782c11fd11ae908e3f852056b2539993ff4a3 |
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
tweak the arm if conversion heuristic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 35075a7e81338c0eea00d1bac6e0d4ffb9c82c82 |
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
tweak the arm if conversion heuristic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3d4b9e00aa7383a94189f8eb4efa80226291d885 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b7ba5781e61099368499502636667be801945235 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ee4e0fd45a7c4ee58e5dbe6809338f44db5978b7 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
respectively, and add some more comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| c5f413a74c296864d54c8e1a3391e7b15c9b2f97 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
respectively, and add some more comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 0c0e24ffceb034dbb951da77a728472823851d2e |
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
try being more permissive for if-conversion on ARM V7. see what the nightly
test run permformance numbers say as to whether it helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fceabef52cfdb9243f483af9030797a343cca2d9 |
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
try being more permissive for if-conversion on ARM V7. see what the nightly
test run permformance numbers say as to whether it helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4d2ee1bf11af864e99c15e622406256a218ba775 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renamed NVdImmFrm to N1RegModImmFrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a271174771adce635d29219225843ddb3fb17770 |
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renamed NVdImmFrm to N1RegModImmFrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 4756f0ebbf866404e77cdd4d32cf7feb7fce23d1 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix typo in the comment for N3VX class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 841e828702df6c28f2af25930cc06e23bd8fcc88 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix typo in the comment for N3VX class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 7ae22f384ffa05455f329fc64c832cea85cce371 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| be7849ee7329bd849b09c086b862ed0506ed01a9 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ed4632eaa8faa98b2b6d0eaa52a91d79fd350260 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdVmVCVTFrm.
Converted some of the NEON vcvt instructions to this format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 3ae9a57c74346e8697ebd64d3139a0ee6b78118a |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdVmVCVTFrm.
Converted some of the NEON vcvt instructions to this format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 5d9945242c27bb5f4c21a23b7b7e8d3ef39d5df6 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdVmImmFrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 927b88f771ea0c9f511fd0a92dc4a6d4024fed7e |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdVmImmFrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 35b8d26e23f3379633190a1209539993484adcba |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
|
| df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6b |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
|
| 052c3813accd31c1d6e5f533301ada89ddfd3156 |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix bad indentation, 80-column violations, and trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 011355944bc914b556d43ca4e3b422049791de08 |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix bad indentation, 80-column violations, and trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| ad4d8ec1d98bde55ab1813fe0c54cf947f81b547 |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdImmFrm.
Ref: A7.4.6 One register and a modified immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 785516adc5f3de0911eca1ff94283e6bc8ace7ca |
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdImmFrm.
Ref: A7.4.6 One register and a modified immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 2194448857f6c2525d9b041e6665ac05d6c19f47 |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some instructions to match the corresponding NEON opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| c289a0252bba42248d7b11699dda27feca8860b6 |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some instructions to match the corresponding NEON opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| d0a74632055346014293bf0c3341e899910747d3 |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VST1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 11d98997590a1d636b04c4f0756eded6b2d037f3 |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VST1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 93e7f565dfa8ab025449fbc926210d90edd2c41c |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLD1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 621f1952430ee8b01b21ac94404e52500d79838b |
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLD1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| d993310197e1ad54801651dc2dfe7c81cdd7f81a |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename one more NEON instruction that I missed earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 62ef3c89103484c394389129f1c8ee6f5c9f0f53 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename one more NEON instruction that I missed earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f2cc3780aa04d256935f07edc6aea62d05ad6009 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Regroup some instructions. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 052ba45bf85a3cdffdbdd016a78bafe03ed40e82 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Regroup some instructions. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0ae8449059b4e55e3c9b15e810ffbc1ccf4805ff |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| a6979754da61adbf1e7e21b5fc22a52d9074887e |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 331cdffb6731fd86a5ef1f8f49eb56843fcb7dd6 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove some redundant instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 58393bc3fdcc0d1f58f4da72388e44d5ed62f927 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove some redundant instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a4f5fe1090ed699aba4647162fc3ff470b2b3503 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
specify encoding bits in arguments instead of "let" expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 39842553e89e2c34a7dc31c4b4f118991baa3693 |
22-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
specify encoding bits in arguments instead of "let" expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 686b173a02f572c9671fde378368134a9adec317 |
22-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| fa72340ba096dbe0f765651e425c5c6aa8259931 |
22-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 6c566968feccfd14f70bdd2381848bb4857a9beb |
20-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 5d067fe1580772a8e012ff0acc06e21e9b95d340 |
20-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| b0d7be6eb6b7a0d33687b5ca37ea7a67b5032824 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6652: Use LDM to restore PC to the return address on ARMv4.
Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| c88d0722931b8442cd347bd530e2182d164c82c6 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6652: Use LDM to restore PC to the return address on ARMv4.
Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 255e748b064722604ac95dc365639f0035c3e48a |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
EONPreAllocPass.cpp
|
| 226036ee731a2041f37f28f958d2b6a50373f4f4 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
EONPreAllocPass.cpp
|
| 029da9589fbb6ab0321af1cdc5582fa93074907a |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d5fadaf56ee1e8ee137d34bed6749bd3b11ffd88 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8119e92ebf6d7183c9afab1fa06f66890d07951b |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of VST2, VST3 and VST4 with address register writeback, and
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4f4f93f9d624f4fc8af2c508c1895961674f8e9d |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of VST2, VST3 and VST4 with address register writeback, and
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3e98d3665ef3b9438abe1942bcdda9a36f71c573 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instructions for double-spaced VST3 and VST4 without address register
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 068b18be0da9ea5f76b727997a9de5d88eccd734 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instructions for double-spaced VST3 and VST4 without address register
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6877421a1d94a035c06e0bef8fdb2bb5b72b8cff |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add VST1 instructions with address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 25eb5013d0516e7ba5105a1ca25c9f61d2ddb0b2 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add VST1 instructions with address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 29133b0786a7a86297ae5c975a6cce5b4f9d45ec |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a1023645f88a50bee7997dc355426049cc0c9799 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d22476d2e14f1fcf13348255b50484741c03a220 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy some more comments and whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 41315282f9bff0a627838b6f4b706ef966354a51 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy some more comments and whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e5cc860fef2e9c7278d3ab14fd60b1ac1314e0f0 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 92cb9321a1bced8ba118e7970ab16e8e4f8f455a |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 15b46a4dd523ea0d20c084a3806d9f3ae37f0435 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy some comments and whitespace for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 667a13e1be0b2994b7d109b6117647738a5915a4 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy some comments and whitespace for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 14e26b3f55b772d277c9b56670a4d3bbd35f9e77 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 95ffecd4fe404b622c3f984995bc9e849be297a0 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 23406948a7dc3a969cfc1d1f7c9515063ac8b856 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instructions for double-spaced VLD3 and VLD4 without address register
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 00bf1d93d7c3274754f56c180556d4475cf91059 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instructions for double-spaced VLD3 and VLD4 without address register
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 06ce5bf37becf3bd6126cb5325bd2f6230c95d00 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add VLD1 instructions with address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 99493b2b535697632e63be6d2689aaac6212e755 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add VLD1 instructions with address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b127434012c8a17e481f57e94459f8003b318601 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert the rest of 98679.
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U lib/Target/ARM/ARMInstrVFP.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 55c9cb5a222e1c26ded70d78b2b7ecc83fb54351 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert the rest of 98679.
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U lib/Target/ARM/ARMInstrVFP.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 95be1abbfb804a32e710569acb2322425c73219e |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a very bad typo. Since the register number was off by one, the ARM
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 98330ff8e344d2e88c0a2166901d394e813e8162 |
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a very bad typo. Since the register number was off by one, the ARM
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| caf6bd5053a4dfffc6a403732eaf3dc05a0049a7 |
20-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NLdStFrm Format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| caa608e97c07ffe988dd7c76516b9f81ad8ffc0a |
20-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NLdStFrm Format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| a51f67fd47ba88fc54cdf3f8abc67883a1f13dd1 |
20-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Revert r98679. The disassembler will be updated to depend on the existence of
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e86425f22443881ae1051419b4f47114271db79f |
20-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Revert r98679. The disassembler will be updated to depend on the existence of
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 899588eebff371c519d09d10dbadef03dc810ba1 |
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert this change, since it was causing ARM performance regressions.
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| 76a312b7d1c2b41394696510506967cd0794b831 |
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert this change, since it was causing ARM performance regressions.
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| 12eb6cde809e11737427f15ec2d194d69326f55f |
19-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renumber LdStExFrm from 28 to 11 and shift the existing format values to make
room for it. This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
|
| 81f04d59f6216d0e105daa9bde2250ca6af35fa5 |
19-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renumber LdStExFrm from 28 to 11 and shift the existing format values to make
room for it. This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrFormats.td
|
| 9c19026c6175cc8ed16153765d856b2b429c946d |
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set SDNPVariadic on nodes throughout the rest of the targets that
need them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 60e9eac357dc6e6d9396f02b171baf9e70d97649 |
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set SDNPVariadic on nodes throughout the rest of the targets that
need them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 6ad99550f3416b80aa852d03fbcf0ec0d5bd0f5b |
19-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Remove a memory leak from ThumbTargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98936 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.h
|
| c3e45f1ee2741935cf15f0ad7e3e7694681fa125 |
19-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Remove a memory leak from ThumbTargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98936 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.h
|
| 22bc2c0e66421974fc3cce564d6acc4b04effc2b |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98928 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 6b7c2cf5d46ef9d73df66163d3296bc4435a5e20 |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98928 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 3257f986d5c9b3be7db58d4efa271f789b0cdb02 |
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Update comment to refer to the right filename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98902 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 50622ce8cf429067540232ffabc5b53a81f53ca8 |
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Update comment to refer to the right filename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98902 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 2d5880949bac5fb395da458a967893428cf877a9 |
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific fp <-> int nodes when still I'm here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| 341ab138fb3b7b7ebe12371481641f8681cd4e9d |
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific fp <-> int nodes when still I'm here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| c761f639f56add3f00ac84e2379d30d648a8bb81 |
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific nodes for fp16 <-> fp32 conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98888 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
|
| f0d500768d1a42e91c6324e6c8677cbe26df6e27 |
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific nodes for fp16 <-> fp32 conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98888 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
|
| 4875aab9914f89cc8e4de7a1dc96ce72c3fd597c |
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98887 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 6755d97a62fd6796f4146833efb1051fc96a61c0 |
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98887 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 35c7a269c837375dc95e20ab60e8084b1ddb2c08 |
18-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix some buggy ops concatentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98869 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| b7d5226a4ed0d5a7ea2441791cab093741ad5e9f |
18-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix some buggy ops concatentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98869 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 7070982a21f8c5b520efc26dedd8f909dd3e7fbe |
18-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor NEON ld/st instructions to hardcode class arguments that are constants.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98860 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 95808328b4d92e9e5398fe7b38079dcf4ecf1232 |
18-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor NEON ld/st instructions to hardcode class arguments that are constants.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98860 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 7c3f38603828a513dcf5d161848d4f901a95c1b2 |
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
There is a better way coming up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98777 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 6c8648b4c9f3e02b625dd2d32e0315395da88e61 |
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
There is a better way coming up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98777 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 2a2d2e877e92f2f70331b3b06cfdd0e71c3b0700 |
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in the IT mask printing where T means the cond bit in the mask
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing. The disassembler also depends
on this arrangement. This is similar to what's described in A2.5.2 ITSTATE.
Ran:
utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2
successfully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98775 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| b675e255d0def28e9718c62336be6fd6e7a22e54 |
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in the IT mask printing where T means the cond bit in the mask
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing. The disassembler also depends
on this arrangement. This is similar to what's described in A2.5.2 ITSTATE.
Ran:
utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2
successfully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98775 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 16a9be72afa1d346f9b2be88afb61897e124ea92 |
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Refines 98745 so that it only contains the patch related to the output of the
addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.
This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp. It is used by disassembler as of now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98774 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 77bdc48eb66396cbc4f81bfd1ac9de257b83cf41 |
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Refines 98745 so that it only contains the patch related to the output of the
addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.
This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp. It is used by disassembler as of now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98774 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 164fe923dac9b977ab0e3d923978cf0ba875d959 |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98769 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 87949d4d5af6f77e3ac1fbd2d1c0fcb327ed92a6 |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98769 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 6c69015d29ae6318a076f596be373fd96cdb14eb |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3f
in svn r74988 but the format field was never widened.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 89ef7b797ae949edd592f5f71dddbae6ea35c2bf |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3f
in svn r74988 but the format field was never widened.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98768 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 7a969d17cd8be3009224197ac249f6e84700df57 |
17-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
98745 contains something unrelated to the patch.
Remove it from ARMAddressingModes.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98751 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| e6f83878bc7cc26ae2fcf3112e6a9fe687e8eba6 |
17-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
98745 contains something unrelated to the patch.
Remove it from ARMAddressingModes.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98751 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 09a43769d7a947c7af72c74955aac4dd12dbaaca |
17-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 9e08876a2ae329feb7a76dbfe33666cb58033c00 |
17-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| d1092146fc9355099588c5742bdc78d6787bec85 |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 98683. It is breaking something in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONPreAllocPass.cpp
|
| a43e6bf69093b9870548e7d782ea148e2ddd6449 |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 98683. It is breaking something in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONPreAllocPass.cpp
|
| 7474bb0fbb9640f6f799eea35d7fbaebd2312a09 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant writeback flag from ARM address mode 6. Also remove the
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONPreAllocPass.cpp
|
| bb6c77e6b9be405fb4d57c8ee4cddc2018df392c |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant writeback flag from ARM address mode 6. Also remove the
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONPreAllocPass.cpp
|
| bc6543220fcf2d3e29740db297b4ccf736a21fa7 |
16-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.
This is for the disassembly work.
There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98679 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| 2b0272e43de501891f09068f0a562792d4881044 |
16-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.
This is for the disassembly work.
There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98679 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| a256a75c0333dcbac0e119dad233782527db513c |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant writeback flag in ARM addressing mode 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMCodeEmitter.cpp
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 2d357f6b44159c59dbb58e03a22f94312696d064 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant writeback flag in ARM addressing mode 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMCodeEmitter.cpp
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| dfa5da942162f3e44b08d27e4df9e7d94f17e13d |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the writeback flag from ARM's address mode 4. Now that we have separate
instructions for ld/st with writeback, the flag is completely redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| ab3460519e8013cdba33a416cefd55dfb418999c |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the writeback flag from ARM's address mode 4. Now that we have separate
instructions for ld/st with writeback, the flag is completely redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 2830d1937d97bce9d0cb2538d8582638a45fa5b7 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix unused variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98642 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 9e54b6ab3f14ec3743ba92a7a18bac3bce96ae1f |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix unused variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98642 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 95c5fd1ea67f2612d5bd780f569fb6d33700edc2 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r98637 into '.':
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.cpp.inc
akefile
humb2ITBlockPass.cpp
|
| 49d9dc4dd205b615beb7af160ef974eaabe4d1cf |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r98637 into '.':
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.cpp.inc
akefile
humb2ITBlockPass.cpp
|
| 83eb6f1fd620dc8249ebe4cfdd99dbe67817bb43 |
16-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.cpp.inc
akefile
humb2ITBlockPass.cpp
|
| d30a98e43ae18e1fc70a7dc748edf669d809c685 |
16-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
isassembler/ARMDisassembler.cpp
isassembler/ARMDisassembler.h
isassembler/ARMDisassemblerCore.cpp
isassembler/ARMDisassemblerCore.h
isassembler/Makefile
isassembler/ThumbDisassemblerCore.cpp.inc
akefile
humb2ITBlockPass.cpp
|
| 1d7bcd8876e207fd82646225539eb0d8db8de293 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| ea7f22c31d0d12923eaab6840322431cc0222ae9 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| b1a49d08ce463feae809d902c386954d9b5e4d4d |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap a long line and add some parens to be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98596 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 8d95e0be13079339c2b84f245fb1665953e2bc77 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap a long line and add some parens to be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98596 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 07a9f1bfc948604e35d50f2d3691b14127b88b38 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass.
Radar 7459078.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98586 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 33cc5cb9837469dabf31cc5a474e2c27d2b7d144 |
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass.
Radar 7459078.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98586 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 12759cef26b06f95d1290e60c2bb27a7b411edb7 |
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| 505ad8bed3321bc4b99af8fba4844efe2fe9e67a |
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetObjectFile.cpp
RMTargetObjectFile.h
|
| c002b5792482bd4d74855addc22f448b8bb9199f |
15-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix an ambiguous pattern, contrary to expectations, scalar_to_vector
doesn't have a type constraint on the scalar because we don't have
an 'sAny' type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 77144e719f6450c67612bbdd93635f523a41236c |
15-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix an ambiguous pattern, contrary to expectations, scalar_to_vector
doesn't have a type constraint on the scalar because we don't have
an 'sAny' type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a8f50d8f3b00059c1711a6fb980b3df445a1eeea |
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add substarget feature for FP16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 631379e79c0971c5bac13629b8caf8912ed4c35c |
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add substarget feature for FP16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
|
| 881c2e565f54f5585a3697583d2552442706d956 |
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add codegen support for FP16 on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98502 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
|
| bec3dd25c76c825c179ef35794a8fa3620cf2559 |
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add codegen support for FP16 on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98502 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
|
| 359731acbae700a9590257899bf54c05fee8a9cd |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the DBG_LABEL MachineInstr to always be created
with an MCSymbol instead of an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98481 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 6ffcccab5191ef1dcde876800c24a1f58b3b7ad8 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the DBG_LABEL MachineInstr to always be created
with an MCSymbol instead of an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98481 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 8574dddd63edcb47af66df3ea309ff03a6b04549 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98463 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 7561d480953e0a2faa4af9be0a00b1180097c4bd |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98463 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| e3330170d608053806e37c4dc953f15cf47b3388 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change EH related stuff (other than EH_LABEL) to use MCSymbol
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98459 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 1611273351d75b5cbe2a67485bb9831d5916fe26 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change EH related stuff (other than EH_LABEL) to use MCSymbol
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98459 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d13daf889c4864428fa13fdf88a50a2fa6367c34 |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the now-unneeded context argument of MBB::getSymbol()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98451 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 1b2eb0e8a6aaf034675b17be6d853cb1c666200f |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the now-unneeded context argument of MBB::getSymbol()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98451 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| f4853459db476c7487bc5b4b5bd68c5c7f995600 |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
rearrange MCContext ownership. Before LLVMTargetMachine created it
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 11d53c129fc9c2a4510605ec0a1696f58750af52 |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
rearrange MCContext ownership. Before LLVMTargetMachine created it
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 713a8646e6db41f46ffca0806115ab16dd7e653a |
13-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix another warning. There is a functionality change but I believe it's correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98430 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| e17245dbe970faf29af408056f43ee543724d7fc |
13-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix another warning. There is a functionality change but I believe it's correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98430 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| b9ee99d999a51b1d9869853cba4b69e0b5b95e54 |
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
base register updating load/store-multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98427 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrVFP.td
|
| bffb5b39bea3288bc557b10f3ed1864e6c7857e0 |
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
base register updating load/store-multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98427 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrVFP.td
|
| 5ef33c75e408528b75baa2e0584711309959791e |
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 815baebe1c8dc02accf128ae10dff9a1742d3244 |
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 618911a4092206888f3808184919881efbd8a3be |
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine the code to build VLDM and VSTM instructions, since they are
mostly the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98402 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3943ac38c946aaac21dbe686978d098770d7679e |
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine the code to build VLDM and VSTM instructions, since they are
mostly the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98402 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| fe460493143961f8225ccb85f75d974986af059f |
12-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy up. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98398 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| e4193b20fd30e59c389814835ed2f6b3bc3b225c |
12-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy up. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98398 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| d98a3acc2c5aaf86769a3c7bee88893721e37a84 |
12-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98395 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5027064c69c89ff605479d9e7eab2395a54b31e9 |
12-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98395 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1fa7b53035a38da8edfffc1fb00c30fbd61eec76 |
12-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Fix LLVM build when the user specifies CPPFLAGS on the make command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98394 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/Makefile
smPrinter/Makefile
|
| 150ae119761df40ca12f5d975a667778a7d011d7 |
12-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Fix LLVM build when the user specifies CPPFLAGS on the make command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98394 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/Makefile
smPrinter/Makefile
|
| 2acc03c6ad219876410de4a0fa7f8ef42a97166d |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
inline GetGlobalValueSymbol into the rest its callers and
remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98390 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| d62f1b4168d4327c119642d28c26c836ae6717ab |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
inline GetGlobalValueSymbol into the rest its callers and
remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98390 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 5e318698ce09ecc215fffc3e3cfbe64a79833931 |
11-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98285 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c0b5dce3fa24202d842cdcd1eff9e02b33e22309 |
11-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98285 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a9480cb333bdb8b7d11cb4012e5a7b02e8f087c5 |
11-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
When outputing a non-lazy pointer for a stub, we may need to fill in the value
for the NLP because the object it's pointing to may be internal to the file.
This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:
GCC_except_tbl:
.long Lfoo-.
__ZTIA: @ This is local
...
Lfoo:
.long __ZTIA
LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98218 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 52a50e5d0e6ac08d86706dbdd8f4a5dbb44da4cb |
11-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
When outputing a non-lazy pointer for a stub, we may need to fill in the value
for the NLP because the object it's pointing to may be internal to the file.
This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:
GCC_except_tbl:
.long Lfoo-.
__ZTIA: @ This is local
...
Lfoo:
.long __ZTIA
LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98218 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b79f0925ab184c9cd8716340d27b88cb70002506 |
11-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98217 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| ae1757b4527715564c8db95049286cc2c3cdece4 |
11-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98217 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 7bd90eea10c84a2dbc72f84dd702346ac472a465 |
11-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM buildbot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98215 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5265a12f531be9456a238badc4e9ae43581effb3 |
11-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM buildbot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98215 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d2436aace0508a6f157cb35bc7230aef8d942790 |
11-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Lower small memcpys to load/stores on Thumb2.
Radar 7686922.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98210 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 4d6113ee0699ac1eff46971881179de53e2eb810 |
11-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Lower small memcpys to load/stores on Thumb2.
Radar 7686922.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98210 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| cd37910893c8c4400998b9578e433d65a99b04f8 |
10-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix an obvious typo in an assert.
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98200 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| fbacc888eeb5636574cd2fec51c00fcbc8873117 |
10-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix an obvious typo in an assert.
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98200 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| ce99651283626c14f32f25d4b0dc486e14ffd41b |
10-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98199 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cebae36f57456fe6b0e13726acd1e0250654f02d |
10-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98199 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ac183b1b5cee11f753e8fc008bbb6e61bc9a93fd |
10-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure the LR gets pushed in functions that use vaargs. This fixes
400.perlbench for the nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98183 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81 |
10-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure the LR gets pushed in functions that use vaargs. This fixes
400.perlbench for the nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98183 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e4c4bef88ab36061a5e2bf80f3e80729fec58bc3 |
10-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
comment why we use custom epilogue for t1 functions using vaargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98182 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 004453e85e72a2a2ea9a70fc6b7b368feb877c4c |
10-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
comment why we use custom epilogue for t1 functions using vaargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98182 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 07bc4c66b068f3e15138c8330bc36ae961a92e54 |
10-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| dd0f3cf189c34542901178bfca0a319b74d69a05 |
10-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 72121e4e6261beba09f5d22854cfcc3332f7c5bf |
10-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set the temporary bit on MCSymbols correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98124 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 98cdab53c302a2d6686fa428c0e896b1fb195311 |
10-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set the temporary bit on MCSymbols correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98124 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 5a729995478d86e9f559b53d2ee4fb9b8c26e90b |
10-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Clear up the last (famous last words) frame index value reuse issues for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98109 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 7c617b5e53987d786451dd668b5113f2e2b983f8 |
10-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Clear up the last (famous last words) frame index value reuse issues for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98109 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| b2247c71f6be3cb12c8aaf47c45d225e2e056856 |
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 |
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| c5f7bb4d203754a38d85c6a8537499ce264245fb |
09-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| a2c618a0f08a331e3f45bd5108423b084c2986ed |
09-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| e0444f1f0d5303238263cab54773f6e7d8a4e6b7 |
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 4e501545cd12d903d35096f42eb5fdbe4603d5da |
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 46718f5a8c23ad90bb2e974b0a5f3e8462766b2e |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
The ARM EH experiment worked!
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98068 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetObjectFile.cpp
RMTargetObjectFile.h
MakeLists.txt
|
| bdc38e5aa27bf57b4315b961a172e250bcb1bd69 |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
The ARM EH experiment worked!
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98068 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetObjectFile.cpp
RMTargetObjectFile.h
MakeLists.txt
|
| b63a802baa747b858ac64a9230b0cfe3af09d10d |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
bear with the awful code. It won't last in its current state beyond tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98040 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 94a1c631dbcad0c92032259444aa40b795b3d283 |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
bear with the awful code. It won't last in its current state beyond tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98040 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 341930ca152e4dcf70c609b5b0ac9ac3502f1cce |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Print blank line and clear stubs vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98019 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cf6f28d84af09b38e96307007cd93760a7ca42d7 |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Print blank line and clear stubs vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98019 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4dfe49627d49476660378d6b5f4b39de8593f489 |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
MC-ize the stub printing in ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98018 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| becd83e3f4eb996f8e43189ce482267b3b8351a8 |
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
MC-ize the stub printing in ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98018 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5ea11bb8e64516f169f4d2e839f25b03f53736ef |
09-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
don't reset defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98004 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 82f05078b08f086b868e096ff0bb89324ca5c1d5 |
09-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
don't reset defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98004 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 6753310ec552a38fcf81b0cecac8f6c36a36903a |
08-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
humb2InstrInfo.cpp
|
| f5fd499791bd65a31183324dabc5eefc201f9e2e |
08-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
humb2InstrInfo.cpp
|
| 4e624721ef14562d4f8f7161356fe129ad3c9d00 |
08-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix a bunch of partially ambiguous patterns on ARM. As an
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| d10a53d5a1a5f5a729b55638acfb25d3871df70b |
08-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix a bunch of partially ambiguous patterns on ARM. As an
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
|
| 8e4674b1659726ad5a6ea240cc41160866b9dfc1 |
06-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial bits of ARMv4-only support.
Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| ce7bf1c55f5238870bae2909cd368151f1d813d1 |
06-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial bits of ARMv4-only support.
Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| 3a1e3927dabc414a5afa5b50a13b9aa170e162f6 |
06-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 epilogue code generation needs to take into account that callee-saved
registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97867 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| e68bd742451aae5fcdf280e823d2829e11d184da |
06-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 epilogue code generation needs to take into account that callee-saved
registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97867 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| fff9efb51e49e327acf6815063ba9c0c4a396e95 |
05-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Trivial comment change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fb86d78a45212b66c806a286a56bfd5d0ca77247 |
05-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Trivial comment change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ebdab78932b99809eb2eb2de9f1bbb1bb40e3d60 |
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 267124cff299922b3d92c5f2878fa285df2f1505 |
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 919644c45dccf74192347cc02c72e682069cdaf2 |
04-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6478: The frame pointer spill frame index is only defined when there is a
frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97755 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 436e6e7b5c85f12b7c2e41b7fd5c48e5d4d72912 |
04-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6478: The frame pointer spill frame index is only defined when there is a
frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97755 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b5a2ab22574a56127efcae74c69269e40f06d807 |
04-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| bbf39b0fd9c83f1d46ca5f858e66de66fb64ec98 |
04-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 97c362a27fe8b8f27837ec887b18d1257ff9e2e7 |
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0635fc5c2726bff3a6cbe91d2ad0f3bcda00671a |
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 09bb7a31c262d4e75a101084336c987f0085344b |
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97675 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| cb721da4c64bb9a844cf5180647dc926a5fd5f24 |
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97675 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 8cfa01cfb53183e28d45e72fba1099f5153c26d5 |
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
and STRHT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e54a3ef0873f0b298a9369fa0101c11230020cdb |
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
and STRHT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ed93c07fec80dfcc70cf62f1a6bd39f9bb0e5aa7 |
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97632 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0f7866e796a0fc66bafed36378df274aed18f4ce |
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97632 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 11fd549ebe3895b606a394ba8a0c239424b806cf |
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 506049f29f4f202a8e45feb916cc0264440a7f6d |
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 0129bca0bce1634150bc14700f8d1b4e750919e9 |
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unused instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| bc9d22c99a0a883cce88af37c1bd6746162df543 |
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unused instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3d48b87e20e053cd2ae6d72e99d6c690d243734d |
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a43398283dcb34568d2283dafbdfe0fa66b05033 |
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 306c6903936dbfa08d32c711025f9f3aba86711f |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 10a77e14a0b41ebb1c0ee9c07b28550d96acd60c |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0b4932e69129ab897d94cd68dea84d1da9a2481f |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b5031ad4c002004c919f9b42d754361cf53b7d51 |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8bec96d80e52207ad5840258d9aa60e3251ad154 |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 93042d1dc803b26c7dce7bb75858e6a8c721d9d0 |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 6d519bfe0bb32e61c60df9827f8b9b7d66dd3d78 |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
AL is an optional mnemonic extension for always, except in IT instructions.
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 9d3acaa1a015c4499595eaff529686a517c14e15 |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
AL is an optional mnemonic extension for always, except in IT instructions.
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 3b7450da0c5896e8d9e07723c07231d05bfb6162 |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Change some asm shift opcode strings to lowercase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97567 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7cfa51ebd8304eb565d8d6f2b1e50a55ef04d1ca |
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Change some asm shift opcode strings to lowercase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97567 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 33ddaa3abd51020af9a179e1a683282420098639 |
02-Mar-2010 |
Xerxes Ranby <xerxes@zafena.se> |
fix typo add missing (
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97565 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 901a8b7c6b2525889282add0d902ce46e111e0c2 |
02-Mar-2010 |
Xerxes Ranby <xerxes@zafena.se> |
fix typo add missing (
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97565 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| d572a01f9619b7b45c525a4d68f02164fcacf2ee |
02-Mar-2010 |
Xerxes Ranby <xerxes@zafena.se> |
Unbreak llvm-arm-linux buildbot and fix PR5309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97564 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 02735c97fd21f21ab6120aa3bd607b81d3bf5a3d |
02-Mar-2010 |
Xerxes Ranby <xerxes@zafena.se> |
Unbreak llvm-arm-linux buildbot and fix PR5309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97564 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 6411e3e62ea9dfe23f5fa24b9d6a84da7ec70a98 |
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7c306da505e2d7f64e160890b274a47fa0740962 |
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b99f6f386c561b66675f0b9798487d12ee7a1600 |
02-Mar-2010 |
Eric Christopher <echristo@apple.com> |
Only save vector registers if we've defined for the vector registers.
Fixes PR5309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97554 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 8d17882efae2706c4a7a09db28ef3abb66c9dce0 |
02-Mar-2010 |
Eric Christopher <echristo@apple.com> |
Only save vector registers if we've defined for the vector registers.
Fixes PR5309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97554 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 1ca34452bef99e9607f302b2abb54693b7114076 |
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 46ada19645c981a0b7932487d163f7582074a4d9 |
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e6f5471be802e40237d50eb52b6eab7c087966d9 |
01-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
bit should be set to 0 instead of 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| ad4df4c0da1a0e4b091321e1ffdc7973669e4273 |
01-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
bit should be set to 0 instead of 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 6debe022afbe5ada4c5cfda0876c3088c6061d33 |
28-Feb-2010 |
Dan Gohman <gohman@apple.com> |
The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| bc9d98b52d008d857c7423d7b43fb32022b926a2 |
28-Feb-2010 |
Dan Gohman <gohman@apple.com> |
The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 50528855a3a5fd32aefe594f573c51f7853583b3 |
26-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
|
| adc7733a64b65096cbd6066c212a9daa6e278a9a |
26-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
|
| cd9965a04d180996ce0aa277e567b3582dad4fd3 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6341c5a4c4019d4ff2a06bd69d4425324d6a7f81 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 99442df562535a009d0022cdadca78921977db31 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ce6275fd2ceae4cae7ac5c249e21de3d7527e9e2 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f1fab372d87dcebe635e465d3ba6ee6778dc4ba9 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2333655ed04637ffd049b9299685a0752aab8e8d |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 880d7af912e3067b30ec0f2029f453497f217cab |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
WFI, SEV, SETEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97149 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d86d269f08ec9a00bbceccef7d11fc430a8af76e |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
WFI, SEV, SETEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97149 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| fe73c98af21bccfaa2016ad98aabb10858a16f2c |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added tNOP for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97105 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| bd2c623903d4b9f4f1c8192bcf48811dbd3f7bc4 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added tNOP for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97105 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 145b5ebdaa64fccc0119b27fff04e9c253066c3d |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added tSVC and tTRAP for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97098 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 4c61cdd307929a125d1a503971a16cf55e31b252 |
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added tSVC and tTRAP for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97098 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 4460a1a06c2bff50f30edc9fe0f246640178192b |
24-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Create a stack frame on ARM when
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.
In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97071 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 657baec0af38d84e24e4738b0696bb99d1517179 |
24-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Create a stack frame on ARM when
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.
In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97071 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 9a176e2eda33ca927e76fe41fa77cbe2b32a4407 |
24-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97065 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e742bb53a3e68b88eac172782fd99cd98f89f4b3 |
24-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97065 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ed5852c5efc475390ab437324ecf9eff705f34a5 |
24-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
A8.6.405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97052 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d88360495a6eed8853b4eead04e163f3e5aa632f |
24-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
A8.6.405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97052 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| fc252708ccaa1eb067c6f04de7da7e5959cb8393 |
24-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97046 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 9e6396d05ee43858f04b0f52eb7da6240845f530 |
24-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97046 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3df03de89c640c257d95cfb8106de81621ae7c6c |
24-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed typo of opcodestr, should be "vst1", not "vld1".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97044 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 39b03163a7f639b1c75c348bec425c35dc89eba4 |
24-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed typo of opcodestr, should be "vst1", not "vld1".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97044 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| fb36419a8347792ab37b26caf44cf5e267f4ddfe |
24-Feb-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Remove an unused variable. Was this intentional?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97022 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ff28103b192a7e818f92628c2a4e34e622c1a142 |
24-Feb-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Remove an unused variable. Was this intentional?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97022 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 30c6aeb02e4f8bf3bbd5e34feccb757dbfc04365 |
24-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly VST1 (multiple single elements) which stores elements to
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.
A8.6.391 & A8.6.393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97018 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f50e83fd03f179616d030982efa7005640f03300 |
24-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly VST1 (multiple single elements) which stores elements to
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.
A8.6.391 & A8.6.393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97018 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c873ddd79ea24ebfd9a264ba33976d9015afad2b |
24-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
handle very large call frames when require SPAdj != 0 for Thumb1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97013 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 5f366af2ff36cc65fe4964194b07bf1455828ff0 |
24-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
handle very large call frames when require SPAdj != 0 for Thumb1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97013 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 731eb315ab273a47dc2eec2dc5bfd52f7a5a9288 |
24-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f9a4b7653d2a838b344dc3cd38b37f7803059d79 |
24-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 39fb124f7d1d3174623b0e673dcff44e4ddcfad5 |
23-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.
A8.6.307 & A8.6.310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d7283d9c54dbc45d47ee0fbed0fbdcbf0ae74f23 |
23-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.
A8.6.307 & A8.6.310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 84ce50ccaebfc2eb904791111dd03df750bde3a6 |
23-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Spelling. s/suppor /support /
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96954 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| cf453ee70a1ae03cc641686fd5db0f8a7d8ce250 |
23-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Spelling. s/suppor /support /
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96954 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c2b70b58adfcb26aab3142e234d48d12bfdf462c |
23-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
(immediate #0) for disassembly only.
A8.6.283, A8.6.285, A8.6.287, A8.6.290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96856 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 363ac58263dc4ce7c380bbaddb64f90b507fb16d |
23-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
(immediate #0) for disassembly only.
A8.6.283, A8.6.285, A8.6.287, A8.6.290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96856 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| fc9ef99541ff7370e20223d6d4c48473c6460d40 |
23-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VCEQ (immediate #0) NEON instruction for disassembly only.
A8.6.281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96838 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| ec5a4cd14c09e3d36b24411b8cd42166d91102f0 |
23-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VCEQ (immediate #0) NEON instruction for disassembly only.
A8.6.281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96838 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1ec98d37dba535b039287f750e7ec12363982f9f |
23-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.td
RMInstrThumb.td
|
| 4642ad3af1cf508ac320b9afd25b065f08b36574 |
23-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.td
RMInstrThumb.td
|
| f95d729f9e82f345ddc81a80b547fc7ce46ad799 |
22-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up a bit and fix for when SPAdj != 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96818 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 5a0815fae849038c0f125d04ea948785f52d35cc |
22-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up a bit and fix for when SPAdj != 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96818 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 4829e866c3939bd149a49420875bcacbc90570c4 |
22-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
The predicate index isn't fixed, so scan for it to make sure we get the proper
value.
Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96817 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 4c7628e43d8468f215ea345545479b6d728cee92 |
22-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
The predicate index isn't fixed, so scan for it to make sure we get the proper
value.
Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96817 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a21836942c9854fdfa3f42d52b255e83aa521a19 |
22-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,
for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2ec5e49a2ba3c8a6ea53c13d4393d57ad1dbb64b |
22-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,
for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3920088b8ff02e7c071399f3b6b7918a436ba27b |
22-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a bunch of instructions for disassembly only:
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96795 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 667d127b0bd0e78f135cd4c0d6adccf197b44e5b |
22-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a bunch of instructions for disassembly only:
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96795 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9699a91b4a682fb83ff5d4de72e558aa6ce5240d |
21-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Undo r96654. The printing of ARM shift instructions in canonical forms can be
handled in ARMInstPrinter.cpp.
And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96719 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b92a23fcfcd2578caa2fec8f2e85121f438d4658 |
21-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Undo r96654. The printing of ARM shift instructions in canonical forms can be
handled in ARMInstPrinter.cpp.
And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96719 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4a6943c195de8df683174628024411cb1eddfde1 |
19-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 1a2e8686f8137a1a2329952ffd1e21969ea1658c |
19-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 56164b0b017230d361a0c01174c8c8536f8136b1 |
19-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.
DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
asr r0, r0, #1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96654 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8f5e04098fe14d4a0e4da67b93ed471ba863e3e9 |
19-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.
DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
asr r0, r0, #1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96654 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 60f445031000f4a264412387932fce0de1000f00 |
19-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| cf43e60544041c127bb875fe4cf0d0ae96cd6c78 |
19-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 2c5c1378439260e8df3595f3096dd06dc6f2d339 |
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96619 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 39a4bb35276206d7ef0ff51dbc984aaf50bf659d |
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96619 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| bc1d2dcfe9ce42ee701fddbb6c5b36075bd97094 |
18-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 9f6c4c141ffa9c8b13e90dce2f2285c4479ff403 |
18-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| ac0ff71247e32d48f016df9eaa447d9591aec763 |
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96565 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| adb561d4e0a37c21159405dde90d2ef2d1a5eef9 |
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96565 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 1b082c721c530626062b2c34a9c1dc25255ad6d3 |
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly only the variants of DMB, DSB, and ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96540 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fd6037d6139e5d0055e94162aa140e61826b65e1 |
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly only the variants of DMB, DSB, and ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96540 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7c7fe6e9c7ad2188fadd64c563ccc0509fb57903 |
17-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the NEON N2VSInt instruction class: it's only used in one place and
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96525 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 69bfbd61c6a9f9f9a6fcddacc7a9be7e02ea9a2d |
17-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the NEON N2VSInt instruction class: it's only used in one place and
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96525 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d662e381a8a7db4cbb273e910c7e3e6240f5d915 |
17-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added CLREX (Clear-Exclusive) for disassembly only.
A8.6.30
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96523 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b94362791596962bc92b501d3c3150937058b3bc |
17-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added CLREX (Clear-Exclusive) for disassembly only.
A8.6.30
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96523 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 154999fd977eacbf89fc72ef54c6dab424d2e45e |
17-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
More cleanup for NEON:
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96521 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3c0f96e05472693ff9a59366726e4a3da5e05471 |
17-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
More cleanup for NEON:
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96521 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9412fa8811c0d7d10f439e74301ef81dcb564811 |
17-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added RFE for disassembly only.
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96519 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fb566795c6feccc2a931236fcf30e3b068933d7f |
17-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added RFE for disassembly only.
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96519 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4b6003e74ddabeff61557796af145fab66b3972c |
17-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add a note, from PR5100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96490 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7180f10fc78a0b8cdf93cc6293de977b6899f686 |
17-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add a note, from PR5100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96490 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8d0907fdc00c682257d92a7c4105ec1595e93c43 |
17-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added BFI for disassembly only.
A8.6.18 BFI - Bitfield insert (Encoding A1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96462 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b2503c096f46ff0c38b66b7bcc324e3a5ddc837d |
17-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added BFI for disassembly only.
A8.6.18 BFI - Bitfield insert (Encoding A1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96462 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1d2c421295cf9d1c57ecb4d4af34155f03de3ef4 |
17-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap lines to 80 columns and generally try to clean up whitespace and
indentation. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96418 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9abe19d0b9b36dc42d5ae94f7ef236f126da55c4 |
17-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap lines to 80 columns and generally try to clean up whitespace and
indentation. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96418 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| bb428439ec046b66fbe602e5c84d453e3fe8dc63 |
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle tGPR register class in a few more places. This fixes some llvm-gcc
build failures due to my fix for pr6111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96402 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 0eb0c7401c34c0b4604f732ce54db995eead14e6 |
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle tGPR register class in a few more places. This fixes some llvm-gcc
build failures due to my fix for pr6111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96402 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 33cb418af3a40f1789b18e92a8272ed73ac413e2 |
16-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add SMC (Secure Monitor Call) system instruction for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96401 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0296f3e50446094f5c484e155e8c1838eb9f5a0c |
16-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add SMC (Secure Monitor Call) system instruction for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96401 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6003048a50bbce4d7a087adb44bdcb5210d656e5 |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 80dc116ce3be18be2866db8fe13f03d1d6c4372f |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 09b5e1bbbf13cb871805093c5b166144123fc6fa |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 6417171026447cde57330114e7df2a22bebfc135 |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 2aad8d591862c1154522440f64f56456785d034e |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 39be8fcfdcad1b01997b22739a889d7c819600d5 |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 5104d8ace666d9bbe7ad02f5cadeea547dbb5a53 |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96383 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cd862b19b8348ad5bc21c9fa95d08427c86aa053 |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96383 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dba8f2c6b79a7c5312146027368cc64c2b5f290f |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates.
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.
This patch handles ARM mode. Thumb2 will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96381 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0a145f3d90033a69f3a2554d7a2da1834e4512f5 |
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates.
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.
This patch handles ARM mode. Thumb2 will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96381 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a6ad743a622db87dedff213307866b209517330e |
16-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly the following instructions:
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96380 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 64dfb7835df4705fd1cf07b53d8b4845a8f444f0 |
16-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added for disassembly the following instructions:
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96380 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8776f3e7190c4524d89f57463700fb30d8183b5d |
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr6111: Avoid using the LR register for the target address of an indirect
branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96360 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
|
| 1665b0a2246c83a2c123be105a1a167cf2b423fe |
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr6111: Avoid using the LR register for the target address of an indirect
branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96360 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.td
|
| df89a64cefcd537edf4f117eb777e476d97fe3bf |
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Put repeated empty pattern into the AQI instruction class.
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96297 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7dc9747e891a1d7945daad8d2752f2fc7d2ccf92 |
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Put repeated empty pattern into the AQI instruction class.
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96297 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 84d365c9f4cc0ea5e33f84c90732f69779bbcda6 |
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move TLOF implementations to libCodegen to resolve layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
smPrinter/ARMAsmPrinter.cpp
|
| 362dd0bef5437f85586c046bc53287b6fbe9c099 |
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move TLOF implementations to libCodegen to resolve layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
smPrinter/ARMAsmPrinter.cpp
|
| f80681ead6c31677f300779fe356c77e34678396 |
15-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 014bf215c3457bb34fee348265e8f63a70b4d503 |
15-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bec37592c754180c184384f5846600a9fc01a7bb |
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96230 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1b58cab38ca788be1e64815ab65dfd43e66c98b6 |
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96230 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2e3f1e5fe0eb1442b27411f372a5d26f72665fcb |
14-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Try to factorize the specification of saturating add/subtract operations a bit,
as suggested by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96153 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2faf3919d4a9f7dcd5cfae6ee447a650ffc6d40a |
14-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Try to factorize the specification of saturating add/subtract operations a bit,
as suggested by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96153 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8f3e19d0616863eabb4b29669ae3359b3fc0fbbb |
13-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add SETEND and BXJ instructions for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96075 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a1e762151029e95b949010be6ee2fa690c0055b1 |
13-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add SETEND and BXJ instructions for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96075 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7f8ae1bc1fd9ef029bc354361a41d1e2667367bb |
13-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach MachineFrameInfo to track maximum alignment while stack objects are being
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96069 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 7545f49a5edfe19612d03e683d8b955c03018056 |
13-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach MachineFrameInfo to track maximum alignment while stack objects are being
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96069 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8e1357046124234cb535d41ca107a26204a3d7dd |
13-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a bunch of saturating add/subtract instructions for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96063 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 08b85f371e036beb8b07ad58c4f53920be24ad2a |
13-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a bunch of saturating add/subtract instructions for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96063 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5a79afabd1dec640c140a60bc0d41c3415c363d8 |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96032 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| f4d81051ff40d9e4e71f0b1b84a85ed907076525 |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96032 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 61a8b753dabcf5b92517474a8cc0349ee4d82e24 |
12-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3f7aa79c2a46d525cf0468ad74ef2395246a309f |
12-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 100142226fff02a341cdb461ad668270f6524066 |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 83498e55e20077e2a6b05b335a62101b03ac44e0 |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1d7e5c88a3651508ee05a96448668c2b488a5091 |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96010 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b3e1bf54b29354c6d332cfaffcc86cd776fd4ca8 |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96010 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b868901a8b1424861085bce05a2c178de855f10e |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95999 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b98e16031841b3536a03ca4072fb241ff32c517e |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95999 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| edf090c9115caf0d31e418b008129dd26275b37b |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
MRRC, MRRc2. For disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 906d57ffe826c29eeedc1d4f77542fd3f2349b8f |
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
MRRC, MRRc2. For disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b47fed8f78bf9f246d28ab6be8f32ec656aee210 |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95916 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e4c7f0f6ec2fdc1b58541dab4445761a5e9c6e2a |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95916 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7253c40c9d802b329111f1239fcd313c8adda05b |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
Sorry!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95892 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 811663f799ce1af18ef704fab14afc02ac94b652 |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
Sorry!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95892 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 3dd3f8084d1ed8e41148e832ae34aeedf90329de |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VCVT (between floating-point and fixed-point, VFP) for disassembly.
A8.6.297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95885 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 27bb8d0a88538eeb20436457922e21e196519ced |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VCVT (between floating-point and fixed-point, VFP) for disassembly.
A8.6.297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95885 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 37dfb594fc90df6710810b997ccc076625030bfa |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95884 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| c6f7b27fdab506bc15d6e5f356adf1e455d1d571 |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95884 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 44ad4432391ed496f24adc1da7a327815f404520 |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
as the "Permanently UNDEFINED" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95873 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ba6e033f4f2b22dce4766a55dead8385a955fd46 |
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
as the "Permanently UNDEFINED" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95873 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e264f62ca09a8f65c87a46d562a4d0f9ec5d457e |
10-Feb-2010 |
Shih-wei Liao <sliao@google.com> |
Check in LLVM r95781.
RM.h
RM.td
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMBuildAttrs.h
RMCallingConv.td
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMExpandPseudoInsts.cpp
RMFrameInfo.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMJITInfo.cpp
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMCAsmInfo.cpp
RMMCAsmInfo.h
RMMachineFunctionInfo.h
RMPerfectShuffle.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMRelocations.h
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
RMTargetObjectFile.h
smParser/ARMAsmParser.cpp
smParser/CMakeLists.txt
smParser/Makefile
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
smPrinter/CMakeLists.txt
smPrinter/Makefile
MakeLists.txt
akefile
EONMoveFix.cpp
EONPreAllocPass.cpp
EADME-Thumb.txt
EADME-Thumb2.txt
EADME.txt
argetInfo/ARMTargetInfo.cpp
argetInfo/CMakeLists.txt
argetInfo/Makefile
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
humb2SizeReduction.cpp
|
| 1b6d4f77e6d40ba50c62972d9aae398f56670d19 |
10-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95784 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 85d5a89f8d03f5b4beb6c68f1ea9283e0dbb3594 |
10-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95784 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 726d397a8cc48a5cb5d2f8a0fe10f7f17f7d4afc |
10-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
print all the newlines at the end of instructions with
OutStreamer.AddBlankLine instead of textually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95734 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8e089a9e4d6b7aa2b3968c38644f926f60a7c670 |
10-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
print all the newlines at the end of instructions with
OutStreamer.AddBlankLine instead of textually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95734 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7c313be63eda14427fe2dbf0bffbf3f8d5b509a2 |
10-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add VBIF/VBIT for disassembly only.
A8.6.279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95713 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4814e711ab64cab1d241a97476a905f1d8136877 |
10-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add VBIF/VBIT for disassembly only.
A8.6.279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95713 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1bfdc7451f08f0dca69098474b3dcb69ddb04659 |
09-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VMRS/VMSR for disassembly only.
A8.6.335 & A8.6.336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| c9745049e6df8dbf56061a75b5d070b16331428f |
09-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VMRS/VMSR for disassembly only.
A8.6.335 & A8.6.336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 4052b296030e3523b9a4a8d1e4a9af9091a8d7e8 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
|
| e560a78d3626c2accf49cf38f3c90c53d516b9a0 |
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Radar 7417921
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95686 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
humb2SizeReduction.cpp
|
| 4152778605dcab9e650b2cd03e2d8dc12f20aff6 |
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Radar 7417921
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95686 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
humb2SizeReduction.cpp
|
| 2e1f0096d3d4b0f0bb2f0b80da30a52ef79bf8b3 |
09-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added vcvtb/vcvtt (between half-precision and single-precision, VFP).
For disassembly only.
A8.6.300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95669 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2d658df87300704ca5dbc902bf97b906b90418e0 |
09-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added vcvtb/vcvtt (between half-precision and single-precision, VFP).
For disassembly only.
A8.6.300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95669 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 230ef32a135d8999407d312daaafe5affe8ca1f7 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
this is done, tested by CodeGen/ARM/iabs.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95609 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| c133457269306ef8fa45b4e8990bc462e710feaf |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
this is done, tested by CodeGen/ARM/iabs.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95609 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8d96fc111c1e6d2467e71ad576a379d71ce523cc |
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
tighten up eh.setjmp sequence a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| a87ded2695e5bce30dbd0d2d2ac10c571bf1d161 |
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
tighten up eh.setjmp sequence a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 00b26de3dedf0164ca10a377b3f49b687c327175 |
08-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add VCVTR (between floating-point and integer, VFP) for disassembly purpose.
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.
A8.6.295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95584 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 15b423f7724a0a8ae657f7b66fb090d68008182d |
08-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add VCVTR (between floating-point and integer, VFP) for disassembly purpose.
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.
A8.6.295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95584 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 714b9c72ac64734e04efa36fa4913265c64decbb |
08-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95560 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7edd8e38c4ad710cd5158de2ffa8eb92b4527375 |
08-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95560 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| bbe7726eb81a82e657e3882611e96693fffd260e |
08-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 23401d6f8c9e488aac9a70c1639bcaec0dd75458 |
08-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 49b02f29a6277220befb8fe6841713ad4dfff9c2 |
06-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
Radar 7614112.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95456 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| e6373eb8264ba4804de28d8224e9f7725d3a483c |
06-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
Radar 7614112.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95456 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 92a90ab2be83ad2671669d69555252d3b0fe914c |
05-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95397 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7acca6707bf91173bc1c5970bffc0ed55b285f85 |
05-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95397 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7765306eef752f506f6d2720de53dc14197b3cfc |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
make MachineModuleInfoMachO hold non-const MCSymbol*'s instead
of const ones. non-const ones aren't very useful, because you can't
even, say, emit them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95205 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d269a6e460a71a6c5c361a26c56c91fdb9486f45 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
make MachineModuleInfoMachO hold non-const MCSymbol*'s instead
of const ones. non-const ones aren't very useful, because you can't
even, say, emit them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95205 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ba4a4b0033dcc771f78db2ff1d1638ad35e876cc |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
print instructions through the mcstreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95181 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 850d2e2a1b58ea30abed10ca955259d60d07d97a |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
print instructions through the mcstreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95181 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0c920438c1f21ee6d9befa4aac8b884b8cafbc9c |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
rejigger the world so that EmitInstruction prints the \n at
the end of the instruction instead of expecting the caller to
do it. This currently causes the asm-verbose instruction
comments to be on the next line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95178 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d1ff72b8a797304f146e4293db8c814231ea8cb3 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
rejigger the world so that EmitInstruction prints the \n at
the end of the instruction instead of expecting the caller to
do it. This currently causes the asm-verbose instruction
comments to be on the next line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95178 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ff259dbe71427fbe989d2f886f08c00e369df771 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
sink handling of target-independent machine instrs (other
than DEBUG_VALUE :( ) into the target indep AsmPrinter.cpp
file. This allows elimination of the
NO_ASM_WRITER_BOILERPLATE hack among other things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95177 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 0d883e3f8484491d010b8f8b7a1aecc58cb5fa8e |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
sink handling of target-independent machine instrs (other
than DEBUG_VALUE :( ) into the target indep AsmPrinter.cpp
file. This allows elimination of the
NO_ASM_WRITER_BOILERPLATE hack among other things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95177 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
|
| 876e7f04bbe49f63030a1164b42a8e3b8004cb24 |
03-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
As of r79039, we still try to eliminate the frame pointer on leaf functions,
even when -disable-fp-elim is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95161 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 985d45dea357cbfe718b89cebd84b20b1298ab93 |
03-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
As of r79039, we still try to eliminate the frame pointer on leaf functions,
even when -disable-fp-elim is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95161 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ff116f99c64e1ca085c9d1387f7bd6eb8e4dbd67 |
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 8d2970ba91fc2161bf5fc3d073a59cd4f3dc45a6 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor code so that LLVMTargetMachine creates the asmstreamer and
mccontext instead of having AsmPrinter do it. This allows other
types of MCStreamer's to be passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95155 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 56591ab218639d8a6e4c756ca37adaf20215c3b6 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor code so that LLVMTargetMachine creates the asmstreamer and
mccontext instead of having AsmPrinter do it. This allows other
types of MCStreamer's to be passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95155 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5e78e7e610cd34c0573c64e857d0aee6b44d7e8b |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
tidy some targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95146 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
|
| 55fed86353fb39924378dc0e5d29cb273f5e2138 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
tidy some targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95146 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
|
| 11d88be3b07e41ef0eec781cd2fff01d25039c89 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
detemplatize ARM code emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95138 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 33fabd7cc17c60a066c2891244a376684d774fc9 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
detemplatize ARM code emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95138 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| a06694d3d85c7a604ef0068b687cd5f28a903173 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95134 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| e0faa547059c8d10cf34e63ea26a994291116228 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95134 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 503c48cbce6bbaeae5d0c8277b15172074630e2e |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate all the dead addSimpleCodeEmitter implementations.
eliminate random "code emitter" stuff in Alpha, except for
the JIT path. Next up, remove the template cruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95131 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| f1d6b107d2ea4518d240ee93bf4bffd53e71206d |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate all the dead addSimpleCodeEmitter implementations.
eliminate random "code emitter" stuff in Alpha, except for
the JIT path. Next up, remove the template cruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95131 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| ca6c93430e98e3fb0eaf40aa543ea1dc45cf35d7 |
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ad3ead17205f81df0a39562f15b30909c328ee22 |
02-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95112 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9474d550ff8d2be251792cf21f777d85e052ed5e |
02-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95112 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ba9fbe717cae724f48ffb4a38bac0b3e8f866540 |
02-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a
Rn operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95025 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 92e63d817f9aa35afc5e37af8fa31e22463e61c4 |
02-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a
Rn operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95025 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9063a77c72cadae2d09ab225884b5bee4aaca1be |
31-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 48d5ccf86a74fe13597e651ead3670acda115497 |
31-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94955 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 75761f371d323e7a24951c03b52515d7a000bddd |
30-Jan-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 90cfc130d618ecb0539e475c343ed805ee124f8d |
30-Jan-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f363f2bb1168133f7cace650666001cbdf1f02d8 |
30-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified encoding bits specification for VFP instructions. In particular, the D
bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94855 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 69a8c7f497b5686d55798a0aa4663a6e0d5bc12b |
30-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified encoding bits specification for VFP instructions. In particular, the D
bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94855 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 1d40b3738f819d8cfb67b6b71d83642036388cd0 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Give AsmPrinter the most common expected implementation of
runOnMachineFunction, and switch PPC to use EmitFunctionBody.
The two ppc asmprinters now don't heave to define
runOnMachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94722 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d49fe1b6bc4615684c2ec71140a21e9c4cd69ce3 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Give AsmPrinter the most common expected implementation of
runOnMachineFunction, and switch PPC to use EmitFunctionBody.
The two ppc asmprinters now don't heave to define
runOnMachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94722 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d2f089fa97185c4659d22de5dc7bb36a7c54b05a |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
switch ARM to EmitFunctionBody().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94719 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a786ceac5c888761d83d84d35eb16150be57cc6e |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
switch ARM to EmitFunctionBody().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94719 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d7dede2bdd47620b6f8ac8e3f72d454bac8c1005 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Remove the argument from EmitJumpTableInfo, because it doesn't need it.
Move the X86 implementation of function body emission up to
AsmPrinter::EmitFunctionBody, which works by calling the virtual
EmitInstruction method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94716 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 14c38ec2afeaf25c53a50c2c65116aca8c889401 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Remove the argument from EmitJumpTableInfo, because it doesn't need it.
Move the X86 implementation of function body emission up to
AsmPrinter::EmitFunctionBody, which works by calling the virtual
EmitInstruction method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94716 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8559cf724e8fb6a74ee227709b3a634edb2f46b4 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Drop the argument to AsmPrinter::EmitConstantPool and make it virtual.
Overload it in the ARM backend to do nothing, since is does insane
constant pool emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94708 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a2406190ca28dc5901dfe747849c8eda9c29d7ee |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Drop the argument to AsmPrinter::EmitConstantPool and make it virtual.
Overload it in the ARM backend to do nothing, since is does insane
constant pool emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94708 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0ee0d725fafc774958582e21d94929d79aa6086f |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
switch ARM to use EmitFunctionHeader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94703 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 953ebb769ada06d22f8ae4963651530b9cb84830 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
switch ARM to use EmitFunctionHeader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94703 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a42ba8245c295afa5e6feac6e4b3f6e853f3e319 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the ARMFunctionInfo::Align member, using
MachineFunction::Alignment instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94701 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMMachineFunctionInfo.h
smPrinter/ARMAsmPrinter.cpp
|
| 7d7dab02783fb4f1f5d0cf274c52a4fb059bfbea |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the ARMFunctionInfo::Align member, using
MachineFunction::Alignment instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94701 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMMachineFunctionInfo.h
smPrinter/ARMAsmPrinter.cpp
|
| 62de4e7b460f8ffbe0ee71a5a09503790102943f |
27-Jan-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Kill ModuleProvider and ghost linkage by inverting the relationship between
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94686 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| f0356fe140af1a30587b9a86bcfb1b2c51b8ce20 |
27-Jan-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Kill ModuleProvider and ghost linkage by inverting the relationship between
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94686 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| e3781183a5499329db1165cfa732f13adf9dcbe4 |
27-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust setjmp instruction sequence to not need 32-bit alignment padding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94627 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb.td
|
| c90a153ad04a2f0cc212c5bc7206d655807b90e0 |
27-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust setjmp instruction sequence to not need 32-bit alignment padding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94627 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb.td
|
| 6b6ed5994d4c2be6e2087a969b35f55226d82608 |
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| fa5b938385d54d51a5b8cfa5487eff0a4599f755 |
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
constify a method argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94612 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 30c6b75ac2eef548c18110a38c9798ea5314caba |
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
constify a method argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94612 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 5e969572f5b9e519eb01837cd84f129e46b6b892 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Eliminate SetDirective, and replace it with HasSetDirective.
Default HasSetDirective to true, since most targets have it.
The targets that claim to not have it probably do, or it is
spelled differently. These include Blackfin, Mips, Alpha, and
PIC16. All of these except pic16 are normal ELF targets, so
they almost certainly have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94585 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| cee63322eaccc2f1067bdf5eab506e440f867da1 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Eliminate SetDirective, and replace it with HasSetDirective.
Default HasSetDirective to true, since most targets have it.
The targets that claim to not have it probably do, or it is
spelled differently. These include Blackfin, Mips, Alpha, and
PIC16. All of these except pic16 are normal ELF targets, so
they almost certainly have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94585 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 8fd77a1841661ee1254e50baf3afb58cb0a395b7 |
26-Jan-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF.
Original patch by Sandeep Patel and updated by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94582 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 2e2563bf8e0f0a7f8c923000c0206855f16968b2 |
26-Jan-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF.
Original patch by Sandeep Patel and updated by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94582 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 3036c9be66d46f9c44cf75f7c6d449653b8c0892 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
don't set to the default value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94580 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| b3732fbabdab453a17a74f0fcce507d9567b8d6b |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
don't set to the default value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94580 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 84d5ca9524a5d23f88083d0663ee99dca739df21 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a new MachineBasicBlock::getSymbol method, replacing
the AsmPrinter::GetMBBSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94515 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| f71cb015c1386ff8adc9ef0aa03fc0f0fc4a6e3e |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a new MachineBasicBlock::getSymbol method, replacing
the AsmPrinter::GetMBBSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94515 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 74da888bd8c3d6bb980bb95ec0bc5bc57d6b9157 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
don't bother setting the AsmPrinter::MF ivar, now that
AsmPrinter::SetupMachineFunction sets it. Note that systemz
and msp430 didn't. Yay for reduced inconsistency! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94510 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1e459c446786f46ed865183f1c6adb17e2e8fcea |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
don't bother setting the AsmPrinter::MF ivar, now that
AsmPrinter::SetupMachineFunction sets it. Note that systemz
and msp430 didn't. Yay for reduced inconsistency! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94510 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9e096318a10b4ea3c03f16bdb8b8d151c3713f6f |
26-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Minor jump table cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94475 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1f9b48ad87a5dab4a6c3805c369414c831e4451d |
26-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Minor jump table cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94475 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c42059f02ee4a9a96916652703345d58e1be2fce |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
fix quoting problem jim noticed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94472 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 281e7767df71b3f727ade80a16ff0c4fe5a49dd9 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
fix quoting problem jim noticed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94472 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b10c7e2e10bb899f1f48cd33195c68b31ecc2db0 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
prep work to support a future where getJumpTableInfo will return
a null pointer for functions with no jump tables. No functionality
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94469 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
|
| b1e803985d3378538ae9cff7eed4102c002d1e22 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
prep work to support a future where getJumpTableInfo will return
a null pointer for functions with no jump tables. No functionality
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94469 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
|
| 7e51ffddf94162f3c6d9c0b8379dc1983b2110fe |
25-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| aeb326aad70acd1dd8b08564be4165eabc9ef542 |
25-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| c6f0f30bb97c21286e49c6b5b91999c1012de275 |
25-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Implemented ARMInstPrinter::printThumbS4ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94457 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 541ba7dd9269a67e3f1da5e0add7bbddcb6b4f9d |
25-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Implemented ARMInstPrinter::printThumbS4ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94457 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 1b457cbee9b748a30b56c63c8a75a86cc13ea0f5 |
25-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94455 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| e43b6c9695f2489b69aa9ea798f3c9e281c16239 |
25-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94455 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| c180db2ec498bf68f38b7aca097f6bf0350f9e5d |
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mcize jump table symbol manipulation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94441 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0890cf124f00da3dc943c1882f4221955e0281ed |
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mcize jump table symbol manipulation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94441 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ccda1400e725df3834ab6b552c0e00e956687ebd |
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
sink an arm specific method out of asmprinter into the ARMAsmPrinter and
rename it to avoid shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94440 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| bfcb09688c7db15a9f9415d717a5a31c499a2208 |
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
sink an arm specific method out of asmprinter into the ARMAsmPrinter and
rename it to avoid shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94440 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8a747eeebfadc7bbd7de8218cbd0d4208bbb9345 |
25-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM does accept the .comm directive alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94408 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 546ae6ec7793470cfb176d8e9c518bd14340d8d8 |
25-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM does accept the .comm directive alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94408 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 473d2db15ef81ae8c07079ea3f9721a150f212e9 |
25-Jan-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix PR6134.
We are not emitting alignments on Darwin for "bar". Not sure what is the
correct way to do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94400 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| f166ed7324d3708a74231f9f86fd148f811038a7 |
25-Jan-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix PR6134.
We are not emitting alignments on Darwin for "bar". Not sure what is the
correct way to do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94400 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| e9a40677cd1fd95ed7e9b75a1df19449f432ad9e |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94378 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/Makefile
smPrinter/Makefile
akefile
argetInfo/Makefile
|
| 43b5f9312d56be400af031f7487a99b75b7b0f97 |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94378 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/Makefile
smPrinter/Makefile
akefile
argetInfo/Makefile
|
| d70deeb19ecfe335eb475df22a1411e9e6927a44 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mcize lcomm, simplify .comm, extend both to support 64-bit sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94299 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 9eb158d5b4cd4f6fc80912e2dd77bdf13c3ca0e7 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mcize lcomm, simplify .comm, extend both to support 64-bit sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94299 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 3e99011e0d264e0e0e44dd638777ecb29101ad12 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94296 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1b46f433e02155daba8ed3b1269c86ce63c9713b |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94296 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2d7c8149c012f5f600b61339a9ba590c850693ef |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move the various directive enums out of the MCStreamer class
into a new MCDirectives.h file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94294 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a5ad93a10a5435f21090b09edb6b3a7e44967648 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move the various directive enums out of the MCStreamer class
into a new MCDirectives.h file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94294 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5c804558fe5a69a7534b8a3bb7420ec1a483a1c8 |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Stop building RTTI information for *most* llvm libraries. Notable
missing ones are libsupport, libsystem and libvmcore. libvmcore is
currently blocked on bugpoint, which uses EH. Once it stops using
EH, we can switch it off.
This #if 0's out 3 unit tests, because gtest requires RTTI information.
Suggestions welcome on how to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94164 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/Makefile
smPrinter/Makefile
akefile
argetInfo/Makefile
|
| e73a31f667ad2fe03e25c97ac45b58c30d7f07c3 |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Stop building RTTI information for *most* llvm libraries. Notable
missing ones are libsupport, libsystem and libvmcore. libvmcore is
currently blocked on bugpoint, which uses EH. Once it stops using
EH, we can switch it off.
This #if 0's out 3 unit tests, because gtest requires RTTI information.
Suggestions welcome on how to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94164 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/Makefile
smPrinter/Makefile
akefile
argetInfo/Makefile
|
| 291d6690fd435a775e00003e8b6237d2882011fd |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
create a new MCParser library and move some stuff into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94129 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c6ef277a0b8f43af22d86aea9d5053749cacfbbb |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
create a new MCParser library and move some stuff into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94129 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 40e4b11b7d72d126588a54f2247dee5b855e574b |
22-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
EADME.txt
humb2SizeReduction.cpp
|
| d5d2baec2609da3ade9ca205e87c88d35e9e6976 |
22-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
EADME.txt
humb2SizeReduction.cpp
|
| 939a31427d4d23ad68c2919bb8002e15a9fe5a2f |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
inline and radically simplify printDataDirective. It will eventually
go completely away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93994 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ea3cb40fab5dc84caa0c6c6bcb650261b4b6e724 |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
inline and radically simplify printDataDirective. It will eventually
go completely away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93994 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 50f82ef05abe8d27ecb77f6ffa1bcefb51e383c4 |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
revert 93934, removing the MCAsmInfo endianness bit. I can't
stomache MCAsmInfo having this, and I found a better solution to
this layering issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93985 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 8eeba35babf3114966fc4e6e8522057e46b610db |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
revert 93934, removing the MCAsmInfo endianness bit. I can't
stomache MCAsmInfo having this, and I found a better solution to
this layering issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93985 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| a703be764c744c8643098db9ffa9f103ef39384a |
19-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap some comments to 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cb9a6aab02f07cda005c7c078d8e4a3463017866 |
19-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap some comments to 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93940 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a918216872b12caa3613c08266cfd59a1849c7af |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
give MCAsmInfo a 'has little endian' bit. This is unfortunate, but
I really want clients of the streamer to be able to say "emit this
64-bit integer" and have it get broken down right by the streamer.
I may change this in the future, we'll see how it works out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93934 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| c7b8814bb4f2e6052060d6118d3bc3b66f5c5b0b |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
give MCAsmInfo a 'has little endian' bit. This is unfortunate, but
I really want clients of the streamer to be able to say "emit this
64-bit integer" and have it get broken down right by the streamer.
I may change this in the future, we'll see how it works out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93934 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
|
| 3cc5fa0acaa893d9dc5fb52229b0803d3ed60922 |
19-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Promoted the getTok() method to MCAsmParser so that
the two token accessor functions are declared consistently.
Modified the clients of MCAsmParser to reflect this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93916 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 18b8323de70e3461b5d035e3f9e4f6dfaf5e674b |
19-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Promoted the getTok() method to MCAsmParser so that
the two token accessor functions are declared consistently.
Modified the clients of MCAsmParser to reflect this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93916 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7d8eb70d8d0a68e31d0860c22c227eff56ab6f23 |
19-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove predicates when changing an add into an unpredicable mov.
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 35f0febcb66b5a50a5a750efcbefc95f7fc25c7b |
19-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove predicates when changing an add into an unpredicable mov.
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 34b4a466415f98a648ea594f950cb2fdca2dadd2 |
19-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Propagated the parser-side Lex function's declaration to
MCAsmParser, and changed the target-specific AsmParsers
to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93900 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| b9a25b7744ed12b80031426978decce3d4cebbd7 |
19-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Propagated the parser-side Lex function's declaration to
MCAsmParser, and changed the target-specific AsmParsers
to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93900 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a71dc60dc2bb5a154d9195dfe2d3126f7c7967d5 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Generalize mcasmstreamer data emission APIs to take an address space
identifier. There is no way to work around it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93896 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| aaec205b87637cd0d59d4f11630db603686eb73d |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Generalize mcasmstreamer data emission APIs to take an address space
identifier. There is no way to work around it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93896 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e9b2eed90ebc564917e62f79a5da0a72c394aadf |
19-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
For aligned load/store instructions, it's only required to know whether a
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMTargetMachine.cpp
|
| e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3 |
19-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
For aligned load/store instructions, it's only required to know whether a
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMTargetMachine.cpp
|
| 30a4ee2219f496f9e1ffbf0b68f6c312580c12ef |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
zap the ARM version of PrintGlobalVariable, which I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93863 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8ad9a775019c69a07bb8258f7ff2849d594956df |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
zap the ARM version of PrintGlobalVariable, which I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93863 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| bc6b5f6b1a84d6d193b13d1ca63476fee0b6e15b |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
some cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93853 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cfd910ebc459776c326b1bdb47e25ae056a6c734 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
some cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93853 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 41e516af8959ebc60606dc7cc6f95c5c29fea000 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a bool for whether .lcomm takes an alignment instead of basing this on "isdarwin".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93852 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7517b249caa793a9a01e4b6aff9c47fd88a153cc |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a bool for whether .lcomm takes an alignment instead of basing this on "isdarwin".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93852 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d960947255c0e5d28eab6d76a02222133af1f1f6 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
hoist handling of external globals and special globals up to common code.
This makes a similar code dead in all the other targets, I'll clean it up
in a bit.
This also moves handling of lcomm up before acquisition of a section,
since lcomm never needs a section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93851 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 48d64ba9d846229339b2431b298620cb8a01ffc5 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
hoist handling of external globals and special globals up to common code.
This makes a similar code dead in all the other targets, I'll clean it up
in a bit.
This also moves handling of lcomm up before acquisition of a section,
since lcomm never needs a section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93851 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2f2fe05fa39eac3b0067ccadd5dd8c985d5a09fe |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move production of .reference directives for static ctor/dtor list on
darwin into common code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93849 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 71eae713153e564ec743c5c4162ff258c255de78 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move production of .reference directives for static ctor/dtor list on
darwin into common code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93849 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 53f7eef9b27fda28dc68672bb9261f1611bad972 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use BSSLocal classifier to identify 'lcomm' data instead of
duplicating the logic (differently) in lots of different targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93847 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c1ef06ac5264cb43f148590091606f0ed90a72e9 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use BSSLocal classifier to identify 'lcomm' data instead of
duplicating the logic (differently) in lots of different targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93847 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c07400c8451d6706a8581814784f17f1bcf027a2 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that elf weak bss symbols are handled correctly, simplify a bunch of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93845 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 56b1319fbe18e886f7cff415b45df404fac39623 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that elf weak bss symbols are handled correctly, simplify a bunch of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93845 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9b7400533f5a2ff9aa2d7bdd899be05dccb033e3 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
introduce a section kind for common linkage. Use this to slightly
simplify and commonize some of the asmprinter logic for globals.
This also avoids printing the MCSection for .zerofill, which broke
the llvm-gcc build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93843 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a3839bc3714e6a84222f45cf4c0f1a20a88b10cd |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
introduce a section kind for common linkage. Use this to slightly
simplify and commonize some of the asmprinter logic for globals.
This also avoids printing the MCSection for .zerofill, which broke
the llvm-gcc build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93843 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 63b6b4e7fc5da5205de4875363e8c2110611b35f |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change an accessor to a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93839 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6e3be14be4eadd9aefea654611c808eea9eb8aea |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change an accessor to a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93839 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 87edd27219b2b1e80ff485be96b91a733aeb4a32 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Cleanup handling of .zerofill on darwin:
1. TargetLoweringObjectFileMachO should decide if something
goes in zerofill instead of having every target do it.
2. TargetLoweringObjectFileMachO should assign said symbols to
the right MCSection, the asmprinters should just emit to the
right section.
3. Since all zerofill stuff goes through mcstreamer anymore,
MAI can have a bool "haszerofill" instead of having the textual
directive to emit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93838 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| aac138e84dee1cb3ffc1035b2a1e4361fe0b4f80 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Cleanup handling of .zerofill on darwin:
1. TargetLoweringObjectFileMachO should decide if something
goes in zerofill instead of having every target do it.
2. TargetLoweringObjectFileMachO should assign said symbols to
the right MCSection, the asmprinters should just emit to the
right section.
3. Since all zerofill stuff goes through mcstreamer anymore,
MAI can have a bool "haszerofill" instead of having the textual
directive to emit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93838 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d7da8fccf37c8a2e08e2095ce2436fae4b67866e |
19-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| f609bb8466e28ef63eb4db9de485583c6d5b8bc9 |
19-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 46e4380ba4fd91d54cee4970dc2c586ee1dd6ad0 |
18-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Minor cleanup for jump table printing. Need a reference, not a pointer, for
printing via <<. Otherwise we just print the pointer value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93777 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6a19947dd6b4e180017acec351d33edb7b40361b |
18-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Minor cleanup for jump table printing. Need a reference, not a pointer, for
printing via <<. Otherwise we just print the pointer value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93777 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b48276c7037cde3426aadc00b0e6b960c506a808 |
18-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch). Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93759 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| eb231ce51dcbcbd464fa639f0dc0d2e39d487285 |
18-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch). Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93759 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| f1f92ff1dc0ef8a055d567db9aa7cbf338649849 |
18-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Patch by David Conrad:
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 3482c8003ad0c88469b7333aaf658036e3fd0468 |
18-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Patch by David Conrad:
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 82dcfa3215e4390287f194f33a0183c5d14a17a2 |
18-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Emit spaces after commas in Neon register lists. This is more consistent
with the rest of the assembly output, is easier to read, and matches the
expected output for gcc's Neon tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9fedc33ca8af58cbb2c0b405ef40e8d486f2f64b |
18-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Emit spaces after commas in Neon register lists. This is more consistent
with the rest of the assembly output, is easier to read, and matches the
expected output for gcc's Neon tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93703 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1e9a11b57bff0f237a15b2b67eafd71a1e220aa4 |
18-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
remove the MAI argument to MCExpr::print and switch overthing to use << when printing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93699 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 8cb9a3b13f3226b7e741768b69d26ecd6b5231f1 |
18-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
remove the MAI argument to MCExpr::print and switch overthing to use << when printing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93699 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| ce40984980d8cc39e903382478c111d967aed337 |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that MCSymbol::print doesn't use it's MAI argument, we can
remove it and change all the code that prints MCSymbols to use
<< instead, which is much simpler and cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93695 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 10b318bcb39218d2ed525e4862c854bc8d1baf63 |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that MCSymbol::print doesn't use it's MAI argument, we can
remove it and change all the code that prints MCSymbols to use
<< instead, which is much simpler and cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93695 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a21a9cc099e960134a6221445baff1d4aa9a50fc |
17-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
The Neon "vtst" instruction takes a suffix that is the element size alone --
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax. This helps us pass a few more
of the Neon tests from gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93677 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3a4a832223e5649d97587e1be1e2d83f94a4baaa |
17-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
The Neon "vtst" instruction takes a suffix that is the element size alone --
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax. This helps us pass a few more
of the Neon tests from gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93677 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 207fc5bdaa92d75a059ce6da9f9751bca15cc780 |
17-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix an off-by-one error that caused the chain operand to be dropped from Neon
vector load-lane and store-lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 507d32aad2152a9b889df085feca2f653925456c |
17-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix an off-by-one error that caused the chain operand to be dropped from Neon
vector load-lane and store-lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a6f2a103c7713d0184ef7a6c6b1933db3547b3e2 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
rename GetPrivateGlobalValueSymbolStub -> GetSymbolWithGlobalValueBase,
and add an explicit ForcePrivate argument.
Switch FunctionEHFrameInfo to be MCSymbol based instead of string based.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93646 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7a2ba94d03b43f41b54872dacd7b2250dde4c7bd |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
rename GetPrivateGlobalValueSymbolStub -> GetSymbolWithGlobalValueBase,
and add an explicit ForcePrivate argument.
Switch FunctionEHFrameInfo to be MCSymbol based instead of string based.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93646 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 86974d4af1c5f4fbdd5ad2f1a271bafa78e276a7 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate uses of mangler and simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93615 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.cpp
|
| 9ab19f25aaca858928901f9c520c666a4c815ebd |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate uses of mangler and simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93615 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.cpp
|
| 651adf3e889d924389d6230602083c6e9bae794b |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
MCize a bunch more stuff, eliminating a lot of uses of the mangler
and CurrentFnName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93594 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 12164414dd3daa6974985eeb2e89bfb93cf07641 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
MCize a bunch more stuff, eliminating a lot of uses of the mangler
and CurrentFnName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93594 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 67cce68221c693cd2c80cf2a16b626b6abfc67e6 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a version of AsmPrinter::printVisibility that takes an MCSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93587 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 53d4d78d9a2c26a67ac8f6e81cc149702103fc2c |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a version of AsmPrinter::printVisibility that takes an MCSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93587 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0028c84401fcd8d2e6f9acc50c1ffbbc2172bea8 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use MCSymbol instead of getMangledName() in all cases except one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93582 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| f0aacf8201d96da7d56181e5d02af711e5f8128d |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use MCSymbol instead of getMangledName() in all cases except one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93582 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3ec04731eb45adb6622a62456d1bc605711c5f42 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mc'ize a bunch of symbol stuff, eliminating std::strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93578 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8b3787586ed92df55131ad38c16646b7eba401a0 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mc'ize a bunch of symbol stuff, eliminating std::strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93578 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2eb781d9dee5c87fd2efac8dac12ae47c4526544 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a AsmPrinter::GetGlobalValueSymbol and GetExternalSymbolSymbol
helper method, use it to simplify some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93575 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6b04edee11c2bb35a48b1c42f867b4ba8cdfff97 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a AsmPrinter::GetGlobalValueSymbol and GetExternalSymbolSymbol
helper method, use it to simplify some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93575 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 45c45c8f43de3a269381f4e155e428abce7e4488 |
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Update Thumb1 storeRegToStackSlot() and loadRegFromStackSlot() to properly
handle physical registers R0-R7 when described as having a non-tGPR register
class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93564 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 98793b9468a242348879334c5821fb6b5c784517 |
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Update Thumb1 storeRegToStackSlot() and loadRegFromStackSlot() to properly
handle physical registers R0-R7 when described as having a non-tGPR register
class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93564 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| c1e662a6d626833993e5640b9ffd1a74ea74501a |
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Name change for consistency. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93480 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 867bbbfff7752b86be14f38644599e9da88a5f78 |
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Name change for consistency. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93480 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3cb6277d7f2dd5b0d47a327b4c5d1fa8188e28ae |
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5efaed3bf46c829ff8767fd804815c5471f83310 |
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2786524f204eda405c56041c0f01921d52a5f0ef |
14-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
the disassembler can properly decode Load/Store register/immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93471 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 51bc5612b3aa7685774c7fea856297f5276ffd3e |
14-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
the disassembler can properly decode Load/Store register/immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93471 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 22f480d087d3d436ba0103347b148de68eb7363b |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Split the TargetAsmParser "ParseInstruction" interface in half:
the new ParseInstruction method just parses and returns a list of
target operands. A new MatchInstruction interface is used to
turn the operand list into an MCInst.
This requires new/deleting all the operands, but it also gives
targets the ability to use polymorphic operands if they want to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93469 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9898671a74d3fc924347e679c45edaa685b3fe6e |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Split the TargetAsmParser "ParseInstruction" interface in half:
the new ParseInstruction method just parses and returns a list of
target operands. A new MatchInstruction interface is used to
turn the operand list into an MCInst.
This requires new/deleting all the operands, but it also gives
targets the ability to use polymorphic operands if they want to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93469 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f66e4ebbdc4bf8d6d48f3d17c4595824c95bc180 |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes in TargetAsmParser.h
Pass in SMLoc of instr opcode into ParseInstruction.
Make AsmToken be a class, not a struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93457 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| f007e853e26845cd6866b52d646455fc69f4e0af |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes in TargetAsmParser.h
Pass in SMLoc of instr opcode into ParseInstruction.
Make AsmToken be a class, not a struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93457 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6fdd73946f6584c82bfa00168917d7f8c32f4c77 |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
introduce MCParsedAsmOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93455 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7659389d0d4d315d30877592221da6a6f663114a |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
introduce MCParsedAsmOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93455 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| df0cdf4e5721593c1315edf47f3b96021767895a |
14-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARM "l" constraint for inline asm means R0-R7, also for Thumb2.
This is consistent with llvm-gcc's arm/constraints.md.
Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93436 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 09bf003983bb35190ce9932c4edc9a7635f379c0 |
14-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARM "l" constraint for inline asm means R0-R7, also for Thumb2.
This is consistent with llvm-gcc's arm/constraints.md.
Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93436 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 99fc640242e391ba584711dc5f80780a90e8f5e4 |
14-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't fold insufficiently aligned ldr/str into ldm/stm instructions.
An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.
This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.
Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93393 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 069e100f9a79a63db177a521fd790f4d77d1209c |
14-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't fold insufficiently aligned ldr/str into ldm/stm instructions.
An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.
This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.
Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93393 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 12dc2ed67ddc67d4c40a0bb5f7ec5b5abe886d6b |
13-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93349 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 12360917ef08364050ef134ed70c69136465eaba |
13-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93349 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c7ef3b239ed85144a2e3e0aa3fa50a8be5b1a9fa |
13-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix pasto
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93342 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 15913c999e5fb03cd26de00a48dd3cf1780ffb43 |
13-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix pasto
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93342 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 52f39f00b758593f7c4c0b9f0f831b3e7fbd0d9e |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
upgrade and MC'ize a few uses of makeNameProper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93310 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 09533a404c7a80c1ca619c627bfc636b243ecd16 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
upgrade and MC'ize a few uses of makeNameProper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93310 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a38b287aec4e06a2aded8bc7809f0f949955ade5 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change Mangler::makeNameProper to return its result in a SmallVector
instead of returning it in an std::string. Based on this change:
1. Change TargetLoweringObjectFileCOFF::getCOFFSection to take a StringRef
2. Change a bunch of targets to call makeNameProper with a smallstring,
making several of them *much* more efficient.
3. Rewrite Mangler::makeNameProper to not build names and then prepend
prefixes, not use temporary std::strings, and to avoid other crimes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93298 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4813035b726e7f0a3fd17bec437185fc72a50988 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change Mangler::makeNameProper to return its result in a SmallVector
instead of returning it in an std::string. Based on this change:
1. Change TargetLoweringObjectFileCOFF::getCOFFSection to take a StringRef
2. Change a bunch of targets to call makeNameProper with a smallstring,
making several of them *much* more efficient.
3. Rewrite Mangler::makeNameProper to not build names and then prepend
prefixes, not use temporary std::strings, and to avoid other crimes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93298 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1b584eb1eca786cfbdf36dbdc6d35dde13f10185 |
13-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the JustSP single-register regclass.
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93280 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMRegisterInfo.td
|
| c5b7ef1519807c05ac30af982f49abd555f03177 |
13-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the JustSP single-register regclass.
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93280 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMRegisterInfo.td
|
| c514d692bcfe7b3cf718fabc08de624f155813a8 |
08-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Minor change, change the order of two "let Inst{...}" stmts within multiclass
T2I_bin_ii12rs definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93006 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d248ffb7d57cc7aa4216b79741b372026936ea0a |
08-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Minor change, change the order of two "let Inst{...}" stmts within multiclass
T2I_bin_ii12rs definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93006 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5a1410489f9f35c3fd9d3c8425b522d41309985d |
07-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92876 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 9631864688c593711f82bb8d21f8b724c628d786 |
07-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92876 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d13c6ce32c2de48b62b925999174028150222ce7 |
07-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 30ac0467ced4627a9b84d8a1d3ca5e8706ddad63 |
07-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 9b2e3114be9dc39a2d95cd4f50fb2591ba3fda47 |
07-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Addressing mode 6 (load/store) instructions can't encode an immediate offset
for stack references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92871 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ce3e769c15be90463abf14bb71b5a8e1205d3661 |
07-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Addressing mode 6 (load/store) instructions can't encode an immediate offset
for stack references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92871 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a9aeaea8a97c346c50f6069ecba1a31c84017831 |
05-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Undo r92785, it caused test failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92796 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 83142991613730bc857739c6179660ccffebe379 |
05-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Undo r92785, it caused test failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92796 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 71c64a11a03ed4e78ac67b4a01c79f09e6bdcbe9 |
05-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add Rt2 to the asm format string for 32-bit Thumb load/store register dual
instructions. Thumb does not have the restriction that t2 = t+1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92785 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 83f1136cfdbfb6ccbdcd23f1f6e35b72bfaeb306 |
05-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add Rt2 to the asm format string for 32-bit Thumb load/store register dual
instructions. Thumb does not have the restriction that t2 = t+1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92785 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5f082a7df38fa6d7b53c0d7baeca8d74f097d659 |
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| eeb3a00b84b7767d236ec8cf0619b9217fc247b9 |
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 572d6dca91884892cde12d9cde0c79261f52131f |
28-Dec-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add missing include (for inline PATypeHolder::get).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92222 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e55b15fa4753ef08cbfa2127d2d220b77aa07d87 |
28-Dec-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add missing include (for inline PATypeHolder::get).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92222 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| f504c9b27cd0b72be034e59419e711dcf3c24383 |
28-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92193 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 9bf50f45e7f1ea82b391673b8e0903b5c4e2460c |
28-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92193 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 2a377215b3f9fda270997eb1643d5c8c2e0ed45b |
28-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "ATTRIBUTE_UNUSED" macro (and use it). It's for variables which are
mainly used in debugging and/or assert situations. It should make the compiler
and the static analyzer stop nagging us about them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92181 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 079b6f5ee5c3516b773a3ad71874c14e8ea7479c |
28-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "ATTRIBUTE_UNUSED" macro (and use it). It's for variables which are
mainly used in debugging and/or assert situations. It should make the compiler
and the static analyzer stop nagging us about them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92181 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a39e3180c2b9c8debfbdc77d1726f9f23b70ec90 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move kill flags when the same register occurs more than once in a sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92058 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 1dbc38f52e2d6436ba79048013e42d96187993d8 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move kill flags when the same register occurs more than once in a sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92058 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 1342a3e9465505305d72800dcb2479d35ccfe3b5 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle undef operands properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92054 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 158a2263bd221a6920c6c7f7f96d6272344efb8f |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle undef operands properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92054 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| cad17d74d47071cbcc4c8e0797b08a0abb7e1c83 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make insert position available to MergeOpsUpdate.
Rearrange arguments.
No functional changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92053 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 6528966eaeaf38244ce165ef7c80326aa34a55ca |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make insert position available to MergeOpsUpdate.
Rearrange arguments.
No functional changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92053 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 22f06b0197c781a49b3d76550cdf09070b7c2f07 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Perform kill flag calculations in new method. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92052 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3063aed8d29cf2418fc1c3022a3dd9c8de0e4922 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Perform kill flag calculations in new method. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92052 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 16d776db31bc211a9f97844bb0f6c32ec21d9d9c |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move repeated code to a new method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92051 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| f8e33e513f2620ea30fda7f17bc227729b7621b8 |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move repeated code to a new method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92051 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 7db0c5186ca4472324f3a7723c0879814fead47d |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a SPR register class to the ARM target.
Certain Thumb instructions require only SP (e.g. tSTRspi).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91944 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMRegisterInfo.td
|
| 24b34f8f3e301cce56be80dfa9a28a3dc8e0270a |
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a SPR register class to the ARM target.
Certain Thumb instructions require only SP (e.g. tSTRspi).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91944 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMRegisterInfo.td
|
| f0039ba077d1a149bab0a3099556adeb802657f8 |
22-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use proper move instructions. Make the verifier happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91914 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| e9912dc553bf7e37494eb9b07e8ff880f0481a56 |
22-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use proper move instructions. Make the verifier happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91914 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| aa18176a76f0e31db7af3973c7ca6072f1c15318 |
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d |
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9ea182b5db526734a15b5fcdca13cb8dd77e78e2 |
21-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Delete the instruction just before the function terminates for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91836 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 102ebf16b6eb46e3021b9e8db8a1bc163bc64639 |
21-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Delete the instruction just before the function terminates for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91836 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8cb4138c0eca1101911d01679a35a9013a73fd78 |
19-Dec-2009 |
Douglas Gregor <doug.gregor@gmail.com> |
Fix a bunch of little errors that Clang complains about when its being pedantic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91764 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| cabdd7425d30f7eb659ecb0cc5efbc4052dd78a8 |
19-Dec-2009 |
Douglas Gregor <dgregor@apple.com> |
Fix a bunch of little errors that Clang complains about when its being pedantic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91764 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 6d10effe861d12574c3285e8e31f704107aba3ba |
18-Dec-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix libstdc++ build on ARM linux and part of PR5770.
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.
Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.
For a patch that make us detect problems like this earlier, take a look at
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html
With that patch we assert as soon and the new instruction is added to the garbage set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fda60d35c247c239857ebaae8650b06f1154e68e |
18-Dec-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix libstdc++ build on ARM linux and part of PR5770.
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.
Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.
For a patch that make us detect problems like this earlier, take a look at
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html
With that patch we assert as soon and the new instruction is added to the garbage set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4a463881df0d3cb915f252f12958eeda9256445d |
18-Dec-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5afffaed5c0095930020947322633f0d0b02ffed |
18-Dec-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8ae68e420a7fd0e4bc77674860a3d2fb619a3b15 |
17-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| caedfbc6ae4cf039721fcfdb6fb16b4e78002500 |
17-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0be22d12589480b482126c2d8eb816a9590d54d8 |
16-Dec-2009 |
John McCall <rjmccall@apple.com> |
Silence a clang warning about the deprecated (but perfectly reasonable in
context) increment-of-bool idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91564 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 6eeccd4aa4f332bc60ae120ea5753a4020b75a61 |
16-Dec-2009 |
John McCall <rjmccall@apple.com> |
Silence a clang warning about the deprecated (but perfectly reasonable in
context) increment-of-bool idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91564 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 724d7a167ac9c576db2e9217adfbee9ac8cd7b24 |
16-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Mark STREX* as earlyclobber for the success result register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 587b072f23789010ee20a487cca458a0e724c6ed |
16-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Mark STREX* as earlyclobber for the success result register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| aa640d3fc7563e889ef2ef93994b4c6ff38933f1 |
16-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| bbc71b2904644bfa85d8785328dc08d61c534467 |
16-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| b6bf5b926d84470a0527691b20f60c31f6bf7978 |
16-Dec-2009 |
John McCall <rjmccall@apple.com> |
Every anonymous namespace is different. Caught by clang++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91481 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| bd13cb911cb40ac6a82db12deaef775a9d19ff4b |
16-Dec-2009 |
John McCall <rjmccall@apple.com> |
Every anonymous namespace is different. Caught by clang++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91481 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 43a22289bdf5f2e1d884de469b9ab5b849c077b7 |
15-Dec-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91464 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 32d7e6ebde29faeea75ecb718b4281414b0eea0b |
15-Dec-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91464 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 0d810c281064e69c6a0cab4f9f43870628628566 |
15-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added encoding bits for the Thumb ISA. Initial checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| d68e119c0fea54f47d0f3f0b5282dcf6cd19d8b9 |
15-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added encoding bits for the Thumb ISA. Initial checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| e6e14f2cfc4e8bd346bf3fa7a5ac87b6ebf422ff |
15-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
nand atomic requires opposite operand ordering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91371 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c67b556b5b9c45f393e62fa7ffd4c70b932af2be |
15-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
nand atomic requires opposite operand ordering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91371 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6fdbe657ebacf9e1bdb1e2cebfe82a9549d86d3e |
14-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
between BR_JTr and STREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ec689151f29d328e9edcea2740c3a1d978aab6a6 |
14-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
between BR_JTr and STREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91339 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ba16e07fc539e23bb604defb021187e64c04702a |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
v6 sync insn copy/paste error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91333 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 80dd125e173e059783afef782df2ab895c643da5 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
v6 sync insn copy/paste error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91333 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6eee903ab286e1a0093c5091bb30fc35e00cd86b |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add ARMv6 memory and sync barrier instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 7c03dbd8ede6f43063df56eaa6d63f7ae1721892 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add ARMv6 memory and sync barrier instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 8ac1d378d72ad45806ab86d316bd50ca5e7f861c |
14-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Fixed encoding bits typo of ldrexd/strexd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91327 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c474796438beebe6928ff154b5fa53cb98107867 |
14-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Fixed encoding bits typo of ldrexd/strexd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91327 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5b595cd6311d7b9670268b69096b55dd1a384d35 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91321 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a36c8f2c2e6a20080e6784a73e30fc2c8c67c584 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91321 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2d6e24935ebc8902bd9b22f73ba02fa31d60f8bb |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| a623f5a58dd7768b0cf4dbb61b1fffa8b4d07cca |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| efbc1f057fd24bd540ab94dfcac298d6762aa3bd |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
add Thumb2 atomic and memory barrier instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91310 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c219e4dd5919e2b72b80698fd50aa05e1580a55b |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
add Thumb2 atomic and memory barrier instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91310 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 31b2740914c8fec8580a8dc1000e3b5295309dfb |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91307 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 015d3b570412588241599bee0ef3400354666785 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91307 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 63437d96828f86ca3833c58964c4a5d4b142aa07 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
ARM memory barrier instructions are not predicable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91305 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| f6b2862e813cd75e337238bb3321d3a512b54f06 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
ARM memory barrier instructions are not predicable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91305 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| c83030d61279ac68b9532896fea512ae408387de |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
add ldrexd/strexd instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91284 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d7d72d66b799aaab1c48a67a0cbb5c9a70794cec |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
add ldrexd/strexd instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91284 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c7e4ddcbcad547e5513dfd7eefe8c1ae97e84485 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
atomic binary operations up to 32-bits wide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91260 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c3c2354ec9b56c3097752537020150da8694dd62 |
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
atomic binary operations up to 32-bits wide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91260 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 241896971376c9bf4b5856c44c65084c8bf6e3cb |
12-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Framework for atomic binary operations. The emitter for the pseudo instructions
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| e801dc4a7b89f68f40ff2753de988c482d4d117f |
12-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Framework for atomic binary operations. The emitter for the pseudo instructions
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| c6095894e7cd3c7144575ba6e2596bb5a3d3adc0 |
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91150 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c8f9e4fdc584c6bf48dc0f42083d05b707024b20 |
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91150 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7e6324988a184400c4a79d684746f91c3c5bfad3 |
11-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91143 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 0291d7ed0942b218c58ddd900a8f6b3dd80ad023 |
11-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91143 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 7853967b2bec37e6093fa595cc42aabbad964059 |
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Update properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91140 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 66869104dd67a5d01347c29f7499c4836c59fd0a |
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Update properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91140 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 437d699dc2b7e690254435cb93d7bbd21bb88217 |
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
|
| 5278eb802fae2ee1a7b2a428596bc364d8bcd9db |
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.td
|
| 37582c3385a5259c279f4da155b7659f4272ff71 |
10-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add instruction encoding for DMB/DSB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91053 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cbd77d2cb1812ad142412fa0a16d835fa468efe4 |
10-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add instruction encoding for DMB/DSB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91053 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ba744f662e83517b2b940145a24d6cbb453f52f9 |
10-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91003 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 3728e96a6c0f68f4f5b656c2372e9cbbe6e74d86 |
10-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91003 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 9e5c8a8cdfc3a0267b026851bf08a9507474578e |
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Support inline asm 'w' constraint for 128-bit vector types.
- Also support the 'q' NEON registers asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| d831cda3e74235704f163d5a18352584d537517a |
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Support inline asm 'w' constraint for 128-bit vector types.
- Also support the 'q' NEON registers asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| f7374f702cd95402ff597457c8b3772cf3770ecf |
06-Dec-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Dynamic stack realignment use of sp register as source/dest register
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 7cca606aaa6fee6ff4f548aa3686608b6be1f208 |
06-Dec-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Dynamic stack realignment use of sp register as source/dest register
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 01696988ff3c98744cce105372803d4ed903f988 |
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| d003075f1b3921f20ac9da8e0310afa4cd9b2f04 |
03-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
remove out of date FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90490 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 4dc4a61c0c47611fef23e06145ece9f63b2a8dc6 |
03-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
remove out of date FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90490 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 12fac174a70da350938ffa425d60e5f314ca5a8d |
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
fix a build problem with VC++, PR5664, patch by Alp Toker!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90419 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 56856b1f46ec1f073ceef4e826c544b8b1691608 |
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
fix a build problem with VC++, PR5664, patch by Alp Toker!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90419 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 171422980d99d7689b2cac01504b981e87b61905 |
03-Dec-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize canonical forms of vector shuffles where the same vector is used for
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 324f4f163350487243d3a93b2a79f5eb2edc3b03 |
03-Dec-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize canonical forms of vector shuffles where the same vector is used for
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b44b429549bc4c4f950d56d4f6fa0ba486856cc6 |
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 7896c9f436a4eda5ec15e882a7505ba482a2fcd0 |
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMExpandPseudoInsts.cpp
RMLoadStoreOptimizer.cpp
EONMoveFix.cpp
EONPreAllocPass.cpp
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 4d20ee6d9a35d9498ad170c55ba714b346237a55 |
02-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Factor the stack alignment calculations out into a target independent pass.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90336 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseRegisterInfo.cpp
RMTargetMachine.cpp
|
| e27d205d5d4d53cceabcd6325533fbdf9c0cee42 |
02-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Factor the stack alignment calculations out into a target independent pass.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90336 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseRegisterInfo.cpp
RMTargetMachine.cpp
|
| a0fb7c4e1ae9b7c87037bc6a72adce439d23484c |
01-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 exception handling setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90246 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrFormats.td
RMInstrThumb.td
|
| d122874996a6faa8832569b632fd73a32ace7ae7 |
01-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 exception handling setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90246 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrFormats.td
RMInstrThumb.td
|
| 6e1b1ad3abeb24f6da12afe63ac7a1074c1e3dbf |
01-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90243 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b731e876498dd07308e35a03329cbf0801c0b882 |
01-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90243 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| cf4fad276042adc440ff0d119b9fb67a94814ccf |
01-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90173 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 208d76cad96da282a9d9c6631dd34b3d50742262 |
01-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90173 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 90868102bf6144cae08570ddcb96099d9d63c06d |
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMSubtarget.cpp
RMSubtarget.h
|
| 15217e63bce6c161b355b63d6496c7c327d15817 |
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMSubtarget.cpp
RMSubtarget.h
|
| 3bff42e81121019af3ba61a13f087bba6ed37c54 |
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix some more ARM unified syntax warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90141 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| afa1df467b04182c959e6c3031df5377a0062153 |
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix some more ARM unified syntax warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90141 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 68722a84a011e2e2a8be3b3c6a09a2bbb477d390 |
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor target hook for tail duplication as requested by Chris.
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89814 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| f8c4cfb7cc330234112e1378dac6424d9956add0 |
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor target hook for tail duplication as requested by Chris.
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89814 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 6b2b23a3569d8cefb165601454cc1dede80d30d6 |
24-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable predication of NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| d7f0810c934a7d13acb28c42d737ce58ec990ea8 |
24-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable predication of NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 9f433ab362f406dc8336ae2445bcfebbd133a8a1 |
24-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Data type suffix must come after predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89723 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 9d172d5ee779124a721a01f7db1ab3a41593e7b5 |
24-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Data type suffix must come after predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89723 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| a414f36ad4dca3554e1313a4715b3856ac4066b9 |
24-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
humb2SizeReduction.cpp
|
| 5cdc3a949af0cef7f2163f8a7acbf3049c226321 |
24-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
humb2SizeReduction.cpp
|
| 71465ac298b594109d9f6e9c8b4fc97051840a8b |
24-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80 column violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89718 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6935efcb667bcd4dd3a00bbd420461e1fadba73a |
24-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80 column violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89718 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f8f9acf65f39634e24604568f1cab3cca14ff18b |
24-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
* Move stub allocation inside the JITEmitter, instead of exposing a
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89715 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
RMJITInfo.h
|
| 108c838093704650378b194fe9afc5ebb9e91455 |
24-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
* Move stub allocation inside the JITEmitter, instead of exposing a
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89715 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
RMJITInfo.h
|
| c61b56c8b54d3abdf197464c00ea9b3613aa5889 |
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMISelLowering.cpp
RMInstrInfo.td
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMISelLowering.cpp
RMInstrInfo.td
|
| 89acd2fc3e3c28cedeb8f5b5d5d378425b6d2f49 |
23-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Allow more than one stub to be being generated at the same time.
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89708 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 0261d795f83a45dd53d82e511ae672d6d1f4e298 |
23-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Allow more than one stub to be being generated at the same time.
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89708 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 09c61b35e2c8a6cf9bcdf42f8d07a8ac26238eac |
23-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89706 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| f81bf15552d3df7dd341e3970a002b9e35ea4992 |
23-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89706 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 8d450b25083d0f488b2e797e79eb92172eb2c48d |
23-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
move fconst[sd] to UAL. <rdar://7414913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smPrinter/ARMAsmPrinter.cpp
|
| 77b02beb1fa3a96efc05081889d1ae4ffecb44a7 |
23-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
move fconst[sd] to UAL. <rdar://7414913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
smPrinter/ARMAsmPrinter.cpp
|
| 9ee642f0b2272dab1086aa3421d1958e63a066f6 |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89699 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| da1aea4d7551d05cfb28a565b9750b7965cd620a |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89699 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 66e70cdbb4097df5f9f9341663441fc431015307 |
23-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89694 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 15e6ef886deedafaf3fcbca8226891ba54dbff9d |
23-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89694 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 6c6fa9a41918f91b9ea6765cfc0eb566e68b2de0 |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89693 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| b16ed11cb4ca0a55647335847bd69a3810290be9 |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89693 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 46f784e7a92f51878af9c6c0cdb8312b2d188303 |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Partially revert r89377 by removing NLdStLN class definition from
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89684 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 7ebd32a1b87553d98215ae159489c1407e50e34c |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Partially revert r89377 by removing NLdStLN class definition from
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89684 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 0c1d2c1183243d983ee60d2fa0e30c1aef4981f4 |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
should be left unspecified now that Bob Wilson has fixed pr5470.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 131c4a525791c8178d693917bcf3a248028dfeff |
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
should be left unspecified now that Bob Wilson has fixed pr5470.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| dfaea1cb45cae9e1ca8dd6b3398ab39dbab074d3 |
23-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Minor itinerary fixes for FP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89672 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| 7776452a181202397fc1d70fab059f0faaafe0c7 |
23-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Minor itinerary fixes for FP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89672 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV7.td
|
| afc3436c0a1089f70f879e539a464a6ac281ba21 |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89618 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a37aa546224ec03ba1f1a1598e0781af4b692673 |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89618 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 5902f6d18693f3a787615a98e7d3e36b8888ce62 |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Generate more correct debug info for frame indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89576 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 50f8516d2dd87e6c02a46fa349b75101f9db8619 |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Generate more correct debug info for frame indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89576 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| eee8617c0f283222d9f2f0d9b24c9ff0b2eb7d9e |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Revert 89562. We're being sneakier than I was giving us credit for, and this
isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 21ce2e3c74d3b64a9dafde190d18dbf3aa003112 |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Revert 89562. We're being sneakier than I was giving us credit for, and this
isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 3af6d702411a66e6d02ebfc566083fb78336d5e3 |
21-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Darwin requires a frame pointer for all non-leaf functions to support correct
backtraces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| f3b33d0b2a50777ddb467e8adefbb018b16570d2 |
21-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Darwin requires a frame pointer for all non-leaf functions to support correct
backtraces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 67abceccf77faa1bbaab2e22c4d7e173927ee12e |
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
EONMoveFix.cpp
|
| ac0869dc8a7986855c5557cc67d4709600158ef5 |
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrNEON.td
EONMoveFix.cpp
|
| 1432b62b04c33ad89f4249ef73f2e73740db18c7 |
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bef8888a9197655512f156e50b10799da7240252 |
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2f6bfd4a20638089c8d00a40c2f4cd9e8b63e691 |
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remat VLDRD from constpool. Clean up some instruction property specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 4aedb61d039580113982827e397d3ebbd0e0dbba |
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remat VLDRD from constpool. Clean up some instruction property specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| b3de86391c62a6519caa0d6ea12197326efbb793 |
20-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
The verify() call of CPEIsInRange() isn't right for the assertion check of
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89473 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a9562568e5c2a897e3a51b18700eeb70f0dda48c |
20-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
The verify() call of CPEIsInRange() isn't right for the assertion check of
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89473 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 871fc2c9d35287f0feaeb077f4ce892da9436d06 |
20-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Remove verifySizes() since it's not adding much value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89443 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| de8b1dbf95811fa2fc38bd677453f75811eb1029 |
20-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Remove verifySizes() since it's not adding much value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89443 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ef4c5b2c4971e741cd583f5c351e8328e72e93fa |
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also CSE non-pic load from constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 9b82425cb0105fd5704f6b9bcd5e7693b05b1759 |
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also CSE non-pic load from constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 69aaa0084163fa280cdae34786d3dd67695753c9 |
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9ef4835bd879e1baa5f59619b958cae57d516481 |
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 0fbd6ad19b836a8138007e82176581755e206c7f |
20-Nov-2009 |
Eric Christopher <echristo@apple.com> |
Update comment to reflect instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89414 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 0dde97156ce75d14498185e34c5d20c66a0c38d1 |
20-Nov-2009 |
Eric Christopher <echristo@apple.com> |
Update comment to reflect instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89414 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| ca890b1973ef53d6c7ece027c037f6de1260cb4b |
20-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
When placing constant islands and adjusting for alignment padding, inline
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89403 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 4d8e90a026a29a812616690bd77b72e0b5ae6c75 |
20-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
When placing constant islands and adjusting for alignment padding, inline
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89403 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 3327e8265b77a0ddf6d59dfb891cd311c571ac91 |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor cmov selection code out to a separate function. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89396 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 07ba906413ed0e8e196a6795665f349ba8fdca4c |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor cmov selection code out to a separate function. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89396 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9a5dc8bb0dbc4fab3b9594c9a94edcb82e5f6eac |
19-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89377 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 5c376ff9f08513686293b26c86b2c116b976d6b9 |
19-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89377 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 49f755b9ed789fa5088c1340e5c9d7b026c89263 |
19-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89369 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| dec6de92d1425c88f319179fb4a0b0a23f781df9 |
19-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89369 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| cc7bfb11acd970d4cd4da36ae281065b22be5123 |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89337 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| ed54de40a712ab6471a6c369e30d827017a67757 |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89337 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 91fd9e4f6f0cd25369fafa3a81312fba451519cc |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
More consistent thumb1 asm printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 2ef9c8a43d1030bf65cafedf4b4b3f04d30180ce |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
More consistent thumb1 asm printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 8ec49859a25324df48adf6b899d26b679e7a6ab2 |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89326 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 5b397c93a50a44e3bfc58bd8fd95357c0cba3f1e |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89326 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 462517808063f450416dd5693adbc31293e9ba9a |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate more * 4 in Thumb1 asm printing for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89325 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a64ce4591762b93030cd2a2ff202bbd5badfecdd |
19-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate more * 4 in Thumb1 asm printing for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89325 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| eb368aa30f54a1388c341e6f443c9c6f96216fdc |
18-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Add ARMv6 itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89218 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMScheduleV6.td
RMScheduleV7.td
|
| ebb5cb92169a04dd94fa65ae18aead271db3a4e5 |
18-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Add ARMv6 itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89218 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMScheduleV6.td
RMScheduleV7.td
|
| ecce4b7c8a9afdf9ca01e9c017871492a406ebfe |
18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a few places that were missed when we converted to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89214 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a3003004aa70f068cdc64389ea2379f9c019ff49 |
18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a few places that were missed when we converted to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89214 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 19194a2f4d58b62e438b2c28f4b42966931cd397 |
18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a target hook to allow changing the tail duplication limit based on the
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMSubtarget.cpp
RMSubtarget.h
|
| 834b08af8d3d8fc6c76ac6ca40674565689e8d7f |
18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a target hook to allow changing the tail duplication limit based on the
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMSubtarget.cpp
RMSubtarget.h
|
| 35ccbb7056c9c20ecc158d701fb3b00fdd795601 |
17-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable arm jumpt table adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89143 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f04777b945e272ccec21c7080bd5480d78a14fd2 |
17-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable arm jumpt table adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89143 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| aa4af890f3ecfcb21e9a0ce4f21304aec7fa087d |
17-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6
alignment imm (in the same way). Fix asmprinting for non-darwin platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89137 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| bce3dbd9be29a42f32eb888086050cd620f2133b |
17-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6
alignment imm (in the same way). Fix asmprinting for non-darwin platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89137 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3f6474095adef9b9dc65ef94b481785caa086ea7 |
17-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
distinguish between them and the more generic instructions (add, mov, and ldr).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a9ea9ec1941a97b27355da704a3ac8ecd27e87c4 |
17-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
distinguish between them and the more generic instructions (add, mov, and ldr).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89108 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bd75ded296f631b4b59f5461340de1e1a2beae01 |
17-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
When moving a block for table jumps, make sure the prior block terminator
is analyzable so it can be updated. If it's not, be safe and don't move the
block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89022 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a0a95a3c1cea79757854cf39ba07734b39e2b0e9 |
17-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
When moving a block for table jumps, make sure the prior block terminator
is analyzable so it can be updated. If it's not, be safe and don't move the
block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89022 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ff43a627bcc5f09f467393f4041d8969efe87949 |
17-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89000 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 9d52e8db8acaa3326c5a7674959ecdacbceb916a |
17-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89000 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7fcb07aa007c643df80ffaac78ed860fe7c0ceea |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Make the pass class name more explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88964 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 7bde2971330d8d64d6650d002db9c1ce77f4e4d4 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Make the pass class name more explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88964 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6b4b40736acfba22d0befa1badf2b3f851e53c13 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
make pass name a bit more clear
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88961 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 074fb0252d20dfc4b03bc902b94e11d9cd8592d8 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
make pass name a bit more clear
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88961 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 896373b0146c9a789b003bb7a15618747db484bb |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Simplify thumb2 jump table adjustments. Remove unnecessary calculation and
usage of block sizes and offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88935 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 08cbda56b6a45a2c29bdf3d9668ad614ad86cb77 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Simplify thumb2 jump table adjustments. Remove unnecessary calculation and
usage of block sizes and offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88935 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 98f9f85767a7837d985e0dc421ea825f14469378 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
clarify comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88933 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9249efe4c7451e83fb4c904fd7fcc8edfe08d815 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
clarify comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88933 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| fad80ae623fc6897ea32966208814e9a4c70802e |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
back off for a bit. tracking down weirdness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88919 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b2e86bb142c882c68c54723f65c572def9bf77cc |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
back off for a bit. tracking down weirdness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88919 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 313cc22c734cfef8794dbfaf8a4ac9040a5cd9f6 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88917 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ca215e7804ca5d85e19e31850c3ba3d155624e89 |
16-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88917 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 860fb5bb3ded49293473d043b5206742c14b3476 |
15-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMTargetMachine.cpp
|
| a44321776ecd96fa0344335d3027758be3386e45 |
15-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMTargetMachine.cpp
|
| 4b93798c0fd881d607fba728f7c138f8def59315 |
15-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
set the def of the VLD1q64 properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88873 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 6cb6788b79bcec64886880697fc69b82a296f671 |
15-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
set the def of the VLD1q64 properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88873 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b4b383b2502314ea3868c5646d201ba463974752 |
14-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88812 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9c477f54f3c3e2541205f24bfe89b22da7b6e096 |
14-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88812 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1b8810510f177de84116be20460126c81b4e2575 |
14-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88805 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 00a6a1f0225b01229134ecee7a853be638703c36 |
14-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88805 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a88d1acbaefb5416a147dcdd2199bb43ab70983d |
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
|
| d57cdd5683ea926e489067364fb7ffe5fd5d35ee |
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
|
| 770b4d6907dab297589a12d3bf89f926c0b400e9 |
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 0cd22dd7383111192571884eb941ac2ccb668025 |
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ca9b04ba02e321977d03e79a5bbd4c95eb23a0d8 |
13-Nov-2009 |
David Greene <greened@obbligato.org> |
Move DebugInfo checks into EmitComments and remove them from
target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88697 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1924aabf996be9335fab34e7ee4fa2aa5911389c |
13-Nov-2009 |
David Greene <greened@obbligato.org> |
Move DebugInfo checks into EmitComments and remove them from
target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88697 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e6e30350b685bd4c9eddf4a88cb5dac41ee61eb8 |
13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 |
13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 08ca9519152539cb987a447473da7bffb0ddada1 |
13-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Block renumbering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87056 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| c1a07be185d50fb3201782e4c832356f612480fb |
13-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Block renumbering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87056 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 0b6f987c42f5224cbba161d8f8705a2085548515 |
13-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
use lower case for readability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87054 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| f4cbc0e421174de0eb38fb1ec46deddb082536d5 |
13-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
use lower case for readability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87054 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 8ba3999a322f98167aab91baf54a4119b1fa518b |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Make the MachineFunction argument of getFrameRegister const.
This also fixes a build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
|
| b9c2fd964ee7dd7823ac71db8443055e4d0f1c15 |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Make the MachineFunction argument of getFrameRegister const.
This also fixes a build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
|
| 6424ab9738972c0a9d5f588c59645f85782cf68c |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
|
| 2b0dd3fed34eb77a58c42aee574e171fe5d983df |
12-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Update TB[BH] layout optimization. Add support for moving the target block
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86999 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 80697d1b266cd3cd3b92edd424d66d573db6b4b1 |
12-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Update TB[BH] layout optimization. Add support for moving the target block
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86999 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ae466e3c7583e38941203c6de310f4749ccc529e |
12-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use table to separate opcode from operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86965 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b9d2c03d200bea99470766b0fb53dd07e11b086a |
12-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use table to separate opcode from operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86965 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 3a2ce50346bc55508a38e13d389bcafab7eb4c29 |
12-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
isLegalICmpImmediate should take a signed integer; code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86964 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 06b53c0d51f029eb754b40350faf5ba4b33c4bcb |
12-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
isLegalICmpImmediate should take a signed integer; code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86964 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| f7ecb28b62f3fd1539b294e07c6cf3ab9b61f1bb |
12-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86945 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 01dec0e545de18aadcd3911563a93d10a625be80 |
12-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86945 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 2621469af6386370b3bf8d41f9a76733b7a4e94b |
11-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86858 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 77e4751011da2d6afa930ab91f7baee39e7c7e89 |
11-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86858 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 9c7d61e9f372f1a6daccb4df389520193d58de67 |
11-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Do jump table adjustment before constant island allocation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86857 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f4997e87e3131a5609b54b18c6d94833827e9dce |
11-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Do jump table adjustment before constant island allocation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86857 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6ae593cd1381ab2f6aff6eb1309a1a7b5270c8c6 |
11-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86791 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1fc7d715aa35703fcc4a87ece718a8c447e8ee72 |
11-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86791 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 4137d7cdf726c8d94ef376603d909b69037a9e91 |
10-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb1 address mode printing, instead of
[r0, #2 * 4]
Now
[r0, #8]
This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86707 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4b6bbe1e9c40fb58eccaf3671432661016663aab |
10-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb1 address mode printing, instead of
[r0, #2 * 4]
Now
[r0, #8]
This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86707 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 979c7ab12dfb8913593c05cb303b947c5b06d1f8 |
10-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86706 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 1e13c797e51f031e0e22149dd3f606ad56f13c42 |
10-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86706 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 2a0ca3b82e4e78705e37f2b3d9092bc9767b8306 |
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 |
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 526dd742a7832e90f52ac99c24a4370d3d98d347 |
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 0855dee564f80160abf95497475306af38ab7f84 |
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| af0ec43f7322c579e2abb859bae4cc8075ec8e0a |
10-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Now that the default is 'enabled,' a separate command line option for ARM is
not necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86621 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 803b48a155eb2b3f9fe3823ecd7cbbd0089b2809 |
10-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Now that the default is 'enabled,' a separate command line option for ARM is
not necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86621 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8674f03b85cbf65f4e15902a68e089341b9f1743 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable dynamic stack realignment by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86604 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 92eb919e807c2c7ba5c5cde131a340ea0a77f94b |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable dynamic stack realignment by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86604 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 65d8800c4b8ae965422e75b0f3309191ae23fbc3 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Set dynamic stack realignment to real values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86602 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ad353c74adda55556f7a3969721c3e49ac16d570 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Set dynamic stack realignment to real values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86602 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| cdc498061580523723269ee368d6b7adbbb02699 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Work around assembler not recognizing #0.0 form immediate for vmcp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 43cca695a81ddc4a8a1f98d959047ba16edc3d72 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Work around assembler not recognizing #0.0 form immediate for vmcp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86548 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| e2fda536ff4bd38be9f9ebea6ad90ce0b48d0e12 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONMoveFix.cpp
EADME-Thumb.txt
EADME.txt
humb1RegisterInfo.cpp
|
| e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 |
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
EONMoveFix.cpp
EADME-Thumb.txt
EADME.txt
humb1RegisterInfo.cpp
|
| bacc516181e4772892c2a61ce0acc17074fedf1e |
08-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
|
| 31bc849123011b8eae6bb3c79876d9a3c26a6a1d |
08-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
|
| be9db751021d3849e4cd2590e4e4c7ec4f50b221 |
08-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| fdc834046efd427d474e3b899ec69354c05071e0 |
08-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 0e426c27d48dd7f1890bfa71b7566a7cfb05c4e2 |
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup of file header comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.h
|
| 31c24bf5b39cc8391d4cfdbf8cf5163975fdb81e |
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup of file header comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.h
|
| 04d92822f7e9437186a873e4f6335b4c379c5d65 |
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Support alignment specifier for NEON vld/vst instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMISelDAGToDAG.cpp
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
EONPreAllocPass.cpp
|
| 8a5ec86a3d4d599984e52c0c5a3a6a436607cf3e |
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Support alignment specifier for NEON vld/vst instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMISelDAGToDAG.cpp
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
EONPreAllocPass.cpp
|
| 812c299cb8ac1c341552584fbbdfca9a75ffe764 |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2ldrpci_pic can be used for blockaddress as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86400 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| bf992817f28bdab09fe1d1349561efb0c89fb0dd |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2ldrpci_pic can be used for blockaddress as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86400 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 1b60b1603b3be4b41b2e3a6820fe116835ec7dd9 |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
indicate what the native integer types for the target are.
Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 59a9178fbedb88427c8ff9e5fa7a8f2038f80a2e |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
indicate what the native integer types for the target are.
Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 59ab8afb46d74604f438d78213a641c038c519b8 |
07-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
It turns out that the testcase in question uncovered subreg-handling bug.
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| e8ea011cc766b37a957d5966655526096bf49fea |
07-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
It turns out that the testcase in question uncovered subreg-handling bug.
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| e63aa1f6906831c4a1b8bf2f2bc1ee23a4e3c3c6 |
07-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Make the need-stub variables accurate and consistent. In the case of
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86363 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 2d274412ed9aab277e070690c574714ec544cf94 |
07-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Make the need-stub variables accurate and consistent. In the case of
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86363 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| ca529232f661d674617b7d5e51102cf4ee9a6ffb |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
EADME.txt
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| d457e6e9a5cd975baf4d1f0578382ab8373e6153 |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
EADME.txt
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 626474d3ddba098f44d1a372314418a63c152540 |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 78e5c1140adc926e7c004748c1c912bfddd875b4 |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 80994a152341401f8151ece592fd0a07dd14ae1f |
07-Nov-2009 |
Ted Kremenek <kremenek@apple.com> |
Update CMake file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86325 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| b6aae88ac003183cd386c7db2ce123b4d10b7a22 |
07-Nov-2009 |
Ted Kremenek <kremenek@apple.com> |
Update CMake file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86325 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| d139b9495d8e6a18ac8c7d3a7767f7e0db76a673 |
07-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86319 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0430152a11ccf5f6079d97c519b4a86dd49739e7 |
07-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86319 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ab81483d946285672c43aa85f78f912321e95348 |
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86310 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.h
|
| bd79fc8ef2543c16239f840a03b6c338cf42399d |
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86310 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.h
|
| 7921e58057a3a19e15877cfd18fcbeb828e919f9 |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
RMTargetMachine.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| b9803a8fa65f043c96612fa9c5aeeee12739db2b |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.h
RMExpandPseudoInsts.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
RMTargetMachine.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2ITBlockPass.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| d271d8b61f3747846a4ac40f9c49a9b9ca71bc67 |
07-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Honour subreg machine operands during asmprinting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| fc2cba8362b603b376ea9a27b257579efaff14ac |
07-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Honour subreg machine operands during asmprinting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6a14a00bb348755ff7974c56ff8df9845deb68f3 |
07-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 54c78ef2fed32e82e6aea8cbeb89156814eaf27c |
07-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| e4582d9e08187fb0d75c51ddb139f3ad3a45642d |
06-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| e7e0d62efda2445b735052ca45bd74fb002e34c3 |
06-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| de46a5b60ea8cf3db0b613172667a7038470c578 |
06-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Pass StringRef by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 2928c83b010f7cfdb0f819199d806f6942a7d995 |
06-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Pass StringRef by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| bbc43963b76f8e54e6cee47defde4868586665fd |
06-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the printing of the leading tab into printInlineAsm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86199 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 40c57860dad429d3c938ed5f918c2c66f3b5fa72 |
06-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the printing of the leading tab into printInlineAsm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86199 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7abf0939c0cf058c89bfdf010ebfa0377fb17034 |
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 73bb251cd7a535fb93bb3a52eda61555fb253f41 |
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f1d76577adf6049e5e7b389bc928d3367e8acbc3 |
05-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86068 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 4371cda7f8fc21fc3192ead122ba48b0152fb0e4 |
05-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86068 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8db35425f1cc0dfc5275e413a302a03d99a3c038 |
05-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86064 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| db1751a9222dbfc62e6d7c2ec0b084d353068931 |
05-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86064 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 688ef4595d8d624bb968d508432a64a2652176ae |
04-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
If a function has no stack frame at all, dynamic realignment isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86057 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6db06a0866cd36fec05e6d9afb357ce8efb575e9 |
04-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
If a function has no stack frame at all, dynamic realignment isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86057 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6023c439e5e7ed8cfcb63488e411e3f04f2515da |
04-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
dynamic stack realignment necessitates scanning the floating point callee-
saved instructions even if no stack adjustment for those saves is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86056 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c5848f4ced8f9174e7141c0d2589acaafa13ff35 |
04-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
dynamic stack realignment necessitates scanning the floating point callee-
saved instructions even if no stack adjustment for those saves is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86056 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 7f251671d1a905be12347721af468b8e31ad9d6e |
04-Nov-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Print out an informative comment for KILL instructions.
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86041 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ad68264f590f05db3731a452fc91dc22bc75167d |
04-Nov-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Print out an informative comment for KILL instructions.
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86041 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2527652d0530076c4fcfc114b4a950bbfeeaa77a |
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
The .n suffix must go after the predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| b9f51cbe983c0635625982a8ab5dd2158e063b74 |
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
The .n suffix must go after the predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 98fd6060b428475e227274836140601d27016a4f |
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use ldr.n to workaround a darwin assembler bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7883fa942ff004b9c441ff9126a9d57b29d22a5e |
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use ldr.n to workaround a darwin assembler bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 276f816673b1257798355cedad6f1529c75af3dd |
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb2.td
|
| 5a1cd36019ca3cbae811f2800631b5b56a9ffdc2 |
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb2.td
|
| 3e5ab0bd7db07a568cb543f7c78c1bc5ab70efa5 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
fconsts / fconstd immediate should be proceeded with #.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b23b2015eb5ee5d19735d82b2b585c6671310542 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
fconsts / fconstd immediate should be proceeded with #.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0c7403016afc834b7c310a5676de5ba5dfd1ea2c |
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move subtarget check upper for NEON reg-reg fixup pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
EONMoveFix.cpp
|
| 747409a290e119601c8fcb8bc429aafcae186179 |
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move subtarget check upper for NEON reg-reg fixup pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
EONMoveFix.cpp
|
| 5d63848cf8c3a3b885f75dd0be11e5e217c254e9 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f6c0bffa8d6308ba0f31df0bb57f194b24aca83f |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 74f8efd28d43839bb2513ad39c93a5ae317c3764 |
03-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
For Thumb indirect branches, use "mov pc, reg" which does not switch
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| af14e663ac9bbdd8b545552da60fe807754c9988 |
03-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
For Thumb indirect branches, use "mov pc, reg" which does not switch
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| f865754812e17df0cee7e4a1d387bac6603f015b |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ba908640b3e0c1218748776e244d4b7234451155 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8ef1ec1295a24dc9ed54952005a3f2cab20165c6 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85870 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85870 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 89947e524969d671c7cb8763fdc333ee02727338 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 3f4e47be0a9b26501baf0ea0017795ffb2e79fc1 |
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 53716298997391af4aa6547150f9162a942312ff |
03-Nov-2009 |
Ted Kremenek <kremenek@apple.com> |
Update CMake file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85861 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 92dbd0b3201dd343887c57657847d6f63d22cb03 |
03-Nov-2009 |
Ted Kremenek <kremenek@apple.com> |
Update CMake file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85861 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 3ed3a35a6549891d3a9ef08bcc9caaf21703a537 |
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMTargetMachine.cpp
EONMoveFix.cpp
|
| 7aaf94bb0dde65e70b417208aaf859f7292a31d1 |
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMTargetMachine.cpp
EONMoveFix.cpp
|
| b6057985f14be94252b2741f5e8ae338879395a6 |
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert r85049, it is causing PR5367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ab453e06418cceabc909527dcf38a4914ef61f77 |
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert r85049, it is causing PR5367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 1c9eda2cdfdd2fa0f49365d669d74968e1a925e2 |
03-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert previous change to a comment. The BlockAddresses go in the
constant pool so they don't get wrapped separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b62d257cf5adf89599e185e8cbd2b15e05e054dd |
03-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert previous change to a comment. The BlockAddresses go in the
constant pool so they don't get wrapped separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d1da913d170e20cf91fd12f9da5d733f171bcb7d |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Put BlockAddresses into ARM constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 907eebd5a6779e8539ef7bf63550a5b72de76ab2 |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Put BlockAddresses into ARM constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| b7209bfc4cf90c88ce0d1795184e99fe54091c53 |
02-Nov-2009 |
Kevin Enderby <enderby@apple.com> |
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
have been passed as a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85823 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 60131c0d0bb04d0ae3c13cbd055616c71d86e8ea |
02-Nov-2009 |
Kevin Enderby <enderby@apple.com> |
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
have been passed as a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85823 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9a8ec820614ab5b5a0edef1297cbc4cec4b1c3d9 |
02-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix schedule model for BFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 2f54a2fd8542aa6280d1c5da18ac314d16550676 |
02-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix schedule model for BFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| a07d68f6f017c73cbca1222cddd6baf40974974b |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Hyphenate some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85808 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 31ba10b7431de1c320c6027d86d4592d6fde4a8f |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Hyphenate some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85808 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 62acbf19235b3b20a24958b973538e35ec6f2d67 |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for BlockAddress values in ARM constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85806 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
smPrinter/ARMAsmPrinter.cpp
|
| 28989a8ddc665dce4dde368e8c000a5769871b63 |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for BlockAddress values in ARM constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85806 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
smPrinter/ARMAsmPrinter.cpp
|
| d737897784e400b7c2642030b362faf42493a398 |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Prune unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85805 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 69e8445ced222d856c850963586800f9385d110a |
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Prune unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85805 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 8ff61c68cde1cf4d785362c21f4a316436d14a22 |
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
These are done / no longer care.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d3e18fad7e7c6839a3d343f77957a488754d06b6 |
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
These are done / no longer care.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d9ca3d1e7116200fe9e62cb9397c783d1d653159 |
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add an entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85797 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| e3b88fc01e64200c3685c1b14eb23a3f4625edf2 |
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add an entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85797 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d9a5f772aa33a15e8ae9db61010ea0e347b771ca |
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ARMBaseRegisterInfo::copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 7baae87d8f188262e07922348d88201f32514b1c |
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ARMBaseRegisterInfo::copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| f817d7bfb1568b67a790dbae0ea05e162b6bc560 |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2ae0eec1c03fa005136b8724faab38048878f253 |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d9331217b489a204b9264bb424ebf83612e1b29e |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMRegisterInfo.td
|
| 3a639a07ea14f2e404fb1d3a14005ff468543911 |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMRegisterInfo.td
|
| 1853b6e277b38bc8d796951f371cbc5824b21aff |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
64-bit FP loads & stores operate on both NEON and VFP pipelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 2e1da9fea468e33f8fedd4295ef4a73a0ccb5714 |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
64-bit FP loads & stores operate on both NEON and VFP pipelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| eed9c14b562d5c43c787b0a74c99f3adf6238f6b |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| f95215f551949d5e5adfbf4753aa833b9009b77a |
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 1ac1b43d80bf7bac148dd5d4ad3dd98054cf9408 |
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a couple more places where we are creating ld / st instructions without memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| e3ce8aab0a6de939f8cfa4f8cb2e3a3bf4e1fe21 |
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a couple more places where we are creating ld / st instructions without memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 3e9fef42389147453ebcbe12543ae9f1c6530f7c |
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 48d8afab73d72418cf9505a020f621014920463c |
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 538da74ec2d9bb494a7704e195515c8be8b5b373 |
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use cbz and cbnz instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| de17fb6e4dd8f169f707d58d4e124c8d4d2c7dba |
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use cbz and cbnz instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| 67420bf16a60b1ae36b4d38187b3dd43e73fee51 |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
them for scalar floating point operations for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8cd0a8cb821263be4dc40b0b376ff02bfbd89f88 |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
them for scalar floating point operations for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a3bddfb18197f4b00b161db0c643e433f79e67e6 |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64-bit logical shift right inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bcf2f2c1592c96b3adcfd784e0699e8c55f65e5b |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64-bit logical shift right inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5480bad7b9ba0a765d937631674f2b65f8eeea1e |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64-bit arithmetic shift right inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b4a976c304e98fb4160549a92e35610b310dfd93 |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64-bit arithmetic shift right inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 998eacce4edb2421d0b40349057d8c30c1585ade |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64 bit left shift inline rather than using the libcall. For now, this
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c2b879fcfe3834597948d5dd6044a3f32baee275 |
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64 bit left shift inline rather than using the libcall. For now, this
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 326d7242e283922daf63e607bbc84e1498f76da7 |
31-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb2.td
|
| 9eda68988e7772c40f6125750a965ddb85acc25f |
31-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb2.td
|
| 13f60e83d6add4d7159c322a7ccc1c36c26a115b |
30-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Updates to the ARM target assembler for llvm-mc per review comments from
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9c41fa87eac369d84f8bfc2245084cd39f281ee4 |
30-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Updates to the ARM target assembler for llvm-mc per review comments from
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 4381e3bc06cb247d7d57658b2c6134c24021d316 |
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a note about Robert Muth's alternate jump table implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85624 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 57f224a5a473462f85e94c457c7548af27c37f0b |
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a note about Robert Muth's alternate jump table implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85624 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 0d20d17a4707634b1973053699fa027c313c8220 |
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 929ffa241480bfe8b45c48cc64a8e0de38ec2421 |
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| eac0e8f344245ea3d5f7d78eac4033e8c64f18ab |
30-Oct-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
This fixes functions like
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c1382b745faa62bc6f2570a193bce6aee8d78885 |
30-Oct-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
This fixes functions like
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8f743387c77dd5cdd20a6441e5da8271b52ca233 |
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM codegen for indirect branches.
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMMCInstLower.cpp
|
| ddb16df91257e4c4d2be5343e2c7c7ecbfbe8bf4 |
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM codegen for indirect branches.
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMMCInstLower.cpp
|
| ebb14ff86fe1abf66d63985844fed583fb2044a5 |
30-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Dial back the realignment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 95d9504d46a18d65facca9a86cd53fa03cba1eca |
30-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Dial back the realignment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 30afe01e7ef78e1d2c01c924161ebe53bf02a3de |
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 533297b58da8c74bec65551e1aface9801fc2259 |
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 9823cc9df2fbd6e8bd106e223718996f0a68a1d2 |
29-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
To get more thorough testing from llc-beta nightly runs, do dynamic stack
realignment regardless of whether it's strictly necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 84e58d03c910aa6ea8557d2f2f9de1f96162cae1 |
29-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
To get more thorough testing from llc-beta nightly runs, do dynamic stack
realignment regardless of whether it's strictly necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 93ab5617a1e187a411418c1ea38b312b6aacf850 |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert r85346 change to control tail merging by CodeGenOpt::Level.
I'm going to redo this using the OptimizeForSize function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| a597103c328e29fb763e7a4864bd7c29a588fc9d |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert r85346 change to control tail merging by CodeGenOpt::Level.
I'm going to redo this using the OptimizeForSize function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| ea6986525fadfd6488bc28e4ef99004d2b2aa519 |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 8d4de5abfa1bcd974554ea14904ebf7af289e84d |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 116b72c4dac37340eff42e02af6e6a0b60252578 |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
fconsts and fconstd are obviously re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85410 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 30c80211b648c7344e949af594a9a191a1d36acc |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
fconsts and fconstd are obviously re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85410 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| b666f8884f79e76357655ae65a0395cc72d06400 |
28-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1e |
28-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| fa281b8ec7167ba67ddcc8d441f6ff1685c83998 |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c59420867eec22f7fb562b5b53deffe98b511505 |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7c7a3ff2b1b7be0f3a3f5a3ca0b01a182b0d2fba |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use fconsts and fconstd to materialize small fp constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 39382427f1095f089d73a7dd3d9a371dea75b781 |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use fconsts and fconstd to materialize small fp constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrVFP.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| f061fc84a89aa961b3f5e25dce93fa5ac033c090 |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add an indirect branch pattern for ARM. Testcase will be coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 04ea6e5150dd02fd60513a3d9fd1407aea350c02 |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add an indirect branch pattern for ARM. Testcase will be coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| afe63293c930f39f6f6d4ac6e76da0d3546dfca4 |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Record CodeGen optimization level in the BranchFolding pass so that we can
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| cd4f04d6bcb7aefa24d92582fbadfe17519f4756 |
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Record CodeGen optimization level in the BranchFolding pass so that we can
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| fe8db6e76137272e242fc806826b15aaa934845b |
27-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable virtual register based frame index scavenging by default for ARM & T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a6a99b4e160eea0060b25fbdeadc3437cd67d617 |
27-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable virtual register based frame index scavenging by default for ARM & T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b004ed5cee7a2d006860c017249c16d6331c0758 |
27-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 3dab2778571b5bb00b35a0adcb7011dc85158beb |
27-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| d55c2acab4373802918c5c83eb9fcc7fd0f1349a |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 90d7dcfdd9f0ad435e57d476109630998faaa698 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2b4d1db83d22c184d42fed3e4863fe6253476a01 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
BL_pred and BLr9_pred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| eadeffb30658de2abc798178dd7b645e68972db0 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
BL_pred and BLr9_pred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 66eeb81868889994314fc49be900868351d6f1a8 |
27-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
instruction format that already takes care of setting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f3b0d1a555eaa46931e4ec1b11e434e8cba2b5d7 |
27-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
instruction format that already takes care of setting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1bf7944abd6a4205d09769377fbcd9240ab416d8 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 76b39e88e470171292850d8cebc5d54227b43883 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5663974f0438575c0e45d0bcb5ce0391eb5a5f96 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Test commit. Added '.' to the comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6a3b5eec8919da6c45addb6254ffb929af243378 |
27-Oct-2009 |
Johnny Chen <johnny.chen@apple.com> |
Test commit. Added '.' to the comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 8f419e24e13ef1e9090c6e96b18da9bb45338ed1 |
27-Oct-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly align double arguments in the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| f87611272bd9b97c738e18ed046b38e0b5acdebb |
27-Oct-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly align double arguments in the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| c1db4e53b11822ff3262d6b741974ef78ce04ea4 |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Now VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| dd22a45acc24ff1e4954fda753c555a6365d1dec |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Now VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 08540a929721efe42893675068f8a5a1767afad5 |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 699bebac4f3320b5a9a3c94ac76502caf61dd711 |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| d3f9bc403327201a4cbb416f6627d1c54c0fcac8 |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
|
| 162e30921da0ce1863672d4ca5fef541498fe6be |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
|
| 2aec46ede15c195de15bdafc25e9760b6d9b5c52 |
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
bits. Johnny, please review -- I do not have a good track record of getting
these right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dda9583e5194c08ddd409f3e1c211e17acd6d5b8 |
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
bits. Johnny, please review -- I do not have a good track record of getting
these right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ccd00e369b68760c043986705ca45bb06e233f1e |
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| d9ecd3108f32b33e38b5ba0ee3963062d6ecc115 |
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 3a308521257a4c8fc6e816bdd4218ade39e1edfe |
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
bits. Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7e053bb33ca68e815f032fefb9ab7e45a455369f |
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
bits. Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ad5789c4fd62e77a8d27c43db98384ed9762dfe7 |
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Break anti-dependence breaking out into its own class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 2e7be612d5d0eb42ee3ae08194dbb03b750cc6bf |
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Break anti-dependence breaking out into its own class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 20f9924817aba90dc88c43b247671c6542fb523c |
25-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
of -> or
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.h
|
| dd5694203b8997cedcb40e4f1f12cd8a1999fa89 |
25-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
of -> or
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.h
|
| 4f9656021235a937c7c874487dbbb5780f3b0427 |
25-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
humb2RegisterInfo.cpp
|
| f639e9f9e6a9f0315f018ee71f1e5ae744b0c519 |
25-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
humb2RegisterInfo.cpp
|
| 7da9a9ca5eb152a5d570c29b6b873dda02148925 |
25-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 4f54c1293af174a8002db20faf7b4f82ba4e8514 |
25-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 146c8488a42d45d57f0e25abccb008d7e9b8d135 |
25-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget subreg indices when folding load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ed3ad212ec34fa2866fb70f9e52ddda31032ea3b |
25-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget subreg indices when folding load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5a44ef9fd5f7c3964ad79b94778261175dea5c33 |
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 492d06efde44a4e38a6ed321ada4af5a75494df6 |
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
EONPreAllocPass.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 09549369a6f7976934e21a49befb6d9f46abb56b |
24-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5a850beb2e3032e6ff3474ce5317f5454060328c |
24-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 852f708684bb34dea4f22b2c46829c49e671e2b7 |
24-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Restrict Thumb1 register allocation to low registers, even for instructions that
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 2f1abe2dae50e7bc29b20fcad3ea127cdb597532 |
24-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Restrict Thumb1 register allocation to low registers, even for instructions that
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| db980fa1680f4a52fbd9c940284df543fcac97b1 |
24-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
FIXME no longer applies. R12 and R3 are available for allocation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 7388037dd15b13bc5705dee6ca85d5aacced5ce4 |
24-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
FIXME no longer applies. R12 and R3 are available for allocation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| e56e4a63f19ea3b7e40d84704d9b066698722db6 |
23-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 4c3715c2e5e17d7216a96ac2baf9720630f04408 |
23-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| df6a663b5b5a592c4dffdea732db0fe0d1453e14 |
22-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 84843. Evan, this was breaking some of the if-conversion tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| bac6ed4ba4b5b912470e3c48f86c3e74a2f36d7b |
22-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 84843. Evan, this was breaking some of the if-conversion tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 2147b5787db9e84e22c5d008db703ddce3ae9d86 |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 87689d3b7049ecfa41de24a310bac7365c2dbcde |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| de6ba0a0863d45638958b1c0e47aab50c9fbaaa0 |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| faf93aa23390389375b8e52f0dd1c3727ed07ee8 |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| a14a20abbaa4fa993b66ab746dfedad633e3f974 |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim more includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 62d1723a9cbce2019aac862f51952a58146a6bf0 |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim more includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 6e38eb0b9332d2af9d3d0db0bc94a1fdaa5c709d |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 268c79350e1b5997c92d65b39f6129d85f5925fe |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8776641c8937656b395e6bf9256f90c60c616103 |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 8000c6c535c5a1d8515299072b51fd1baa8b632f |
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1190aa49e2e41435881d3a76052a29a2aff9f632 |
22-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Missing piece of the ARM frame index post-scavenging conditionalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 41fff8c19ab6d8e28f5362481c184ad628f8c704 |
22-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Missing piece of the ARM frame index post-scavenging conditionalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 86320274fce17431f8ad60ebd9e89c2e7bcacc04 |
22-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
for a few bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 1d6827bbe947730cb91d68a9fd9c469f7f56a6ae |
22-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
for a few bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 2b1ec3887477e72d994e996b7e0422777172b7d0 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Most of the NEON shuffle instructions do not support 64-bit element types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 20d108140e8a4ba9b5e2dd1662e26e5c2282d567 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Most of the NEON shuffle instructions do not support 64-bit element types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1afc8e26bf2580d78e824666534049f5693c09df |
21-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrInfo.td
RMInstrThumb2.td
|
| 65b7f3af76d0ba5bce49b56ab3e18f970b95f9d1 |
21-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrInfo.td
RMInstrThumb2.td
|
| e33f252643208755c07a6b43082f20d05b15af42 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix NEON VST2LN instruction encoding.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b27b51aaa6602a2062ab0f778b87628fb70e0a0b |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix NEON VST2LN instruction encoding.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e0053d22f825bf4749beaa282a4263e945aebcbc |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 84732. It was the wrong fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 407d57489ffea4818e22379ace0bad70ea2fe9f5 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 84732. It was the wrong fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 89ef28530fcc03f47245644eb67085b94efd0bac |
21-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Match more patterns to movt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 2095659a8551fb222d145bc8dfa6cf5d15048e42 |
21-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Match more patterns to movt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 34fdb7750482a92c156acf8a4be9d1550386717c |
21-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
tidy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.h
|
| 1ce75ef5efd6e12ddf62d6f428bf9da960ff7880 |
21-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
tidy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.h
|
| 6a77292423d0cc8955e56147b98b7d39c253eefa |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix some more NEON instruction encoding problems.
Thanks to Johnny Chen for discovering the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b3c83593608907408c2122d924f52b1dfb653b76 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix some more NEON instruction encoding problems.
Thanks to Johnny Chen for discovering the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 52e0d9d2677019df9209470c4cfcdc0a69365842 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Leave some NEON instruction encoding bits unspecified instead of setting
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 507df402b09be986b40251fb83cb0c8a2e586b68 |
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Leave some NEON instruction encoding bits unspecified instead of setting
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 38f422c8143b1a7c99796e40e295c677e11fbff9 |
21-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84687 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| a7cc65283af74e8681522d4ede4d7c15d04f58e3 |
21-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84687 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
|
| 0ea1568b4728e4de08c89594b232fa9fba80b5d4 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Disable by default while debugging
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 3229b0bcf1fe5e9381f306ed30c37cec0377395a |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Disable by default while debugging
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 860507d1bbced055f324e91a18de4f5ddd650a4f |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 18ed9c9a2bd7f1f56129495b499264c58b5cc4f4 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| fdaec7c0cbc5d6abdf7db2561af08f90a9856742 |
20-Oct-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Random #include pruning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 174101e13a6f24f6f2737e043194f0ffae925bb3 |
20-Oct-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Random #include pruning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6d01a09e9033c335655d9652b6a609e41d4db8c4 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
implement some more easy hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84614 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 235e2f6a68b5f37d6c1b554330eebc8d32f1aca9 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
implement some more easy hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84614 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 9ec22035cfa3affa2e5e5a026fe228716831a781 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
Implement some hooks, make printOperand abort if unknown modifiers are
present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84613 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| bf16faa16a7042c6d899e08730398e7c2e9c0edf |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
Implement some hooks, make printOperand abort if unknown modifiers are
present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84613 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 6cc1d3464849d68ba734f6ff8f54b934f53e218d |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84611 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c6b8a9920787505468931e56696cef1245e25913 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84611 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 75b4315d0399ae642397f7deec028adb1802a8bb |
20-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
Wire up the ARM MCInst printer, for llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 2685a29a8d4ced7791bb671e28f9fe51c74eb3bb |
20-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
Wire up the ARM MCInst printer, for llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 86fc0730e6c0f4c2f6fdb0a9296fa4eb2802ef53 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
functions are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 8fa4efeabf705cfc217eb88a67e7398691c76ade |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
functions are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 81d33cdd24ad12950350365eb634134292e357e1 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable post-pass frame index register scavenging for ARM and Thumb2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 7e831db1d4f5dc51ca6526739cf41e59895c5c20 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable post-pass frame index register scavenging for ARM and Thumb2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 7960fbe0b2679bda3c6db9ebf0c13d0e0f1f8a3b |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
lower ARM::MOVi32imm properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84583 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 161dcbf79955ed11b6760fda59f1e203380d27c8 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
lower ARM::MOVi32imm properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84583 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| f5044e84ffc2dfe993b050d96403ec1170645903 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add support for external symbols. The mc instprinter can now handle
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84582 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| 292df8eb1f2e8967499161804e85772f5fd3a711 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add support for external symbols. The mc instprinter can now handle
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84582 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| a2483d54b25eb8f19ca58419b01918eb5a4a0a1c |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
get fancy: support basic block operands. Yay for jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84579 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| 96bc2173bb4909be0058e4eb2171f37a66e361dd |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
get fancy: support basic block operands. Yay for jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84579 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| 37cd7db2c8fa2817637d8b5ecafcc33a167865ed |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add supprort for the 'sbit' operand, MOVi apparently has one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84577 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 233917c07282564351439df8e7a9c83c9d6c459e |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add supprort for the 'sbit' operand, MOVi apparently has one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84577 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 31c1d7b06d5f7ec47ec96d99275faee9624cffd0 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add support for instruction predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84575 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 413ae25fb593319caa6e5a16f986863057665331 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add support for instruction predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84575 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| e4eb7345116dbb08a81742416317b707b6c2cb76 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 017d9478d52e56fd20db29eb40e0665cce9f094c |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| c8d6989f39c90afddab819efd17372519278e71c |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Refs: A8-598.
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 1fc1dc0682b9e3648acd2e9b3b426db87d9f2dcf |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Refs: A8-598.
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 77ef7774b592306694272b141712dec57a94caab |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add missing encoding bits to NLdSt class of instructions.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 780d207d1c73e53834df9eb9ff0a1b07b235dd04 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add missing encoding bits to NLdSt class of instructions.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| aabf5bee0bd2fc12e02937511e4e28d400c8211e |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
handle addmode4 modifiers, fix a fixme in printRegisterList
by ignoring all implicit regs when lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 306d14f9aa9fe6891f5df447fe9e0a380de02501 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
handle addmode4 modifiers, fix a fixme in printRegisterList
by ignoring all implicit regs when lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMMCInstLower.cpp
|
| 46999f20018606012039e3fe0861ea8d0a632593 |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable allocation of R3 in Thumb1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMRegisterInfo.td
EADME-Thumb.txt
humb1RegisterInfo.cpp
|
| 6009751244909c277e6cee8e74a4ccf1846953bc |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable allocation of R3 in Thumb1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMRegisterInfo.td
EADME-Thumb.txt
humb1RegisterInfo.cpp
|
| e1ca870b6187d888ca1b83095fc0a37b38a33613 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
use EmitLabel instead of text emission
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84562 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5a207897bc4f267fc32aaba7d0248c9f9edef637 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
use EmitLabel instead of text emission
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84562 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2743f3605a9fcd16f1045a8d9bcb8950cab0860e |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add a twine version of MCContext::GetOrCreateSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84561 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7c5b021793e8c8184c655040ea5e169b55c55063 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add a twine version of MCContext::GetOrCreateSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84561 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4c565d8576a1ceb933301e7437723978ba985553 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84558 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| a70e644820db9c58f201bd27ed3c28f81261a0d9 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84558 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 976a864c9995dced48ffaca18ff68921f0a4d5df |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| d482f55af135081aee7f7ab972bb8973f189c88f |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 817d551945e7ce46b12f8b3d022c7a7a0e90275e |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84553 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 4d1522234192704f45dfd2527c2913fa60be616e |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84553 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| c8bdad042bc8e9f7c0aad7194ab4c120f38aba01 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add register list and hacked up addrmode #4 support, we now get this:
_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84546 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| e306d8d6cccea7461974cec2b0daa2933867eb22 |
20-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add register list and hacked up addrmode #4 support, we now get this:
_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84546 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| f1977ef5f64e12407799dbb7b6c113b4b0567db1 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add addrmode2 support, getting us up to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84543 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 084f87d445620bd63573c0e8d9adf776dc62d87d |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add addrmode2 support, getting us up to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84543 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 9521525ee4beef3f057a4b1921399322c5060f97 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add jump tables, constant pools and some trivial global
lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84542 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| 6f99776f6c1d6cc93a62192099a0fd8cc2cc3a0c |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add jump tables, constant pools and some trivial global
lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84542 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| ba9c060b0e2a2bc7cadcbc2bff3a8e025f00213d |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
reduce #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84536 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 8514e21deb12714d84038e6afa1b755a9d335098 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
reduce #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84536 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| cc309683cabf05c1ec7175ecdaf5ba97a36fb1cc |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add printing support for SOImm operands, getting us to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84535 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 61d35c273e2196c87986829fdadccc7e301fc7a8 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add printing support for SOImm operands, getting us to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84535 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 799e7c15430c30c25ad374e2022c23b88a27a7fe |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
wire up some basic printOperand goodness, giving us stuff like this before
we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84532 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 8bc86cba60fbb35fbfb52cc32b9e451e6b903a27 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
wire up some basic printOperand goodness, giving us stuff like this before
we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84532 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
|
| 1526e99433566fb172e9f82340455fbf783963a0 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add the files that go with the previous rev
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84531 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| 9cf0eb5e58fa42802af7e5776b39909516ca74e7 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
add the files that go with the previous rev
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84531 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMMCInstLower.cpp
smPrinter/ARMMCInstLower.h
|
| da6d01a3c6e8fcf1685b7903f966ac6c27cd6c62 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
wire up skeletal support for having llc print instructions
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84530 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/CMakeLists.txt
|
| 97f06937449c593a248dbbb1365e6ae408fb9dec |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
wire up skeletal support for having llc print instructions
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84530 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/CMakeLists.txt
|
| fd73ff4241505512fbaba4781c019338774893a7 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
"something" when printing MCInsts, it will just be missing all the
operand info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84528 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6a71afaec18e5bcbdb838a5e094f51e9f8ea864d |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
"something" when printing MCInsts, it will just be missing all the
operand info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84528 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8d01409390c7392f92540fa207556c2acc2ed89b |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
stub out a minimal ARMInstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84527 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
smPrinter/CMakeLists.txt
|
| fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6b |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
stub out a minimal ARMInstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84527 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMInstPrinter.cpp
smPrinter/ARMInstPrinter.h
smPrinter/CMakeLists.txt
|
| 1c7f8d32d6edd39000fbb2643828d86d2235b139 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
simplify code, reducing string thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84521 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b8f64a72d83b26ca29612081f3906272368a3692 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
simplify code, reducing string thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84521 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d9a6f16cfc733a242378b2bd57f744e46f88fed5 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84520 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e4d9ea83c0d4bcc535bd978e1afa599eb3ebb893 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84520 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5212138dbd0f9b3f1b0ce4db245fc43f7e29b242 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84519 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b0f294c14b4e7098e5170ecfd528bcc9682ce0c7 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84519 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 14f3c57043c80ba21e32c04f4b911872a154fc86 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
remove dead map
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84513 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ee8b32981ea70e6751dea1e2bfdb8320ca859bf7 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
remove dead map
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84513 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 882baf592d34dab3679b411d457b5a36f6b53a22 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
don't bother trying to avoid emitting redundant constant pool alignment directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84512 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a10343f0393d76c78e4b34a77c70eff7198ed52e |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
don't bother trying to avoid emitting redundant constant pool alignment directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84512 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| fe284f7efed56c46bae93eb3980924544ec9f513 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
emit .subsections_via_symbols through MCStreamer instead of textually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84509 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 74cd3b7ceb61b9335fbed1a124324fffd96ded6a |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
emit .subsections_via_symbols through MCStreamer instead of textually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84509 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b8db78262d2760d34ef451cdde7b20b9177a2f0e |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
cleanup doFinalization -> EmitEndOfAsmFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84508 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4a071d667d995b00e7853243ff9c7c1269324478 |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
cleanup doFinalization -> EmitEndOfAsmFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84508 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 174e2cf99df2011a0d56e96dcdb32c1ccaf4f464 |
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5505bc1c26d335e9a0f22f2c55fcf7544037b2d9 |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84326 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 491f54f1fd700204db0a19efde0cc2627641d711 |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84326 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1f99657b2abd791d220018261e21d9f4008708b4 |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 6553155172a2e74feff1253837daa608123de54a |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 77e61b46fce5e165ecfedb5666c43b3d2c1dc971 |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| bf125583f8bd8196a34921276add7f304b7c1433 |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 86e24b01e3cfdd1d2f533df99be1824515b677c5 |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| fa16354e0370fe884830286923352268b036737d |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 1302f57663145190ad603a572aeeadb066def866 |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
I am no spelling bee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84250 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| b46aea10324263dd63492fc5c1d54800e980c8f8 |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
I am no spelling bee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84250 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| cae7b0e6150f2fe795277324bb7107dba39a78e7 |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable post-alloc scheduling for all ARM variants except for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| d3dd50fec00fbbb76edbfaff4d613f1248d21c9e |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable post-alloc scheduling for all ARM variants except for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 11891b19a322b2bf91180b7be3d322a280af5f8c |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84246 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| fee0c1074c68a61d15899fb8cb31f1902fa9e509 |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84246 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 05538f12cafe7defa2e94364b8f0efba3ace7483 |
16-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix more NEON instruction encodings.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84243 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1dd43484088d2189ad7eb27ab702e98d4885c123 |
16-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix more NEON instruction encodings.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84243 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8ab1f273514d6d87fa421c9bc8fc819615707dbf |
16-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert svn r80498 and replace it with a different solution. The only problem
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 934f98b5368c10a77599dab7dd6ec969c8b2f385 |
16-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert svn r80498 and replace it with a different solution. The only problem
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 28d7ecb80c7a6a39039e73f1f3aa8ad91bf05bd3 |
16-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 452b54a8aebee45088b2157a66ae0f9f6a9088fa |
16-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 85f30d7362b1e8543f1988d02548e6f00949c3fe |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84206 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6f122625dde52dd112ca18cc016e4846734b9a4f |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84206 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| e6e22392e070a3159fe844aefedbdaad6973e423 |
15-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fix ARM memory operand parsing of post indexing with just a base register, that
is just "[Rn]" and no tailing comma with an offset, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84205 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e2a98dd2a4f007d5d9d3c71460cfbe0a825b8993 |
15-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fix ARM memory operand parsing of post indexing with just a base register, that
is just "[Rn]" and no tailing comma with an offset, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84205 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 7bfd59f06e8d1e8242d8775fe4e15a792394c698 |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a potential performance problem in placing ARM constant pools.
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references. This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84202 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b923953733ee6b0f477cd767dcc16f94a0966158 |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a potential performance problem in placing ARM constant pools.
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references. This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84202 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 804b26d218ceff164c578c1fdbf8c2a14d52aaf8 |
15-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
More bits of the ARM target assembler for llvm-mc, code added to parse labels
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these). Some clean up of the operand parsing code
and adding some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84201 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 515d509360d81946247fd0f937034cdf1f237c72 |
15-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
More bits of the ARM target assembler for llvm-mc, code added to parse labels
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these). Some clean up of the operand parsing code
and adding some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84201 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 57d88c38edb3667eb54c26571bcee5d57ae8ef12 |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Be smarter about reusing constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84173 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 549dda9d82a5ec0a0cbf429a18d33a8e66062424 |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Be smarter about reusing constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84173 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a9cdce8ba7928ac8a5176243fbf847415130f644 |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix another problem with ARM constant pools. Radar 7303551.
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them. My recent change exposed a problem in this area. We may
sometimes append to the same block more than one unconditional branch. The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.
This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before. The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block. The insertion point could be out of range. When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.
The fix is to only append an unconditional branch if the block does not
already end with one. I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.
There is more to be done here, but I think this fixes the immediate problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84172 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 36fa5321bacf351f47d6193f56c464e6ab93b934 |
15-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix another problem with ARM constant pools. Radar 7303551.
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them. My recent change exposed a problem in this area. We may
sometimes append to the same block more than one unconditional branch. The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.
This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before. The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block. The insertion point could be out of range. When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.
The fix is to only append an unconditional branch if the block does not
already end with one. I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.
There is more to be done here, but I think this fixes the immediate problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84172 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| d4897545e4e21d0dbdc788c5576f4b80071a95d8 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix instruction encoding bits for NEON VPADAL.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84146 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b3642dcceeff3ff4045271c87105b5bfbf44c489 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix instruction encoding bits for NEON VPADAL.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84146 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 4a567357c7179b5c3c39f21d774578f362a4c033 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused variables to fix build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84144 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 681a2ad40357fbf0415977d76323e9a03ada84ae |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused variables to fix build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84144 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d9921a052e234642eb7db4f77ae777123d73b62f |
14-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Inst{11-8} for vshl should be 0b0101, not 0b1111.
Refs: A7-17 & A8-750.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84131 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b9d319b5854640b363d332ce9840026900b9f663 |
14-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Inst{11-8} for vshl should be 0b0101, not 0b1111.
Refs: A7-17 & A8-750.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84131 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| cfb46c5a762f118fbe73fb50eec5be56a1fcd247 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Set instruction encoding bits 4 and 7 for ARM register-register and
register-shifted-register instructions. Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84124 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 8e86b5195bca5a7301bb3d633b56b1d1f58221d9 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Set instruction encoding bits 4 and 7 for ARM register-register and
register-shifted-register instructions. Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84124 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e4ff1a619f2a68222def8d30406ceb9f768ad410 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor code to select NEON VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 24f995d84b1fcb556f07ee40983f287cd13b2aa2 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor code to select NEON VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5ccc85a153111ff9f03ec36b0f78ffdd27e3ff09 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor code to select NEON VLD intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84117 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3e36f13ba738d9ab9123aadd486ab919f517387f |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor code to select NEON VLD intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84117 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 10c6f85c9ba78275c9f6de2ac9ea136200a09d10 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
More refactoring. NEON vst lane intrinsics can share almost all the code for
vld lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84110 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 9649344cb5e919f0d251c8b5b966259f3e7445bb |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
More refactoring. NEON vst lane intrinsics can share almost all the code for
vld lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84110 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 98e68ba7ff1b12e185eb7fa677683cc00e1e97e1 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor code for selecting NEON load lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84109 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a7c397c9c30df38901751abdcfa2c1c5e310d2e5 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor code for selecting NEON load lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84109 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 404500c0966b24922b62c6718713afdee5b88b7e |
14-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Correct comment about ARM immediates using '#' not '$' and TODO for modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84055 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 079469f649d8da3923b9f747d7062c84e01cc4ae |
14-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Correct comment about ARM immediates using '#' not '$' and TODO for modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84055 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 31a5af59b207ac90e75ddd830ff6c2e916b4a7ae |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
by creating TargetConstants during instruction selection instead of during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| e72142aa5b8bcd9266a5a2f88e4e227dd178f233 |
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
by creating TargetConstants during instruction selection instead of during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 4d4c8b383ab4e089c9662cd3f6a0afdb144ecf6f |
14-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
More bits of the ARM target assembler for llvm-mc to parse immediates.
Also fixed a couple of coding style things that crept in. And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84040 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| cfe072401658bbe9336b200b79526b65c5213b74 |
14-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
More bits of the ARM target assembler for llvm-mc to parse immediates.
Also fixed a couple of coding style things that crept in. And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84040 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 5f742e55de300e938ae76643a8e640913fc7a40e |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
NEON VLD/VST are now fully implemented. For operations that expand to
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 73d64a6fd3294b2b265d4ca7b5c9f76989459fb7 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
NEON VLD/VST are now fully implemented. For operations that expand to
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6855b2222d78ecf39a0855bec858c8c395e04538 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revise ARM inline assembly memory operands to require the memory address to
be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 765cc0b9d59bf63dfcb02e3d126ea1c63e16f86f |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revise ARM inline assembly memory operands to require the memory address to
be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
smPrinter/ARMAsmPrinter.cpp
|
| f7a7fc9585a5dc3afa894b6e5bdfd26fd17eca38 |
13-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Fix method name in comment, per Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84017 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4e1ed88026dadbb508930b3dd30f84bffd01da7e |
13-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Fix method name in comment, per Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84017 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bb4648a936134616f3bef1097520afd80b496970 |
13-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 47eedaa8fa597e3302012b0ef8f24c4886ef6188 |
13-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| ce7c9ebddf4e1742e71087fae5abf239061475f2 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some ARM instruction encoding bits.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83983 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5361cd2c7d2cd83ac3668bb553a4e63c282d05a2 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some ARM instruction encoding bits.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83983 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f0976f41d9100957bf1eca01436dc8546d95ee39 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix regression introduced by r83894.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83982 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 4796ba2e701f302f9628af6e2fb4b491dc2e4b94 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix regression introduced by r83894.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83982 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b072c755593e95a598b683c12be63c359e274c02 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a tab. Thanks to Johnny Chen for pointing it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83973 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a7fcb9b840775a8b45b63d597b88f8f05b12b962 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a tab. Thanks to Johnny Chen for pointing it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83973 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7bbbc7d65719ff18592a21cb2246e7fa68e213d4 |
13-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fix two warnings about unused variables that are only used in assert() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83917 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 6bd266e56799703cd2773cadc4da8bc3c5107fdf |
13-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fix two warnings about unused variables that are only used in assert() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83917 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 1449b8594c0a82f80d198ddadda5d23795cad922 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Delete a comment that makes no sense to me. The statement that moving a CPE
before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb. Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83916 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| af4b7352193e4a024d4a4e87cac1ba1589e4de57 |
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Delete a comment that makes no sense to me. The statement that moving a CPE
before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb. Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83916 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f5286ef78bba77aed8e21685baa8567e63316937 |
13-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fix a problem in the code where ARMAsmParser::ParseShift() second argument
should have been a pointer to a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83915 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 9d36962ab66f728291f0921b3b4851a37d303e95 |
13-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fix a problem in the code where ARMAsmParser::ParseShift() second argument
should have been a pointer to a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83915 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 96b37b64f271bec34a6a650fa875acff17cb53d5 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change CreateNewWater method to return NewMBB by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83905 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 757652c5ba820bbea75d8713d7bf3749e4113778 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change CreateNewWater method to return NewMBB by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83905 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| e5001730bd4aa9b23daa7861ea3ef08c35e77777 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Last week, ARMConstantIslandPass was failing to converge for the
MultiSource/Benchmarks/MiBench/automotive-susan test. The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now. Radar 7291928.
The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it. There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code. The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range. On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted. The second CPE had
been in range but the newly inserted entry pushed it too far away. Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range. Etc.
Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references. In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs. This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it. This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs. This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.
To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion. The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses. This is a very simple change to the code and should not cause
any significant degradation in the results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83902 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f98032ef64a777fe63d390539f901d7d6d4e868c |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Last week, ARMConstantIslandPass was failing to converge for the
MultiSource/Benchmarks/MiBench/automotive-susan test. The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now. Radar 7291928.
The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it. There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code. The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range. On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted. The second CPE had
been in range but the newly inserted entry pushed it too far away. Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range. Etc.
Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references. In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs. This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it. This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs. This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.
To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion. The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses. This is a very simple change to the code and should not cause
any significant degradation in the results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83902 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 31d9eb561b52a70ac181ad610115e35ab86298dc |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Another minor clean-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83897 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 32c50e8f9920bb7835eb42926945c9a1e6385de5 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Another minor clean-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83897 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 8454df9db700b63793f4f73f3df6e69d4a54572a |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83894 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| d637c1a4955c750b64414c4429ec707be2d8b990 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83894 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 93312097c5c22dac9e6fa9b2e63ab29708f51ba0 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use early exit to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83874 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 3b7573517ccd0f8f9e4bc64cf1923bae68e40d3f |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use early exit to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83874 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 688468aa23fe332955436b2acd062fd9bf289f8d |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change to return a value by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83873 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9d16f2c0baf91445764751b7c92cd1ff6d6d43f8 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change to return a value by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83873 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b15413cce529d24d6ae4e52116eac7c56f042023 |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a typedef for an iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83872 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 034de5f65f9139954cb01d94eaebbaefd294946e |
12-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a typedef for an iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83872 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 78e1a77cde46b7ba5de7d39b3a6db14e058f897c |
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Mark the LDR instruction with isReMaterializable, as it is rematerializable
when loading from an invariant memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83688 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 59ac57153be779fb2eaa1f2af2ad5fa05dde730b |
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Mark the LDR instruction with isReMaterializable, as it is rematerializable
when loading from an invariant memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83688 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 60bc0274f8e3cc55dd9332c4f404afee1c675b95 |
09-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Added another bit of the ARM target assembler to llvm-mc to parse register
lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers. Also added the
rest of the arm register names to the currently hacked up version to allow more
testing. Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83673 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| d7894f105a3c397a3d7f5c5136eee39f5865e64b |
09-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Added another bit of the ARM target assembler to llvm-mc to parse register
lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers. Also added the
rest of the arm register names to the currently hacked up version to allow more
testing. Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83673 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| c7692e0185faaab4a68386afc362d95be591b455 |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 5631139a699578e3281a1ae09f2cdf4d332179c8 |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| dbffb21337be67595a47585d60e8dda083038601 |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 8cdb26968669692e88ee0e4a444032bbd52da0d2 |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 18e94a7a1d02201407370ce9f73be9798bd4b7cc |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| c5c6edb74f5586f2436d8aafe638703ab56dd5f1 |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 7a8c6dfd8b82ead296bebcb567580cf08c5d449d |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
Also fix some copy-and-paste errors in previous changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 62e053e5a1e36ce8b59bf3311e84b619356da96c |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
Also fix some copy-and-paste errors in previous changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 47a1ff630bcc4c6ad5fc198b0b1fe9f7cd07a85c |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 0bf7d998b4e8a3edd2495bae6c35083a535b461a |
09-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 9c196ef25d4afaf139cf282e439df7afa2c4e6ad |
08-Oct-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 632606c724ebcfa6a9da71c443151e7a65829c99 |
08-Oct-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5687d8a26c08d089c60df2c92d048ab85bcdb2b9 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 30aea9d96ef8226749ff1eb73c2f3cb19668e077 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 5642cc9b885987140f2f385af99fd6ad3ff47845 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some unnecessary initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| cd7e327cdf6f3b6171905dec615cc7bf3b24f1ac |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some unnecessary initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 67902736c48e80706297e3141221c4951a15dabc |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment (indentation was wrong).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83565 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| af4a891273b82798e97ad3e59359d93f3c8d6c19 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment (indentation was wrong).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83565 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 94b5d43b15023b4757c1b08838104c6a14438e45 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| deb3141cf522cdd9f9330c8100280031ba5e0d9d |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 508ceee8273f7a4f579c60fd9e1ad2fee9f40241 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Cleanup up unused R3LiveIn tracking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
humb1RegisterInfo.cpp
|
| 1f30dcbd8dcf18cabb4be780fcf492869d5dcab9 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Cleanup up unused R3LiveIn tracking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
humb1RegisterInfo.cpp
|
| 4820d98aaad1442bfb4efb104a2ac91b64bc3a36 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Re-enable register scavenging in Thumb1 by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 65c58daa8b8985d2116216043103009815a55e77 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Re-enable register scavenging in Thumb1 by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 7200e5d850492bc316cf1cef72cfff01fb88fdb5 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 5adf60c03bcc72dd5462bdc4a5c72c1247a7879d |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| dd43d1eec2d82eb61329b5940fc2c7f4165cd9ed |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 24e04c535f528c27955664a8f4524ae33213e453 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 7ce4750b6014e38275dcf2878b6ca15a7111ac6d |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 0ea38bb93955a64477a66f9adca7eadab6635050 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| da8caccf975ceec8914586e3f0ae7e46a228e640 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| c67160c010b9aae5e7f912eaeee42cd0da6880c5 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 8c3be587276cc116d834bf213f80149e40add2b9 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| a4288080e62c6ecf94ebeafe84ab33a3b627d209 |
08-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| c7d2c5396f2876ed2ac8e5c3b65291a769a90767 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
reverting thumb1 scavenging default due to test failure while I figure out what's up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 9f3a559dff691bc1ed85089cb0870cf30a4a2d96 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
reverting thumb1 scavenging default due to test failure while I figure out what's up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 1d57f4b9260b0e0133e79e4fad874dfaf1739975 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable thumb1 register scavenging by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| ec1434dd8970f9bcd410ef6ffaa2d440995cb18b |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable thumb1 register scavenging by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| b172116673cb33453971b6308941bc7cbd2f624c |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some instruction encoding bits for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| b07c1716248cebf00b37ed5d89581369b1191a87 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some instruction encoding bits for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 931c76b4c08ea058d90f9fd5f5a59aea52010c0d |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 63c906343468dca4ac67ed85242d5a9fee95d57f |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 2a85bd13a0155cef6081a7f78e4b59c70ba8f5b4 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 66a70639dae4cbead3f9799406d98cb4293f2af5 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 5fa67d35b87341e9990fb7b3a26e3de7e76c0e64 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| d285575f87f1315a38bd23f89e75a776e102cd39 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 004a2e16d3ac693fad8bbd5a6798406653f672ba |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 7708c22baafcbfa407fc3441d73f6f3533ccf455 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 308327301d99c310723d2ac204dc1fc513f89243 |
07-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Add another bit of the ARM target assembler to llvm-mc to parse registers
with writeback, things like "sp!", etc. Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| 99e6d4e8392497d950d48b03f45c79b7dd131327 |
07-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Add another bit of the ARM target assembler to llvm-mc to parse registers
with writeback, things like "sp!", etc. Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a8b4362ee4e3a8442c18c5c951594a018cb7a682 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| ff8952e8a9dc01bba9605e90bd3b823d3cf43619 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 520f5611addbb5e14f6c0140155c94690e421414 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rearrange code for selecting vld2 intrinsics. No functionality change.
This is just to be more consistent with the forthcoming code for vld3/4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 228c08b8ddff75a9d5d617ab12eb683a25fe17a8 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rearrange code for selecting vld2 intrinsics. No functionality change.
This is just to be more consistent with the forthcoming code for vld3/4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b67fb2b7be5c577e88578d240998a7ed3bf210db |
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| b58f498f7502e7e1833decbbbb4df771367c7341 |
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| f68604a29b3058546a6ec8d7f244523d59893a3b |
07-Oct-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
and register spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
|
| 249fb339ad9d4b921a04de738b9c67d27e328bb7 |
07-Oct-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
and register spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelLowering.cpp
|
| 91e27daccce0af4bff6f9299fa52c8cbbeab5ce1 |
07-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Added bits of the ARM target assembler to llvm-mc to parse some load instruction
operands. Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts. This is a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| a7ba3a81c008142a91d799e2ec3152cfd6bbb15f |
07-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Added bits of the ARM target assembler to llvm-mc to parse some load instruction
operands. Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts. This is a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
|
| e9829cafca9811fa616f8046ce384b797814fa67 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld2 operations on quad registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.h
EONPreAllocPass.cpp
|
| 3bf12ab860751a55fc8c16517a992497b98be11b |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for NEON vld2 operations on quad registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
RMRegisterInfo.h
EONPreAllocPass.cpp
|
| 3360945de1c4c74c224806f22405ad8081b29701 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use copyRegToReg hook to copy registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83421 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 349d82d40003cb6e6c604c5a447ba692468a50a6 |
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use copyRegToReg hook to copy registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83421 91177308-0d34-0410-b5e6-96231b3b80d8
EONPreAllocPass.cpp
|
| 3443c216b30567ecf229ce43fe31ecb60e5e7ed3 |
06-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment typo.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a3e8bf8412481139827b61f83bdd84637af800b8 |
06-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment typo.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5fda434b0d4932d63b21ce3b5dd72c18e855da26 |
06-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Instead of printing unnecessary basic block labels as labels in
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83392 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e3cc3f3c84abfdf8eb3bd19dfa806ceea49f15d6 |
06-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Instead of printing unnecessary basic block labels as labels in
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83392 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5450fc15cb5de674d4e5203ab9ace59d3d6c38e5 |
06-Oct-2009 |
Devang Patel <dpatel@apple.com> |
Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83363 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
smPrinter/ARMAsmPrinter.cpp
|
| af0e2726835e096e32c30c1b88cc7a6232a6ef69 |
06-Oct-2009 |
Devang Patel <dpatel@apple.com> |
Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83363 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
smPrinter/ARMAsmPrinter.cpp
|
| adf4cf604eeca26d6a854945893fa6c264e02900 |
06-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 540b05d227a79443b2a7b07d5152a35cb6392abf |
06-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 82cdc06a6626e9a9fae300fafaeae9702ffb3808 |
05-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
strength reduce a ton of type equality tests to check the typeid (Through
the new predicates I added) instead of going through a context and doing a
pointer comparison. Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83297 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| cf0fe8d813727383d630055bb9d1cde21b00b7e7 |
05-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
strength reduce a ton of type equality tests to check the typeid (Through
the new predicates I added) instead of going through a context and doing a
pointer comparison. Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83297 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 8af7b535e3d97a9edb29b0ce3e6c4a4529b081a8 |
03-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a comment to describe letters used in multiclass name suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83257 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 916ac5b0690c529ce9a1a3615d84a48a5c907a69 |
03-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a comment to describe letters used in multiclass name suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83257 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 64c60918f15571fbb4dabdfa074c2bcdc0b9296d |
03-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix encoding problem for VMLS instruction.
Thanks to Johnny Chen for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83256 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 8f07b9e8a954c95a42afd4883bc422526b640b8b |
03-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix encoding problem for VMLS instruction.
Thanks to Johnny Chen for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83256 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 6f2bf0bd6f1ff49887d30f3433d05bd906e6b3d3 |
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
getFunctionAlignment should return log2 alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83242 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 048e36f5369b500c15c7e74933904983724981bc |
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
getFunctionAlignment should return log2 alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83242 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 4a6e6dd500a86c44803aa7b1414c8603d9e5c753 |
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Forgot about ARM::tPUSH. It also has a new writeback operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83237 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 892597943adc02583af32a86b4289f1fb02d2e4f |
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Forgot about ARM::tPUSH. It also has a new writeback operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83237 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| a2e9ca91163c46e55d5ee9e16efb3a1ab6a01467 |
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move load / store multiple before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 62a1b5db44e87eaba053483041943905b4a4046c |
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move load / store multiple before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 736fed9ff71ae677a7c947ac80ebb42a527de0dc |
02-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 9843a93e830e76f96e9a997b3002624a28ca5aa6 |
02-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 089aa85274d26ebec4989ac1ceeefba7fca5e5ea |
01-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| 471850ab84301dd47cab2bf8d694fcb5766c1169 |
01-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
|
| a9a6b6528197d68ea551f665bc6be722a0009630 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM::tPOP and tPOP_RET each has an extra writeback operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
|
| 10469f8e48e007989b0469e677d4000a1311ecd2 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM::tPOP and tPOP_RET each has an extra writeback operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
|
| 7c8d5ea09fb5e7a585533f711b9540e9b3b95a5e |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 0d92f5f76884513f8f5e014c61cb7a72ff576fa5 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 713ff84d1467c64ad625681baa355b49bcc44ca3 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Update ARM JIT emitter to account for ld/st multiple changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83192 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 7c043d7319330aaa8235384456ef2abccaa59716 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Update ARM JIT emitter to account for ld/st multiple changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83192 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| b43a20e3bce6b4b16151ec25ef3541494fce8425 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
|
| d20d6586759fe7a53ec8b1dde80622cda49e31b8 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 86049dcedaba49929bf6e4c1cd84f9d85cadb987 |
01-Oct-2009 |
Devang Patel <dpatel@apple.com> |
Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b0fdedb3fd123a47e7deca75d1e6f7d64218b07a |
01-Oct-2009 |
Devang Patel <dpatel@apple.com> |
Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1f9b67a27f82ba4d75625c2e260d40cb3b662393 |
01-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83178 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 29e066965fb84b3aad2840815c6d0602dafb0b17 |
01-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83178 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b5f835ee6e48aedbffb804a6bf5308465867e67b |
01-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 812209a58c5520c604bc9279aa069e5ae066e860 |
01-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cd8cb7f1e4075f66179e15deb0c0aecaf09fe4be |
30-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
The AsmPrinter base class contains a DwarfWriter member, so there's no need
for derived AsmPrinters to add another one. In some cases, fixing this
removes the need to override the doInitialization method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83170 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b6e4742da7ecada32ba8d018f7292a837d5d90a9 |
30-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
The AsmPrinter base class contains a DwarfWriter member, so there's no need
for derived AsmPrinters to add another one. In some cases, fixing this
removes the need to override the doInitialization method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83170 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 65a2b9aff1084c5c54afd4577555a5bf3b124114 |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Clarify comment phrasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83148 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 460c482ed38f5c2f91e29eaacf241928d3d77edf |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Clarify comment phrasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83148 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 140523508f5e2af96e8c01218b4c4fc1c73abcdb |
30-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a option which would move ld/st multiple pass before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83145 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 792e1f6df9d70970b5f658d56344ded87f3d7b42 |
30-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a option which would move ld/st multiple pass before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83145 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| ce096d7654254793f6df9dcfea8e44345afa42bf |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
When checking whether we need to reserve a register for the scavenger,
the size of the saved frame pointer needs to be taken into account.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83136 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d1a5ca6cb11763059ba1ee1c965cc69abff92e38 |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
When checking whether we need to reserve a register for the scavenger,
the size of the saved frame pointer needs to be taken into account.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83136 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c6f0c0268cdad78cdc3b8d4b4ad597d1c3ce7ba2 |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| c732adf3a1718d1b3e08adb11652100cab1efad6 |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5147f1174ae1b6f8af2bc03d8f9915bda2937961 |
30-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
For Darwin, emit all the text section directives together before the dwarf
section directives. This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations. Radar 7255355.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83127 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0fb34683b9e33238288d2af1e090582464df8387 |
30-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
For Darwin, emit all the text section directives together before the dwarf
section directives. This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations. Radar 7255355.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83127 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cf89a609bc2c368e2c5c970131edc40c08175893 |
30-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| 0dad89fa94536284d51f60868326294b725a0c61 |
30-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| 278c839fdb36f39a25935fd83e12144b374d4e75 |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
minor cleanup and add clarifying comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83117 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 17487ba60d171aa32b17e6c3ad6d5809e78f9868 |
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
minor cleanup and add clarifying comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83117 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 350c913b054b04ffd2c0041e8cf63d6031cb060b |
29-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| fa1be5d99153a4709740ce5aabba3793e9f77982 |
29-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| e68f04e420b7b2422586e4927db982f30c654e2f |
29-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83023 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ec9eef4a15157fc0a05feff933848aa9283bd1af |
29-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83023 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 56a506296805c4967326a41bd5b0ae3202ace90f |
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83008 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| fd847118eda59dcfa318dcb0895d1764c2a7a0ba |
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83008 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 8f12c7cd04af1b2eadddf46f00bf9527fa484188 |
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
|
| 26207e5bf1123a793bd9b38bcda2f569a6b45ef2 |
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
|
| f4ecc68efa92c06e2de1937f2a6408f57318ee3f |
28-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMTargetMachine.cpp
|
| 522ce975327e1aeba8317b233cdb54366e2645b5 |
28-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMTargetMachine.cpp
|
| 16c012d9a28fe4db3ee081192a587ad7f30d4cc2 |
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
EADME.txt
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| 5adb66a646e2ec32265263739f5b01c3f50c176a |
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
EADME.txt
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| fe89b6a96501aabf8edbd991e9fb81108ecde782 |
28-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
Disable rematting of it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82975 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
|
| b0d8d781380cb2ea94692d25533f3bd04fd78dce |
28-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
Disable rematting of it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82975 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
|
| 609289558295a0f4a1f6529c14ffe96db547ec41 |
28-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 6a2fa325c1763a0fb27eceaa78b3a9bf683416bf |
28-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 340684f156c06a256649f09657a198653fbe8881 |
27-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable pre-regalloc load / store multiple pass for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
|
| e298ab26b11cf6e278b4876bbc5b890e234d4029 |
27-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable pre-regalloc load / store multiple pass for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
|
| 0e367e3f0866e9f690b307b4feefaec8d4a3bdfb |
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Really remove this option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82838 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 72c158f90865852cd19aa8efb524ace74797fbba |
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Really remove this option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82838 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| c2bb61fd9699873daeba366e97019d660c4006ca |
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove a couple of unused command line options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82837 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8981572662300b97d166dacbfee188e463ff503c |
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove a couple of unused command line options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82837 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 7f4c4564fc1f3955b136a050941b236467fca747 |
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82836 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 8f05c1004a642ba79c609b40cb3b6524d810b5f3 |
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82836 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| e222c72bba42281674d39d3d33dd75fb8f926ce5 |
26-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Regenerate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82814 91177308-0d34-0410-b5e6-96231b3b80d8
RMPerfectShuffle.h
|
| d1c37f5b2099233dc337f8b652de70d36e8f3b2c |
26-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Regenerate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82814 91177308-0d34-0410-b5e6-96231b3b80d8
RMPerfectShuffle.h
|
| 65561df4eb4eb52ebf75755e9f9eafa36929fa0e |
25-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up and prepare for Thumb2 support. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| eef490f45919c8f279e40b8b5ef09f612ec6ce2c |
25-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up and prepare for Thumb2 support. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 4e3bb1bc735783b73f2dcca82c86b7faca1a87e8 |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 61fda0d889b3578fe435455679182c231a649aac |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 36bff0c1f84aa517c66320c6864e4443e818e574 |
25-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Finish scheduling itineraries for NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82788 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
RMSchedule.td
RMScheduleV7.td
|
| 658ea6099724d0aaf5297a02b185f8351fcab389 |
25-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Finish scheduling itineraries for NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82788 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
RMSchedule.td
RMScheduleV7.td
|
| e55e52532c4a76b7ec83e530e3fe3b0bc0b8c00c |
25-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some comments to clarify things that I discovered this week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82773 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58 |
25-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some comments to clarify things that I discovered this week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82773 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c1c8b5e19b33c8b5e52c4b516669181f18feb98e |
25-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
|
| 0035f9c3b9982eeef098b608fceb7572df969b3e |
25-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
|
| abd0e3ddaf34e1589bae68eecb9fcfb7f14ac297 |
25-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| 3d6cb88a64fe67064de206405951eb326d86fc0c |
25-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
humb1RegisterInfo.cpp
|
| ed17499ee7446c5da5638f6c4c34eea660808a3d |
24-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Make the end-of-itinerary mark explicit. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
|
| 1f528956921561f277a8c697e0202ac1e9a9c1d5 |
24-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Make the end-of-itinerary mark explicit. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
|
| 78caa12a415bbd16db04088be6378398d4909b6f |
23-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint NEON scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrNEON.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 127221fbdceba333f5e243f5278a691a7d182898 |
23-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint NEON scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrNEON.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 3fad552803d264b6bf83981de305e7080cb8ef4f |
23-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
ARM does not support offset folding (yet). Disable it for now.
This fixes PR5031. Unfortunately, there is no small testcase :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82643 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 48e19352840a5f7012493ead894e81a2dbec1778 |
23-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
ARM does not support offset folding (yet). Disable it for now.
This fixes PR5031. Unfortunately, there is no small testcase :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82643 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 35d4912e3b08a8a2d0e01c0ef8b23407f8efa8db |
21-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Cortex-A8 VFP model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| b2bb7db9e242c54a4a84448ab503015a148e9286 |
21-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Cortex-A8 VFP model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 98cb5536ab1aa5667bb5b602bf691631f3bbaffc |
21-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Register the MachineModuleInfo for the ARM JIT, and update JITDwarfEmitter to
assert if the setModuleInfo hasn't been called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82441 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 003de66227d235a9ca7373d9cb2c0b1b6ae5b81a |
21-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Register the MachineModuleInfo for the ARM JIT, and update JITDwarfEmitter to
assert if the setModuleInfo hasn't been called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82441 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5f3a54090af5d61d35de2158542ff76fc9ef053f |
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 764ce99aff6b5db12d99c31467c9e9b7c5612cf2 |
18-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a typo in an assertion message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82284 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a15de00f8246f19180b26ee5fe7ff8f436e0de08 |
18-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a typo in an assertion message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82284 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d7dc983029cf293dd67637c27b92c04c0baf968b |
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 94ef1628bb9b33484a3887a742fb4cc662b41fd8 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand vector floating-point conversions not supported by NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82074 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0696fdf3220c4cdd7fc518274048a35091cc17b1 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand vector floating-point conversions not supported by NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82074 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 71dd44de32bd74e60887991c9f06ab3917229a52 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand some more vector operations not supported by Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81969 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 642b32910425ce98059cf659c7cca84670435568 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand some more vector operations not supported by Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81969 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 098abb4f0f560ae8e2c2e649f7e16046740f3cda |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Neon does not support vector divide or remainder. Expand them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81966 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1633076c47f10a8d8735e81588e9cb07ac32efc8 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Neon does not support vector divide or remainder. Expand them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81966 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e8fefa0a3f88ebd6f5e24617ca5d5fe7c4734ef9 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand all v2f64 arithmetic operations for Neon.
Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81959 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 74dc72e89bba8c67d2c9e455bad20f067b180499 |
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand all v2f64 arithmetic operations for Neon.
Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81959 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 19f0725ebd200ab818b0431a64943eebf61c794d |
15-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for
VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR. The asm printer,
however, silently drops the offset, producing incorrect code. Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81879 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| e4863f47596794df3dd955b6b7064863c50eabe4 |
15-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for
VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR. The asm printer,
however, silently drops the offset, producing incorrect code. Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81879 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| fe9c3803a79895c50881154a3a381f61692e13ae |
15-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 85111a9c07ad2bcb91cbccf34d0653dc4687d774 |
15-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a045a696be25f2dec8969a68283582b33d660aae |
15-Sep-2009 |
Ted Kremenek <kremenek@apple.com> |
Remove invalid add_dependencies line to unbreak the CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81827 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
|
| 83d255e43ef223b0556a61ab33d514db83cd434c |
15-Sep-2009 |
Ted Kremenek <kremenek@apple.com> |
Remove invalid add_dependencies line to unbreak the CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81827 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
|
| 3d711a3d76b29a8b13ec316c81d0161df47818ce |
15-Sep-2009 |
Kevin Enderby <enderby@apple.com> |
Added the first bits of the ARM target assembler to llvm-mc. For now it only
parses the .word directive as 4 bytes and ARMAsmParser::ParseInstruction will
give an error is called. Broke out the test of the .word directive into two
different test cases, one for x86 and one for arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81817 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
smParser/CMakeLists.txt
smParser/Makefile
akefile
|
| ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70 |
15-Sep-2009 |
Kevin Enderby <enderby@apple.com> |
Added the first bits of the ARM target assembler to llvm-mc. For now it only
parses the .word directive as 4 bytes and ARMAsmParser::ParseInstruction will
give an error is called. Broke out the test of the .word directive into two
different test cases, one for x86 and one for arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81817 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARMAsmParser.cpp
smParser/CMakeLists.txt
smParser/Makefile
akefile
|
| 3107c9ecfee9c403e89e3d5eccbc00d1099fc151 |
14-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
trivial whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81773 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| a67240399316f42d0da235053c77d71e6204f21f |
14-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
trivial whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81773 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| f0a25de172e71282bba275a51ce75849e5407f8b |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove all but one reference to TargetRegisterDesc::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 762ccea600158bb317dcccdff3303e942426cb71 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove all but one reference to TargetRegisterDesc::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 213703ced9eeaa585c06387ae3c643ea4701462e |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
the tblgen produced 'getRegisterName' method does not access
the object, make it static instead of const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81711 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d95148f073c31924f275a34296da52a7cdefad91 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
the tblgen produced 'getRegisterName' method does not access
the object, make it static instead of const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81711 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9222169c3ad7e619d1a8ab155b7a1118182c3c34 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
make tblgen produce a function that returns the name for a physreg.
Nothing is using this info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81707 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 05af2616d0df19638e799d3e7afadea26d96a4ba |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
make tblgen produce a function that returns the name for a physreg.
Nothing is using this info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81707 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2faa4ef57551d45e7b58b1827ae8156cea221637 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
replace printBasicBlockLabel with EmitBasicBlockStart,
now that printBasicBlockLabel is only used for starting
a MBB. This allows elimination of a bunch of arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81684 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 70a54c07a0807bf89d1a8b4414e53298c376eb61 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
replace printBasicBlockLabel with EmitBasicBlockStart,
now that printBasicBlockLabel is only used for starting
a MBB. This allows elimination of a bunch of arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81684 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c6f802dd7f346ac5a44bbdc57d264ed928fe1e7c |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
convert some uses of printBasicBlockLabel to use GetMBBSymbol
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81677 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 325d3dcfe4d5efc91db0f59b20a72a11dea024ed |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
convert some uses of printBasicBlockLabel to use GetMBBSymbol
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81677 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 02791b0d5c7fe12bf1ada874da30dd5d0440bc98 |
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix merge problem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81658 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 2a52122b304045e73a4a174259ffcde772e33040 |
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix merge problem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81658 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| daf700156a4b1aec6f85be6f611f2f949b154f75 |
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Define proper subreg sets for arm - this should fix bunch of subtle problems
with subreg - superreg mapping and also fix PR4965.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81657 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 20c35ec427b4feefb827392b2cbed4cfdcaa015a |
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Define proper subreg sets for arm - this should fix bunch of subtle problems
with subreg - superreg mapping and also fix PR4965.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81657 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 3600d16e551d4b49d3d8df86d5c90061804d5c7f |
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| e56f9085b1e96f0cc302c678f1c00877676e455e |
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 5b01f934c23227abf954e317b5b65cc77f38c21d |
11-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Revert array initialization regclass change so that the initialization stays static, not runtime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81560 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 82b3c2e40417098f9af0c33150c4b1c66ae1747c |
11-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Revert array initialization regclass change so that the initialization stays static, not runtime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81560 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 21f15abfa99b786925bb1b36717b454ac800251b |
11-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Update register class references to use the global constant ARM::*RegisterClass names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMLoadStoreOptimizer.cpp
|
| e11a8f565c6a019ddc54667227be9c4d8f117473 |
11-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Update register class references to use the global constant ARM::*RegisterClass names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMLoadStoreOptimizer.cpp
|
| 50e503fc4a90ecd8e98266c4a68c566e5f3e315f |
10-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Proper support of non-lazy indirect symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81422 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 08669746d04468898b094908484946216628d359 |
10-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Proper support of non-lazy indirect symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81422 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 71429f87316fc88ebe54b904c4b1326a71fbc3ec |
10-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix double load / store multiple encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81403 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
|
| 10bf734e6e0b5aba79dc199d611dcdec54a1e48e |
10-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix double load / store multiple encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81403 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
|
| 10371a5fdd1b829b3ce0cbd6d0721c700bde1e55 |
10-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cd3b9a4f17cf78f208765ab2ab01f2019a9e5651 |
10-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 32d4cc74e1075b6d9f77c75ff6099784ad4f15b2 |
10-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove DebugLoc from MCInst and eliminate "Comment printing" from
the MCInst path of the asmprinter. Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter. This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.
This also fixes an xcore strangeness where it inserted two tabs
before every instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81396 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c5ea263a23f4f15587e35c9cb07cf72a9fba7613 |
10-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove DebugLoc from MCInst and eliminate "Comment printing" from
the MCInst path of the asmprinter. Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter. This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.
This also fixes an xcore strangeness where it inserted two tabs
before every instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81396 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e34788cb7ed482bf3b51075f1b06ccc03021fbac |
09-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
hoist the call to processDebugLoc out of the generated
asm printer into the "printInstruction" routine. This
fixes a problem where the experimental asmprinter would
drop debug labels in some cases, and fixes issues on ppc/xcore
where pseudo instructions like "mr" didn't get debug locs properly.
It is annoying that this moves the call from one place into each
target, but a future set of more invasive refactorings will fix
that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81377 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 634cca377a8254cfe8a5afe99ef2e6c6db7f0c6b |
09-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
hoist the call to processDebugLoc out of the generated
asm printer into the "printInstruction" routine. This
fixes a problem where the experimental asmprinter would
drop debug labels in some cases, and fixes issues on ppc/xcore
where pseudo instructions like "mr" didn't get debug locs properly.
It is annoying that this moves the call from one place into each
target, but a future set of more invasive refactorings will fix
that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81377 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 52f6f63fbd1339c08b982355b62b85dc344add50 |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81318 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 28d63b169938fa95cf481b64ef6e4bc1849dabef |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81318 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| c84d4d3a2e752a4ba621587c066c1177cb8d5f40 |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure to make stub region writable before emission, executable after emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81311 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 04cedd3c8f6c7d00e06f63a49aaef05d1d4a726f |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure to make stub region writable before emission, executable after emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81311 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| a989293ca8e2c88ac10cf6fb577a9ece58b7b845 |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81310 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7995ef3b18357bb4a77ff7e9e4981eae7947e765 |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81310 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7b3c2ad4b0e7825170e90aadb07fe99408d4046b |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove comments which don't add much to .s readibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81306 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| cdf23b950a0a4c59b48b5dc6f18ce38383e3cc3c |
09-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove comments which don't add much to .s readibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81306 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 14636a5b8822276713045b4322b1f9f9c0c7c600 |
09-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 2ba62ef7f201b2e8f61c6988e76b40c7c8a6a191 |
09-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| dd528195c766db4211a29e0955e5f888f322dc37 |
08-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 6ca0b9e7220911a6d1fccf34e532e69c7e37cd2f |
08-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 05db668fe21feee223e19fe50ddeb6456ddebafb |
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| c2d98bc0d682419f09659d94afefd6a6266dd6ee |
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 5c3f915679bede35de38a5702359ab5befc38b95 |
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some unused variables and methods warned about by
icc (#177, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| b7c5bdf843419e4222770475c27932c4c8e5c303 |
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some unused variables and methods warned about by
icc (#177, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 9c2ed5cff22b49e07be176f3d4830b5bc67739c6 |
04-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80978 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e9952213086c865eb678bd3f4c9c7d849f0249d2 |
04-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80978 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3d88e9179113826d90cfe1653b8497e59798858b |
04-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Calls clobber FPSCR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| e8d82c0e4fafb95b1807ce4387a48587537bcb51 |
04-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Calls clobber FPSCR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80956 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| ba2cf3d635dcc68ac416f56b767fd79d77ea7c83 |
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
|
| 63476a80404125e5196b6c09113c1d4796da0604 |
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
|
| b261a1986acd86bb414d8e9e190a4e15742efc44 |
02-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
More missed vdup patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80838 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 69d1c1aebf009e58157e233cd7f2338e654e8d05 |
02-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
More missed vdup patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80838 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5838baa4a8aedfd453a5b0663425979c77e4e285 |
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d5496d944b0095cfd0d1cc93386a3c569b7f06d5 |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
reduce size of SmallString to something more reasonable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80710 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ee793a6c197b2cccfee96c6da1bbe6a2048830cc |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
reduce size of SmallString to something more reasonable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80710 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c2d6585e5e77e5b44a9440f7cb821dada5009692 |
01-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for generating code for vst{234}lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 8a3198b770c9fa7e8319a96bcbcfd85202342eef |
01-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for generating code for vst{234}lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 1e58780928c42ba7c34deb7bbb35c17391b3d36e |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Use raw_ostream instead of sstream
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80704 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c40d9f9bae70c83947bf8fa5f9ee97adbf1bb0c0 |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Use raw_ostream instead of sstream
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80704 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 02b0e35f988abea2d6e5a07a854b4c6192872355 |
01-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
RRX reads CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80699 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| ca01a8d4aba723e3b1838e5e2034efbc7efa859d |
01-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
RRX reads CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80699 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| d14b8b63b3557e85950beb061a1d8b01cff4eadf |
01-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generate code for vld{234}_lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80656 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 243fcc5a6901e75e7ca5c374e706a634593ec17f |
01-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generate code for vld{234}_lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80656 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 4b673ee8fb5f7351de61d8bc06fb8958aa846d93 |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Fix compiler warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80650 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 27830e39c4e960a5c372deedfcd082d6393d9355 |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Fix compiler warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80650 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 5e0257f9b7567c8c285ee3115c10d552c7c037fb |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Clean up LSDA name generation and use for SJLJ exception handling. This
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80649 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 3fb2b1ede30193b59a651328a946174196b20610 |
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Clean up LSDA name generation and use for SJLJ exception handling. This
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80649 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 08ed20d6841e1879cff1c6b7717b64fd400dc913 |
31-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80615 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 029599bf018c4000cf1b8d93ca9b7e05063dd6a0 |
31-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80615 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| b759ebc5bc48ee93a9f4b031ec6ed3247028d77c |
31-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Normalize makefile comments and sort cmake file lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80584 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
MakeLists.txt
|
| b4f770b68a2f1890e17f634b695d19bb7d07168d |
31-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Normalize makefile comments and sort cmake file lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80584 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
MakeLists.txt
|
| d33527768525e6447c6fdcf521ffb975165dbc7a |
30-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add missed pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80502 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| d91aafd0055a10230f3d606a933b2dac4f68284b |
30-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add missed pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80502 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 243874430bb02c8f76b7603cbc8f31ebf2749785 |
30-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
Remove the assertion and generalize the code for ARM NEON stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80498 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b00c03bb3548d1c2fd7ae95d6921d1aebbd5ca87 |
30-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
Remove the assertion and generalize the code for ARM NEON stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80498 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cb7c98d9ef32354166106ff8218fb9fcbb8b2d24 |
29-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not assert on too wide splats we don't support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80409 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 71624cc7861c5ceaa72786aef2cd290bbb7fa33c |
29-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not assert on too wide splats we don't support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80409 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 44e0a6cee931258a05b190f9e6e411a6d276c96a |
29-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add missed extract_element pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80408 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2324bdc1ee1b4b1a92ccde15848d2f2ad4662232 |
29-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add missed extract_element pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80408 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| c299914a58baed2d7cf594494dbba60880d476cd |
29-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
|
| e4e4ed3b56f63e9343e01bf0b2ecd7c1f45d296c |
29-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMSubtarget.cpp
RMSubtarget.h
smPrinter/ARMAsmPrinter.cpp
|
| f14af431e0f9724474dfa923ba940ecaf19316c7 |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning, round two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80354 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 19bb87d0f80f3e6eed38a9fa267bf2b0474aeaab |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning, round two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80354 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 3ab6715ba17ac6726bd92a4514c68c5e58c3c884 |
28-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| d17479e8458d17575e2532d9e8a61057b057a33d |
28-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| c24bcdb66bd5b6904147ac443ca44da2660f9223 |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80338 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ca7943226e1d58f4f3ae936f93aa03c2a72289ae |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80338 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 5e1d21856de4bf387cccf8365885c45c87642dfb |
28-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
v4, v5 does not support sxtb / sxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 0e87e23f6e5f6615cf178933dcdec7a49436bb7a |
28-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
v4, v5 does not support sxtb / sxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| aa152ae811d8e0ffd01c7a8b454d595cb1a1a31f |
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hopefully the final missing part :(
scalar_to_vector is fully legal now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80251 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b5fb4282cd2968be81a853c0f3199d167e402bdf |
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hopefully the final missing part :(
scalar_to_vector is fully legal now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80251 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 872393c20ee29eaae1746deed115f06192526f64 |
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Forgot about actual change :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80250 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b5cdf873bcfb216e1866d05693822741313b5076 |
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Forgot about actual change :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80250 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| baee7b2a5501a45a59554b5bafd87264a2edc442 |
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Transform float scalar_to_vector into subreg accesses.
No idea whether this is profitable or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80245 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| fdf189ac9709bd4b645f23010689fd4686c37cc8 |
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Transform float scalar_to_vector into subreg accesses.
No idea whether this is profitable or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80245 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 9daa0677ac901b0f54bdba31dc3913b92df58e50 |
27-Aug-2009 |
Misha Brukman <brukman+llvm@gmail.com> |
STRD and LDRD require ARMv5TE, not just ARMv5T.
See http://llvm.org/PR4687 for more info and links.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bf16f1ddc47303bbbf343152997a342c0c4140bc |
27-Aug-2009 |
Misha Brukman <brukman+llvm@gmail.com> |
STRD and LDRD require ARMv5TE, not just ARMv5T.
See http://llvm.org/PR4687 for more info and links.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 363cd759d4186bdae7b49e89a0d434749d6198aa |
27-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
humb2InstrInfo.cpp
|
| cdbb3f5d3311e0f46d22bc8daa211b2fab3541cb |
27-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
humb2InstrInfo.cpp
|
| b1b88455b18224867a8d2fc6c3202b6ce12e0a1c |
26-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80117 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 31fb12f93a30cca700a20088e97d8b05d13d5fca |
26-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80117 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 886f20275a78a1b03b83a8145a62f5e4cfbb1c99 |
26-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand scalar_to_vector - we don't have any isel logic for it now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80107 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1cb852b0ea0a63cd9b93306e2397d97a0688192c |
26-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand scalar_to_vector - we don't have any isel logic for it now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80107 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 82d30b73d3a37de0ec7960a4e099ef9e255d4f11 |
25-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove some unused SDNode definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80015 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a123239a5fcdedf7254802dba44f0dfb4af5e907 |
25-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove some unused SDNode definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80015 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 316062a4d193609d98e80e64389fc2094ad8c515 |
25-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expose the instruction contraint string as an argument to the NLdSt class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80011 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 2a9df47abd75c0337e0254f09070f90023509066 |
25-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expose the instruction contraint string as an argument to the NLdSt class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80011 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| da55128a91134c0199390afe1c0081b3574fad93 |
24-Aug-2009 |
Dale Johannesen <dalej@apple.com> |
Make linkerprivate work for ARM and PPC. Testcase covers
all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test. Generic seems to be
the best available, maybe there should be a Darwin subdirectory?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a60e51f7e81bdb99ca331776a06c93dfd6043762 |
24-Aug-2009 |
Dale Johannesen <dalej@apple.com> |
Make linkerprivate work for ARM and PPC. Testcase covers
all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test. Generic seems to be
the best available, maybe there should be a Darwin subdirectory?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8755dee89ba6ae78f867a5f117212b569c2681fb |
24-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the last uses of Config/alloca.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79873 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| dbe89cd2f019c23f41fe6471b8bfe0b45cc1c1ce |
24-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the last uses of Config/alloca.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79873 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 7966fe8c4e6a6699adbbd789cb3d897021f4b9e0 |
23-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove Streams.h from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79853 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 072a56e37de0e4872ce0340b0bd5585ba15fd0c3 |
23-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove Streams.h from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79853 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 2c6014b7beb12b2eb1f2487d3b52ebea13b7f58e |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the last DOUTs from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
|
| 893e1c90a03a53cf13f73849324e83612688428a |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the last DOUTs from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
|
| d71b0b0bc402d151d7ea364cad32ad44ac7fbee2 |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove various std::ostream version of printing methods from
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79813 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
humb2SizeReduction.cpp
|
| 705e07f578e2b3af47ddab610feb4e7f2d3063a5 |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove various std::ostream version of printing methods from
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79813 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
humb2SizeReduction.cpp
|
| a2cb51a5eaa6f188ad128c2ab7430081a99776ff |
23-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Forgot to update some CMakeLists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79780 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| f682f3d019794d4402b73701a06a4bb117f5d5e7 |
23-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Forgot to update some CMakeLists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79780 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a5ef4d36198b2b591b592c595978ed7d3ac96a18 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 33adcfb4d217f5f23d9bde8ba02b8e48f9605fc5 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| cd4cab9054f1d9573675c7d0beed14b59f14ab3e |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79773 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
RMMCAsmInfo.h
RMTargetMachine.cpp
|
| 2807afa664b579af4c559b3880d6763b9e7e236a |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79773 91177308-0d34-0410-b5e6-96231b3b80d8
RMMCAsmInfo.cpp
RMMCAsmInfo.h
RMTargetMachine.cpp
|
| 621c44d3606307a3e9e56add33539c78c0009ab9 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.cpp
RMMCAsmInfo.cpp
RMMCAsmInfo.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrInfo.cpp
RMMCAsmInfo.cpp
RMMCAsmInfo.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| c3d25a1ce7c6718d6304464aacb2005c1ae99de7 |
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
|
| f44f5f18682a475983b00d9941df5952a6d34e2b |
22-Aug-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ce392eb3ea16b781de89b7ff8f42c39f8b3df30e |
22-Aug-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 30ff44954a2b0241c9b508f9cf2b79c9193f20ac |
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 4f38b383d5089c49489a9a56d8efd0eb76048b3f |
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 8446276f4b086edd69bf329e88a2047dafc8a31f |
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
now using shuffles instead of intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c692cb77aaa8b16bcc7fe0c70d47adce94c43911 |
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
now using shuffles instead of intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 394bbb86bff564329dc3c7728956428188147246 |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 051cfd683f698b0061656fbff01d3971d2f3d58c |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 0a0297852932f078c1872b9585ee1a2e4491d6fd |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79624 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMPerfectShuffle.h
|
| 1c8e581832440a114c9587d41473d107de4cac74 |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79624 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMPerfectShuffle.h
|
| be262ae09d3579c9c17930fc4fc7012b84a8bc71 |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
|
| 62e84f177d4519bf719d188496faf8b6c247e3a7 |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
|
| 755fa0b4fd5f69b1a47747d0a3007082d2936dc1 |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand EXTRACT_SUBVECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79621 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8e6c2b90410ae8c8f5a9a89e35de1dcc62840dbf |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand EXTRACT_SUBVECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79621 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6c28c006c732c46bef1f367edeeb992051307e2b |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide vext.{16,32}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79620 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 5da894f5c45ad7130158e4d85fea93ae450692ba |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide vext.{16,32}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79620 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrNEON.td
|
| 2a0296f324bd6d4c342bbb525793add75da96cea |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79619 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d0ac234b1b3a88946ad8bb52677764f3e3eeb8b3 |
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79619 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 9d35d080280ff92147d325ac65b3f120e96f7560 |
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d4b4cf524b8afc342b618254d69f48f214b60093 |
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| af35b283da82d4bdd623e8b7d5ae0c16fe55e4fb |
20-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious copy-n-paste bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79535 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 89d177f017f5a41898f373f5c75a91eed0e96c8c |
20-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious copy-n-paste bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79535 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 236ccb5fa1cd720da928d85124fdbd0669633e10 |
19-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Update Cortex-A8 instruction itineraries for integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 5d598aaf3de7f506749f4a0a142fe0121854e1a6 |
19-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Update Cortex-A8 instruction itineraries for integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 3ac391379082bc13e9d8a374ed8f8fbf66c6131f |
19-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for Neon VEXT (vector extract) shuffles.
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| de95c1b88be44d4af916af8fba9d7940b7e98e32 |
19-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for Neon VEXT (vector extract) shuffles.
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 73266f9a953d9cb0833df1208c455725f5adf2ef |
19-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate AsmPrinter::SwitchToSection and just have clients
talk to the MCStreamer directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79405 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6c2f9e14fdf14d8c1c687c6bd9918183fa7f8a7f |
19-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate AsmPrinter::SwitchToSection and just have clients
talk to the MCStreamer directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79405 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a793115a75b24b6b59de79d12b331a4829c6b9e2 |
18-Aug-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify RegScavenger::FindUnusedReg.
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMLoadStoreOptimizer.cpp
|
| c0823fe7c679ca8f7d1667a310c2fca97b9402d5 |
18-Aug-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify RegScavenger::FindUnusedReg.
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMLoadStoreOptimizer.cpp
|
| b4c98a3b126da90477787b721329eb227a181e37 |
18-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix revsh pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 51f39961c3558ee71b6323d3713e9ddd2354e099 |
18-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix revsh pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 84b4f2ce266b1bf1616f0f29cdc61db461f53b00 |
16-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79189 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 9ae7d44d95de16be5ed7bea7e1117160d9e2d5ce |
16-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79189 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 5c433f394bc5e2ebc4025bdaad5960124de3f40a |
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reapply r79127. It was fixed by d0k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| af5663405834ca7cf4a847f2efa2d624ce99b1d8 |
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reapply r79127. It was fixed by d0k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 7f3ce7ac58e53176f491d4433c7a7d15988ab78b |
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| f865ea85bd9d3e04aa795ee03cfc8db339f8c9b9 |
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c109ecf5d6f45edee969a74caabf24213a70d6dc |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change allowsUnalignedMemoryAccesses to take type argument since some targets
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 088880cb192fb6dd5b1bf85af62023c5ca3da38f |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change allowsUnalignedMemoryAccesses to take type argument since some targets
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ff5c7c42d1f1c13ad8ba7f0449a3ca785a19fb95 |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turn on if-conversion for thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMISelLowering.cpp
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| bc9b754091ea281e769e487f396b40f6675b9edb |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turn on if-conversion for thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMISelLowering.cpp
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
humb2ITBlockPass.cpp
humb2SizeReduction.cpp
|
| e8e9b04005a57d638d97de966c8a55c0b68dff56 |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not use frame register to reference fixed stack objects if the function is frameless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79067 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 010b1b9e7b11bced0b277a4d808226ba2af3044a |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not use frame register to reference fixed stack objects if the function is frameless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79067 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| fee1f6802d01a05fa8e80cc4ad301e8f2062ac81 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 98a0104014e9bb6ed89c2572f615351fd526674a |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| cdab71fbe3e03cd2481f648ce9f8ea24e3fc73a5 |
14-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Allow targets to specify their choice of calling conventions per
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79033 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 72977a45a8ad9d9524c9b49399e89fb9a3a676ed |
14-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Allow targets to specify their choice of calling conventions per
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79033 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a71c2b6f6ed989e6f9d41c5b0c14e8ba98b0a57b |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 lsr hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79032 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e6c835f42418c0fae6b63908d3c576a26d64cab2 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 lsr hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79032 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| bdab42c850b035ae48f7ee7ca1bcb467a3c0e976 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79026 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 59bc0604e5283d4f57d074a99891e6b744b4d333 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79026 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 41cb734efafb8fa8bc22a0f33dd137b105b95be6 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79022 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bba9f5f37859f1d53ff061695bfc8c22133c6f0e |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79022 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f7b61a1072a2bdb4a6ba40ba1103663c4f1d8c6d |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also shrink immediate branches; also more assembler workarounds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| 31b99dd76035067b1c3cc6c7e9d663b7b0210938 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also shrink immediate branches; also more assembler workarounds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| 4c292c3564ca6b8102e16d23c4ebc048bc3fc8d9 |
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Now that all the legal Neon shuffles (or at least the ones that have been
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78995 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 22cac0d9b328ef89a6aafdbda9cd0cea71f8ce46 |
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Now that all the legal Neon shuffles (or at least the ones that have been
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78995 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f4f1a2736f5cce5e6b7459dde6084332d87f21e7 |
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| c1d287b4b73487b6ab094a253a7357addc1d8b84 |
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 206f6c43cc7b1e8d6ae108a6cee78182e608ac7d |
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 0ce371082565330672c276f76297f46b362d74b7 |
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| a441c1a63b3ee5756a43e561bcd245e198313a98 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ADR and LDR from constantpool late during constantpool island pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| a1efbbdbf3217598f334a6f39dab84ca06f5de41 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ADR and LDR from constantpool late during constantpool island pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| a3ec27c1d07bf29ecd06c0575a0d86c3cb80dce5 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78968 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
|
| 1135a232eb99c033d820d2b278e6f1d19a45cd29 |
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78968 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
|
| 35b4707edb32008b1a7976dcbf3920b1160fc1c6 |
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMLoadStoreOptimizer.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| ee3b6c614de852e172878213380d9de311687779 |
13-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert 78892 and 78895, these break generating working executables on
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| b42dad4761968b4b052e72494ce1bf0c7b3aba3e |
13-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert 78892 and 78895, these break generating working executables on
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 3990e39b87261086add8cf1399b8af195fa0673c |
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add missing defs of R2 and D1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| f35d21617e9c6616eb127355b7c7cd3a5aa7cc58 |
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add missing defs of R2 and D1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| a346e714f2836fdbb07582c5c7d4e8bb3ffafaf2 |
13-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Finalize itineraries for cortex-a8 integer multiply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 6d3d9c3fc3b98e9c12ca38acaffa77cf02deffe6 |
13-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Finalize itineraries for cortex-a8 integer multiply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| dd4f75b26fa233ce68361d709adf757dcdfdde55 |
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Remove unnecessary newline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 8db5cce0217a2b76a954cb97de95c91e76edf59c |
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Remove unnecessary newline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 207a4ba3cce02d3073f24980f45251304d5808b5 |
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Correct comment wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 1add659b0a70bf2bdaa3cb93fa5961359fb7df45 |
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Correct comment wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 2868cf17878628907f07ceb5cf0eb27c91a9bbcd |
13-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
tPOP_RET now has predicate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78898 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 48bd7e3bbc481cd9b99a981f7d8e06989774f9d2 |
13-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
tPOP_RET now has predicate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78898 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 628c99a8051b17b605fc489d11f3e49c5d8e6e67 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a fixme message about canonicalizing floating-point vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78897 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bfcbb507c232bd386b37abcbc5f478d8a9cccde9 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a fixme message about canonicalizing floating-point vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78897 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 62255b5d072362c0f6d1fd7610ff51014ab44c3a |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert r78852 for now. I want to do this differently, but I don't have time
to fix it tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78896 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| bab812b4b0126839fe6e026aad54c90164c89765 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert r78852 for now. I want to do this differently, but I don't have time
to fix it tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78896 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 54bf800f169cc9594cd79da984fa0c7e32d3b30a |
13-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's ok to spill a tGPR register as long as it's still allocated a low register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78893 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 86e5f7b6f8cbe20ee564f3b566ce23419ac44ec4 |
13-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's ok to spill a tGPR register as long as it's still allocated a low register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78893 91177308-0d34-0410-b5e6-96231b3b80d8
humb1InstrInfo.cpp
|
| 9fa0f937cb7795a5b6676788e36608b9bef4ff19 |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
don't need to be exported from the .o files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78892 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| b2d3169d96ee780e6b8f43230e36e41d97ed3140 |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
don't need to be exported from the .o files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78892 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 26d7ecd5f45419ebe39e07188218c00c0ab3a916 |
13-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change MCSectionELF to represent a section semantically instead of
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78890 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| b808588a3a5febe931896b3779d159ba90d836f7 |
13-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change MCSectionELF to represent a section semantically instead of
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78890 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 24e23171e85612b1435c265e6e23cc6f9e713f84 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78884 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 28865062c1ef60e47f0ac23a5ebc22eaf0d1b184 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78884 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| beacf650c3fa2f7dddc55abb94f654a24c22b56c |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use cast<> instead of dyn_cast<> in places where the type is known.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78881 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d06791f6d0b302eeee7189ea8182565594ffdc0e |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use cast<> instead of dyn_cast<> in places where the type is known.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78881 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2aa282f4941f44996dc3e56f658a7a932dfb6531 |
13-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Various AsmWriter output cleanups. Use WriteAsOperand instead of
PrintUnmangledNameSafely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cf20ac4fd12ea3510a8f32a24fff69eebe7b6f4a |
13-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Various AsmWriter output cleanups. Use WriteAsOperand instead of
PrintUnmangledNameSafely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e38b37db20ac7cf9f2db06876eddc5ae5febf273 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize Neon VDUP shuffles during legalization instead of selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78852 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| af385baa1d0438104a67b63a61b264c7cde43c50 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize Neon VDUP shuffles during legalization instead of selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78852 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 0847927af373a2abd24d2ab46c113fda33416e8e |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize Neon VREV shuffles during legalization instead of selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78850 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| d8e1757eacbcbae6657558f40fdada4279a9d1ed |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize Neon VREV shuffles during legalization instead of selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78850 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 3dbe9443c80ab668ad5cc8547fdb874634f25818 |
13-Aug-2009 |
Dan Gohman <gohman@apple.com> |
This void is implicit in C++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78848 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| a9ad04191cb56c42944b17980b8b2bb2afe11ab2 |
13-Aug-2009 |
Dan Gohman <gohman@apple.com> |
This void is implicit in C++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78848 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 5ef42ed623f1faff939c895a583afa2c27c66619 |
12-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 114a266c942ac2dc1e98047a00337ecbc81f7380 |
12-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 396d85707b679cbd8227918df11f90c7302068e3 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
PredCC is meant to be 2 bits wide, like PredCC1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78829 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 3aaccffbce9146aad97929d5812fb6271a7443ef |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
PredCC is meant to be 2 bits wide, like PredCC1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78829 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 4b6e4983844989b5a88421f2ac8aa54bed7de166 |
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMScheduleV7.td
|
| 1a8f36e3ce5b9c230781b66600c81536128abfb5 |
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMScheduleV7.td
|
| f2d915d7810e0ceb04a207bd6c15c6542ede83e8 |
12-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add catch block handling to SjLj exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78817 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bff392384ddb032c732c38ec78b91d7a25dcf467 |
12-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add catch block handling to SjLj exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78817 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 66b3400110159b259b0ae25bbd13fc660ce1f61b |
12-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix TableGen warnings. This partly reverts my previous change to this file,
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78815 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9f7d60f460151bf5ba9f90372618cd769216b314 |
12-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix TableGen warnings. This partly reverts my previous change to this file,
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78815 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 23c001b507d051c94f514242b0ce1ddc3cb941fc |
12-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
register naming cleanup (s/ip/r12/)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 378756c0f2d0d5393356ca3711530beceb201e05 |
12-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
register naming cleanup (s/ip/r12/)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| d88f9fd3f28cee69b0fcdca59532824d5617577e |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78802 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| a7ac47cee1a0b3f4c798ecaa22ecf9d1be9c07e6 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78802 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| bf4111cb1e3f47364d51932c99e34ee9c2cdab0e |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb.td
humb2SizeReduction.cpp
|
| 007ea274f4ab85bfc7698240eb5afd5a779ec330 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb.td
humb2SizeReduction.cpp
|
| b08935563a0e9cdb1c1ef89fad7254c24b72b582 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove another Darwin assembler workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78779 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| e0d7fe85505b14c014a9da78e891359a99c1e0a3 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove another Darwin assembler workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78779 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b9d5cff0f31c0588f3ca7b77f4c53794995921b0 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78778 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c972165b114477a57f0c6e0984b1be81d5ccdd82 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78778 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| f9e5b5ebb4d7f30a32bd1ba6527277519c186f20 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove an Darwin assembler workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ea253b99e907a4171d49547fc5d99c837af5d0b9 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove an Darwin assembler workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 427fd7a3460d708a2daa35a6960bbfab1f135eb3 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ADDS, ADC, RSB, and SUBS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78776 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 05c269c64593d8cc6aeb0780a5a8afbb86da5691 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ADDS, ADC, RSB, and SUBS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78776 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| ee27bece1030da55f205fde76986fe27d746d656 |
12-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add missing chain operands for VLD* and VST* instructions.
Set "mayLoad" and "mayStore" on the load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78761 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| dbd3c0e06dcd4b94c291388b365a93a3710335af |
12-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add missing chain operands for VLD* and VST* instructions.
Set "mayLoad" and "mayStore" on the load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78761 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 9deae0bef2ad6e84d289db7d3ccfdcdc2c69886f |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrinkify Thumb2 r = add sp, imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb.td
humb2SizeReduction.cpp
|
| b89030ab6554d84de4331c2853edac4dbf8da9b9 |
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrinkify Thumb2 r = add sp, imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb.td
humb2SizeReduction.cpp
|
| cae14fd2f334ef46b141a5e400fc43528f5e5b43 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change the asmprinter to print the comment character before the
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78737 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| e2b060161c92ddf60b5d020f981451e9e34a3f02 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change the asmprinter to print the comment character before the
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78737 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| eb75972692419eee5ea85909cea17b04abeeddc6 |
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 546952fd600ddba3f1eb6d4f93ff4eb42821a962 |
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| ca22f87bf12d401bf7b3f0411daaa5184131dfa2 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
factorize more darwin TAI stuff. Note that this gives
darwin/arm support for .no_dead_strip
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78734 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| e28a2e8b70e926324575ddec0a1565c6dba7d404 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
factorize more darwin TAI stuff. Note that this gives
darwin/arm support for .no_dead_strip
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78734 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 75dabac7cf3820b5463852b4404851a740fb3228 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
factorize darwin ProtectedDirective and SetDirective.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78732 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| e2811a74803d24fff45a186d2871377d248cec1c |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
factorize darwin ProtectedDirective and SetDirective.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78732 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 9364e7229cb5678ecd26c2a4181b2e7603322ba6 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
all darwin targets have .space and .zerofill, pull up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78730 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| b6ba9c36dbc54c85b86b29d9491c457b4de8b60c |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
all darwin targets have .space and .zerofill, pull up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78730 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 1bc7ea6ec052737d0dc444a568d6e9b9745f6669 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate template from arm TAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78729 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 5f28ffe6c25a8dea55aee425648e4942c04e4f3f |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate template from arm TAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78729 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 7fbb0a1d451373a93b58b31f40e4e7c275d5c9eb |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
template in PPC backend for TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78727 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| c89ecc5c2f6c089db328e2856aadf9fd4a1a0bd3 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
template in PPC backend for TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78727 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 94958144886d364172e378c033ce2453ca7e7b5c |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrinkify Thumb2 load / store multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 4b322e58b77d16f103d88a3af3a4ebd2675245a0 |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrinkify Thumb2 load / store multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2SizeReduction.cpp
|
| 36e3a6e235ee8b21eba777686b4508f71248b869 |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
humb1RegisterInfo.h
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
humb1RegisterInfo.h
|
| d9236ecabe1bd73e89ce5cdb12da8a1bfdc67a0d |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
pass the TargetTriple down from each target ctor to the
LLVMTargetMachine ctor. It is currently unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78711 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 0a31d2f6456069adba19b8aeca66c68b633c38b4 |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
pass the TargetTriple down from each target ctor to the
LLVMTargetMachine ctor. It is currently unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78711 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| df97304b68f46fc1afed8a54b71eaea20973a8f4 |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78709 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| dfab291702a9c6e88981047bf6a3fe42f7d508b0 |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78709 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cc6e66ab427fd02a31b06ad6302098be72899516 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 eh_sjlj_setjmp implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78701 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb2.td
|
| 5aa1684e5da9a85286bf7d29da419d261a70c2f2 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 eh_sjlj_setjmp implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78701 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrThumb2.td
|
| 89116de4c762ecba8215146476297f5c2357ba57 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
fix GetInstSizeInBytes for eh_sjlj_setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78683 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
fix GetInstSizeInBytes for eh_sjlj_setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78683 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 909610aa7b45b775b151fd8338d71e20f0fbf1f3 |
11-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
This void is implicit in C++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78678 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 327365e58fd8aa2159be77f86b8017da814c59e1 |
11-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
This void is implicit in C++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78678 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 770d718405114860f3874871848e345873bf7cb4 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMSubtarget.h
RMTargetMachine.cpp
RMTargetObjectFile.h
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 764ab52dd80310a205c9888bf166d09dab858f90 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMSubtarget.h
RMTargetMachine.cpp
RMTargetObjectFile.h
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 3fe420be2d2032ac5dbeae61c170b64d9acd4e1f |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78665 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| f128787f941bb372e80d69b786ed144d8606a292 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78665 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| a855ffa77adc5e3ebfc9e296956e56c601be38da |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78659 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
humb2SizeReduction.cpp
|
| 195c71b472d3f83c1051d2b87f4e93cc928b6ec9 |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78659 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
humb2SizeReduction.cpp
|
| e8f37121a379584bd03b8f724f5a63eafcbdb3ee |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78658 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
smPrinter/ARMAsmPrinter.cpp
humb2SizeReduction.cpp
|
| 3a21425dbe09c7ac85e6b156f82184dd6132435a |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78658 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
smPrinter/ARMAsmPrinter.cpp
humb2SizeReduction.cpp
|
| 64cfb7f95ab073d275cd96a2fb5d6a5b57abe14c |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78657 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1cf5783dd73e72adc60aa2d037728cdcd13938ca |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78657 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 275468af219080d7c1d1b52baf64c2d85950f962 |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78655 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 4a8ea215e69e9ca19c8acf1c236b73860188a023 |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78655 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9d9601b8d4ac9cbf37dca95d2b95ffcead4ea508 |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Adding a blank line back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78654 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 7fb8c3ffc0b41d60ac935b8f3550f262a28f155d |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Adding a blank line back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78654 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 8f10b3f2521e99168e7fb89310270d821a0b00fb |
11-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
|
| b0abb4dc4203b903d8d0b48a952ba0a6312eeeb7 |
11-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
|
| 1c2660e35128fd67548385951ea81ace076a835b |
11-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78632 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f24bd401eb453f3e15e69a093b3943f7946d5bed |
11-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78632 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2dc814624f67cd6ea1f6e005a287365c92f95fe5 |
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78629 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f35290ce8d562eb80bc6e5f2b07c423f7e10a132 |
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78629 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 0325b5c4797722ce65d145a4e80c7ed4c36baa66 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add stdlib.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78627 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 3034e8fb1f1d65d335cd88ee3bbc5feb6e86d732 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add stdlib.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78627 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 29feb6a583204de0948def1d59d186e4b837ef52 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
SjLj based exception handling unwinding support. This patch is nasty, brutish
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMInstrInfo.td
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 1b747ad8a0694b86e8d98a8b9a05ddfe74ec0cd3 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
SjLj based exception handling unwinding support. This patch is nasty, brutish
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMInstrInfo.td
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 02f6f9f1055d0a0abf5d14eaeeddcaf3f65be0ab |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 3a1f0f6785e27eb8ede455a3583ca8c885d3911e |
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 3f20cb6d9679205620a4fd51d3ec9aa73bf3a508 |
11-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bug where DAGCombine was producing an illegal ConstantFP
node after legalize, and remove the workaround code from the
ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a407ca16c29b4e91ef3cf9e188ac2e3ab6920cd8 |
11-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bug where DAGCombine was producing an illegal ConstantFP
node after legalize, and remove the workaround code from the
ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| ac9de036dc0e4065ee2c03419f11515a34ce505e |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
humb1RegisterInfo.cpp
humb1RegisterInfo.h
|
| 4b358dbdfc1bea92346785e4227f2eeeb8beee46 |
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Use NEON for single-precision int<->FP conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78604 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 338268c67fbb7252702bf400495771068750466b |
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Use NEON for single-precision int<->FP conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78604 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| a0c69eb90d53b9f5e7f4a1e070ebbaf3d0d4bda8 |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
SimpleValueType-ify a few more methods on TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d6662add687f20cffa0755e410efbb40de4dcf23 |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
SimpleValueType-ify a few more methods on TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 898c62b4036f13a156a58c437f43f4fcb17923a0 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle the constantfp created during post-legalization dag combiner phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78594 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e2b861f7d91c09115cd637614b1bc5f5154bce1d |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle the constantfp created during post-legalization dag combiner phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78594 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a4509893aacf06a14f470c0981aa90b7248423a8 |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 70671845adce8ab36ae596bb06d0375459a7a2af |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7f1ac7fb49bc11464120fc29541c3efef52eed96 |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
split MachO section handling stuff out to its out .h/.cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78576 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| f9bdeddb96043559c61f176f8077e3b91a0c544f |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
split MachO section handling stuff out to its out .h/.cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78576 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 05fbaf65399b1894965304256dbe2abd0decbe19 |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
arm only needs to emit one .align directive for hidden nlp's, not one
per pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78574 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| f3231de60bb64c3f6fc6770b3e6174f4f839a4f3 |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
arm only needs to emit one .align directive for hidden nlp's, not one
per pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78574 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 13089a4eb9c13664c597485e561d6d5476f0cfba |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make sure that arm nonlazypointers are aligned properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78573 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c076a9793936b140364671a5e39ee53bd266c6c3 |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make sure that arm nonlazypointers are aligned properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78573 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 48e1359f978cc5959179860de764ea40e91c42ea |
10-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint scheduling itinerary changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| bcf81629b85218ba86d9a4b4fdd06d4c182ba9a0 |
10-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint scheduling itinerary changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
RMSchedule.td
RMScheduleV6.td
RMScheduleV7.td
|
| 56634756463eda355e2841cac0d39f110e94a47b |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Watch out for empty BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 65f2e7887a8b70b3ee63ef535a6bcfe8a170c074 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Watch out for empty BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 2db61f9d268c48db9df76d76a550b0e45fdfcabd |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
rev, rev16, and revsh do not set CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 8442d00a0ea750200b34a7fa94b5b72033da65b3 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
rev, rev16, and revsh do not set CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 0fdb1d4baf7a431a1250711710e6ced341b93835 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 0d3007bb32c9085e6d45264133248a98379e2d8a |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 3bc97d6ee3eea839929f8a7389c5ae95d6302223 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| 26cc252a43c20eccbd49ae92dea8b5a1bb02cdc2 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| fab4d981673c13470c7f13076d25d4b7180550fd |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support for folding loads / stores into 16-bit moves used by Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 19068ba71a480d9b5032fd9f87eb412e8beb09f4 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support for folding loads / stores into 16-bit moves used by Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ebc39166f670961c5008b06762745a0d03cf1b39 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 229464564243b24fb12cece515d727673e726994 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 5fa65db760b50a43a68ab7577c56cc8fa362427c |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use tMOVgpr2gpr instead of t2MOVr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 052053bbe3169a3574cb5af026cf0a5d616ae04d |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use tMOVgpr2gpr instead of t2MOVr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 6dadbee58837a1ce323b16aa818c6fd753f432f7 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| e8af1f9afe5e70e1d4ec4d00a6870428dba88692 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
humb2SizeReduction.cpp
|
| d2f87a67623caff88d29d01be4acf74b0b3e479d |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 09d97354edb65473e61337f543b66855896de134 |
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 72a676aa4aa35b3eef2ac29b5bb79b4f941c1948 |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ff4bc460c52c1f285d8a56da173641bf92d49e3f |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 71efb4f6e333b5ed9718e017abac16d4c312f23f |
09-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| a56c57e5f0876e7c47adbdaa59248fee3131d3be |
09-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8
humb2SizeReduction.cpp
|
| e2be3383447e747354ae2dfe965f8617136f88d6 |
09-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use subclassing to print lane-like immediates (w/o hash) eliminating
'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 8e9ece75db5045ec057efbbdba6550fa0d85e695 |
09-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use subclassing to print lane-like immediates (w/o hash) eliminating
'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| d0d09fcf74cd20325acc3dcc38007c4ebc2816ff |
09-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 892e18239308f8a02a4c83758616be84a459c19d |
09-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 849290adaa476e99074db8e0519faca0a2284564 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
now that getOrCreateSection is all object-file specific,
give the impls an object-file-specific name. In the future
they can take different arguments etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 0c0cb7123346beab4e0d3ad6ce9570560b14971e |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
now that getOrCreateSection is all object-file specific,
give the impls an object-file-specific name. In the future
they can take different arguments etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 85fb26f6020af85ba9c3a3b68b15c218f2cde280 |
08-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Update CMake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| cf1e764a1c1a15f3710ca41ecad5662527fca21f |
08-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Update CMake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 49284e74a5be31b2a2c99c956ba296f978b2e3ab |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add insert_elt / extract_elt patterns for v4f32 stuff.
Did anyone tests v4f32 ever?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 06af2ba80991e57063abe55b84b32e650973f1ac |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add insert_elt / extract_elt patterns for v4f32 stuff.
Did anyone tests v4f32 ever?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| f141141c3776a621442485520316c3bd45ab370f |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Lane number should be printed w/o hash
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 3405201bcedd8c509f484cc342fc2d6304dd5da3 |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Lane number should be printed w/o hash
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 3f08766da2675d1c8b57303b5e263d878abfb0cd |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use VLDM / VSTM to spill/reload 128-bit Neon registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
|
| baf31088f1472f48ea5ae81f0b93636cc44ca444 |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use VLDM / VSTM to spill/reload 128-bit Neon registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
|
| c1eaa4d40719e34857f514cf567ea3a373d30608 |
08-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| b6ab51e8297281888b85eee8c38215eab2649c4b |
08-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 3b169335b47956cfde20ff854bcb5bf052e928a8 |
08-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| 64efd90f8c878214abc29afa3d1c1e7bfe854a49 |
08-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
|
| a108309120c616b456aad9d22255f1e6e7a1d442 |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a skeleton Thumb2 instruction size reduction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
humb2SizeReduction.cpp
|
| 3eff16e27a4b0e9dfb8c0061faf10fdce9f4df4e |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a skeleton Thumb2 instruction size reduction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
humb2SizeReduction.cpp
|
| 05a1bfd2c76c5dc568560a6ef265eacf1873bccc |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMLoadStoreOptimizer.cpp
|
| 8fb903604e83dfd63659c919042bf2bfed3c940f |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMLoadStoreOptimizer.cpp
|
| a42214a57ebee527a50abb0b06d32a9b13738749 |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
tADDhirr should target GPR, not tGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 57834cdee56cf3df2ea0a7010d3977adc007d5e5 |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
tADDhirr should target GPR, not tGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 44690b2c1e034f9927df3fb797ba19085368ef4f |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
I can type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78453 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 34f8a029e341a74fd02ccb198f4d4f0c8b38c015 |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
I can type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78453 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| ddb259a23c415dff73cf9d85ae835f533690fdfd |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make printInstruction return void since its result is omitted. Make the
error condition get trapped with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 41aefdcdd1c1631041834d53ffada106a5cfaf02 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make printInstruction return void since its result is omitted. Make the
error condition get trapped with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 38d4169aa39ad934c13b3f0ae0f18132d570521d |
08-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Make NEON single-precision FP support the default for cortex-a8 (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 767a952a6fe812466b21ea3ab5748a15aec6ebfd |
08-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Make NEON single-precision FP support the default for cortex-a8 (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 8e4585fb9ab25b18366ca6b50c67fb28b9bae40a |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak the stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| a55fd4a23f1d766790acc07d25c6c0013d4bca30 |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak the stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 9c913fbc77965d161856c9e797ca3f10c09dcb55 |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
2 more vdup.32 cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 32a1b257813e133ba1146289a9aa43ed8ad9c00d |
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
2 more vdup.32 cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 6fc3248620145044629a08b9202c6afc8a9f2dde |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78418 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
|
| fcc716352b893b45da2d6aa9d7afff8ba1ad0527 |
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78418 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
|
| 9b53104dfd8c2bb2d9eca8b000a998f100196d5a |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| d77c7aba83bb290b9b62ede38b6ddbc9b790c6ef |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| bdd3fde4845351a49cabf7d42a391a0fa155f479 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
This is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78399 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
|
| f12288e8aa27a7cb1e48e1fceccd5cf49876104e |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
This is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78399 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
|
| e61fb9c959d6703dbcc5ac919470f0c37ee01109 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78398 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
humb2InstrInfo.cpp
|
| e118cb614643c568716ee612366cae4c365a8aa3 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78398 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
humb2InstrInfo.cpp
|
| 46961d83a791897a1eac69dce49b49408728227d |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix support to use NEON for single precision fp math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 1d2426c4701650846922d312eb742cc55385c721 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix support to use NEON for single precision fp math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
|
| 3c05d13bee9053f2350cfd5d650f106add305c27 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Error out, rather than infinite looping, if constant island pass can't converge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78377 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b6879b2b84df2f642cd39f5bf58584c4a39f8080 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Error out, rather than infinite looping, if constant island pass can't converge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78377 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| d6053af8ed2d4e9cf4fecd0594e2c2b250287f12 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
tBfar is bl, which clobbers LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| 53c67c0218d8420234dd71bf2d9df3388909af77 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
tBfar is bl, which clobbers LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| 6d29b324f77099bf84fefbf8cb529de5141e1080 |
07-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of namespace pollution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78363 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 7db949df789383acce98ef072f08794fdd5bd04e |
07-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of namespace pollution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78363 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 815c23a1ce10135b3158451b56c3ff469febbef3 |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
EADME-Thumb2.txt
humb2InstrInfo.cpp
|
| 861986401e05e437cb33bfd8320d510b956fe41e |
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
EADME-Thumb2.txt
humb2InstrInfo.cpp
|
| 6a209cd114d8d1db00ddad1af7f73ae13b3efa98 |
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VST[234] operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
EONPreAllocPass.cpp
|
| b36ec86c01e3c3238dca621648f017aef96dda60 |
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VST[234] operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
EONPreAllocPass.cpp
|
| cfd6765463c874dd55c8efff6fe87a7c5aa43b92 |
06-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 8b7d7ade85fd0103316295440d4950f39ab08419 |
06-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrThumb.td
RMInstrThumb2.td
RMInstrVFP.td
|
| 163757aba770b06c111275ec23c1f416ac132c96 |
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Neon does not actually have VLD{234}.64 instructions.
These operations will have to be synthesized from other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 0cedab9a0d5127049ac1da54e2891d91796e5c61 |
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Neon does not actually have VLD{234}.64 instructions.
These operations will have to be synthesized from other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrNEON.td
EONPreAllocPass.cpp
|
| 2267933252114a408c8b9448a85744b41a069ae9 |
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
MakeLists.txt
EONPreAllocPass.cpp
|
| 70cd88fb7b5b77f8bbca7417e624d11b6e22a7e7 |
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
MakeLists.txt
EONPreAllocPass.cpp
|
| 2105b90ab62c2b09b380f7b89a4383fe07f8a19e |
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 7bfdca0206f51132b26094c6f83a5ac97ee0f943 |
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMInstrNEON.td
RMRegisterInfo.td
|
| 7bd8d73d4825087d6e3b8e6c5295b74b6c3e6218 |
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
hardfloat case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 058c251d4ac23bb3f9ca66eb0e465fa2c6c66f42 |
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
hardfloat case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9d6269e95bb3723d78398c9e60a08ddf14af51ea |
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 14d9495403e4c0129119a79322ee4e744b2eced8 |
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 02e15b8bf527067fb347214f77c2c8166ae0078a |
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Missed pieces for ARM HardFP ABI.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
smPrinter/ARMAsmPrinter.cpp
|
| 567d14f07cd62bfb9dd0edd90144a0a840450f7a |
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Missed pieces for ARM HardFP ABI.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
smPrinter/ARMAsmPrinter.cpp
|
| fa0c2a8234fd76deaef312499eb1e4c4ad83d112 |
05-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| e22f4da01d57f51757663fdcae986af0aeca49fe |
05-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 4a8ee1bccdaa28cf8d0f2236911b531b80bdd403 |
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove a redundant declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78216 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 7f0f2515a01596a2785aca9ee5f630ecc0ab134a |
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove a redundant declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78216 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 21ff88337d1d7b5da364c4a97471000edb4cb686 |
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Disable NEON single-precision FP support for Cortex-A8, for now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| ce3c1f2a0e726832286fde44cd3b0c4be605c19c |
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Disable NEON single-precision FP support for Cortex-A8, for now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| c6d513775142204b35aa0b30a59940a2ebf73ae9 |
05-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Remove dead code. MDNode and MDString are not Constant anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78207 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| bccdcb1857f400206ed07984dc04e229c6013cc6 |
05-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Remove dead code. MDNode and MDString are not Constant anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78207 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8916f80c379a4e57d6950ac2ef89de5159e9cd0b |
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
By default, for cortex-a8 use NEON for single-precision FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 1f0e404c87675ce75e34bcd91395c660fe1d4ac1 |
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
By default, for cortex-a8 use NEON for single-precision FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 3f19e31f3ba41771d31f8e54eb2f054af668c1f3 |
05-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 61f4b721b2f268ffbd0be614a4f328d541fa1d81 |
05-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 5bf205713e799a2072967a00b6d8550229c8204f |
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Oops. I didn't mean to commit this piece yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78146 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| aa289d5e7f526b3586a2b1e0b5bb6c1e5af9ef5d |
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Oops. I didn't mean to commit this piece yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78146 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 9178de1d2b1e0787539b83ed54ad505ff13169e8 |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| c2cd97a71c66240b49a6af5ad38b2d950a0181d5 |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Don't flush the raw_ostream between each MachineFunction. These flush
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78137 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1c55fab53455f11fbd7bde69d0c5911031218e35 |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Don't flush the raw_ostream between each MachineFunction. These flush
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78137 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 055a90dd7e4c218f53b5ee646afd6be06a18d6f3 |
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
RMTargetMachine.cpp
|
| 4a3d35abefa3a1f6558ef88b25f2a320c76d5328 |
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrNEON.td
RMTargetMachine.cpp
|
| d16eb2fb217128c28c5ce2fefbd08d3e9236aa5c |
05-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 35d6c41fde95422fb8483be0ac0af2b1425a4b13 |
05-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 560d2d0754776d68b93fc927ab4a193c81bf9319 |
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Replace dregsingle operand modifier with explicit escaped curly brackets.
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| c00479253b92dd79b0345e4229af62835533347c |
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Replace dregsingle operand modifier with explicit escaped curly brackets.
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 06c0e626b6021938b64b376d677631936ac21b56 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 9e7a312391cb955bfc148d15a69adcaf7cc3ae50 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| bc7c05eba593dc873637ba6b42afe4fb153c8ff0 |
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add NEON single-precision FP support for fabs and fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 53e4471adcf34cac253d2486e6b29c331e2d973e |
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add NEON single-precision FP support for fabs and fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
RMInstrVFP.td
|
| 363d9f7dfd775af342c58be35a5abf9b69735f0f |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
In thumb mode, r7 is used as frame register. This fixes pr4681.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 3425df44b511de2e45524a885b370fd8f5d139d3 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
In thumb mode, r7 is used as frame register. This fixes pr4681.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| f31748c9a78aa89062d31ef7eb6875d8c8d45cb5 |
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Match common pattern for FNMAC. Add NEON SP support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| b84f3d427c2f301f2836a743547e6a20bd8ee8a4 |
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Match common pattern for FNMAC. Add NEON SP support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
RMInstrVFP.td
|
| dd19ce43bb9742c41d90123b2ae0fc5661d6e27e |
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 42a83f2d15cbbc08f5be19856198e3c885221e9c |
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrInfo.td
RMInstrNEON.td
RMInstrVFP.td
RMSubtarget.cpp
RMSubtarget.h
|
| 6ddebfe77a1ba265baed2d425a864347d8adbfac |
04-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Ooops, I was too fast to commit the wrong fix :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78060 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 939ba32747d472032e8c3a5f3ea4feadcd6f622e |
04-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Ooops, I was too fast to commit the wrong fix :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78060 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| b9d8a9988f3aaaad5010f5f16125d497ff7e279e |
04-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix a typo - this unbreaks llvm-gcc build on arm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78059 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| 20e037a8c506c9918ffe25e092a6a593187d93d5 |
04-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix a typo - this unbreaks llvm-gcc build on arm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78059 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetObjectFile.h
|
| bd28ace99fe2bbdcaa9defca497319c85ff839a5 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78057 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| eb084d16712ededa4486e1dd05ba98aa3d40646c |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78057 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 8fb4cc6678e482b01e6026d274fc575aff3e7134 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78032 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| f0409ea488ec2cf27daeb192d18e206b11c6360f |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78032 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 4bb74e76a5e6858aa90a2cabbf48a627e6554a48 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple pass fixes for Thumb2. Not enabled yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78031 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 27934da97bcb7a6a4949dfc0c449d99f43077e98 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple pass fixes for Thumb2. Not enabled yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78031 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 809fadb4f63a99752a8dd02b5f6c817984571db4 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| fa2ea1a8cf2e3fe4dae19032868010e917629d16 |
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d2a2e002bfb53b66ab5f5421e9bcf5ff319e09a6 |
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
results to fixed registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| a599bff101095e528198ae85739fe8b97ffba82b |
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
results to fixed registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| d99b111729ce68370a436b04abfa457c921fbecc |
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Minor cleanup. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78024 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 916afdbc2d4af2596894c4ccc179b4445fe659a7 |
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Minor cleanup. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78024 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c3f5a2bca13dd75d12f05d91c940b6d1cb24553c |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
use TLOF to compute the section for a function instead of
replicating the logic manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78011 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5e44e472d61fd113095e7b0825a0146703e500d3 |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
use TLOF to compute the section for a function instead of
replicating the logic manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78011 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 21f0cc2c7ad63f4f0d1b88d9a971c3d70b27ba45 |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert macho stub emission to use SwitchToSection instead of
textual sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78007 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| f61159b574155b056dbd5d6d44f47f753d424056 |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert macho stub emission to use SwitchToSection instead of
textual sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78007 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 96ba605eda9151eb197e6c907fedf08e1e9aa882 |
03-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
Add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| a6d658620f1b8803825d3d3adc5d5ed9b36dc422 |
03-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
Add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 98c00ab7ee4842f1faa79d2fcf46476d02c4eb99 |
03-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d5fe92efbc1774ada25a1cfa18009bfc5c6e625c |
03-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 356fba7852c5e44ca0d77c9a68c5cfd819263d9b |
03-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
These are done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77949 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
|
| 9072c8198de8730a1332ca5e03a2a597631b7615 |
03-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
These are done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77949 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb2.txt
|
| b2c36328d32febf103f04c1cbd77e42749e241fa |
03-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| a8e8984ee4c197634839cf228f5b1d79a77fa4b9 |
03-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| f5c2b85a55d67bb0b4711932ecb3a4bfb7a1974f |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Move most targets TargetMachine constructor to only taking a target triple.
- The C, C++, MSIL, and Mips backends still need the module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| e28039cfd1a9c43b5fa9274bf19372d96f58f460 |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Move most targets TargetMachine constructor to only taking a target triple.
- The C, C++, MSIL, and Mips backends still need the module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| b711cf09b31c5498b18293768ae4323ecee304ef |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 3be03406c9c3b2075d5ae416499af2f15f703d6f |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 72d228decc0b7d1cd28738b728cb289e5403f14c |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move dwarf debug info section selection stuff from TAI to
TLOF, unifying all the dwarf targets at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77889 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 18a4c16726db2b8874c7b84d04650dda80746074 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move dwarf debug info section selection stuff from TAI to
TLOF, unifying all the dwarf targets at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77889 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 20f98d18cbda767491b6d97413dcc10dedb21b76 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77878 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 24def37c85cad01845e5fb2efc87e4d5471a2a6a |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77878 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 5f1fdb3d639bc0300b5a40f1a1c62178fb534668 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| d90183d25dcbc0eabde56319fed4e8d6ace2e6eb |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| c7ac3c140866e50ea684fd1315445fa1d58de353 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
turn some templated inline functions into static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77873 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 7bbd178d4bf1181d337e5fe657926d677c2e33aa |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
turn some templated inline functions into static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77873 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| e3cfb273a3fe3b0f7cf832e7cff8dd2b45fc1062 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo
defaults to being ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77866 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.h
|
| 9ba8c6872dc722d0f9f804fcd67bace4acfe67ba |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo
defaults to being ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77866 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.h
|
| 7dd4ffc0a889f3c4ee0c3454ea37502466955293 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove TargetAsmInfo::TM, which is now dead. The basic TAI class now
no longer depends on TM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77863 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 8d4a0a328a89d1f3c7ad83048e04ace53b6ba781 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove TargetAsmInfo::TM, which is now dead. The basic TAI class now
no longer depends on TM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77863 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| b5c952a6aa643bfa7a002013f46e199e7a86bb3f |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert ctors/dtors section to be in TLOF instead of
TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77842 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetAsmInfo.cpp
RMTargetObjectFile.h
|
| 80ec2792b2b271eca55743a3cc4c8bca214fa705 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert ctors/dtors section to be in TLOF instead of
TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77842 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetAsmInfo.cpp
RMTargetObjectFile.h
|
| 25f3b84f767dfecf6a006ea41e78e3145218df2b |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
REmove dead fields of TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77820 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| b80610cd13e7accf6db0924c75d0914bf566922b |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
REmove dead fields of TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77820 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 04f40fa7a8b534f215e4dfc71261f166cc6149c9 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Workaround a couple of Darwin assembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMInstrThumb2.td
|
| 25f7cfc3cccba6f569f29f79ea533bae960b93c0 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Workaround a couple of Darwin assembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMInstrThumb2.td
|
| 7c002f3a33492769762ebbc2bd75a06b32d9db74 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 13f8b36205607ff87ad0c4daf28f63b2660e7c0f |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 68e4b5869c777bbb8256dde0a971172751105518 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
RMSubtarget.cpp
|
| b620724e614c6594e7b269b6ea7d8483947ea944 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
RMSubtarget.cpp
|
| d3c3a237b71e55ee6f8bf0126ed48bf7a4ba4079 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2BR_JT is mov pc, it's 2 byte long, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77744 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| a0ee862f2e3a0d202244e02459ddcf0dca0e8607 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2BR_JT is mov pc, it's 2 byte long, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77744 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| dec08246cef517841dbfbf7802c240225ffba622 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 movcc need .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77743 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1119776b19872cad8366835f12ee682788879951 |
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 movcc need .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77743 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e6ad12f8febebcdca8ea6b0e48014786267df1ea |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
switch off of 'Section' onto MCSection. We're not properly using
MCSection subclasses yet, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a87dea4f8c546ca748f1777a8d1cabcc06515d91 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
switch off of 'Section' onto MCSection. We're not properly using
MCSection subclasses yet, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2ee6e2d788b7fc1a6869740da53c52174be25179 |
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ff6ab176192b4f7d345abea8391dfd3094d994e5 |
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b6a03389e694fb958d6e29fa3fcbf8d698d77a7e |
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
|
| d26b14c34cbcee1448b86b524578fc51cc979023 |
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
|
| 013162700841c12357dc27f2a4a268c967c3eb50 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f26e03bc7e30162197641406e37e662a15d80f7e |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 49f2d5bb20cd0e7f0ced36850ee68138cab399a5 |
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| ee42fd309ee6a8febfafb97c2f3b6f2069758c5e |
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 11c550b84be68c7c04d5564b6ae7c358ff78b252 |
31-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77632 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 07337c0fcf04fff3f62d3727097347f8be299c9e |
31-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77632 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 481216a0382a90b8b7e07213bf15f569f9e72fd1 |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Darwin assembler now recognizes "orn", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8f652532365afed2274ec3b8513bb8faef16d2c2 |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Darwin assembler now recognizes "orn", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1f69767d5bffd998b94d2b52b6c1a421dab4e732 |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Darwin assembler now supports "rrx", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7c92f3ac99c39d745e909390edb71c72bafecc24 |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Darwin assembler now supports "rrx", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c289648b9f47ff8e8e38b80e1da9cf87b94e492a |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Cleanup and include code selection for some frame index cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d8c95b5ac2ae0619c22434dbdd993196ea82489b |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Cleanup and include code selection for some frame index cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f84412287e8401cb3070eed750dd965256aa3bd4 |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add missing D* register clobbers for Thumb-2 call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77611 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3e4b22d9836f66ba72dd105567a77be05030f747 |
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add missing D* register clobbers for Thumb-2 call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77611 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ecd9b641b95362a050045ffcd2ee2b650a413f80 |
30-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a random codegen deficiency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77598 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 513503961dda4a4ce7d196771961d92902ca790d |
30-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a random codegen deficiency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77598 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bfea4859278283431cfbac082a279e4f2742d0bd |
30-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Switch obvious clients to Twine instead of utostr (when they were already using
a Twine, e.g., for names).
- I am a little ambivalent about this; we don't want the string conversion of
utostr, but using overload '+' mixed with string and integer arguments is
sketchy. On the other hand, this particular usage is something of an idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77579 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 7f93dc8345fb33652973e35cae4c3b58addf4f87 |
30-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Switch obvious clients to Twine instead of utostr (when they were already using
a Twine, e.g., for names).
- I am a little ambivalent about this; we don't want the string conversion of
utostr, but using overload '+' mixed with string and integer arguments is
sketchy. On the other hand, this particular usage is something of an idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77579 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d9a908af4aa1f77d4b93de192d3041894f3fd587 |
30-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77557 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cf661e2c562e7b3ac35ff2aed916615356e0f2c1 |
30-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77557 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e12c92dd389065e194d94e032440caff188b261f |
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
tbb / tbh instructions only branch forward, not backwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 8770f747a98194056805f1b7cbcb0b75a7633b87 |
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
tbb / tbh instructions only branch forward, not backwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 45f6baf7d90d6cde0332db07fc2ba0cf8b7d2f98 |
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add VFP3 D registers to the DPR register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| d600522608fb3374456af83dfcf51586bcabfb57 |
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add VFP3 D registers to the DPR register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 9e7344841ca5369461277f1c7e75bd987e0bc613 |
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure Thumb2 uses the right call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 20a2a0aff3221e2c777558d714753bae0f296c8d |
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure Thumb2 uses the right call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 1937700fa5dce81f6c36c9314786a04f1bc99279 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 2cfd52c507bd5790457a171eb9bcb39019cc6860 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
|
| 80ab2a83805a1005679ba97d308219b460bd6a4d |
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Fix an obvious copy and paste error.
- Darwin Thumb2 call clobbers r9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 0531d04d002c6d9489b4d1a85f49734e5c27e6f7 |
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Fix an obvious copy and paste error.
- Darwin Thumb2 call clobbers r9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| d3902f758c2c8164db3bc67640f6ded24250aa6c |
29-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change Neon VLDn intrinsics to return multiple values instead of really
wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| b7d0c90c449882c8ec697c8989244dba2dc917ae |
29-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change Neon VLDn intrinsics to return multiple values instead of really
wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2931fe435726903f4b8c63ab542e27620dc1a2f3 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
pass the mangler down into the various SectionForGlobal methods.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77432 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e53a600f065075731d0aeb9dc8f4f3d75f5a05f8 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
pass the mangler down into the various SectionForGlobal methods.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77432 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1b2b3e209303c078ada99f0a74bad71defe1cf7e |
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
humb2InstrInfo.cpp
|
| 5657c01949dca6c012ac60d242d1a8d2ffdf5603 |
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
humb2InstrInfo.cpp
|
| f5a9816e20d5f885cd8c9fb4ca7d8846124e0edc |
29-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77401 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| d9453784fbcbbf052a32752d00e3b7d0004fda55 |
29-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77401 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 7c368855a7d367bf6009c59cd14c8aece9d80bec |
28-Jul-2009 |
Devang Patel <dpatel@apple.com> |
Rename MDNode.h header. It defines MDnode and other metadata classes.
New name is Metadata.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77370 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0a9f7b9c3ebe7d0ec033462e1a7c9101279956f9 |
28-Jul-2009 |
Devang Patel <dpatel@apple.com> |
Rename MDNode.h header. It defines MDnode and other metadata classes.
New name is Metadata.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77370 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5c03715743f38b03b73c74b9e7c7b2faa2d28977 |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| e7c329bf4b48ba3a4539183dc2d0804db6f4042a |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 5282105af8b0aade81f78588d49990e366f845ce |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove support for ORN to workaround <rdar://problem/7096522>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6340632d3b32bdf73c390195698ae337cb753e51 |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove support for ORN to workaround <rdar://problem/7096522>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8fa356f2123103af328eada06440e4c277268b07 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
more simplifications and cleanup. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77350 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| b180d992d81f97862af6089dfe899d0363cac6f5 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
more simplifications and cleanup. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77350 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 91f064f3e1f3f40f07e666a3587ab49abafda4d7 |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add workaround for <rdar://problem/7098328>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5743854f47c00118f7e667c68c10db5ce76225b3 |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add workaround for <rdar://problem/7098328>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 28faffe5c44cc59195968365f388cc9c52c537b8 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4bb253c60f895131371aa2ad1bfa5a2bea213f78 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7cdd24ce79a4ab41234dc546fccdc7f9525ba59e |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3583df7676bd194faf21eb24ff7790928502852a |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 5b4eafcf72bb3b094921a92757b8b374ea13c08c |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| bae20a6353583089224b94280a2dd69805dca247 |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
humb1RegisterInfo.cpp
|
| 5b249dfab8f983563ef0bedbdddd59b8c38a9453 |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77301 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 542383d93b146e11a1d70c01f8afea8ea9f08eff |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77301 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 5a3605f37d2c4b3b7d01dfdde0ddce456696fc4c |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb2.td
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 6495f63945e8dbde81f03a1dc2ab421993b9a495 |
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb2.td
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| c4c40a9f14d66de770ba7c0922be07dca7e3b827 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 87affb9593562fea5185159da28cff7e78ede43c |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 1f0962756dc46a2909250d242dfa2953eb15e036 |
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 27c016ba84f5607b3610f0ae63d36742ba0083f8 |
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| c9d138f505b515e96eb761a7b2138cd27f3f9536 |
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| b79a26b1b5ea8106e664d5951ddeb711fe5f0cc9 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77233 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| fa199f3c168947f91e1935d23b5fd6ee3027ddd3 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77233 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 4ffaf27e34ab7567ac06409fc3a259a7934d4bb4 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
More DCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| e0f21bd47f3fed91124e3d8187e1bf8a66c6aef3 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
More DCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 4abacf956e3caae49e6d1e6600820f09f6e29116 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77230 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 78703ddafe3d037f75d8ca188e4829d238289ac3 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77230 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ccf6536207ad87bfe62569bb560573cfb529b99c |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of more dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| fc17fb0aeed584b8560461ab2843d0676a243f29 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of more dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 9399ff2369c6919e277afab10dc67d37386a7095 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77222 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 293f8d9b8800ab68c64b67f38a7f76e00126715d |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77222 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 2c03f6d1089da3175a70901a832840fc56687fe9 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77221 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 83e0e36be8390fee1235783731f6c64aa604b7ee |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77221 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 03c5e0db6b035c01e6e425b53939bb49e56397f8 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of some more getOpcode calls.
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 5ca53a7ad821613d324e4189ddbb0d468a326146 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of some more getOpcode calls.
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 3bc1afec44eefb1aa52d84423e98515497dd0cea |
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 does not have RSC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 752aa7d2fe9af9d1bbd027f563e861f854bd40fa |
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 does not have RSC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77201 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2f6f113c9eede5bccde2d88eb84af0681b37038e |
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add ".w" suffix for wide thumb-2 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| af0d08d55c58cc34a373ca5f0b45e852c31e59d0 |
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add ".w" suffix for wide thumb-2 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 64630569a623462f384d546addd4d9547600900e |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77186 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| e346694a81cbead3289d11057111fba46aa30aae |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77186 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| d8310520a75c10de2678e931f984e0c500e0ee43 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate SectionFlags, just embed a SectionKind into Section
instead and drive things based off of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77184 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 5fe575ff4fdefc1b003a009b1b9282526a26c237 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate SectionFlags, just embed a SectionKind into Section
instead and drive things based off of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77184 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 7b8b13ae655c54cfa770e74d11c02b04e2728dc6 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77182 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 1f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77182 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| ac5c1f00b23e82802e657570fd4f9f4f75832710 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 5732ca084aaa0cd26149e50dd4b487efff37fe41 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| d8b20e21a86f904ab2a67f4b0e837f312df226e8 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb2InstrInfo.cpp
|
| 08b93c6a70ae59af375f205cfcffeaa3517577ab |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb2InstrInfo.cpp
|
| 15b7a580a79d2e9db8dff2c489181fa3a8d791a1 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 0841e77fe8580b74d80f6432a4f5bfc78a80fd60 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Just use a single isMoveInstr to catch all the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 68e3c6ae49ff67cba98403e43b5bd0c2499caa41 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Just use a single isMoveInstr to catch all the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| df827f201fc83119ba8d0d89d6ecb7d8fb2b012c |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb.td
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
|
| d83360694a6d82772cf31a0be8a64570c2e5cb88 |
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb.td
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
|
| c51585bc4b9c3463853ed251846fc9609901129e |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77165 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 0fcf4dc6d367216ff51501af282e33e93da8586f |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77165 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 2d26465b799957820943cede4cb19cc2056cba9b |
26-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor. Get rid of a few more getOpcode() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 30b2bdfa734d59bb7bc769dc2f06e4900a77f6f8 |
26-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor. Get rid of a few more getOpcode() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 23e2b80c58046994ba60bc9d6c7b0b2bfb894549 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Eliminate some uses of DOUT, cerr, and getNameStart().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77145 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 93b67e40de356569493c285b86b138a3f11b5035 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Eliminate some uses of DOUT, cerr, and getNameStart().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77145 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 68c9ce7c9e803dcb79ff465770e6dafa65f12779 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Factor commonality in triple match routines into helper template for registering
classes, and migrate existing targets over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77126 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/ARMTargetInfo.cpp
|
| 8977d087c693fd581db82bcff134d12da0f48bd3 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Factor commonality in triple match routines into helper template for registering
classes, and migrate existing targets over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77126 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/ARMTargetInfo.cpp
|
| bfa8b2c02c927c58f8a0a4b1ff8c04d7eb747069 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill Target specific ModuleMatchQuality stuff.
- This was overkill and inconsistently implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77114 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/ARMTargetInfo.cpp
|
| fa27ff296d3694a68e7abb3b6b7629588def3e58 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill Target specific ModuleMatchQuality stuff.
- This was overkill and inconsistently implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77114 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/ARMTargetInfo.cpp
|
| c1cd72e05f3324eb2d7f1db44848e11541a8fa5a |
26-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM Neon VREV instructions.
Patch by Anton Korzh, with some modifications from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| 8bb9e48752b4a88e512ceb8fb802e2cdf8150e7b |
26-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM Neon VREV instructions.
Patch by Anton Korzh, with some modifications from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrNEON.td
|
| e03513b6e418341df9f2c18559c3e3557ac9b695 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove Value::{isName, getNameRef}.
Also, change MDString to use a StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77098 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 03d7651c3652e1f0cc86e79b26585d86818da9cf |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove Value::{isName, getNameRef}.
Also, change MDString to use a StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77098 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 123157a91a9c00c42cc7a91b03b4ed2db0b6d197 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Simplify JIT target selection.
- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77060 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/ARMTargetInfo.cpp
|
| d6fd377f3333922c4e928019cdfa124ff7f4dd2e |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Simplify JIT target selection.
- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77060 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/ARMTargetInfo.cpp
|
| c680b01a5af67194871ad98d1b85b61db34d6823 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add new helpers for registering targets.
- Less boilerplate == good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77052 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 0c795d61878156817cedbac51ec2921f2634c1a5 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add new helpers for registering targets.
- Less boilerplate == good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77052 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 0bdbfae85e3ffbc88045ea32e1f8a6b1f0c89f56 |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| c7423aff68630d7fd1250337505a8e4be09d0f15 |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ce4b3483064d398194cde05457dbfba2abb83bea |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of a couple of unnecessary getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77035 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
humb2RegisterInfo.cpp
|
| c6b54d5a33ca5341da8d6ccc3140a5b67475e7f4 |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of a couple of unnecessary getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77035 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
humb2RegisterInfo.cpp
|
| 4ded2824b2e221e0d55f5b8178a04210c4132e38 |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Another TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77026 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 3c91f36a4588df306284db0dece0590e846b5f55 |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Another TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77026 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 6e2ebc9df94229f84661a37f8b9747e330b9de07 |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
EADME-Thumb2.txt
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 66ac53165e17b7c76b8c69e57bde623d44ec492e |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
EADME-Thumb2.txt
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 005975c04c5ffc4ee07107ad60dd7d465464e6f7 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
"magic" DOUT behavior which avoided calling printing functions when the
statement was disabled. In addition to being unnecessary magic, it had the
downside of leaving code in -Asserts builds, and of hiding potentially
unnecessary computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77019 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| ce63ffb52f249b62cdf2d250c128007b13f27e71 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
"magic" DOUT behavior which avoided calling printing functions when the
statement was disabled. In addition to being unnecessary magic, it had the
downside of leaving code in -Asserts builds, and of hiding potentially
unnecessary computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77019 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 7cdd0cc18a1514e41d0743986bbfffeaf537a5cf |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM code emitter can't handle Thumb2 instructions yet. So don't even try.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77018 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 90daf4d035c5808d310f2500d051c2dd830cc5bd |
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM code emitter can't handle Thumb2 instructions yet. So don't even try.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77018 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| eacb44d0bb89c608c4465b7900eea3afc0f0be0d |
25-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| eed707b1e6097aac2bb6b3d47271f6300ace7f2e |
25-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| ace089079584cced3e3562d271f38b9d9ef3f8f8 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Uh. It would be useful to actually print the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77004 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0b6afa8c71f3ee32d42390c0c46c28ff31aa6325 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Uh. It would be useful to actually print the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77004 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4e50240d2aeae32e8b98473c4baeea257d180ca0 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76995 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| 40efc251cd7a52dd2375ec95ee38b1be4572178f |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76995 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| 370b544e924604d0e85f3620ae9917d45bceb1e1 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76991 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 49f846805efe101ae8e6dcff6311cc480072845b |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76991 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a609c1db269d37f9443af611b415a9f7af917474 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure thumb2 jumptable entries are aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMInstrThumb2.td
|
| 789476240d6b6f8ad9366cadf790a82bd41bb0b3 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure thumb2 jumptable entries are aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMConstantIslandPass.cpp
RMInstrThumb2.td
|
| 1f999061d3d6de5f9fb54e8793889cdb59a53627 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76984 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 23606e35ab48ab106ca0fcd29338349d5d77f54a |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76984 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| b437c25e587031168324b50079aa2db3317663ad |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Replace use of std::set with SmallPtrSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76983 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c324ecb7bc93a1f09db29851438ec5ee72b143eb |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Replace use of std::set with SmallPtrSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76983 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d1aa70a7dba5800c8c40e25131c1f037b83052e8 |
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 23ed52752bb40a9085c9d36bbc6603972c3e0080 |
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1InstrInfo.h
|
| 87bc69bc872258a4e16d38e5b10ee9816765c7a1 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
use section flags more correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76944 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c440cc7f2c1e1e02fb4526babc9ab99986beb6e0 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
use section flags more correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76944 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 16b8d7f1487d69ad759335774b7350b666d104b2 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
reduce api exposure: clients shouldn't call SectionKindForGlobal directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76941 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| fb3431aec52f1d4d9305159d9f4e652c81b4d9fb |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
reduce api exposure: clients shouldn't call SectionKindForGlobal directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76941 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 872df0d9836c1641c836b687b0d2419d951edac8 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 should use the register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76930 91177308-0d34-0410-b5e6-96231b3b80d8
humb2RegisterInfo.cpp
|
| 865763bf80625aa3f06116335b067bf7ad76061c |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 should use the register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76930 91177308-0d34-0410-b5e6-96231b3b80d8
humb2RegisterInfo.cpp
|
| 64d673e5f3213c620eafd3f9011fdd3ddac37666 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| b74bb1a7a471a77e793d90de158aa4bbc67fe94d |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMInstrInfo.cpp
humb1InstrInfo.cpp
humb2InstrInfo.cpp
|
| 7938afc0b087519f71c2cbba499057c523948cb3 |
24-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb2.td
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 5ff58b5c3ab6df332600678798ea5c69c5e943d3 |
24-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb2.td
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 65c264243983974d40f2bb610b63b6aa20fe0d36 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 does not allow the use of "pc" register as part of the load / store address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| eee839dd3c5cb87e51a522b4800674d7680fef70 |
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 does not allow the use of "pc" register as part of the load / store address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f6e7e692ddf32f101a85eed9661b8e2b9e422e4f |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix up ARM constant island pass for Thumb2.
Also fixed up code to fully use the SoImm field for ADR on ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76890 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| d3d9d66dd211d1267e764c7294876d9a227f04ca |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix up ARM constant island pass for Thumb2.
Also fixed up code to fully use the SoImm field for ADR on ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76890 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6683bb6a7d82f45a10742a914d3c7d0d30d8e753 |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| 81c102ba6639c807825b59df99ac41f3b14d191d |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| df272512181f7db8fb865c58272c47a9e2bd52c6 |
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb2.td
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| b53cc014d0f47b898c9daca34566c16dda6c4c1e |
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb2.td
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 28b3ffcf68128fbdb8e56157520202ed57a57e8d |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76872 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 697712c7d42cbd30fe07367abdbfa0620666e3a3 |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76872 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| d1147266c27f635be76b988769f4c9b8eec922a9 |
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix typo in addrmode definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| e1e52edfff9f24d1e3f308cd126ff7ffac514ed7 |
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix typo in addrmode definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76806 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 9cf1e3e34210388fe79b88f264fca2d13029b2ee |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| eadf04992aea8d3efbc89d8e5920044d7a652e22 |
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 08754dbf3644527cf8b38b0ccc4671a2f69b54ec |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate a redudant check Eli pointed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76762 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 78dd9dbdfb55f1f1878e5000bd1f4ab1a0607f01 |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate a redudant check Eli pointed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76762 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 27396a68bc6b9251d92c0f3aa8aee4f5b12860cc |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 756da12ae4030259d98fefbe26f840d49f71898e |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| 996796e23d5aa0ee948924cab45a07e37495e48b |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76728 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 4a8b7d030bf815baf082bc066c84ba091bc4e31f |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76728 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| a862fe87a5c632a3cc1208f3c0478ab9ebc7ff3f |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a obvious copy-n-paste bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76727 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 3b6627b9440f5588d326747896739e1f9c3d9ce2 |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a obvious copy-n-paste bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76727 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 6eb1493cc7275257232f2001f9d653538ef9ea1d |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid one of the getRegisterNumbering. Also add D16 - D31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76725 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
|
| 8295d99bff6f8e3dfdfdaf1871cb72adab423f20 |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid one of the getRegisterNumbering. Also add D16 - D31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76725 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMCodeEmitter.cpp
|
| 8523043feee8ebc0beca32a3bb75eefabfa8df81 |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add an entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76711 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 064a6eacab8038f1021004b24f49fe70597f6032 |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add an entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76711 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 175b6540352920afd47979cecb8c2667a3f7fdd3 |
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| e922c0201916e0b980ab3cfe91e1413e68d55647 |
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelLowering.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| bf2498c21108f07430f029ef952ae08b2b37b25c |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fixing cp island pass. Step 1: Determine whether the constant pool offset can be
negative on an individual bases rather than basing on whether it's in thumb
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76698 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 5d8f1cae76e4e424bf3b4392eddb3f4dbf38662a |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fixing cp island pass. Step 1: Determine whether the constant pool offset can be
negative on an individual bases rather than basing on whether it's in thumb
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76698 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| fdd472e94ea163893337db1d9c267cb1e7e69b79 |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76693 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV6.td
|
| 7fdf962e5c8c58650b08e25ba2443f3252674b3d |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76693 91177308-0d34-0410-b5e6-96231b3b80d8
RMScheduleV6.td
|
| 690b8d58190f71ff277f1f8b74a13ba35bedce4f |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
no really, I can spell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76679 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 354c0165e755fd857bc89792243b82387ee3936d |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
no really, I can spell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76679 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 8f3f851edb0f3339c8913f666492d3be9843e854 |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add an API so target-independent codegen can determine if a constant
pool entry will require relocations against it. I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76678 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| cb4596364369ea36ff5675eb12fc62d0c6f1f0dd |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add an API so target-independent codegen can determine if a constant
pool entry will require relocations against it. I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76678 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 0d68fde3e710982a02ff383488fc31aa3923cc7b |
21-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add fake v7 itineraries for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSchedule.td
RMScheduleV7.td
|
| 6762d91c05324d7f931bb8dedf64e1559f66d0fa |
21-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add fake v7 itineraries for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSchedule.td
RMScheduleV7.td
|
| ae9822178ceb757bb0778146cf899bd715382f4f |
21-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make AsmPrinter::doFinalization iterate over the global variables
and call PrintGlobalVariable, allowing elimination and simplification
of various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76604 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 40bbebde9d250b875a47a688d0c6552834ada48f |
21-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make AsmPrinter::doFinalization iterate over the global variables
and call PrintGlobalVariable, allowing elimination and simplification
of various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76604 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 58fec0cb1710d68258f2e4463ef4c2918708c3f5 |
21-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not select tSXTB / tSXTH in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 3ecadc816d04c5a0cd690ec9ec6680aeb1fc7bc3 |
21-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not select tSXTB / tSXTH in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c35ff01747d5f5b35430784d3f16c617dcf1bb9b |
21-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| af9e7a7c20d541cfaaaed9dfa21046ac6652cc03 |
21-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 97eb10c18c5505caca89a396f8237f422594ecbd |
21-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
CMP and TST define CPSR, not use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76489 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c27a4547a369a49e94a02063b097911bffa6ae57 |
21-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
CMP and TST define CPSR, not use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76489 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e469911c38df4fa5da32770a3b916ee6af27c1b6 |
20-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Rename Mangler linkage enums to something less gross.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76456 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5c0ba804c02777c53c0842d0be2d16d1d92b9a46 |
20-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Rename Mangler linkage enums to something less gross.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76456 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3ac0d98f57e61a18c6af9265b0533f61ae9ede5f |
20-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use t2LDRri12 for frame index loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76424 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 31e7eba06fdd74d72501b82fbedfb9724346c2ce |
20-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use t2LDRri12 for frame index loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76424 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1ab1cbf8f9313fdd7fd184518a4f382071c9a2ed |
20-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
humb1RegisterInfo.cpp
|
| f6fe9579505be86420beea04f2c9ecb0fd7c55fd |
20-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
humb1RegisterInfo.cpp
|
| df6703e7c10896a3b5e2e9a45dd006050ca49a7b |
20-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Model fpscr to prevent fcmped / fcmpezs etc from being deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76390 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMRegisterInfo.td
|
| 91449a883d4266730261710dfc15b5ec69c1a8f8 |
20-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Model fpscr to prevent fcmped / fcmpezs etc from being deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76390 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
RMRegisterInfo.td
|
| 41a0785fdd228e1563e606f650cef9b3617ab29e |
20-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add plumbing for the `linker_private' linkage type. This type is meant for
"private" symbols which the assember shouldn't strip, but which the linker may
remove after evaluation. This is mostly useful for Objective-C metadata.
This is plumbing, so we don't have a use of it yet. More to come, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76385 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3d10a5a75794356a0a568ce283713adc3a963200 |
20-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add plumbing for the `linker_private' linkage type. This type is meant for
"private" symbols which the assember shouldn't strip, but which the linker may
remove after evaluation. This is mostly useful for Objective-C metadata.
This is plumbing, so we don't have a use of it yet. More to come, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76385 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d75ede054a2651abd1f91520eb3dbebd7c2b3321 |
19-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a regression from 76124. Thumb1 instructions default to S bit being true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76374 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
humb1RegisterInfo.cpp
|
| b46aaa3874d2753632c48400c66be1a10ac18d42 |
19-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a regression from 76124. Thumb1 instructions default to S bit being true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76374 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
humb1RegisterInfo.cpp
|
| 88afc155c23fa1123eb2c42937ddbc5782ca9cc7 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add dependencies from TargetInfo onto .td generation.
- Shouldn't really be necessary, but currently .inc files get included into
some main target headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76349 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/CMakeLists.txt
|
| b384c85877d9fd3e9f3ae8d1b68c7c610bc5a1f4 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add dependencies from TargetInfo onto .td generation.
- Shouldn't really be necessary, but currently .inc files get included into
some main target headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76349 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/CMakeLists.txt
|
| 0b0441e2cbb543e18e764943bb3b9dc32bce1503 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Put Target definitions inside Target specific header, and llvm namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76344 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
argetInfo/ARMTargetInfo.cpp
|
| 4cb1e13769856716261a4d315f8202bd918502c3 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Put Target definitions inside Target specific header, and llvm namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76344 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
argetInfo/ARMTargetInfo.cpp
|
| 6628b5ba0e383904260935a46fe39d61d3e3bd52 |
17-Jul-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
r76102 added the MachineCodeEmitter::processDebugLoc call and called it from
the X86 Emitter. This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76211 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 75402822d6acc1fe62d911771cd7cf8358c718d7 |
17-Jul-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
r76102 added the MachineCodeEmitter::processDebugLoc call and called it from
the X86 Emitter. This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76211 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| ec369ef8ac33ac20f9ab08edeb8a4431a3566c85 |
17-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76155 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| a6e4322cccad525c5b28ddae2875da695c04e90e |
17-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76155 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 24270fab43b2f3314cc6be7b14bfc8e5f2a8828b |
17-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcf |
17-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 463a3e4dd8149ca3f4ab27a71f2a9f48e02c2726 |
16-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 378445303b10b092a898a75131141a8259cff50b |
16-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| bf79dcb6c45fdf395584ce127852e75cf44def3b |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink
variables.
- Module initialization functions supplanted the need for these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75886 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 64cc97212346992892b6c92158c08cd93149a882 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink
variables.
- Module initialization functions supplanted the need for these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75886 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| f0cda48cf2490ed0212fc438beec5e803beb87f1 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift addAssemblyEmitter into LLVMTargetMachine.
- No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 5d77cad60bd82dfa2d00f78e26443d667922efbf |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift addAssemblyEmitter into LLVMTargetMachine.
- No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 3e0ad8b5c033e9640473e7a274dbcd5d71dc4419 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| cfe9a605eea542d91e3db74289b69b7e317d90a6 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| b3cbc675ed99c2f5c8bc1125dbfa27c5727207f8 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove old style hacks to register AsmPrinter into TargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75843 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| f05522974b3c1b9dc2644831364e19d5132e751b |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove old style hacks to register AsmPrinter into TargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75843 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| fe5939fd18b28961606da555f9c0ca5d7099a19b |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Reapply TargetRegistry refactoring commits.
--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 51b198af83cb0080c2709b04c129a3d774c07765 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Reapply TargetRegistry refactoring commits.
--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 1721b8dc5f33106beb57f85ac96a493820e99993 |
15-Jul-2009 |
Stuart Hastings <stuart@apple.com> |
Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 2286f8dc4cec0625f7d7a14e2570926cf8599646 |
15-Jul-2009 |
Stuart Hastings <stuart@apple.com> |
Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| dfd64ca7d0d832485dcae754b5fa50f912aa703c |
15-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75789 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7ecc850cf19b365a88f30c3f300d3979b960fe8b |
15-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75789 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 8ba03b7ed73b410bde95dbcf528ece3782e84a1f |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Replace large swaths of copy-n-paste code with obvious helper function...
- Which was already present in the module!
- I skipped this xform for Alpha, since it runs an extra pass during assembly
emission, but not when emitting assembly via the DumpAsm flag.
- No functionality change.
--
ddunbar@giles:llvm$ svn diff | grep '^- ' | sort | uniq -c
18 - PM.add(AsmPrinterCtor(ferrs(), *this, true));
18 - assert(AsmPrinterCtor && "AsmPrinter was not linked in");
18 - if (AsmPrinterCtor)
18 - if (DumpAsm) {
18 - }
ddunbar@giles:llvm$ svn diff | grep '^+ ' | sort | uniq -c
18 + addAssemblyEmitter(PM, OptLevel, true, ferrs());
18 + if (DumpAsm)
--
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75782 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| f3f4715ac1de3ae4c89eeb96f23d6cd4876cc323 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Replace large swaths of copy-n-paste code with obvious helper function...
- Which was already present in the module!
- I skipped this xform for Alpha, since it runs an extra pass during assembly
emission, but not when emitting assembly via the DumpAsm flag.
- No functionality change.
--
ddunbar@giles:llvm$ svn diff | grep '^- ' | sort | uniq -c
18 - PM.add(AsmPrinterCtor(ferrs(), *this, true));
18 - assert(AsmPrinterCtor && "AsmPrinter was not linked in");
18 - if (AsmPrinterCtor)
18 - if (DumpAsm) {
18 - }
ddunbar@giles:llvm$ svn diff | grep '^+ ' | sort | uniq -c
18 + addAssemblyEmitter(PM, OptLevel, true, ferrs());
18 + if (DumpAsm)
--
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75782 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| d10106b39dd10904a4126f253609afd470fa063b |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off old (TargetMachine level, not Target level) match quality functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75780 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 6c05796294a7a0693d96c0c87194b9d5ddf55a94 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off old (TargetMachine level, not Target level) match quality functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75780 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 8ea70214b5ffcdc5c3693a082cc1ec3cec6ba98b |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Provide TargetMachine implementations with reference to Target they were created
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75778 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 03f4bc5d6cf777c8aa559c299ef7f85126872881 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Provide TargetMachine implementations with reference to Target they were created
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75778 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 6fa4f57aed4e1ff2cb6a85dd08f04b91261814d0 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Register Target's TargetMachine and AsmPrinter in the new registry.
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75762 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 4246790aa84a530b0378d917023584c2c7adb4a9 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Register Target's TargetMachine and AsmPrinter in the new registry.
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75762 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 0eb6699b8f19fc450c7ce61c7ac0638753f92f9c |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add TargetInfo libraries for all targets.
- Intended to match current TargetMachine implementations.
- No facilities for linking these in yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75751 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
argetInfo/ARMTargetInfo.cpp
argetInfo/CMakeLists.txt
argetInfo/Makefile
|
| c984df8602a8b2450cbdb6ff55fd49ba709a391e |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add TargetInfo libraries for all targets.
- Intended to match current TargetMachine implementations.
- No facilities for linking these in yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75751 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
argetInfo/ARMTargetInfo.cpp
argetInfo/CMakeLists.txt
argetInfo/Makefile
|
| 48fe5b85e51ea6468a56159d905b89bcaa606956 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
convert arm/darwin stubs to use the mangler to synthesize all the names instead of
doing it with printSuffixedName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75741 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b1ccad3b0d291a089aac0e9992d320d65cc27dce |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
convert arm/darwin stubs to use the mangler to synthesize all the names instead of
doing it with printSuffixedName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75741 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 494cb892adfe81c0cb786693a0490c36d8cf3a7b |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 4fb63d088bca9fc31e54eb1619e2cb448c3a4b53 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 8735beca681958d0f9544c6231cb27856cbe7bfc |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
convert [Hidden]GVNonLazyPtrs to compute the global and stub names
with the mangler (like x86 and ppc), instead of going through
printSuffixedName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75736 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0a2385455b01186b947148b00c80a89e8a725099 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
convert [Hidden]GVNonLazyPtrs to compute the global and stub names
with the mangler (like x86 and ppc), instead of going through
printSuffixedName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75736 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9f5b2aa7fba203469386acc413c23dd41a713bc9 |
15-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Move EVER MORE stuff over to LLVMContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75703 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 9adc0abad3c3ed40a268ccbcee0c74cb9e1359fe |
15-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Move EVER MORE stuff over to LLVMContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75703 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 9b784f00e4d72b2fa3ec5b270d1439c896e06c1c |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix bad indentation and 80-col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75686 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 8718bc4497b3f7e6e5dde16845179744d54988bf |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix bad indentation and 80-col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75686 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 9fe1423dc142764dc56cf65f38317e0fcd0a7fc2 |
14-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Check for PRE_INC and POST_INC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75683 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4cb73525a943d69da0f2b0c31c1a1d7f3cdd879d |
14-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Check for PRE_INC and POST_INC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75683 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 302008dbeae03364ffffc1bcf77d2eb28897d98a |
14-Jul-2009 |
David Greene <greened@obbligato.org> |
Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75670 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 71847813bc419f7a0667468136a07429c6d9f164 |
14-Jul-2009 |
David Greene <greened@obbligato.org> |
Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75670 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| ef8e1badf610088c4998afd4bc3c65383e741169 |
14-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75660 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 419c6150877bb35bd3a95a3101e47f6615c8e390 |
14-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75660 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 53dadfcae0ea56e86c639a91b33d643a4939a8f8 |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove an extra space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75658 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3eadf00b46fbb2aa59b8771a8d8bdf1bfd7f9141 |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove an extra space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75658 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b3cdde6d77eadb722aff894b1d90498ce70babc2 |
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Reapply my previous asmprinter changes now with more testing and two
additional bug fixes:
1. The bug that everyone hit was a problem in the asmprinter where it
would remove $stub but keep the L prefix on a name when emitting the
indirect symbol. This is easy to fix by keeping the name of the stub
and the name of the symbol in a StringMap instead of just keeping a
StringSet and trying to reconstruct it late.
2. There was a problem printing the personality function. The current
logic to print out the personality function from the DWARF information
is a bit of a cesspool right now that duplicates a bunch of other
logic in the asm printer. The short version of it is that it depends
on emitting both the L and _ prefix for symbols (at least on darwin)
and until I can untangle it, it is best to switch the mangler back to
emitting both prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75646 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b8158acc23f5f0bf235fb1c6a8182a38ec9b00b2 |
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Reapply my previous asmprinter changes now with more testing and two
additional bug fixes:
1. The bug that everyone hit was a problem in the asmprinter where it
would remove $stub but keep the L prefix on a name when emitting the
indirect symbol. This is easy to fix by keeping the name of the stub
and the name of the symbol in a StringMap instead of just keeping a
StringSet and trying to reconstruct it late.
2. There was a problem printing the personality function. The current
logic to print out the personality function from the DWARF information
is a bit of a cesspool right now that duplicates a bunch of other
logic in the asm printer. The short version of it is that it depends
on emitting both the L and _ prefix for symbols (at least on darwin)
and until I can untangle it, it is best to switch the mangler back to
emitting both prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75646 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| bd448e3ca993226084d7f53445388fcd8e46b996 |
14-Jul-2009 |
Edwin Török <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
humb1RegisterInfo.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
humb1RegisterInfo.cpp
|
| cc06725e0fa56905ae2cd0c601d687a852f93c7c |
14-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert r75615, which depended on 75610.
--- Reverse-merging r75615 into '.':
U lib/Target/XCore/XCoreAsmPrinter.cpp
U lib/Target/PIC16/PIC16AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/MSP430/MSP430AsmPrinter.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75637 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 192957d376923cefc993c1b5c04127c42f1008ec |
14-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert r75615, which depended on 75610.
--- Reverse-merging r75615 into '.':
U lib/Target/XCore/XCoreAsmPrinter.cpp
U lib/Target/PIC16/PIC16AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/MSP430/MSP430AsmPrinter.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75637 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 64b9f4289a80f8a9f51f7ad766775277ec41e0c6 |
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rename getValueName -> getMangledName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75615 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b09d2ccc0f23107fc1047694ce266a9cf5e0a3c2 |
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rename getValueName -> getMangledName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75615 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| fb1d14783bcb0c6ffb62bf32e2316d98e8e98641 |
14-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
1. In Thumb mode, select tBx instead of ARM variants.
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| f6bc4ae4a1a2dbf986099ab7b74106e8d273cbe1 |
14-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
1. In Thumb mode, select tBx instead of ARM variants.
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| f354d36027f21554f43b365cd07cf965a7687096 |
14-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix detection of valid BFC immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75576 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c2ffd286af76f8df71af0de18987cde2b2cb467b |
14-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix detection of valid BFC immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75576 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a11dc992517d49419fa563426fe5e0fb86927237 |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix an obvious copy-and-paste error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75566 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| e622087e2064a5496ed9be5d9a8796349cf18b75 |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix an obvious copy-and-paste error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75566 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 0473735371cb31e40f98d7b6022b84be5932bcf0 |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 75309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75562 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 60206140a19bd88d4c2f6a2198baa7f975e1370a |
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 75309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75562 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 651117e5e3e4981137364ff0728083ef28f4f660 |
13-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75513 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| ea670f1dd8067a9b65f952d0548669045bf0e21f |
13-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75513 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 0c5f44ef85612448fb2eac6744f2ac4a5c55298c |
13-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d2559bf3f30cc7400483825414489ec0fb36481a |
13-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75479 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 151026f04f7e7e2dcbd1120e61b1f4222db450f7 |
12-Jul-2009 |
Edwin Török <edwintorok@gmail.com> |
Remove extra \n from LLVM_UNREACHABLE calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75416 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 29fd056d8106c27fb0d9e4602c4d7fbd539219c6 |
12-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Remove extra \n from LLVM_UNREACHABLE calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75416 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 675d56222b6b98d2c22a17aaf69a036e57d5426a |
11-Jul-2009 |
Edwin Török <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
RMISelLowering.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
RMISelLowering.cpp
|
| ef2df966e884524bf2c0003e3361052f4520046e |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't put IT instruction before conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75361 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| ed338e80f92d6efa961d9f8c29239dde1507e683 |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't put IT instruction before conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75361 91177308-0d34-0410-b5e6-96231b3b80d8
humb2ITBlockPass.cpp
|
| 76aeed376644c2ad0fa4e44217d39b3e3567b323 |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb.td
EADME-Thumb.txt
|
| 2f297df02eac140de4e2f85e56bd79abf883360c |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb.td
EADME-Thumb.txt
|
| 7bd2ad18193b56a829bbaf05911faca496c19ac1 |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
EADME-Thumb.txt
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| 446c428bf394b7113b0f18cbacb5e87b4efd1e14 |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
EADME-Thumb.txt
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb2InstrInfo.cpp
|
| b6f656e6ad0719c09f953d79faca7732b89f16aa |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| dd6f63209cba0003e67470938830de2cb6917336 |
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
|
| 9231da32b3a1809a75414616082b28284e3579fc |
11-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of
quad registers and the Q4PR class holds sets of 4 quad registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75309 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 1e44ed88ebb1c381260a0b0777851277a7657587 |
11-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of
quad registers and the Q4PR class holds sets of 4 quad registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75309 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| ce9fbbe7d2492c5343549b0eee3a5a531bd9f2a5 |
10-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75254 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 3ca524e336ad0be449c080235a2d7a38516f0ca4 |
10-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75254 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrVFP.td
|
| 48743562f740ed4b6345b4a01e6d821599b10e19 |
10-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
t2LDM_RET does not fall-through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75250 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| b1beca635fcac095c6227c6518a35e165f8f03bc |
10-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
t2LDM_RET does not fall-through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75250 91177308-0d34-0410-b5e6-96231b3b80d8
humb2InstrInfo.cpp
|
| 4b28db3bbe1251f05072bc273950527b18ae38bb |
10-Jul-2009 |
Duncan Sands <baldrick@free.fr> |
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing
the cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75246 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 179bef36368ebeddbb5cb754fa1e5859e311855d |
10-Jul-2009 |
Duncan Sands <baldrick@free.fr> |
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing
the cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75246 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 37a990869879018d1739489098fd983b1d8686c3 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
More info about Thumb1 predication support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75220 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| b6264decdbec4940f66a8850450ab1c31f058b4c |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
More info about Thumb1 predication support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75220 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 986e3b713f1406d19ce77a12886e8ea38bf00e3b |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75219 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 892837abf35c2c1439af9066a9c2aaa3b3f0e72b |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75219 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d5b67fab9a5293e74626c34c2967ec4b5cf9283d |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a thumb2 pass to insert IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMInstrThumb.td
RMInstrThumb2.td
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
humb2ITBlockPass.cpp
|
| 06e16587ebc81e43b42157fa3afcfd806b59b296 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a thumb2 pass to insert IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMInstrThumb.td
RMInstrThumb2.td
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
humb2ITBlockPass.cpp
|
| f15238c4648722b59ee418119cf3f5ea425c37aa |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move isPredicated from .cpp to .h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75217 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| ab331504452a833f27a030f13525b964545d768a |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move isPredicated from .cpp to .h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75217 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
|
| 859f1f8be6f11797632d51462a54022b37974004 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75212 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
|
| b5619f42f4fdf347380d28357549df09b9ca3946 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75212 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.h
|
| a34fca166572ff4c9192e375d74d89808b3caf74 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove a bogus assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 9c06178e355be69e313820d31878022bc882c2db |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove a bogus assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 995f697df68986ea48f8194239c28d3db9c94de5 |
10-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Replace TM.getRegisterInfo() calls by TRI instance variable.
Use getAsmName() method instead of accessing AsmName field directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75205 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 97354f5181ee6b7999a468bfc5b62c11e11f6318 |
10-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Replace TM.getRegisterInfo() calls by TRI instance variable.
Use getAsmName() method instead of accessing AsmName field directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75205 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| c675135c7e8c69bc61a95ebedd0741dc8354f649 |
10-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle 'a' modifier on inline assembly operands.
This is part of the fix for pr4521.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75201 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9b4b00ad436daeac6f97f77e9b5a3cc67ada150c |
10-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle 'a' modifier on inline assembly operands.
This is part of the fix for pr4521.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75201 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b8d0743fecd1f44323524e60e3aadc835f95755d |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added Thumb IT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75198 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smPrinter/ARMAsmPrinter.cpp
|
| e5564748b7d35df5c06fd243d04ea1eb305d3bc3 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added Thumb IT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75198 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
smPrinter/ARMAsmPrinter.cpp
|
| e1fce341f4ee887c5e164a32f58802c22d264a03 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Another todo entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75192 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 896fe89f55a1620782eb3d421271059a02d92d1c |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Another todo entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75192 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 4adba7bf2b784076191cf3dc67d0c294d1206707 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75190 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 45032f28013aa69d07bf859da9d976947910f059 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75190 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| ad877c8a049fe4252488243715fe3339831a6443 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ldm / stm unified syntax; add t2LDM_RET.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| c50a1cbf5f2b536d396a78a3feb91656a8c8d9f1 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ldm / stm unified syntax; add t2LDM_RET.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75188 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7bd57f8b46a9a6d981fc22792fd9f6ccd83587ef |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
LDM_RET should be marked mayLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75187 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d75223d6c672a0a29beecb42dacf6350e3426b3f |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
LDM_RET should be marked mayLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75187 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6bc6720f9668f3f7fbbe3faa21c21231ac54fbbc |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
Note, we are not yet generating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75181 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 5c874172ac8fd563867efc54022ac4c1571e1313 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
Note, we are not yet generating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75181 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| e3dad534b10bde98cd888de509c948c5f34f9e0a |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a Thumb readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75173 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 6dded67b0d6262964e22163d0ab37c9ee6957c0a |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a Thumb readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75173 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 4df2ea7b4872b73cf5426a7b06e2bbfa7e6afd39 |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Correct comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75172 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| cba962dd6b46fce807dfe3ed97da04ec5ad98c34 |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Correct comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75172 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| cceb78316b524c67f47ae59ee1b019f09d077a33 |
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Handle Thumb-2 addressing modes during FP elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75158 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| 8b98b85c64543e7ec479f40e5c2b5a24aa862fed |
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Handle Thumb-2 addressing modes during FP elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75158 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
|
| a0167020062bbcfe0558faa29dd705ca6f9a8e2a |
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d1474d09cbe5fdeec8ba0d6c6b52f316f3422532 |
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ac0e7d6669b2fd7a1f6b6a30ddc6ec47af6eb4f3 |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reorg includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75115 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
RMTargetMachine.h
|
| 1945b7b5c5da39b89c2a2d3083d02e2aabf3cf98 |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reorg includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75115 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
RMTargetMachine.h
|
| 4a8979320ced9b38019f6f2c074f2d3dbe1b189e |
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use common code for both ARM and Thumb-2 instruction and register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb.td
RMInstrThumb2.td
RMMachineFunctionInfo.h
RMTargetAsmInfo.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 |
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use common code for both ARM and Thumb-2 instruction and register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb.td
RMInstrThumb2.td
RMMachineFunctionInfo.h
RMTargetAsmInfo.cpp
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| dabc6c0de0dff276fc3f7002a6102788a2f89cbc |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add some NEON ld / st instruction static encoding.
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75065 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| dda0f4cb798e5f482247cda4ea9b74977b4601ec |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add some NEON ld / st instruction static encoding.
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75065 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
|
| 8be2a5bd2b7a7296f150053c0a8d8767a810b78c |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
|
| e7cbe4118b7ddf05032ff8772a98c51e1637bb5c |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMBaseInstrInfo.cpp
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
RMLoadStoreOptimizer.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 26cb025878ef21cd1be821246ebc284b59d4434a |
08-Jul-2009 |
Edwin Török <edwintorok@gmail.com> |
Missed an exit during the conversion.
Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75045 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3046470919e648ff7c011bda9c094163062c83dc |
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Missed an exit during the conversion.
Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75045 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4d9756a9843862edb9daddfaa0d8c78ac1c52b32 |
08-Jul-2009 |
Edwin Török <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| f7e1ae349ce59eab9904cc36a88f520524baf585 |
08-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement NEON vst1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 2ed334694fb39332eddef21f6bc7af9bb21aa200 |
08-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement NEON vst1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrNEON.td
|
| 1f0bb9901f04ac2ad87b091504adc54306b4815c |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrThumb2.td
RMRegisterInfo.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 77521f5232e679aa3de10aaaed2464aa91d7ff55 |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.h
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMInstrInfo.cpp
RMInstrThumb2.td
RMRegisterInfo.cpp
humb1InstrInfo.cpp
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| 81332c2a6bda16a1f3586fa219fdf4c5d769606e |
08-Jul-2009 |
Xerxes Ranby <xerxes@zafena.se> |
Fix cmake build.
Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75035 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| cecbc964e1996c39881b3442fc7390e82050f527 |
08-Jul-2009 |
Xerxes Ranby <xerxes@zafena.se> |
Fix cmake build.
Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75035 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 2013b4c6940f16a64c6027821de217fb0e97deef |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Push methods into base class in preparation for sharing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| db5a71a8e01ed9a0d93a19176df6ea0aea510d7b |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Push methods into base class in preparation for sharing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
|
| ed592c08e5c1e0b164f606f8e8fb00199e19660c |
08-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement NEON vld1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 205a5ca6cfabc6cd408634a2fa7f2529956cc2cf |
08-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement NEON vld1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrNEON.td
smPrinter/ARMAsmPrinter.cpp
|
| 3cb884811f68c27210391441d631146faa74f55e |
08-Jul-2009 |
Edwin Török <edwintorok@gmail.com> |
Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| ab7c09b6b6f4516a631fd6788918c237c83939af |
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMCodeEmitter.cpp
RMISelLowering.cpp
RMJITInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
humb1RegisterInfo.cpp
humb2RegisterInfo.cpp
|
| 21a075673bb458972682b9bb178685eca1db93cf |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Start breaking out common base functionality for register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75016 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| c140c4803dc3e10e08138670829bc0494986abe9 |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Start breaking out common base functionality for register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75016 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseRegisterInfo.cpp
RMBaseRegisterInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 41afec29ab583a42c864b213ed1b811e7b39b810 |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
MakeLists.txt
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 334c26473bba3ad8b88341bb0d25d0ac2008bb8d |
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
RMBaseInstrInfo.cpp
RMBaseInstrInfo.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
MakeLists.txt
humb1InstrInfo.cpp
humb1InstrInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
|
| 8f5253baafe027bb8939498d9eb1083febc7339a |
08-Jul-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove the vicmp and vfcmp instructions. Because we never had a release with
these instructions, no autoupgrade or backwards compatibility support is
provided.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74991 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7f6aa2b162e5daaf7b9ccf05d749597d3d7cf460 |
08-Jul-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove the vicmp and vfcmp instructions. Because we never had a release with
these instructions, no autoupgrade or backwards compatibility support is
provided.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74991 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9aa4cd32ed7925de9df616a8ea7de4ff77fa5b00 |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrInfo.h
|
| 34a0fa362dde63cf9adf5917ab2ee2c2b7dd2179 |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrFormats.td
RMInstrInfo.h
|
| ec6e592736ba478f7ec001eae1d68a436fec6dd0 |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a todo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74976 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
EADME-Thumb2.txt
|
| c9a4153eef056fad1fd81e783d683aa99841003a |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a todo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74976 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
EADME-Thumb2.txt
|
| e5f32ae95c6e84d725c5f53430be0b432c283592 |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also statically set bit 25 for BR_JT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74974 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0fc0ade0951f8c0e3adb8899c5878d225e010b97 |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also statically set bit 25 for BR_JT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74974 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 83a32b460a2af4f7f814c337b3ab1ae6a2b897cb |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74972 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| bc8a94540a65907472bf6d6e43c8fea864116cf5 |
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74972 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| 0313767db7f8c70bf43fbebc44ba69cd907fa1fc |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| e253c951b38e47f14a097db6ac7731c857837ae2 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 2597a07e281ad074f53761ee94596f9e3dde36f1 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add BX and BXr9 encodings. Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1c83eb33c3e2f463307fb7e61d5b464833645d86 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add BX and BXr9 encodings. Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cd0ae28436ee134eed18e9297ea4ce9abe1cb72f |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 pkhbt / pkhtb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74895 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 40289b041adb299e4474607066b69b89298e5f70 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 pkhbt / pkhtb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74895 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a5626262c4e3ebac0165f68f9cc89615a6cd155c |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add some more Thumb2 multiplication instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb2.td
|
| 5b9fcd1c8e9f2b7964a82cd383441f568890b561 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add some more Thumb2 multiplication instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrThumb2.td
|
| 451192e123b9429e0f9788e26e4b33db0e3019fd |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74888 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 58541fd62707b6856beee3db9e254b0110607bb1 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74888 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 86ae71d0e423ede6ffd57bc1f627a7c0751a9be3 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
isThumb2 really should mean thumb2 only, not thumb2+.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74871 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 3147fb2cff9ca0d258f8ab20ff23b9c447024df1 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
isThumb2 really should mean thumb2 only, not thumb2+.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74871 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 299ee654a2c92e1909144b23cf470a3be5a91d5d |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add bfc to armv6t2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| 36a0aebac21bb72328ce72a55df6f3fe62c68b7f |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add bfc to armv6t2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMInstrThumb2.td
|
| c8147e1cc967c50f72158cc93ee538a671a85f31 |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added ARM::mls for armv6t2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| edcbada3d06c5cf57d2dfd737eb925872bc6182b |
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added ARM::mls for armv6t2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| aabb9a5359cbb0bf9d25bfb917ecb09c086d034b |
06-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
cleanup, removed some #includes and moved Object Code Emitter out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74813 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| ac57e6e498abccb117e0d61c2fa0f733845e50cb |
06-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
cleanup, removed some #includes and moved Object Code Emitter out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74813 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 71c697382e6165ab1b601866a52c8f6628517e42 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6b61cd185eeb90bec93f042535594132ae1f0f41 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0f994ed52b0db0473d50959aa058f97e49b57fde |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 sign / zero extend with rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb2.td
|
| d27c9fc403ae906c60ca3dfee72001f7e1930492 |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 sign / zero extend with rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrThumb2.td
|
| 2832edfb483e43d6f57fe1617f77766855f906dc |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 load / store multiple instructions. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74749 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2889ccea625942348ea74f51ae2f67d084f44850 |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 load / store multiple instructions. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74749 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d72edde77d9576ac77449a57255593fa8281ccbb |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2LDR_PRE etc are loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74741 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 78236f8c8a0e6bd966afd7e461599336956f7772 |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2LDR_PRE etc are loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74741 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 24f87d81329942fe94010c943b0d1c8e45568b4c |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 6d94f1119644393c0b3e58ad666bb1d020770951 |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 40995c93cda1e65d6b469aa06587e68e930358ff |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Sign extending pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 4fbb9960adcd79888acda1869d26032b9ab44a10 |
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Sign extending pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| aca520dbbde3bfd996b6c32c541b58f863d7f5d4 |
03-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
MakeLists.txt
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
humbInstrInfo.cpp
humbInstrInfo.h
humbRegisterInfo.cpp
humbRegisterInfo.h
|
| b50ea5c48f8b1ce259e034ca5c16dc14af1a582c |
03-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
MakeLists.txt
humb1InstrInfo.cpp
humb1InstrInfo.h
humb1RegisterInfo.cpp
humb1RegisterInfo.h
humb2InstrInfo.cpp
humb2InstrInfo.h
humb2RegisterInfo.cpp
humb2RegisterInfo.h
humbInstrInfo.cpp
humbInstrInfo.h
humbRegisterInfo.cpp
humbRegisterInfo.h
|
| d097aa0cb5d160031b01d8831904cecbabc5ef81 |
02-Jul-2009 |
Douglas Gregor <doug.gregor@gmail.com> |
CMake build fixes, from Xerxes Ranby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74720 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 033080cf6a6f6ca94f20c410204405471c19c535 |
02-Jul-2009 |
Douglas Gregor <dgregor@apple.com> |
CMake build fixes, from Xerxes Ranby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74720 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a90942ea9e09576655ed4e0536d6ab9cba5da657 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrFormats.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| e88d5cee9d6b02bc786df806395a718464908064 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrFormats.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 89191fef3ae68a9bae70df456abab12389cbcb89 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74693 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0412957764de44f63657360a22ce5445a8c87628 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74693 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b1b2abc0e7b2cc0f103c872ec6fadcb2cb370406 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.h
|
| d770d9e7d1f5c65b185897dcf226b3fc64598683 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.h
|
| b04191ff93c1c090f34f06a3a37b8837135d0eb7 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74683 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 31926a78e345c53d36df5e1380a69878fbfb2612 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74683 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| af3f27e2118954b60e0da2325af1832547f7f0cc |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Factor out ARM indexed load matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74681 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| af4550f8265885bdf99b3b3f129f3e6fd24a41e5 |
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Factor out ARM indexed load matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74681 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 970a10d2563e597d2a012fe9b083589873700ac2 |
02-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new addressing mode for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74658 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
|
| 8b024a5eb5b64b482f7d92aad7a3f0e6cac93f12 |
02-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new addressing mode for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74658 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
|
| 267aef56f46ab78167c5d62c93009ad3ba0b3bbd |
01-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74650 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| b864e89fe412879823afca6dffb7e700a5bf8210 |
01-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74650 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 460847893899af98947e63bfefd623564c0e0dd7 |
01-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up a comment: besides the >80col lines, the operation for this
addressing mode is encoded in the second operand, not the third.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74641 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| d4d826e17081808fea81509a959a983ed5df1d36 |
01-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up a comment: besides the >80col lines, the operation for this
addressing mode is encoded in the second operand, not the third.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74641 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 045f2635a5664c0659134e6a5f6c4dbda17550f3 |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 6521982510e67c23441d94dd4c4a7167527356cb |
01-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 2578ba26e72e36dde64be0f52a2788480aad3378 |
01-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| b10d22209eac7e43d917ef2194e7a159b9b1c689 |
01-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove unused AsmPrinter OptLevel argument, and propogate.
- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74579 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 5bcc8bd0c60cfe583ee47852950aad9e532c932e |
01-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove unused AsmPrinter OptLevel argument, and propogate.
- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74579 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 5811e5ccf02d5dce63374048674ba62fff85d35a |
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add PIC load and store patterns for Thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| d1fa120aeec67e94e6ed6056593ccb630fe2db0e |
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add PIC load and store patterns for Thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2af7ed8bb82149223fac41d7fa350035f3083fb9 |
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 load and store double description. But nothing yet creates them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 6647cea111ab4d83483b28712b5ba8244e6612f2 |
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 load and store double description. But nothing yet creates them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 25a8ae3f10965b47ecaa9eda5e997f16fe1d9414 |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
smPrinter/ARMAsmPrinter.cpp
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
smPrinter/ARMAsmPrinter.cpp
|
| bab5da1290d6e8f19a4a291acff93c58ff5966a4 |
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add thumb-2 store word, halfword, and byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 73b8f16b360544bc0f756d92fa2661028160cef3 |
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add thumb-2 store word, halfword, and byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 13d2f4e87ae6b295ce49d6fba72237b351f59de6 |
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Improve Thumb-2 jump table support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMInstrThumb2.td
|
| c9a59b5960088f48c3be234bcc4c79a1ed915d73 |
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Improve Thumb-2 jump table support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMInstrThumb2.td
|
| f615470f4a76d5812e059cb84ae6589ce7501180 |
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrThumb.td
RMInstrThumb2.td
RMMachineFunctionInfo.h
|
| 5e47a9a6e46bd271eba058fb831da1a1edf8707c |
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrThumb.td
RMInstrThumb2.td
RMMachineFunctionInfo.h
|
| 503be11a2d9d735109e821344b21348fceed54ce |
30-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
A few more load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
|
| f3c21b857b8449bcde35e499ef8268c0fec9514d |
30-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
A few more load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.h
RMInstrThumb.td
RMInstrThumb2.td
|
| ec52c89440b58a5817d8cbb461b46f10619ac269 |
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Thumb-2 support for TEQ amd TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| baeb911d60401818dc9fe0db6182cd048e4fdd03 |
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Thumb-2 support for TEQ amd TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8bdcbb376685ce24dfb23087ac2a0c9dab8adfa5 |
29-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| c0309b48b560f119982c02a81416c8c1fd208648 |
29-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
|
| bba01aa595de1de7df8bb731cd11291500d7fc11 |
29-Jun-2009 |
Duncan Sands <baldrick@free.fr> |
Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt
to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74421 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| c91e68a0c4b92bac36c1b03c734f8795a757e669 |
29-Jun-2009 |
Duncan Sands <baldrick@free.fr> |
Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt
to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74421 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 532cdc58e657497cde9cfb163b37c08057ad387a |
29-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
EADME.txt
humbRegisterInfo.cpp
|
| 055b0310f862b91f33699037ce67d3ab8137c20c |
29-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
EADME.txt
humbRegisterInfo.cpp
|
| 0a90fcd0751d899e47798c73d89d808bb1b41f8a |
27-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Simplify a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74385 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
humbInstrInfo.cpp
humbRegisterInfo.cpp
humbRegisterInfo.h
|
| 55ad1f22b4554be3a9547fe7a8d84ce05b3d5c72 |
27-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Simplify a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74385 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
humbInstrInfo.cpp
humbRegisterInfo.cpp
humbRegisterInfo.h
|
| cbce7920f24c5c773c1d1bcb08d8ae85651c9a26 |
27-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
ARM refactoring. Step 2: split RegisterInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMTargetMachine.h
humbInstrInfo.cpp
humbInstrInfo.h
humbRegisterInfo.cpp
humbRegisterInfo.h
|
| a98cbc554ca2cd40426e7c3ff8d1467da32e195d |
27-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
ARM refactoring. Step 2: split RegisterInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74384 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMTargetMachine.h
humbInstrInfo.cpp
humbInstrInfo.h
humbRegisterInfo.cpp
humbRegisterInfo.h
|
| 36f26f4ad36f3790994c63956165a0d13606291a |
27-Jun-2009 |
Douglas Gregor <doug.gregor@gmail.com> |
Add ThumbInstrInfo.cpp to the CMake makefiles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74382 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 1b573d8b206d5d1a13cbf46b859e35e9fbeb3738 |
27-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Add ThumbInstrInfo.cpp to the CMake makefiles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74382 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 19bb7c77c841d60c1f0c2f52af90ea4c25f4a5f1 |
27-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Renaming for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 9cb9e6778c7d458eee7f3e25d304697ad10d8d46 |
27-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Renaming for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrFormats.td
RMInstrThumb.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 691ed1c8a720c05984f28aa42f63bb13c2fd7817 |
27-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove outdated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74357 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8eba8e0ca3497e4f518b5e27117ea22651409c2c |
27-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove outdated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74357 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 4f8708c3e04498e1f49064aafd2e8988bb75d303 |
27-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| dcdaebc592cad9bc23652e3b9fdb552d63bbeb9f |
27-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 65d16eabf2925d39c6109c85c663aaac4e549c6c |
26-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Split thumb-related stuff into separate classes.
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74329 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
humbInstrInfo.cpp
humbInstrInfo.h
|
| d49ea77cbc24776142615fecf75f41e191c765bd |
26-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Split thumb-related stuff into separate classes.
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74329 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
humbInstrInfo.cpp
humbInstrInfo.h
|
| 7e2af1b050283ccf7b690530ac725ad27aef1219 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 has CLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74322 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 24062ac5be1a33d1ef76d399613b7d48a684116e |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 has CLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74322 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3536d178c2188c96ebc8b5b720f952b69f8cb26f |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7ce720b448c581b822577aaf44b73a5aa9689dfc |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74321 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e883fc4de8b1a7f06208cec052c8dee5e647a299 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
ADC used to implement adde should use "adcs" opcode instead of "adc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 93d95bd2c309b1fb8e2a830c441d86556a41038c |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
ADC used to implement adde should use "adcs" opcode instead of "adc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74293 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 2dbffd44a6d2bdc31f6f24a44e98c3dbaca3bea6 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74288 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 83b3593478406b020b7af6ba5402a14507d7d713 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74288 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3e9a99ed18768f5a65046148d32d5aa2640f3b0b |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Simplify predicate CarryDefIsUsed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74277 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2b51d51bc3fc2b9b093f1c940dc6e5570bf0033a |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Simplify predicate CarryDefIsUsed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74277 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 880595f3cd8cce2fdb532c8b3f8facf5a747fde7 |
26-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Let's ignore MDStrings also!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74255 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0f05d22a31bf76a1e066592a567217b73fcc4d7d |
26-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Let's ignore MDStrings also!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74255 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9d4e200bf7e8e4e51ee56e71d5fec4551d45d605 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a note about commuting conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74241 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 151b9afdee10995add2f28790194570e7735f03c |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a note about commuting conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74241 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 1362add0c1239083388eb2b148e7c4fd68b2f781 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
These are done / no longer applicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74239 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b604b2c470aed22a5c583c05b783e61883433a84 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
These are done / no longer applicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74239 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bdd679a0936a6ccda1620e108dc260556bd2f6a0 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Mark a bunch of instructions commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74237 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 8de898abc8deb46a30973958801e9f9f4e9a7d46 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Mark a bunch of instructions commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74237 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 138f60ebbebc275e8bee2f5d916d9e6148c5bf4f |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
tst is also commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74236 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| e864b74e959c3d1135e02bbb0fc13fbea04601c3 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
tst is also commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74236 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 9b4d26fe826a4b8624471b98ce09b84fb7b2813f |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 626742231863db0e9aeef1be1fd48e9f4b7e22f8 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| dcc219682d5930b689dc349436f455165cd8fdb0 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Use MVN for ~t2_so_imm immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74223 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 0919a916bf152e08617e67f9d4b03db4769076e2 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Use MVN for ~t2_so_imm immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74223 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 8768bff8f38323e7fca82917cb9f94648423d706 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Def/Use of CPSR for Thumb-1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74219 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c9ee1189c52930812a987932874667f1e04d6715 |
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Def/Use of CPSR for Thumb-1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74219 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 230576806bf90b61d34bf0ca530fedb36c4a4d6e |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak mingw build. Patch by Viktor Kutuzov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74212 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 9e03cbefc5b3b8772a18d9bd25593ce62137ac85 |
26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak mingw build. Patch by Viktor Kutuzov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74212 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d4e2f051f0273b359564516d372459ba2602f4da |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 1e249e3705bccd20d72d9131e9f904dc10595c02 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb2.td
|
| 375a65d58f015db38ce2a8f3a32ec073ad8e43ea |
25-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 9a36bdbaf135322683f947bc8e20ce4400dc8822 |
25-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74185 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| eab41ba93e711a0a20a069a83f050cab66b1e6e8 |
25-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 74164. We'll want to use this method later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74176 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| e481f127497b20d3abe625ca4c086f85bf8b126f |
25-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 74164. We'll want to use this method later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74176 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| ab46543c1bcaa1234e186059a23c6beba77323be |
25-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused hasV6T2Ops method. We already have a separate feature to
identify Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74164 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| c9028e69f11246a051c3de1457cd89d46e82ca60 |
25-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused hasV6T2Ops method. We already have a separate feature to
identify Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74164 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| f9208f860861a4bebea88de275cb4678e0bd43ad |
25-Jun-2009 |
Douglas Gregor <doug.gregor@gmail.com> |
Add missing dependencies to the CMake build system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74161 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 4b73893d82866fc6889e550bedda0e4d76ad930a |
25-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Add missing dependencies to the CMake build system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74161 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 3d92dfddb11d077a5e1bf3b9bb1b680533a23af5 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 0aa1d8c52d34e9ba1e731a21b16606cd6f4f924a |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb2.td
|
| 10e82e3ff5f86e6c5a3a4ffc94b0104a28ea2cbc |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 add sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74156 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b6c29d55123f6b8c3f9e4d56e4be653a1fd2a472 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 add sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74156 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| ae2ed1ffa3ffb7f3dabaaedc2dd76e7da075c1d9 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Some reorg and additional comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74152 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7dcf4a826ccdf01749b31b55af15ec0ba3b4079a |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Some reorg and additional comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74152 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| f667ab41ed67fa6ed6e3be92a8720820f134f895 |
25-Jun-2009 |
Devang Patel <dpatel@apple.com> |
No need to code gen MDNodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74150 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e4c0c0fab8caadd8159f6bdd6fa03e66d4b4af9c |
25-Jun-2009 |
Devang Patel <dpatel@apple.com> |
No need to code gen MDNodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74150 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 41799700ca318d0eea5b2911588b4ef957b8fd51 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 pc relative add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| a09b9ca10fbec13e4ad47d8108e9c6f9a1b53451 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 pc relative add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMInstrThumb2.td
|
| ba83d7c950a813b2d87b386397e7e086a014acd9 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74138 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 023dd3fb0b2ea3ffd26b672829e4806a9b892b81 |
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74138 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e1225cc5cd22b797c702bcdf4663c6a7bad707b9 |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
sink dwarf finalization out of each target into AsmPrinter::doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74097 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1f522feabf25134249bc7894e04f5b89fa071b7f |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
sink dwarf finalization out of each target into AsmPrinter::doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74097 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| db191f09eb4c5cc1e8b38a377896750cc6361e83 |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74096 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0a7befa8bd56621f51eaf9196417b866962bf7b1 |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74096 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d2e271bb2000bc391c4dd6becb6961f7669ae56a |
24-Jun-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Unbreak build on Linux by removing Darwinism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74046 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b825aaa0289206a63f7e6ce7b5ca7c2d6a2c063e |
24-Jun-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Unbreak build on Linux by removing Darwinism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74046 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 66e8fae69ce44ccd486f5ba55894365700e5fa0f |
24-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Revert this accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74042 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| fd6325cbb23935a9c05b96e9bbfa978565029f2a |
24-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Revert this accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74042 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 984c78acc6fbeccf2ce9f74b66980327e6f50041 |
24-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Move the special cases for constants out of getUnknown and into
createSCEV. Also, recognize UndefValue in createSCEV.
Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74041 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6bbcba18db6d1f4bc0f0157df41cc02627bc4aa9 |
24-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Move the special cases for constants out of getUnknown and into
createSCEV. Also, recognize UndefValue in createSCEV.
Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74041 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ebbc1c43ec79857e75eb3e77cb7aff682ac5f35e |
24-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| a96751fc8ff1cc9a225ffbba73de53e2b9e1ae35 |
24-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| f09f548b55c4b3108c1932ff1f026bedf245abb1 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Test instructions operands were printed in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73990 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b8f7706911028508dc2a6c07fa185139f870c059 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Test instructions operands were printed in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73990 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| f7f986d3a839acd1b022c84707af85679c231c74 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Proper patterns for thumb2 shift and rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| a67efd12263eff2ed0f0a89ce905d59a82d0760a |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Proper patterns for thumb2 shift and rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| b219c69117c7ce88227bbf3e09ade8b39335f77e |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73986 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e870af483799beab9ec95adf89047a37e97b301a |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73986 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6fc534c8801077027c1c8337b9faefb75ca43bfb |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 09c39fcf83952bbe0a56b950f0d90ce4eac773d0 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 2aa7b9f36d68060d41c748e4950b6e76f2a69ea9 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| e499f970585c2462e2de8a38f67f6d11683a6bb0 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrThumb2.td
|
| 27c3243fd9981a6e67fa6a46dcdb382214633b99 |
23-Jun-2009 |
Douglas Gregor <doug.gregor@gmail.com> |
Eliminate object-relinking support from CMake. Fixes PR 4429 and
cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73969 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 7e9e36a23e07dfb0d7ceda3e76450073c0534f35 |
23-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Eliminate object-relinking support from CMake. Fixes PR 4429 and
cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73969 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 3620db86afd453bf60106e0fc31c5c24736383bf |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Obvious typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73967 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 83a2129332250af4648e0501f93cabfa8873e1f4 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Obvious typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73967 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3617371c673a860250a1936b9428babad9a68bef |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| f49810c7e60807c43a68ab02c936a4ee77a4d2cf |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMInstrFormats.td
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| a1366cd674889b0aea4c9388ee285d1f3d591f91 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Minor reorg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73948 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e07715cfba5528dfa368b25d484602ca2b0e1892 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Minor reorg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73948 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 42e6ce94dab7c255ba25ccd30cb89cb2e3cc3d3b |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Replace isTwoAddress with operand constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73947 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 3850a6ae9d1c5f38c94c89237ce87d4270dcac64 |
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Replace isTwoAddress with operand constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73947 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| e60fee02ce7c1ee34faeefde46229b4168c2fd7f |
23-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrNEON.td
RMRegisterInfo.td
smPrinter/ARMAsmPrinter.cpp
EADME.txt
|
| 5bafff36c798608a189c517d37527e4a38863071 |
23-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrFormats.td
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrNEON.td
RMRegisterInfo.td
smPrinter/ARMAsmPrinter.cpp
EADME.txt
|
| 74590a0a7f719a8374872bc555b03a9143f65443 |
23-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add explicit types for shift count constants. This is in preparation for
another change that makes the types ambiguous (at least as far as tablegen
is concerned).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73909 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 1c76d0ee5cda2119c679bab49520dd9cd435ded5 |
23-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add explicit types for shift count constants. This is in preparation for
another change that makes the types ambiguous (at least as far as tablegen
is concerned).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73909 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 801d50befbb28a7151ce1d200e67636fe8268ba0 |
22-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking
for "thumb" and add a check for V6T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73905 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 9170ab6685fcd820c6274e761b8c3a71f25ae074 |
22-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking
for "thumb" and add a check for V6T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73905 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 243b37c26911d4ea493101d3d9a460db7579bd05 |
22-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
For Darwin on ARMv6 and newer, make register r9 available for use as a
caller-saved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.cpp
RMRegisterInfo.td
RMSubtarget.cpp
|
| 54fc124d72512d65d62565cabcd85c7b07496513 |
22-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
For Darwin on ARMv6 and newer, make register r9 available for use as a
caller-saved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.cpp
RMRegisterInfo.td
RMSubtarget.cpp
|
| 74bba87fe677622edba81ae3231d16071854619e |
22-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
hasFP should return true if frame address is taken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 8dcbbdd00ebb4beb8eeb822791df326eee5de827 |
22-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
hasFP should return true if frame address is taken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 3c567d63e688faf9f70111311e1c1acd93465b76 |
22-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73887 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e64e3cf9adb18c9c6711e69e975d098a513ee8f8 |
22-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73887 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 0e6763cfe1afd830c1cd2adbaf99557bdabf6c54 |
20-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Remove unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73815 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e9fe6c7729c0637acadd7564ae8d14c5c9300f89 |
20-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Remove unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73815 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| bd9ea5513cb6be8c2c365605414bdfcafee969be |
20-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable arm pre-allocation load / store multiple optimization pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
|
| ae69a2a12bd0af3fa81957f7896d1a54ad69dbb2 |
20-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable arm pre-allocation load / store multiple optimization pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
|
| 1a45484151060a9c0190e5d1674709eab72cbd14 |
19-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Move up dwarf writer initialization in common AsmPrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73784 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 14a55d952cf238fff42da53a75f39cf06dab184b |
19-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Move up dwarf writer initialization in common AsmPrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73784 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 58f4ce8c91489e13606982c68ec7e6329d91d039 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73761 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b1019480b6806c38432ad3357ae7d756573c0835 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73761 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 16b15c33f9b0d2ce9b0fd301031efc10fecb47b7 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73759 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 7a42b08be8836149ea4e3f95ddcc42e198561df3 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73759 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e00db516add6190879718cee2dc7f822cc9bcafb |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73749 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 974fe5d69187bdf33b0e111ff72e965431df4191 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73749 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 88e78d20071803092fbe0fa7ef085690784bc8f0 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMSchedule.td
RMScheduleV6.td
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| 8557c2bcb8002169d890eb8485e9a1d7219e4343 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMISelLowering.cpp
RMInstrInfo.td
RMSchedule.td
RMScheduleV6.td
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| 2e051ed7b5b9dab4ee28fb67af641e6df9024bc6 |
19-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Mark a few Thumb instructions commutable; just happened to spot this
while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 6b7bb42c365e9b11eda2df67aa5da6aad7632356 |
19-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Mark a few Thumb instructions commutable; just happened to spot this
while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| ca072176f432533f61e4f25165643799f235a362 |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 4e0f25b603c96ce43474441e99252c5cd88c2e2e |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 690b02cc2be75f878ab189295690484f25e98b26 |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| a93ca92379129e87e0130609ac78422fcf6dd21e |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| ecbf73b8ff55100f416aabbb19000b7e5f647b5a |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| b839c3f577e03467bce8904eb2a02b124ec19ec8 |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 9ecae170da642c925fd00f795c9808f2b59640fd |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove UseThumbBacktraces. Just check if subtarget is darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMRegisterInfo.cpp
RMRegisterInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| cd828618b8c6ec58df94aec0f5546f009f2fd0d5 |
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove UseThumbBacktraces. Just check if subtarget is darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMRegisterInfo.cpp
RMRegisterInfo.td
RMSubtarget.cpp
RMSubtarget.h
|
| ccca6f7493b4a8db815cc2746ea50152ddc97c25 |
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| b13bafe5c12dd908b55c559c93adaeb1627ed096 |
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| a3cc1a05c52f029d479ae8379725d199ac2162d5 |
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4 |
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| d7afe4f50ebbf088a87d620301106f599317b511 |
18-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
ARM unified syntax is not specific to ELF; use it for Darwin, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73665 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ff6de365583858f228d07165f5fa7675880e40f4 |
18-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
ARM unified syntax is not specific to ELF; use it for Darwin, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73665 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8b20dabd9924809997e2e10d9acfbffcf8c9c62c |
18-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix asm string from MOVi16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 7c4f7dd43a84b233f94a1fe44faff42ac46b906d |
18-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix asm string from MOVi16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb2.td
|
| 9a2d230f869e8365581358a03a83f028da6f5ef1 |
18-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Thumb2 instructions are enabled only in unified assembler mode.
Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73660 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d61eca533081580d56fabee38f86507d8019ca75 |
18-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Thumb2 instructions are enabled only in unified assembler mode.
Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73660 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ac869fc112b661f59a05ad427f7c4b81e10c7aed |
17-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 52237119a9b41d6d714c96e730d651300b171298 |
17-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb2.td
smPrinter/ARMAsmPrinter.cpp
|
| 1dc5ff4afef80793dca08f72ae4a54703e9d21b5 |
16-Jun-2009 |
Douglas Gregor <doug.gregor@gmail.com> |
Introduce new headers whose inclusion forces linking and
initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73543 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 1555a23335400143f2b54a66aedc4b5cbbb79f8d |
16-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Introduce new headers whose inclusion forces linking and
initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73543 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 1395c2ca582e562e06227a76f07f0c47cf2447ea |
16-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Address review comments: add 3 ARM calling conventions.
Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73530 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| 385f5a99ecc7fee48a7539bc63d3e1d3b5089c0d |
16-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Address review comments: add 3 ARM calling conventions.
Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73530 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| c96184ada49f4f8329506634d267a5ddd70a5d41 |
16-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
GNU as refuses to assemble "pop {}" instruction. Do not emit such
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 29327953097693a0376eaca021046d99c01f9f89 |
16-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
GNU as refuses to assemble "pop {}" instruction. Do not emit such
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| f94f1a9d7526306d3e8dc933c3e367701dd05776 |
16-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
On Darwin, frame pointer r7 is never available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73434 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 88cc7c419401b32b15e7af4038c67e2a81aac55a |
16-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
On Darwin, frame pointer r7 is never available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73434 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| cba026939bcd05dd9ca7b0c9bf44e3ab9c1b09f7 |
15-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename methods for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSubtarget.h
|
| bb6296234238aab74a531b382d92342269bea902 |
15-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename methods for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMSubtarget.h
|
| 7a8393000a5c54eb17f74eeeb0bf43c9ee0a98a0 |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73422 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 675860758ec8926f9803840615366931aca7f8d8 |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73422 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| f746f6a9438bcbf50dd887139eef949f729a6d6e |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73413 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| d780f357941fc587d36d141bab3d78d6ff972dd4 |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73413 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 2108cdf3c64fa7c1db1ca06f96513e6010f66f7d |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Silence a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 7f044287388843d1c094a3c0b8beef47ea403ef6 |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Silence a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 41169551d59e9aee3d9dcd043013d65ee6e33759 |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 358dec51804ee52e47ea3a47c9248086e458ad7c |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 54353c9810ad1b79cf9dc865277f16a750abc079 |
13-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| e7d6df73530a98a5cc5f69ddfd17073b464caa57 |
13-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMLoadStoreOptimizer.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| d97d714f5b5046ea448e7688705db449c8b54536 |
12-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Mark some pattern-less instructions as neverHasSideEffects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| cd799b99cb4a4d7e8f7de59fd9c936812193c9b7 |
12-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Mark some pattern-less instructions as neverHasSideEffects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| c918cc8d280ed65c802265ab2f464649f954d1a5 |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73098 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 2e7ccfce98b925d07788fdd08cccc9ddb3d7004b |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73098 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 1bcd02013b55f0f3756a9fc3bf0b5cc61c19b83b |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert hunk commited by accident
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73097 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| dada95b5b3acbce56440124c242673f30f596f92 |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert hunk commited by accident
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73097 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1171332df0084b39e1b0a84bca73cdc3fcc2c9dc |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMRegisterInfo.td
RMSubtarget.cpp
|
| 0eebf653a7b2978e7761f8d068b6fbec22aea0f6 |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMRegisterInfo.td
RMSubtarget.cpp
|
| 48000e9d644024893c2054ea70429ddd82ea6b79 |
08-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Separate V6 from V6T2 since the latter has some extra nice instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| fbbf1eeccf0cf469f0d8962b1341c8ba22a9dadb |
08-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Separate V6 from V6T2 since the latter has some extra nice instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.h
|
| 9f2fe507257080a9cb8c63a5daba93ff850e4b1d |
08-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add helper for checking of Thumb1 mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73080 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| a7b0ded2a26003d91db6c58d6ad945a39f70585c |
08-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add helper for checking of Thumb1 mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73080 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.h
|
| 54eb122908fc4476bdf45267d552dac1685a43ee |
06-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
|
| 2392efef1bd2599231ab659dd6ba4233bf5df94c |
06-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
|
| 72d2b91bbd0544502b34eb6c2ce9c2ce354932db |
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMRegisterInfo.td
|
| 925492279ae7d93180ebdd689c87cd58522e68f5 |
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
RMRegisterInfo.td
|
| 256a2cb0cac9e5b1fdb3152243f62e4217beda06 |
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
When merging multiple load / store instructions. Use the DebugLoc of the first one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72952 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 87d59e49e9008767896c4c8c80efdc172f1cbd18 |
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
When merging multiple load / store instructions. Use the DebugLoc of the first one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72952 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 5e7d703117e916329e79f371c74460e7b12c67d7 |
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up: return vector by reference rather than by value. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72950 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 5ba71887f918a9da82140210494608df020dcbd5 |
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up: return vector by reference rather than by value. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72950 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 27c2daf02027f431d63995f947294e71b9ba384b |
05-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Remove some unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72948 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| c965ee223c6077250525048106726e12b59072ac |
05-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Remove some unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72948 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
|
| 5cfbcfafcdc536efed5108f56fd5c4ade008b465 |
04-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 1488326156741063fa7a23e1638c13e81d167e22 |
04-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 30551696e8b15251d9b159ffab330a5e14a099b8 |
03-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily revert 72756 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 70fd60bd57250799672378fa2f7c5e804cb3d98d |
03-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily revert 72756 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 68772026f92143a74a2c9a1ea8dbdf5e27facb45 |
03-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fold preceding / trailing base inc / dec into the single load / store as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 9d5fb981b0ebc00e068b9bcb4df7388a8ea94b71 |
03-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fold preceding / trailing base inc / dec into the single load / store as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| e7540d6486731a8c0336ff794f5bbce21e386a64 |
01-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement review feedback. Make thumb2 'normal' subtarget feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 70459bef9ccd73b3a2a44fdd62f2509861112745 |
01-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement review feedback. Make thumb2 'normal' subtarget feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 8e2537be2325a9a04eb61220329581f0f6805e79 |
01-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
|
| 434dd4fd94f5f248492c675e4285e7d67342d4c4 |
01-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
|
| 845290803be4879599bb9a9ec8617d7ad17be326 |
01-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not emit "generic" CPU string. This fixes PR4291.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72696 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d260c248abd57763aaeeadcab4155655a25d9e97 |
01-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not emit "generic" CPU string. This fixes PR4291.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72696 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1ea31ff434f7966f3d8b2c158b4f20950e94e80d |
30-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| a3f99f90338d89354384ca25f53ca4450a1a9d18 |
30-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| c19467424889a76b42eb17134180e42ff528c55b |
30-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Untabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 51b16f473759c1546acbf308a5d3f3e7bf3ea23c |
30-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Untabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| f2e14756aa488fb1b09eb78ffe0055db6581dd5f |
30-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add placeholder for thumb2 stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| d4022c3fbb0705abdc8eddc3ee4a5059f5ef8094 |
30-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add placeholder for thumb2 stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMInstrInfo.td
RMInstrThumb2.td
RMSubtarget.cpp
RMSubtarget.h
|
| 1c718b89ab6c367c2ad96c750af197ef769edcff |
25-May-2009 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72395 91177308-0d34-0410-b5e6-96231b3b80d8
RMBuildAttrs.h
|
| 0c85aabfdcfa966c0c348242bad9a7c5fa2f8a14 |
25-May-2009 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72395 91177308-0d34-0410-b5e6-96231b3b80d8
RMBuildAttrs.h
|
| 1bf0f08cf82ea6414cec0a8d043765cb4be3b122 |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| 6d7d2aa38a247426e2ccf53e3c6ad0315c9a4d8c |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMSubtarget.cpp
RMSubtarget.h
|
| a229f0b618bc12edf071c9cd647792b92921b0ea |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit ARM Build Attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
RMBuildAttrs.h
smPrinter/ARMAsmPrinter.cpp
|
| 88ce667003a33e008d9ecc6811584681787e8150 |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit ARM Build Attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
RMBuildAttrs.h
smPrinter/ARMAsmPrinter.cpp
|
| 7357d8f48490c42cf6237c3a8f982a36258248db |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 41a024385f1220eadc48b48cb4c044a5fbc1b361 |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 7518879697bee64c8ce35c3f41e781f5858285be |
22-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
for ARM. This fixes rdar://6908807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2f95461ee2edf896ef4a45dff40b9f20bcb31de3 |
22-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
for ARM. This fixes rdar://6908807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 896bfc33b96d8c39731c49e60f1311588866926f |
20-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Minor formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72172 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 261f2a2337990bc7cc3d9e20d3338de54b26c74c |
20-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Minor formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72172 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| bc2f9e7df85c7799c9547f5c5b7a8e9ccf4b236f |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4227: Handle large immediate values in inline assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72138 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 6aa219a18c59a9bc0b1eeb6eece09cfabaaefabe |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4227: Handle large immediate values in inline assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72138 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3b2f1927e7e8d03cbc5d0f2b1115815d94218838 |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Follow up on new support for memory operands in ARM inline assembly.
This fixes pr4233.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72115 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 86c212e8945410c34455619a58b15a9e02ec8e0d |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Follow up on new support for memory operands in ARM inline assembly.
This fixes pr4233.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72115 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| fff795c3acbb0b71459ad9aa98f69681f60cda4e |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
the stack. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 04746eae49f1cc28e787b67256a37bf91481bb90 |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
the stack. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 6c982bbaee6f1e404b918283b57baa256f38686a |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 224c244f56025c10e70e4204daceadfb3cdd2c06 |
19-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 6c05eb4c467ec827ca4604fbbf7442e1769664f2 |
18-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e6abdffe06d293b68c498251b5dc9f5dba78dece |
18-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4a9025e422ed25ab99710c550b00e7f141b9febf |
14-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Update the names of the exception handling sjlj instrinsics to
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.td
|
| f95701286664df01a5683a71c9a02c056fed0aa7 |
14-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Update the names of the exception handling sjlj instrinsics to
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.td
|
| d4895b6f4393d30b3e1decd4a2ea87753e0a5030 |
14-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71735 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 6aa7197fb5aa478a5c813d41a11689bb6d8f7abc |
14-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71735 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 79566823f83e7dc1719c5212404acf8995c1c4a0 |
13-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6ebf7bc7405ee79d27d50b70f0c1a474cbea820d |
13-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2b739762c5444433753e4d3a141ff20f40636611 |
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| c10915b85165887e1886179338c7d14925f95c52 |
13-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71610 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.td
|
| 0e0da734bbdfa1d3f55cd04db31d83b97e4556f7 |
13-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71610 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.td
|
| bd8b68ef67b4335d5fbab67af45b7d2ad9be9a3b |
13-May-2009 |
Jim Grosbach <grosbach@apple.com> |
correct register class for tADDspi to GPR since the register will always be SP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71602 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c93f96187459b1f09b328e3cf6eade173909ce53 |
13-May-2009 |
Jim Grosbach <grosbach@apple.com> |
correct register class for tADDspi to GPR since the register will always be SP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71602 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| d6985d51e8edb7b609071e3fc1bfdb6ec302be67 |
12-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up a few minor typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71563 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 39bf051ec2865cd715c41473d2a9fc34ff252534 |
12-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up a few minor typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71563 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ec92b49890412c2de9c0eca5a3d1492b596d8922 |
12-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix 80-col violations and remove trailing whitespace. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71562 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 8494526a2396fd9cde027ab6ae11dd28b54ac90e |
12-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix 80-col violations and remove trailing whitespace. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71562 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ec4f97dd91023f63e05e94a333cdd2d4c57efedf |
09-May-2009 |
Duncan Sands <baldrick@free.fr> |
Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 777d2306b36816a53bc1ae1244c0dc7d998ae691 |
09-May-2009 |
Duncan Sands <baldrick@free.fr> |
Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 98a366d547772010e94609e4584489b3e5ce0043 |
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 5ed22ac54c2530a1d0d140d259f881f3b2040e56 |
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b |
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 58ed5d27258df9688ac2694cf5e3d31f7dbdeef6 |
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| c69d56f1154342a57c9bdd4c17a10333e3520127 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| f4d0c73cc3d9ae305b162f336dc14fbe7972e2e8 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 2e9d5f912a9841d3685ba0241abe1131943fed29 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 11a01bfa097cfe006de022154709b545ee125523 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 8091524d98ca648c195224fab599f1c6afdd880a |
25-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change LowerCallResult method so that CCValAssign::BCvt can be used with
f64 types. This is not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70006 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b5eefaae2badd23836f67b2e3b33ac6c892e57ff |
25-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change LowerCallResult method so that CCValAssign::BCvt can be used with
f64 types. This is not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70006 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d55bd51f311fb00c639da6161584b06cf7cb5e27 |
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69978 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 35f652a919369ea801dd10f8fb6c1c99ba7620eb |
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69978 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4d59e1d666d3187aff11c9b11fe8a9eccade3f26 |
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69977 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 99194c9d87ec8d0cdba4b668969f9eda092accc8 |
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69977 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1c2c462d0f993e3575888d5825b9c25348e6e4e8 |
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unnecessary references to f32 types. After specifying that f32
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69973 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| db994cc3a132e6c9d544dc0c163d0749b169023e |
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unnecessary references to f32 types. After specifying that f32
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69973 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
|
| 998e125a87d49f28c714d8223a37746850401057 |
20-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b6737aa5c91184d77e9569d5fe829674a358b90d |
20-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e3fa9ef936068ab395e9c68062cfcae2d0321208 |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move the AddLiveIn function definition closer to its uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69382 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6c8ca7ebbd7aa97ce4ef26ec2fe9b9b30bfcb47d |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move the AddLiveIn function definition closer to its uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69382 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e65586b37b141cd3ef1515b840d6397ecda12396 |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rearrange code to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9bd06cf878a03ac3b7d4aa9324b3c9c800f2896c |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rearrange code to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dee46d7f6d61ca628725b54c2d24154ebe70ed96 |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up formatting, remove trailing whitespace, fix comment typos and
punctuation. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69378 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| 7cd865e7fa66c2d2ea8ad92f0cc5839bd204d50b |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up formatting, remove trailing whitespace, fix comment typos and
punctuation. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69378 91177308-0d34-0410-b5e6-96231b3b80d8
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
|
| 1f595bb42950088ccb8246e6b065a96027b46ec6 |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
MakeLists.txt
akefile
|
| fd4511769b8f5170ef89d39b7a3c3f6a1d5d305b |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCallingConv.td
RMISelLowering.cpp
RMISelLowering.h
MakeLists.txt
akefile
|
| 2c7dab18648f3d0d6e9373de31065ec3c896c224 |
08-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix PR3795: Apply Dan's suggested fix for
ARMTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68619 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e69efe6fd7ef36ef7b0b72bc311c17367cfbdf23 |
08-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix PR3795: Apply Dan's suggested fix for
ARMTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68619 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 30eae3c02244e18747f9f0dca6946d86d0ccb7f5 |
07-Apr-2009 |
Jim Grosbach <grosbach@apple.com> |
PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMInstrThumb.td
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
|
| 0e4e974119676cf4c46b4fd0b6a29e85c3be562e |
07-Apr-2009 |
Jim Grosbach <grosbach@apple.com> |
PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMInstrThumb.td
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
|
| 8f3434647d3d39b49475239e3be1b8afb06415cf |
06-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle 'a' modifier in ARM inline assembly.
Patch by Richard Pennington.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 5260c4c74326dd6228eaff73d1e634e228ee9f4f |
06-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle 'a' modifier in ARM inline assembly.
Patch by Richard Pennington.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| eec4b2d73061ae87d0a4334a22d9f2a588736071 |
03-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Wrap some lines to fix indentation problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68405 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| c3020a8123aeff760cd7bb0bd6167879dd7be404 |
03-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Wrap some lines to fix indentation problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68405 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 1b46a680151ef85ba13bd9df01f995be8c46964e |
03-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68404 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| ab588a132ffea11835b45631aec173569c97f6da |
03-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68404 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| bf6396bed0597238110aad5b680fd18a4f8769fa |
01-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 221511dcd269d1f619d0004aa7163e9136cfa086 |
01-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d83712ad678ae453f3342762c78142f851d3a2d3 |
30-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68050 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 8fc67d44d18770ca1ff018e3c6ba36c12fa0685d |
30-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68050 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
|
| 0ede14f5c0d9ff8bd30b467367eabad881fa6898 |
28-Mar-2009 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 7ea5276d451c424d65d4a4d1fe296bba1eb25c73 |
28-Mar-2009 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 9d7b5309c267048114f1438ec0366923c99ca34d |
26-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67765 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d9f92ba189b88aac3d6c837ac80de08ce12010f6 |
26-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67765 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 42bf74be1402df7409efbea089310d4c276fde37 |
25-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 42ceb47150b2d423f9668c7b128b90927ac22cb0 |
25-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| f1c0ae9de5365a578fbdfebe4625fb281b0be592 |
24-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not emit comments unless -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 11db8142e9de9bec53cf8dda1a2ac5eb85796805 |
24-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not emit comments unless -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 2a14c521cab397531862415378b67fb3ac00d053 |
21-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a few more indentation problems and an 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 45f01d9b95edc80d99c4434af28ab2e447bd75f8 |
21-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a few more indentation problems and an 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2dc4f54324a65665aed78840bc9d6d5ea5d6e7d1 |
20-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
No functional changes. Fix indentation and whitespace only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0eb45b4752dd98edf1188ef0fe08c647e85d685a |
20-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
No functional changes. Fix indentation and whitespace only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1606e8e4cd937e6de6681f686c266cf61722d972 |
13-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.
Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
|
| 68c1868c4bdc04cd319ea92662aa5aaccf6ac378 |
13-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.
Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
|
| d1980a5acd8509ea34ee2dec5e13de5dbe16af2d |
12-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend. These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).
Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently
with the recently added cp constant select optimization, but is a
very general xform. For example, we now compile the second example
in const-select.ll to:
_test:
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
seta %al
movzbl %al, %eax
movl 4(%esp), %ecx
movsbl (%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal 4(%eax), %ecx
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
cmovbe %eax, %ecx
movsbl (%ecx), %eax
ret
This passes multisource and dejagnu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e4577dcdb3554eb8306dff4731eda1fd695eee4b |
12-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend. These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).
Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently
with the recently added cp constant select optimization, but is a
very general xform. For example, we now compile the second example
in const-select.ll to:
_test:
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
seta %al
movzbl %al, %eax
movl 4(%esp), %ecx
movsbl (%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal 4(%eax), %ecx
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
cmovbe %eax, %ecx
movsbl (%ecx), %eax
ret
This passes multisource and dejagnu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4dc2b39bf89d7c87868008ef8a0f807e0419aca6 |
11-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
It makes no sense to have a ODR version of common
linkage, so remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| b95df796a8a89e5817148cf229fb0152bff9d105 |
11-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
It makes no sense to have a ODR version of common
linkage, so remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| eda2ec35a14df50590f4b0b15f4b85be8d4ed5a1 |
11-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66660 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 13b25fce1fc6de85fbd6d185f8765685e57d9eae |
11-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66660 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 8c6b991635ff589fbe4b8db013bcc1d2ef57a0e0 |
09-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66435 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMTargetMachine.cpp
|
| a5de2fc079f65072277595a7a6e763762081a124 |
09-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66435 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMTargetMachine.cpp
|
| 6501153fc036741a90c616083014b0f8499678fb |
09-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b882875fb6e003d7915f1d5e40741408d0f408b3 |
09-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4b1747430a2d67702958b95d6776396734f184a0 |
08-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| ac1f779b964db12a88ec961867227a61dcc84e12 |
08-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
|
| 667d4b8de6dea70195ff12ef39a4deebffa2f5c7 |
07-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 19d161f714b83cd850fe489aa3fdaa3d3744157b |
07-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 0f8b53f19d29013ab18f3d444cea1e6305405611 |
03-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8387bb3116c16ebf4fd05c5aaa770e3eb243fc61 |
03-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 57f0db833dc30404f1f5d28b23df326e520698ec |
24-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 4f40531823c2b995149ff3a1b721171ad6942363 |
24-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| ef4cfc749a61d0d0252196c957697436ba7ec068 |
23-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Propagate debug loc info through prologue/epilogue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65298 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c036181790b81f9efd806e8b7f37be6af4628a4a |
23-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Propagate debug loc info through prologue/epilogue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65298 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 97357614b5957cc167c261d3be54713802715d9a |
18-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| c909bbb96eafd7bfaf25f6003533c8013526a818 |
18-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| caa0c2caddcfb56de09e016c4c153d0609ffcf6e |
18-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cf84b146984fd7d184efd6548ee91994454ee82d |
18-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 8a43d98644e4c847cdef88c9658a4d821cc72473 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
and one more file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64430 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 36fa7305436a97fd011d3092edc0a8dea4a152a7 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
and one more file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64430 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| b67284057ee130114055309eabe0bcd1af13777d |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc versions of BuildMI from ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.h
|
| e8a10c4ffd228e06a5f6955f3cb9b15e07afe729 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc versions of BuildMI from ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.h
|
| 21b5541814d57d0a31f353948e4e933dbb1af6a4 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 77cce4dd56feafc2e97407f17827384fdd018a14 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 8c4d1b2bcfa63d064a7bcbd9cd23ebe3b282f853 |
12-Feb-2009 |
Chris Lattner <sabre@nondot.org> |
fix PR3538 for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64384 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a1bd6f0aed4c2491ad29b965dbb9c8b54bce4054 |
12-Feb-2009 |
Chris Lattner <sabre@nondot.org> |
fix PR3538 for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64384 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d1c321a89ab999b9bb602b0f398ecd4c2022262c |
12-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 5b8a97b83826d1f4bc64c7b26cca787ac857cc60 |
12-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| eac316468ad31a7bf286528ff9970c5794ba8539 |
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 96d60921d8568680bad2788b80a163fecb1dbdbe |
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b300d2aa3ef08b5074449e2c05804717f488f4e4 |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 24dd9a56e50b4c931ae96a93e67c4ed85e65d989 |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e8d7230f480654cdb8ff1c3d0a38e1e9ab0bd55f |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9bfc017ed383685dbc2f7db5b7f79763057effea |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| de06470330260f5937e7ca558f5f5b3e171f2ee5 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 175fdefc4fe809d3d58c98a8172e63696e0e79e0 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f5f5dce897269885754fc79adeb809194da52942 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate remaining non-DebugLoc version of getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5d398a378ab7be40fc3ea01e846f33b3dc83e265 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate remaining non-DebugLoc version of getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| afca4630b4689e3fd3997682add43f86a6e67a5c |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| f90b2a7742ddeddc448586cc050818a664419e74 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
get rid of some non-DebugLoc getTargetNode variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63909 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b556ed0ac5ed6d7514adaaeafaefec51840d6458 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
get rid of some non-DebugLoc getTargetNode variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63909 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 913ba76a560da1419879168a4a61e0739d636b18 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b3379fbc604cc9e11b8b7fcd1ecb09a40a886697 |
05-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
A few more isAsCheapAsAMove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63852 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bd0ca9c95cb9915cb59bbf507d00169cc42258a5 |
05-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
A few more isAsCheapAsAMove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63852 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b03cc3f88f4585859ea7031f5c5bbecb64202f96 |
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ea99692c6c7dac4b4280286323c548c778de9993 |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0f502f6f44f2756f5cb7b17d8f1d8eae000d51b4 |
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Add some DL propagation to places that didn't
have it yet. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 7f2abf4d0113aca037317ea1d1674ee00f3b1f84 |
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Add some DL propagation to places that didn't
have it yet. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 9bc96a57206cbebaa9b0ba9979f949eb10c1592c |
03-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Create DebugLoc information in FastISel. Several temporary methods were
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63584 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 5aa0ddb0f8b15d4d0f3e6385908593e977360812 |
03-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Create DebugLoc information in FastISel. Several temporary methods were
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63584 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 7d2ad624fa749a6d3edac0d94e9c107989c16304 |
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ca6237b16a68ff5256d47b79908cc3a3a4b61889 |
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1465d61bdd36cfd6021036a527895f0dd358e97d |
28-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getAnalysisToUpdate to getAnalysisIfAvailable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63198 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4e0d6a7d48464188a1a25b544a6355326d3fd3bf |
28-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getAnalysisToUpdate to getAnalysisIfAvailable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63198 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d1e7d9a88b5f4fa5e9a85affc4599c650c591ffb |
28-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Suppress a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63161 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1036173a7c9f1ebed9d2c21126e24df2eb83e09c |
28-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Suppress a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63161 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 4469c53cfc60e011d26f88594f7a690895f7f526 |
26-Jan-2009 |
Chris Lattner <sabre@nondot.org> |
silence a warning when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62976 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b195d3489b7324ea93999cd24437ff6360aae244 |
26-Jan-2009 |
lattner <lattner@91177308-0d34-0410-b5e6-96231b3b80d8> |
silence a warning when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62976 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| f97496a054876b3bb9c0acf424379eb2f48377ce |
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| bdfc582edfccb948b563677e2d82fee5f0ba96f6 |
16-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARMCompilationCallback should not save / restore vfp registers if vfp is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62299 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 643484ec3ec819eccc87f9bf4ec3ab7ee7fce7cc |
16-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARMCompilationCallback should not save / restore vfp registers if vfp is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62299 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| bb46f52027416598a662dc1c58f48d9d56b1a65b |
15-Jan-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| a168fc98dedfc8cac01c34f84b699fe5f48ad76d |
15-Jan-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 96eb47aa1be2f07003241a148e7b7db87bfa9104 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 73e0914848662404cf2aa18eb049ff5aae543388 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b9e1026824b2153acd295edf5cd715bf31b5c226 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ceb4d1aecb9deffe59b3dcdc9a783ffde8477be9 |
12-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
smPrinter/ARMAsmPrinter.cpp
|
| d68f13bf716faa496767a21140fab558adddc19a |
12-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 9b8f542e2746b28721b3ec603c3aaaa10ea708fc |
09-Jan-2009 |
Misha Brukman <brukman+llvm@gmail.com> |
Removed trailing whitespace from Makefiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61991 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
|
| e025bcca322301af5c4a5178b1a64080cb900ec1 |
09-Jan-2009 |
Misha Brukman <brukman+llvm@gmail.com> |
Removed trailing whitespace from Makefiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61991 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
|
| eb3fc289141ad44883acbb91e839ab1b9a0f2025 |
09-Jan-2009 |
Devang Patel <dpatel@apple.com> |
Convert DwarfWriter into a pass.
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61955 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| aa1e84356d47c78a270b0ebceb434a401e59a5b5 |
09-Jan-2009 |
Devang Patel <dpatel@apple.com> |
Convert DwarfWriter into a pass.
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61955 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMConstantPoolValue.h
|
| c24a3f87f866e96b2a9ad691c78113651eaa77d1 |
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMConstantPoolValue.h
|
| 38b6fd67a6c4151ff56414cc3be5092bd7a2ddd8 |
11-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a 80 col. violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60901 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 7416593009a045231c7f2689b4e863d65f502ec0 |
11-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a 80 col. violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60901 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| e5ad88e97fea74dd55675fa3ded89f01fb18f363 |
10-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Preliminary ARM debug support based on patch by Mikael of FlexyCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60851 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMRegisterInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| e4428082555be131bde68c424beeb6643ebf88a2 |
10-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Preliminary ARM debug support based on patch by Mikael of FlexyCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60851 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMRegisterInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 5788d1a169db3346a612a13113348d2709bdd15b |
10-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60828 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 6e561c71f74571ff2a448e7e07cb74047edef776 |
10-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60828 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| c3ccc1aaaf8a58a70d68d947e3b769b727d4e64f |
06-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Clean up some ARM GV asm printing out; minor fixes to match what gcc does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60621 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| 43f73c6bd106fc8b6f63cb6908d0b1aec615631b |
06-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Clean up some ARM GV asm printing out; minor fixes to match what gcc does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60621 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| ae94e594164b193236002516970aeec4c4574768 |
05-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60571 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| a65854f8c54ecbf787262221338a7cffd8e3e771 |
05-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60571 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
smPrinter/ARMAsmPrinter.cpp
|
| a8103dad4e84e031c5845e18268655cc0bfbdb8d |
04-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r60519. It was causing a bootstrap failure:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT barrier.lo -MD -MP -MF .deps/barrier.Tpo -c ../../../llvm-gcc.src/libgomp/barrier.c -fno-common -DPIC -o .libs/barrier.o
checking for sys/file.h... /var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
/var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:symbol: "_gomp_tls_key" can't be undefined in a subtraction expression
make[4]: *** [barrier.lo] Error 1
make[4]: *** Waiting for unfinished jobs....
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT alloc.lo -MD -MP -MF .deps/alloc.Tpo -c ../../../llvm-gcc.src/libgomp/alloc.c -o alloc.o >/dev/null 2>&1
yes
checking for sys/param.h... make[3]: *** [all-recursive] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libgomp] Error 2
make[1]: *** Waiting for unfinished jobs....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60527 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fa13d340473e77fdedb726ff855c1da207db0d20 |
04-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r60519. It was causing a bootstrap failure:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT barrier.lo -MD -MP -MF .deps/barrier.Tpo -c ../../../llvm-gcc.src/libgomp/barrier.c -fno-common -DPIC -o .libs/barrier.o
checking for sys/file.h... /var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
/var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:symbol: "_gomp_tls_key" can't be undefined in a subtraction expression
make[4]: *** [barrier.lo] Error 1
make[4]: *** Waiting for unfinished jobs....
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT alloc.lo -MD -MP -MF .deps/alloc.Tpo -c ../../../llvm-gcc.src/libgomp/alloc.c -o alloc.o >/dev/null 2>&1
yes
checking for sys/param.h... make[3]: *** [all-recursive] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libgomp] Error 2
make[1]: *** Waiting for unfinished jobs....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60527 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| eb83dfde66b4614fe48a572ea2ee1d7b91bcbc19 |
04-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Visibility hidden GVs do not require extra load of symbol address from the GOT or non-lazy-ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60519 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3fe20f9fdf2fd756d7ea7186f1b21a67c5cc8bbc |
04-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Visibility hidden GVs do not require extra load of symbol address from the GOT or non-lazy-ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60519 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c54baa2d43730f1804acfb4f4e738fba72f966bd |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| edc83d6ec19f32ce2a3ea11109674d5370815d8c |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 15511cf1660cfd6bb8b8e8fca2db9450f50430ee |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 5574cc7ede8b35672892ed36be37cd81555857ff |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| f033b5a393c1f0af68a2e93ef73bf0a3d788ae6e |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Update a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5c49fdeed5dce037668a62d7a2665be39857f2e4 |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Update a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 952b839ce9bc0c6d605d8b202c9cd76f7f05a77d |
03-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3140.
Print a single parameter .file directive if we have an ELF target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60480 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 5cf2e553e3a6376051ae18f4eccd605a5703b8cd |
03-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3140.
Print a single parameter .file directive if we have an ELF target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60480 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 41474baac839da410302950305722cb0e026a094 |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| bc1714f32f95112cab85906a3a8c4057546b84d6 |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c70f3295438488e1e34eb212d1f8ec55bbf43935 |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix a missing #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60458 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 8d6ca9bfb5580426590f6628b83279de503a3238 |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix a missing #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60458 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| aaffa05d0a652dd3eae76a941d02d6b0469fa821 |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 42d7bb80eff3a86ca5790d950c399d294b6f9b0e |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 7d9834be329543d61f747af9b48be539492d8974 |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 027fdbe3ba6762b9867c6f891d64f76b7d6a4557 |
24-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 301aaf5364b0e64e779165ec12b217c546a1506e |
24-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 7751ad92daeea5a3502fbc266ae814baec5c03e6 |
22-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make a convenient helper for printing offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59872 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/Makefile
|
| 440f23db20a6c802d407e4f92a541648aaa6d492 |
22-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make a convenient helper for printing offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59872 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
smPrinter/Makefile
|
| 97c573d5de4f729f9b3a5db59c6daa3a6fc7efe4 |
20-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59696 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 63143d7c25ec5d55a87eee12518f849f8e9c6856 |
20-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59696 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| e3066abfcf3b34ef6ff84e851d08f6db35908ac9 |
20-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59678 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 0f6a5612ac72664b641b39ffd17ae3df07ef432a |
20-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59678 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 90feee242584d367473331a187a50bb8490d201b |
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 92adc19be95347225f713db8cc1b5e22ac08bb5e |
15-Nov-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
Adds extern "C" ints to the .cpp files that use RegisterTarget, as
well as 2 files that use "Registrator"s. These are to be used by the
MSVC builds, as the Win32 linker does not include libs that are
otherwise unreferenced, even if global constructors in the lib have
side-effects.
Patch by Scott Graham!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59378 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 4f01235c75be6b458dfc43440854c99fdfd83513 |
15-Nov-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
Adds extern "C" ints to the .cpp files that use RegisterTarget, as
well as 2 files that use "Registrator"s. These are to be used by the
MSVC builds, as the Win32 linker does not include libs that are
otherwise unreferenced, even if global constructors in the lib have
side-effects.
Patch by Scott Graham!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59378 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 7e2cc91d2dfae04014d817efe7f3f071ce97f452 |
15-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix fuitos encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| bd05c5ff3268bfc5533ec6f8a04ff7ff89a4eabc |
15-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix fuitos encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59344 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| a956255ebf51a48b8528b520eafcdfb5f1049a28 |
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59314 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| 7f240d2720ad13acf5da2a8219f1848c02ff4c26 |
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59314 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
|
| ffa6d962a7d75500269ce5d2012b58249fee3d6d |
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle the rest of pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
|
| 9d2c9231ced48ab86dd4707431be7405deeff3bc |
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle the rest of pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
|
| 28f312949e27e6e218ba25d8ca07ed58a96a4bd1 |
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Lazy compilation callback save / restore VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59274 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 649de51e103995ae3efa6ff4aab7c0a7e480bc56 |
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Lazy compilation callback save / restore VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59274 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 35b0bfd06dd5ce8f679a497b3fbfae43667f8727 |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59258 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 0593d64a589a05a2ae3355eb0e4c5ce507bafcbb |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59258 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 3c902e81fae4eaee88729dc7fd97eb78d9cb8650 |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
fsub{d|s} encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59234 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| b4d2a3672cef33a0b03c3e994a237d7cf008d1f6 |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
fsub{d|s} encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59234 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 67fd91f3df132844a7ad8bcc70de118e0a534d9e |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Missed a break statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59231 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 3d89598f1f77b6592f04671cc5d356eb285b746f |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Missed a break statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59231 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 148cad8b308c0f8fdb37b368f2c911861dd2421a |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix pre- and post-indexed load / store encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 81794bb21ef0b38886835eed1995d495e47be42a |
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix pre- and post-indexed load / store encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| cb5798285aa3a3cd93448beda6264152c761e8e3 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove the incorrect assertion. We don't have enough information before relocation to set U bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59170 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| ba3d8bcb52d332b1af1283585e0d01d636bc2899 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove the incorrect assertion. We don't have enough information before relocation to set U bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59170 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 607f1b41a26f6b083399a480ed8547236931db76 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Address mode immediate offset has already been divided by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59117 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 517b3e868e9ad48ac2905dbb52d731962abcbca9 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Address mode immediate offset has already been divided by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59117 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 3f4924efffdb4bb7af408356df86bd8cb83ab89a |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a VFP binary arithmetic instruction encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59116 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| db60806dfc019724a37f8a5d2e997ea38d205f8f |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a VFP binary arithmetic instruction encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59116 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 706329143d0cbe83684275417c514725aab773e9 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix address mode 3 immediate offset mode encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59109 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.h
|
| 9eba91165910dcb37d5751bf43b2e90b83a381d1 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix address mode 3 immediate offset mode encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59109 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.h
|
| 3c4a4ffa3dba5e3c7a0900d0bafe28d7095f3ada |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Consolidate formats; fix FCMPED etc. encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
RMInstrVFP.td
|
| 11838a81de997021b6b914cd725eb4d65c3183e5 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Consolidate formats; fix FCMPED etc. encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
RMInstrVFP.td
|
| 80a119842da2ce2786ea476037001ab5b6c67046 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix VFP conversion instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| 7427338c3da0cf35ecd0ea845ea41e3939eab608 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix VFP conversion instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| d06d48d2b593958a4822ef6f7f3f6b51d177124c |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix encoding of single-precision VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59102 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 8a0454bb13f2db05517e70aae31e0f15f5d252fe |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix encoding of single-precision VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59102 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrVFP.td
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 580c0dfaed1caaf241dfb8c02c11f89d6431ee50 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
VFP fld / fst immediate field is multiplied by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59100 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMRelocations.h
|
| 668d0df68e2c40e4f4073535afcc5ec210d7d200 |
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
VFP fld / fst immediate field is multiplied by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59100 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMRelocations.h
|
| 0a0ab1387a3923769990e91cce8e098366c4a920 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix FMDRR encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| 828ccdc0ffc967ba75d96e1f3c55230047c5a13c |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix FMDRR encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| cb5201f3b2d7147471d33cb2ddd94c5e011055e2 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle floating point constpool_entry's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59087 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 9e280e07770715ab3814954a5ad7d88bc0a3f9d8 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle floating point constpool_entry's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59087 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| cd8e66a1efdb31f0514270387207fb8c63bae4ed |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| bb786b31491ed3cf69247d29cd2d42afa75dc54a |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| 78be83d7c2a5b94e635b0227924a489b8d8937e8 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| 9d3cc18099051234d17dedbd15dfd486b89b9a25 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| 96581d3633edf702b14a60472a1ec5354f327c18 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| c63e15ebf517f96d2ac3a6b969791bf3f9130964 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrVFP.td
|
| 588920b9a5f7004e330e3597872908b4d57e9355 |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Correct PIC function stub codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59006 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
RMJITInfo.h
|
| 5120b9fa2d6559eb94dab3079ff346926c73940f |
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Correct PIC function stub codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59006 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
RMJITInfo.h
|
| 9ed2f80910160bbf8051d91cd74c82d4619885b4 |
10-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58949 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
|
| 8af22c446b6eefa8dddd2412c7d779feb4c7bf0a |
10-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58949 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
|
| 0b45c9957fb7ad47e653fb43d455f6727170dad0 |
09-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Temporary revert my last commit: it seems it's triggering some subtle bug in backend
and breaks llvm-gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58926 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| a0880c082b31450617b7089c362ffaaf9b490a8d |
09-Nov-2008 |
asl <asl@91177308-0d34-0410-b5e6-96231b3b80d8> |
Temporary revert my last commit: it seems it's triggering some subtle bug in backend
and breaks llvm-gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58926 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0f569535676325a94981881eba6f8c7e61630992 |
08-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out offset printing code into generic AsmPrinter.
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58917 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| dbe42758a93dd74acd64dc5c88f7fc0708740143 |
08-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out offset printing code into generic AsmPrinter.
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58917 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| ae166410b992e7eb8652aba1c9010c043a8f6016 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Moved InvalidateInstructionCache to ARMJITInfo::emitFunctionStub which knows size of stub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58899 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 886dafe6e0958d8da971a539954ae4c050c783da |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Moved InvalidateInstructionCache to ARMJITInfo::emitFunctionStub which knows size of stub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58899 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| ce4a70bd7608861e104b04265a0c71e5df8ecefe |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58897 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 2c3267a14d9e81b7507ef2d9d7ea8b3bc5f7efe0 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58897 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 3cc8223a3c062daee763d6db272415a76de38a78 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58896 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.h
RMTargetMachine.cpp
|
| ba96b1a43da968e21c217ed05a65cfbe2a845f47 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58896 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.h
RMTargetMachine.cpp
|
| 103325179a65686d7e7dea3527d3a802b12e081e |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix relocation for calls to external symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58893 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5c454e984a39c417eae57989e54e5c44f2d85557 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix relocation for calls to external symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58893 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 05c356e65aca522244da68d7232c719cb8e45775 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Skip over two-address use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58883 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 2929cc0f51dd998bc00547377f00386758dc962f |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Skip over two-address use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58883 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| e96a490d7a0e224961d37f60f85e8556a64ed2b1 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle ARM machine constantpool entry with non-lazy ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58882 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
|
| 2d011f9f433116e91c2d98e8f3c32bb9608ce666 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle ARM machine constantpool entry with non-lazy ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58882 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
|
| f1bbb9577a42cf7dc3079412f1dd7683e3a03665 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Use ARMFunctionInfo to track number of constpool entries and jumptables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58877 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMJITInfo.h
RMMachineFunctionInfo.h
|
| d3c573ad2b4e96d426e7bfa60092bf9c2596fc56 |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Use ARMFunctionInfo to track number of constpool entries and jumptables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58877 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMJITInfo.h
RMMachineFunctionInfo.h
|
| 413a89f3187581ee94d01cafe167f1deff16493d |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
More code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58872 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
|
| 8600421afe774e20c147d9505e3ddc0c1fc04a99 |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
More code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58872 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
|
| 437c1738ef0ca451b710c31c87166f6abfd04ec7 |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Get PIC jump table working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58869 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| 260ae19f81f574a4ec2c4cc648a63bd4278e4615 |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Get PIC jump table working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58869 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
|
| e5f4de42b5d26f60cec6fab0482eaf579246b218 |
07-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Flush the raw_ostream after emitting the assembly for a function.
This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58859 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| eb94abd06c83b66823049ca0a4ca43a981f81fc6 |
07-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Flush the raw_ostream after emitting the assembly for a function.
This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58859 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 4df60f5491ff35c8a48c2cf14e18a33c9793b3bb |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Jump table JIT support. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| 0f63ae111d5a509911fc61246c1acc62f8c58f18 |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Jump table JIT support. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| 8b59db3f2c72a642251d4f86ea61f5d27e8919a6 |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode misc arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| c2121a25f17c99f2f1b0235bf425842962535ae6 |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode misc arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 97f48c39fd158ad1a701002e2d6798c4b4ae4ab8 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode extend instructions; more clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 37afa438c83f6c25ae29ba269b67240def64fc68 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode extend instructions; more clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 12c3a533c50fe3c7475c1ff7c1bb4b26e36dc6c3 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| f8e8b6224f80c48736ae4387901bd5f84c2781d5 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| d87293ce78ae7568477374cd83b22c84214316fb |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
RMInstrVFP.td
|
| be9982437e064b956575c7e9fb32465309b08cb2 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
RMInstrVFP.td
|
| eb4f52eb6287919fe2bdca62364046af800cd15d |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 38396beca395eae0a5fe0b0f86c9bfcffb272287 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 9092213a5e50d4991f900d2df009d27bddfd9941 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix so_imm encoding bug; add support for MOVi2pieces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58790 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
|
| 7cd4acb355755ff9c52e60095fa7444fff7269af |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix so_imm encoding bug; add support for MOVi2pieces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58790 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.td
smPrinter/ARMAsmPrinter.cpp
|
| fbc9d412efdfa1ed30ff4d2baedc775a5f59c638 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| ee80fb79279be7c84e6f8a3f06403200386a6ef5 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 83b5cf02721cb0f755fde9bd454172bceb356532 |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode pic load / store instructions; fix some encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
|
| c41fb3151784f7fccb4731ef594c4ea3dc685d5f |
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode pic load / store instructions; fix some encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
|
| edda31c412d524531ee6cd3f2d21c2ef85b6afb0 |
05-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 86a926a425286e882a7f3902a525527f17bb127f |
05-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d |
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| cc3df850908f44717e40c3c94e62943c7eae25e1 |
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3eb22e835f253ffd42a050caffa48eb08bdfc8d8 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 861c499fad5407535746fb8c4f101609fdfea1c6 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c7c77297e28189c3c3bccd6e261a84970704b760 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8b37a95ffb1c263f34ea1fe9e0b9846593f96b41 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 142c15e05283aaa4f95ce64a7f6246e4b766eb8e |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Debug output tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58708 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 50a30ea5b2d17a5d574721f4355c0d044aa8b68a |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Debug output tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58708 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| e7fe6724452fc6db75be1957df79bb92f5635b28 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 8ec1b802681dc92db5b8195b84dac32d4422ebdf |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| b0b53491ef32b85bd90c8590faeb8a3fb4b17a95 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58688 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.h
|
| 4a8e3b4f4e6efae315b04d6930e82baa84e746ab |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58688 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.h
|
| e953b89b0d7ef8ecb681dab3bea0db81e41c3cf9 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Stylistic change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58683 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| dfee8858c8305e342b68fa63133b5535851a97a1 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Stylistic change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58683 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 25e04788bfddc54dde7bed65302146b46089a166 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle ARM machine constantpool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58671 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| 5a033a6c9c08d06f316e42b111cc79756c672733 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle ARM machine constantpool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58671 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantPoolValue.cpp
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| 49987360ade8d506782835222f5f00dfc5ef9ec6 |
03-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove a dead switch statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58644 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3cb57c7261a0b4d94a04417b05c754502a3e7a91 |
03-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove a dead switch statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58644 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| afaf12036d0432dd3265436c94a66183b21c2115 |
03-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Minor code restructuring. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58643 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 4a83c42c7ec7a236a0a837ae7e6a13378a82db4a |
03-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Minor code restructuring. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58643 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 0a4b9dc9b127c3fae6069f85a7858db5a06ff3a8 |
03-Nov-2008 |
Jim Grosbach <grosbach@apple.com> |
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 1feed0434ec93100876edf72897700148b74d054 |
03-Nov-2008 |
Jim Grosbach <grosbach@apple.com> |
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 8f092252d3fe75064abe330e0e6f75e213f4ac06 |
03-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Refactor various TargetAsmInfo subclasses' TargetMachine members away
adding a TargetMachine member to the base TargetAsmInfo class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58624 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| a004d7b4de6421de04481229540e5397d25e05ab |
03-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Refactor various TargetAsmInfo subclasses' TargetMachine members away
adding a TargetMachine member to the base TargetAsmInfo class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58624 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 2583b2a713c2f1cd491805a03b6bf2e95dd2fdee |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58533 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.h
|
| 851decbd76290843dd062739d067f327993a9e24 |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58533 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.h
|
| 938b9d8ef78e83926437f8a331dd1e7645e28e4e |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Use better data structure for ConstPoolId2AddrMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58532 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.h
|
| b562f8b205bad45d278863af6644e87c054e6bc0 |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Use better data structure for ConstPoolId2AddrMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58532 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.h
|
| ba44df60d66363ce7490e81b18a35231c3f4c04a |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Actually make debug output understandable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58529 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 2410feaf2f4c50656c58dac673301e20fb3b6cbb |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Actually make debug output understandable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58529 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| c072966838afdd2ac61d59354447ff51b6cf8940 |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Forgot this in last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0d28b38fa07c7274d73e2a8fa4ea8e7211b3347e |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Forgot this in last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58527 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| eb4ed4b266b6f590febe9832016f97c9614a99f1 |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode PICADD; some code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58526 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d6dcbe2281bb989bf4b96f4783b5163d68802c87 |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode PICADD; some code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58526 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| e53a5af96652567847508a3131863a9a186ada9b |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
I think we got non-machine specific constpool entries covered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58474 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| c2cd2abfd243cfd4124cbbc16303b8053d6ff524 |
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
I think we got non-machine specific constpool entries covered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58474 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 65f244261cbe75e2bc525c3d66c3438384e8129c |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
ARM JIT should observe -relocation-model command line option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58433 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| b8b40d6123441802da20d163bdd192b1de58063b |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
ARM JIT should observe -relocation-model command line option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58433 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 0f282439be688babbbf6d54151ddf9a7ebbf3637 |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Correct way to handle CONSTPOOL_ENTRY instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58409 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| f07a9b69d1c91187d73667b46aa423d4325ccf04 |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Correct way to handle CONSTPOOL_ENTRY instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58409 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| 5be59eace58e5a92bb851c4885f9cea7236ac30f |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add debugging support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58408 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| f3aaeed00d5ff37bd445fb956f7a817004afb49d |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add debugging support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58408 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| bc6d876adf01b368c6bdd5984d9dac32589d356e |
28-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Support for constant islands in the ARM JIT.
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the
instruction stream.
Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.
For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58338 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.h
|
| cd40d8954058f9dbfd9192fd0d5f8e0f8d00fa10 |
28-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Support for constant islands in the ARM JIT.
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the
instruction stream.
Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.
For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58338 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.h
|
| 8ad4c00c00233acb8a3395098e2b575cc34de46b |
27-Oct-2008 |
David Greene <greened@obbligato.org> |
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 932618bbd74a0732de8687d0f5a25be8145e90b7 |
27-Oct-2008 |
David Greene <greened@obbligato.org> |
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 28df32b559c358edfa9ae875eb25a6f086306c13 |
25-Oct-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58133 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 7ba56bf365096798e62a803cf3ebb23948e3357d |
25-Oct-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58133 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| c64bdf6aa5160471dfda49a78d4a0e08bc07ac0d |
23-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
remove extraneous #ifdef's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58006 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| ea6e03699e9e0cbe6aaf537ac7f4dee443ee42d0 |
23-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
remove extraneous #ifdef's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58006 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 5c5b6dfd0e1525305674560dd5d995e5f7eff2e5 |
22-Oct-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: Turned some libraries into partially linked objects. Corrected
names of LLVMCore and ARMCodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57943 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 9cc6f1df959dc2aa17ac70309503fcd3832b5cb9 |
22-Oct-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: Turned some libraries into partially linked objects. Corrected
names of LLVMCore and ARMCodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57943 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a9ab95b38b0aec44e26a3b36a6b37498dc2acdde |
21-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
use pre-UAL mnemonics for push/pop for compilaton callback function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57911 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 8eab1c8c9852bb78231148ac4fb2d93b975f4ccd |
21-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
use pre-UAL mnemonics for push/pop for compilaton callback function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57911 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 932a32d2512353478d16c4101582adff404a55a5 |
20-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Update the stub and callback code to handle lazy compilation. The stub
is re-written by the callback to branch directly to the compiled code
in future invocations.
Added back in range-based memory permission functions for the updating of
the stub on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57846 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| c599a35bba7259e9b71aad881f5fc877ee34dc3d |
20-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Update the stub and callback code to handle lazy compilation. The stub
is re-written by the callback to branch directly to the compiled code
in future invocations.
Added back in range-based memory permission functions for the updating of
the stub on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57846 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 8e8b8a223c2b0e69f44c0639f846260c8011668f |
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 46b948ea872c1d1853fc5be4af44794ef3ae7f63 |
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 08c171a5541b033a603674fa0179259714d985a3 |
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2642196a6570e95e1491ee0120f67baa5c3ea351 |
14-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57524 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 88c246fae5a4e41ad79241baff24e450c672f7cf |
14-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57524 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| b8cab9227a0f6ffbdaae33e3c64268e265008a6a |
14-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 669b9bf656d0bdb22bee268c4dec5eb3b3add6d0 |
14-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| e563bbc312f8b11ecfe12b8187176f667df1dff3 |
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| fe5d4021d0884e4cb94a7bb688fa0b02950ee29c |
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
|
| 309c80adb5ece9c2bcc5fe871a440f9d91e12ef8 |
08-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Comment to be explicit that the enumeration values for CondCodes matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57295 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| f81385d68efb6d00d52ad945c6650976cebf392b |
08-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Comment to be explicit that the enumeration values for CondCodes matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57295 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
|
| 76e9661b6c46e211c1e0d5215b92d3bd219e9cff |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57262 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 57a2588bcc546677c1666f44e59b638da3d5fb3f |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57262 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cbc47b89340c8ab995453f2b18ff237c1303e89d |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
need ARM.h for ARMCC definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57261 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
|
| 94a552c8de30d7c5f6aba15b13699490c17b6b7e |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
need ARM.h for ARMCC definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57261 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
|
| 3341262de27dad5e1f983fe072a749356a8f3c78 |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Encode the conditional execution predicate when JITing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57258 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.h
|
| 320c148375723e6e2f850f5e9909da26391a0119 |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Encode the conditional execution predicate when JITing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57258 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.h
|
| 9e729a2de59593b03ddf8a0acb1128ad060548e3 |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57252 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 29c4b0044b6f70e476a669866eb494b50cb229d5 |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57252 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 17a415a4f2d2609544b0bbb83691b568ddb5acd8 |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Fix Opcode values of CMP and CMN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57251 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7abbd4d0ec4f1e536323191b78adaab1923a28ee |
07-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Fix Opcode values of CMP and CMN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57251 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6381a1334afa211fea8ec76ca7b22d26aee940dd |
05-Oct-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57106 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 45d1b62fd1bb0de6e47439a198aecce3e782ca9c |
05-Oct-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57106 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| da8ac5fd9130b70b61be61e4819faa8d842d708f |
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f2b2957318f841e3a74dba30df70d359675f2915 |
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 48b828fdb467655fa630fed41e49e2a481fb6dab |
03-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Indexing off by one resulted in errant encoding of source register for
reg->reg moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57011 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 893b878b975ac42b3ffd7bb4518fbabb42c6e304 |
03-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Indexing off by one resulted in errant encoding of source register for
reg->reg moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57011 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 016d34cc4caa5eac50378c652a5301fb1fbd48b3 |
03-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
NeedStub/DoesntNeedStub logic was reversed, leading to not using a stub
for global relocations that do need them (libc calls, for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57010 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 980dd3b54ea88868526af1846a435fe2bf141ada |
03-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
NeedStub/DoesntNeedStub logic was reversed, leading to not using a stub
for global relocations that do need them (libc calls, for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57010 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| b9f4fa7b400836808bc3beab96482418f418f246 |
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
smPrinter/ARMAsmPrinter.cpp
|
| efd30ba7980fc6a1f1577f5f586692db5a920eaa |
01-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Fix typo s/ther/there/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56924 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| b98d7197d674a5435545acc691236f46eb2ee97b |
01-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Fix typo s/ther/there/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56924 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 5df3186f598163258fabf3448d9372843804d1ab |
29-Sep-2008 |
Duncan Sands <baldrick@free.fr> |
Rename isWeakForLinker to mayBeOverridden. Use it
instead of hasWeakLinkage in a bunch of optimization
passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56782 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| eb3f45fbeb3d009f9861f3c4ff82931b8aefe239 |
29-Sep-2008 |
Duncan Sands <baldrick@free.fr> |
Rename isWeakForLinker to mayBeOverridden. Use it
instead of hasWeakLinkage in a bunch of optimization
passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56782 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 184793fc8a9cf6ecc9147468bbcc068f472b8517 |
27-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 56683 with fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56748 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 33633670b6587af91b91b2b63f2481fc6b16aba4 |
27-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 56683 with fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56748 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| d5d8191b202c0f96f33c826c93d9796451ff7fca |
27-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| f29e2a5ab195a822593a92820338bdf63a85be1c |
27-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 36a55023c1daae86afedf6e6672c0adad7bbe5ea |
26-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| e96a7f565ddcd8855d6cbcecf3f65ea08a65e558 |
26-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7 |
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 67cc9b67faa7d6a72d916b52c22e7a33a44097db |
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e1ad087fcbb51ed66e450d010f849b5792b4b6fc |
26-Sep-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: Builds all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| da2a8a1309f7303008175e1d1ac7d4276c4454ec |
26-Sep-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: Builds all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 32b952a2a60d1091e0e17bb6ce788cd1d41e6f8b |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply 56585:56589 with proper fix for some gcc versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56621 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 3829e8a0e4d29e43d934b78935c3e067db8ff195 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply 56585:56589 with proper fix for some gcc versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56621 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 688535e005f370a98e82c10be7346eb981b3dfc7 |
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily backing out 56585:56589 to unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56607 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| e0f2083a849c0c57991b115cc6895b10272c888c |
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily backing out 56585:56589 to unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56607 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 621cdf0057e74453f8b3420c4c95cacf01faa993 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of virtual inheritance for ARM TAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56587 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| ec2c6e1e97124a5f15c4b1abba707cb87c0db916 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of virtual inheritance for ARM TAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56587 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 00181a33d87d0c7676547d979b2faa1c08c91732 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of ReadOnlySection duplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56582 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 4d43322fbff8d1233d86ba8c2af291352c3aca99 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of ReadOnlySection duplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56582 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 6481873dc042d33c974399a7761a72524d1fe957 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56580 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| bce7851fd6cdd2997666cb7b210448d52fd6e2eb |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56580 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 36133dd324a0583979cb9e219306726428270096 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* stuff for TLS sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56577 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 9a213e410c1f2639bfa8c363300a5ef409a38838 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* stuff for TLS sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56577 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 315690ec2a99e1c0867853955f81d99f548178be |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* DataSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56575 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| cca60fa0d98abdf7dbe69a4ef15c539d80f6e9bf |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* DataSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56575 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| c25e1ea5e9aa54952b6736a9579e25a5c2d8139f |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56573 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 1a9edae76b2e7cf15c5f7c36928b3701ac2ef47b |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56573 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0c8e80607bc3296a4775f05c02f0d11df8e5cb04 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Drop obsolete hook and change all usage to new interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56572 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| cf87a3dd015c7e2acfc0b4feff48fc7fc2a16f01 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Drop obsolete hook and change all usage to new interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56572 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bdd |
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56497 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 868636ebd973e968cc698b48704420ec24a431fd |
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56497 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 0bb41608e94adfe9884bc188457c4f6ae47ea43c |
22-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Make log, log2, log10, exp, exp2 use Expand by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b02a1c07cb1e1b9cdae3bf1ddb0578c779b9c8ff |
22-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Make log, log2, log10, exp, exp2 use Expand by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 057d0c35358841aba449d203622416431163cb83 |
18-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Duh. Default to ARMCC::AL (always).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56301 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| e4c813ccdf946b232816949926386aa6bbcdfa0e |
18-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Duh. Default to ARMCC::AL (always).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56301 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 6d63a728586d56eb3e881905beb9db27f520f5d3 |
18-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56300 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| e6c6162e11557ac485caa2749f0c952e6d052bf4 |
18-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56300 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 3f7eb8eba083677d38cc8c96f00a945399421aaf |
18-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56299 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 0edb69d3fb4b1a30c2bccb76b34e12d6e9eaa675 |
18-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56299 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7fd7ca4e7f775a75f648f03d956c3068c71b991d |
17-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix addrmode1 instruction encodings; fix bx_ret encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
|
| 469bc76e282e1a2f2b646ee1686e9d39337d0223 |
17-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix addrmode1 instruction encodings; fix bx_ret encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.td
|
| 29c57c34efcb6b8ba64e3279cdb68937c113552a |
17-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Specify instruction encoding using range list to avoid endianess issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 18e5d103729374160b2da14415a401c17bbcde6e |
17-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Specify instruction encoding using range list to avoid endianess issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fef06056071dcd275f5ec539713a0dfcc33db436 |
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bdad5cfcd10bce155a51f3658a57ed3866903c5b |
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 014278e6a11fa0767853b831e5bf51b95bf541c5 |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 7f7f365665a22e1b4397d0924f24b929607f9690 |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 2aa0e649bfc0157ea08a1ba8f8c9e905ddb581b1 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix random abort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56184 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 453bbc3a0040eb095c89c4e5c055d7333eb865f3 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix random abort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56184 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 705e3f774254a03ef28a27c1d15903547a0e9d4c |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e7de7e3574245fe4cdee3ea895c3aeabca04db63 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56182 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 00330db76463b811bc5908306a1c7248a1eeaf2b |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56182 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| be3034c28893617d31e9ce7ed9ad2e128e92877b |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rely on instruction format to determine so_reg operand for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56181 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| cbefa59743c85da7ff0df234c49e44f9a951e195 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rely on instruction format to determine so_reg operand for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56181 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 05fc9664018f867b2184589e8a04cc8f056cfa16 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 56176. All those instruction formats are still needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 4c7e67abd5ca98e7bde0683982c935319477c50f |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 56176. All those instruction formats are still needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 55375a44f97dfb4b396d5fdc1f60f967e1553d8e |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Accidentially flipped the condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56179 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 9ae284ff82ab1dc2eabf53e29b97cdf525f99814 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Accidentially flipped the condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56179 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 42d5ee062a4ff8ba63586e091ca68558ac143ed3 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add debug dumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56178 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| efb9181429f459e5e04f1d79533bcdc3dbac2582 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add debug dumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56178 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| a964b7dffe89d22569e96f5801886ef347d01b0a |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unnecessary instruction formats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56176 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 3eb25b3e793196ac12d225fd3fe37c5dc1365a2f |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unnecessary instruction formats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56176 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
RMInstrInfo.h
RMInstrInfo.td
|
| 49a9f2958dadbb1fcdc707ec003a61e9ceef8a4e |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56172 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
|
| 378c3a98dc3cc70f8562e5221d41ef23c38d87f2 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56172 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrFormats.td
|
| 5f1db7bf31eec999a55845f91778143b8b3e0aec |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rewrite address mode 1 code emission routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56171 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.h
|
| 00dc31b291ddde446299bf4b50011fb56758f211 |
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rewrite address mode 1 code emission routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56171 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMInstrInfo.h
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| faeb4a35197737b3674fcfc34fd6e84220aa437b |
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| e5d20f947a002519832005c40c6c60962616a476 |
11-Sep-2008 |
Jim Grosbach <grosbach@apple.com> |
udpate header comment: s/VP/VFP/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56126 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 31b3e6813e0ae7444a5c1d0de3d609e3865eca32 |
11-Sep-2008 |
Jim Grosbach <grosbach@apple.com> |
udpate header comment: s/VP/VFP/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56126 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| b2dfb89e0e7f1ee3e4fe4a3a1b3af148f0aec34f |
09-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Fix logic for not emitting no-dead-strip for some
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55973 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 2d34f9f9db93f596ea731c546d833ab5d6bb5735 |
09-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Fix logic for not emitting no-dead-strip for some
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55973 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 8106b0a995512a847d3d9fb18cbb575c4d3913f2 |
08-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Delete an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55915 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9e087ba2eca95563e56adb7c5fbf5b09d2afd497 |
08-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Delete an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55915 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ae73dc1448d25b02cabc7c64c86c64371453dda8 |
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Tidy up several unbeseeming casts from pointer to intptr_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| 26f8c27c34b44f7d87de74d1de2128c1a02855bf |
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Tidy up several unbeseeming casts from pointer to intptr_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| 7794f2a3a7778bdbc9bdd861db1fe914450e0470 |
04-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 92b33088469bee2ea489b79574d26cd3847220ac |
04-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 95ce1178e40d232cbf8d134030c3dcc8474c704d |
02-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add Mac OS X compatible JIT callback routine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55625 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 5d582a69ee011cf14e31b5d27b0401db0102ce89 |
02-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add Mac OS X compatible JIT callback routine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55625 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 7602e11c3298ca740deb04a246c70560f1743dbd |
02-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revamp ARM JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55624 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| efc43652ace14e19983914ef145d205e1fd45e00 |
02-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revamp ARM JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55624 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 3aac788365086260b4f8318c5563db54cd2d97fb |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Control flow instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 10a9eb8212f68cf86bb53471070bbb9cc2c2b422 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Control flow instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 3c2ee4939b250963fa06483b4c082b279279f4e7 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
ldm / stm instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| d36b01cdc722ea8cd327995358a89a0f19802464 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
ldm / stm instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 5d2c1cf74d2f4794883af4e90bee320a344fa9e3 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
AXI2 and AXI3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| ae7b1d79526c501b622ee1f07273d1ca26d37c8f |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
AXI2 and AXI3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 4bbd5f8a9c39f8274219367895bcfc5d296573d7 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Reorganize instruction formats again; AXI1 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| c5409a8a6317d547dadcdfa5dee7b42442d41d7f |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Reorganize instruction formats again; AXI1 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 840917be2c58ba54d9a70204d08933f7ed107d67 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
addrmode3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| ac92c3f3cc6f3bdcecf8cf162af7113bd3203ceb |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
addrmode3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 0d14fc8cd5cee0b8527192c6820452e96d329e05 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Reorganize some instruction format definitions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 2e62b660eaa8d11d577b9843cb39a2b8db9cea78 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Reorganize some instruction format definitions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 93912739c9afec2482ea3c824ba0e40ab9bdfc03 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rest of addrmode2 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 1a7c1ccaa5bdaf148a5344acd09d1e72c9995691 |
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rest of addrmode2 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 17222df0ecf8b0fbcf17b050dd18174ca845fbe6 |
31-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addr2 word / byte load encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| da02002bbe2fbeb701f14caf6c3cdb5628c291b2 |
31-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addr2 word / byte load encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| b7880ac470c8d83580e9327ecb2ce8efc40ca091 |
31-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| af8f12871bcdc7eb292b3d363b9c6a3fb7c1440d |
31-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| ba705f62b1f78f4854e2640c7a5626a05417c646 |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
TableGen'ing instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| ae8400bc730bd3f84a53affec72c269c76cdd549 |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
TableGen'ing instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 612b79edc92b305bc23a23fc5ef4066ca728921f |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| d075035cc4dab18a33fc75282a7b8bcd2c3323ff |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
|
| 3924f78a9637bcdacefaea2660095e1201661687 |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
MVN is addrmode1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 40d6453fa5b5a806fd60636395a0f06555eb32ea |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
MVN is addrmode1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 130966411f83469b1d9b93df831a2f2146bd400f |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 34a46e1e09fadd67db9262f355af697c29a14cbc |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrThumb.td
|
| 37f25d989a3054b4742f6c92af94a312c26ffb2b |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor ARM instruction format definitions into a separate file. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| 7b0249b93a3ca2fe31c9cf95360816a61ab9b517 |
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor ARM instruction format definitions into a separate file. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrFormats.td
RMInstrInfo.td
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 1c80d116c6a34e02059593964233f2e641bdbc5b |
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 46bf54702f3d06e26fcc6520ad347540696f263d |
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 940f83e772ca2007d62faffc83094bd7e8da6401 |
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 9fa72d9078dbead41d24462d0588135804999171 |
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 944fac71e082cc2664cc71b4d3f6c72bab7143fb |
24-Aug-2008 |
Chris Lattner <sabre@nondot.org> |
Switch the asmprinter (.ll) and all the stuff it requires over to
use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55263 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| 1fefaacfde9c8c1e88d97758b0b3a6aa587698c8 |
24-Aug-2008 |
Chris Lattner <sabre@nondot.org> |
Switch the asmprinter (.ll) and all the stuff it requires over to
use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55263 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.cpp
RMConstantPoolValue.h
|
| f350b277f32d7d47f86c0e54f4aec4d470500618 |
23-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 14a6644251df9ccb261bb4e3ab386b738df36633 |
23-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| ad3460c3c968e33c5b9a07104b9fe5a5c27ff55b |
21-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify SelectRoot's interface, and factor out some common code
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bd3f882ed9e9d043aef38f43e97b680d93100d9c |
21-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify SelectRoot's interface, and factor out some common code
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| cb3718832375a581c5ea23f15918f3ea447a446c |
21-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Use raw_ostream throughout the AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 847b99b2df4534498b514c439324e7c60de5c3b7 |
21-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Use raw_ostream throughout the AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
|
| 6aa38987302a5c272900607b201aa95a0e1eafd3 |
18-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
ARM asm printer can't handle dwarf info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54913 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 426a19c7f371d125ec57a38d4954e4d4d4f78372 |
18-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
ARM asm printer can't handle dwarf info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54913 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/ARMAsmPrinter.cpp
|
| 0bd89712c03c59ea43ce37763685e7f7c0bdd977 |
17-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move ARM to pluggable asmprinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54889 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/Makefile
akefile
|
| 74b114b4beb1498b6a031f55863c56e0fce433ee |
17-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move ARM to pluggable asmprinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54889 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetMachine.cpp
RMTargetMachine.h
smPrinter/ARMAsmPrinter.cpp
smPrinter/Makefile
akefile
|
| 44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| d131b5b3c78084f3b452b97a678c16e815f0a0d8 |
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 1a6c683315bd88dea19b97a8752c0b8cc43e4285 |
12-Aug-2008 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54695 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 465fffc4bccda54a99ac2c852bf5915e6e30759c |
12-Aug-2008 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54695 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| f5b6a47bb57fb5ffc734416d4d5d993e1a06273b |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle visibility printing with all generality. Remove bunch of duplicate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54540 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 78d69aa0e6ad2d32243e3b4e8ff28d6e4572313d |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle visibility printing with all generality. Remove bunch of duplicate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54540 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 42ccc21ce7ae392d9a5c2958786190943fe9aae0 |
08-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Undo most of r54519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54534 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| eb774e1028fdf0bfc475431229b1b7e3c2471765 |
08-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Undo most of r54519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54534 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 711b6dce246c87b5d830966bed823d0e7aa15300 |
08-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54519 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f1012ce19140bc114c4bad429824ff150e623f38 |
08-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54519 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0f3cc657387d44cd7c56e4ddea896a50ab9106b8 |
07-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Switch ARM to new section handling stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54458 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 3cc6efa84bf118b262343b5f15754a4f5d3a6dd2 |
07-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Switch ARM to new section handling stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54458 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 8181bd1f95ae9994edb390dd9acd0b7b12375219 |
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
RMAddressingModes.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| d1b3da621bf5134d304d02177a2c6ff912b0d18e |
25-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54004 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ad7295eddc6feed1df1cc531a9d513b07acda954 |
25-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54004 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e8be6c63915e0389f1eef6b53c64300d13b2ce99 |
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bd68c79fb898ebb9b42140fb39bab3baf3cb8f4e |
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 78d60458d558877a5bf7e326511e302bcf75b8ee |
11-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
add support for returning i128, PR2532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53472 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dc4ac473d31d85958aa22f78314109082502922f |
11-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
add support for returning i128, PR2532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53472 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| dc2fbddd9d204e904b8e61d1da1428579e7c55af |
11-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Trim unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53471 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| 02983113c9d593fc6d0e7c769e88754a980da8bd |
11-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Trim unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53471 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantPoolValue.h
|
| f2452c5f48e13cf3a9e620d22d5040a90133ddca |
09-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Emit debug info for data-only files. ARM version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53360 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2f85df10e8d77563892a880a4e35c7f5d3132ffb |
09-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Emit debug info for data-only files. ARM version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53360 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 526be70f94538a2cc131ab1b0fd9f7264e00d297 |
09-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Back out 53254. It broke ppc debug info codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 5cda776e7b93ac28d6ac6d646078e299ece7906c |
09-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Back out 53254. It broke ppc debug info codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53280 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f71cb9b3ed1d7b3e438e9990ce1587ba275e70bf |
08-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Make debug info come out in data-only files.
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason. I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53254 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ccf4061bc5fb2d49f92e7c3639e0b7f849bcd797 |
08-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Make debug info come out in data-only files.
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason. I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53254 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
|
| 221a4371f95ebdb25ac7d4363accb35c88cb5ea4 |
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
|
| 4542611bb9793e8376d7d5f33b4a1e2d11712894 |
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Minor const-correctness fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53196 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| e4da641adc6f0989b558036c9c238ff3ce050669 |
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Minor const-correctness fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53196 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 1002c0203450620594a85454c6a095ca94b87cb2 |
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e887fdff72486ad0e83f402c8c105fa91fff1036 |
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| ac496a17678473310a3c468a8ac5a5a30426876c |
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 9f1c8317a4676945b4961ddb9827ef2412551620 |
03-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| e52c191890057ab4cec065505b0b27f8586eb1b5 |
03-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| f660c171c838793b87b7e58e91609cecf256378d |
03-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| c6959726ab99e740101d8b5b663aee5fa1332791 |
03-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 4bdcb61af33399d4e01fdf3c47ca1f1f5356e370 |
02-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 698842f7b62573cc6a3af154727e5d59daea4c1d |
02-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| fa607c9cc5d2bd142ad8352bdf5e446517562688 |
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 7f460203b0c5350e9b2c592f438e40f7a7de6e45 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 472d12c47f1704853971a564e03c5490ce5066b7 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| db8d56b825efeb576d67b9dbe39d736d93306222 |
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 34fd4f3c0eb0d6c2ea2d2208a68bf693ca123d18 |
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f9516208e57364ab1e7d8748af1f59a2ea5fb572 |
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f19591c91ec39496d58bf4835640d25abc026da9 |
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 92c439168b552f73b1459d8ce1e31975cdca6d2a |
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 428ac54894f80ba4848d5f13576643f289412e6f |
03-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Add StringConstantPrefix to control what the
assembler names of string constants look like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51909 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 8f03a204f57fcb59b6ac754a632720cb6054152c |
03-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Add StringConstantPrefix to control what the
assembler names of string constants look like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51909 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| c215b3ef5d9627f5fb6fe9034e46bc29ae592916 |
19-May-2008 |
Dale Johannesen <dalej@apple.com> |
Handle quoted names when constructing $stub's,
$non_lazy_ptr's and $lazy_ptr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51277 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a21b5207101fea6703ac85290dbac506b6915dc2 |
19-May-2008 |
Dale Johannesen <dalej@apple.com> |
Handle quoted names when constructing $stub's,
$non_lazy_ptr's and $lazy_ptr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51277 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 |
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
RMTargetMachine.h
|
| b41dfbac74597086869acab8c158bab979ff5d1b |
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
RMTargetMachine.h
|
| 844731a7f1909f55935e3514c9e713a62d67662e |
13-May-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 089efffd7d1ca0d10522ace38d36e0a67f4fac2d |
13-May-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 3bf6accfea3aece45a366a58ade187eb6e5b9b92 |
06-May-2008 |
Chris Lattner <sabre@nondot.org> |
Match things like 'armv5tejl-unknown-linux-gnu' for PR2290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50698 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| accc87c1d9e3f4dacefcba2e1b8621e6ab5d8dd5 |
06-May-2008 |
Chris Lattner <sabre@nondot.org> |
Match things like 'armv5tejl-unknown-linux-gnu' for PR2290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50698 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 1f13c686df75ddbbe15b208606ece4846d7479a8 |
28-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 65118f43f2da7c789cd2fde6908bdac8774a2304 |
28-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 51cc3c13eac78da242f0518fc42580e48dd5304f |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49814 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
RMJITInfo.h
|
| 2b483b5fb10fd3e6223b824726c9403bb47c1e1c |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49814 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
RMJITInfo.h
|
| 52e724ad7e679ee590f4bd763d55280586a8f1bc |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
|
| cb162a0601c07804318bea53afe3f10f87567ef0 |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
|
| 29e4bdbf27c5f03b12dd2bc41d9ccb0d5f3dfdf4 |
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 64fd1a959022d190ca01e9a8ab665ea97c03546c |
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.h
|
| e8b391ea3cf33a68b0c5eeafc448c53b412dd61f |
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.h
|
| 110cf48752dcf86c6d95698c08805f1dd534ac83 |
01-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ARM / Thumb soft FP support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49012 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a87400339fcb3e087996e7ad534816d640c8b716 |
01-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ARM / Thumb soft FP support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49012 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 7d73efce9cfa7af4e1747dbd8c4bf2b948816777 |
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| d27c991cebe48fdf82b5d9eec6c2a1a244f82622 |
30-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 2b06cd3076bbc4547d58109722c79b33366d594d |
30-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 950a4c40b823cd4f09dc71be635229246dfd6cac |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
RMJITInfo.h
|
| 40bd38ebb955c55a8ff7ea4ba252afbb093bc3d2 |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
RMJITInfo.h
|
| cfbb2f074da2842e42956d3b4c21e91b37f36f06 |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48800 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 12300e1e31559e34d96e533506f74f7cb77020a2 |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48800 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 066114555d27d6464762cbcfe0d118b7808b37c1 |
25-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add \t after .set. Fix by Jay Freeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48753 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| f068865fca6c1da137bad228b52a77635687752f |
25-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add \t after .set. Fix by Jay Freeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48753 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 276dcbdc8db6614cfd5004dc7dc35e437ddf9c58 |
21-Mar-2008 |
Duncan Sands <baldrick@free.fr> |
Introduce a new node for holding call argument
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48640 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c93fae3679c1b0ce8da92aaf825630fcc8580a00 |
21-Mar-2008 |
Duncan Sands <baldrick@free.fr> |
Introduce a new node for holding call argument
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48640 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| da47e6e0d003c873da960361549e57ee4617c301 |
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrVFP.td
|
| 3c0eda5a21a0e79a345fc9da0489fdbb5ef6b07e |
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrVFP.td
|
| bfae83139dcb4fffd50b939e1b1224b0126f04d4 |
11-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| e34aa7774f75505a532c5b1de6af79704ad72f81 |
11-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| d2cde68855125b6815b1575f29cd96927614b0cd |
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8d51ab3e4bb3f45ab8818519c5d27154cecf8b72 |
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b8cafe3427a168414400e5dfcbea78996792d2c3 |
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 322e3b73f704add3cd636a47381bacf1c6b2aa00 |
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 27b7db549e4c5bff4579d209304de5628513edeb |
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d1d68074a0e6eebbfdde72a29e14f1cd3e831c67 |
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6130f66eaae89f8878590796977678afa8448926 |
05-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Remove duplicated functions that basically do the same thing as
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47927 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| c7daf1f37a8c97e5ffc44f52e818cf127fae178e |
05-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Remove duplicated functions that basically do the same thing as
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47927 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| fb8075d03f5c87bd57dcc9c5f2304f6b13c55aad |
28-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 45c1edb4f781571f11fefb07a46a2c0f08523650 |
28-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6ef781f3ce0d0311004adba9d1e7dbd7950918dd |
27-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Final de-tabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6c02cd29b5ca35947c8414e7a20667066db64409 |
27-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Final de-tabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d36531249a9a9500e516148e7e72d4c0a7a4d0ee |
27-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Spiller now remove unused spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47657 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| da872539ba284fe9ded04f4231f88c90fc77ea5c |
27-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Spiller now remove unused spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47657 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 74ab84c31ef64538a1b56e1f282e49303412ad17 |
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8eeb97927530a1e53c3529a9b93f94239056d1b4 |
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7c1c261272b43f2a9397c3052819b92c53918075 |
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
|
| 8c90d2a37fdd3b14401035810d3644b2591b992a |
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
|
| d497d9fab6e90499c703f3e672ec001dbfa074f9 |
16-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0531ec5fcd743940a1e3074e94d764cfdbc8c135 |
16-Feb-2008 |
Andrew Lenharth <alenhar2@cs.uiuc.edu> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ec321b4d64ee02a1b90021c09d9513618787c6e8 |
15-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Handle \n's in value names for more targets. The asm printers
really really really need refactoring :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47171 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2b638a76689714aa60182159e7abe69f6b9c05bd |
15-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Handle \n's in value names for more targets. The asm printers
really really really need refactoring :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47171 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 00fee65fd21f9615d1a604b8b7d42cd16a3f6b47 |
14-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
In TargetLowering::LowerCallTo, don't assert that
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ead972ea45c0c4dad4e2e5c8da1ad24abda2ef47 |
14-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
In TargetLowering::LowerCallTo, don't assert that
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e179584f9b740cf3a36bde70f8cab40de59b8081 |
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e2ba64fc3785eb8bcc9a7fc2091c56ef056cbc07 |
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| d0dfc77ceb77510b470773f2b3725de475fc6bae |
13-Feb-2008 |
Dan Gohman <djg@cray.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 9f72d1a73029ed3bfb1f8ced755a1aeeb36fb4f1 |
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 60069456a6994c4ff67051cfb9ebac0d964e2f72 |
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 229fa05f26826290b9d128e7f6ffbc4889478c25 |
13-Feb-2008 |
Dan Gohman <djg@cray.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 3006c39e3a2f137dcb0f1b52d8a1c60a9657ed44 |
13-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
__DATA not __DATA__ is the right segment name on darwin.
Spotted by Nick Kledzik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47037 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 576dc02040d8c3cead1418c184b9693e9996291e |
13-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
__DATA not __DATA__ is the right segment name on darwin.
Spotted by Nick Kledzik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47037 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| bf1caa98549317a8fe84b6f67a2209db9eeededc |
12-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47036 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| a12a0a3e3e78ffc20e113d04756bed36c7a194d0 |
12-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47036 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMTargetMachine.h
|
| 1e57df3b4fd69b2a316d8931dee1b9e033ae3a9a |
10-Feb-2008 |
Dan Gohman <djg@cray.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMTargetMachine.h
|
| 5fd79d0560570fed977788a86fa038b898564dfa |
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 4f2f3f6dce7d350282947012884573f9ef19677c |
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 69de1932b350d7cdfc0ed1f4198d6f78c7822a02 |
06-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 12a9c08252c8e0fcdf5dedcdbf182251012a6fab |
06-Feb-2008 |
Dan Gohman <djg@cray.com> |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 4e3f5a4e9c13f216856515e6f000881f2c850736 |
05-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c439a85b1af63b2854c47e9322e553fe6180f4bc |
05-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c451ac0a42f06355976e5d7d8bc45da16474e3f0 |
05-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
This method should be virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46723 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 2f024ae9f98357d906a148964f3ba64b74a2c949 |
05-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
This method should be virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46723 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 48a65511d0a9d01cba7e146f9aa1187000a290d3 |
04-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Eliminate some redundant code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46720 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c6535bd24fb45d7e091634caa9cdcceb4cfd04c8 |
04-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Eliminate some redundant code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46720 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 3d62d780abbe0c2dd8edd7dd37a27365b2032d73 |
03-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46676 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 93c741add461a257df7bddf8f4700fe4e65f2ef8 |
03-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46676 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a47b9bcbdec16c2fa7cee84e72b5d0a306519a7a |
03-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't do ReplaceUses on a result that doesn't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b9843c70ed88fd1d62542b95af093c58eba0ca5a |
03-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't do ReplaceUses on a result that doesn't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4eecdeb3faf5df864790175da5d58301b751ec11 |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of the annoying blank lines before labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46667 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8b9886912f2d572f2a64ff112131184c41dabae4 |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of the annoying blank lines before labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46667 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 2e28d627d086d38a7e62fc2e3b6f4b9ef24ecf07 |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 334dc1f58d617dcff969a2e107febaae42bbc883 |
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46623 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 36ddaf294db6fbbbac5e79ca0e2d166ea36fe187 |
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46623 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c6c391daddbafa722d9ca87d18f204e9a6e617a3 |
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f14b4476a7dfade92c1f57f5702175f283960f30 |
31-Jan-2008 |
Dan Gohman <djg@cray.com> |
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e637db117eb826a539e230590ee6a5db585f1ffb |
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b625f2f8960de32bc973092aaee8ac62863006fe |
30-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 9a4c92c2b43e51ac531e0dbc319855635a14f905 |
30-Jan-2008 |
Dan Gohman <djg@cray.com> |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
|
| 200e90c74bff0b533c87e2d781815fa61af7b4d6 |
28-Jan-2008 |
Bill Wendling <isanbard@gmail.com> |
If the function has no machine instructions, then emit a "nop" so that
the function label isn't associated with something it shouldn't be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46449 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 43a7816450caef287b0f950ff751da97b592c87d |
28-Jan-2008 |
Bill Wendling <isanbard@gmail.com> |
If the function has no machine instructions, then emit a "nop" so that
the function label isn't associated with something it shouldn't be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46449 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f9c98e650d2795b8edfae8e1560c221029df218b |
23-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
The last pieces needed for loading arbitrary
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 082524cde46d15558f6270208e32cea0fe774586 |
23-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
The last pieces needed for loading arbitrary
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 25edeb32e77fdabbb986787a91a46435dfbaf716 |
23-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Honor explicit section information on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46267 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ae4f62fc7e13cbe25f853fe56e551a2a1ca39cc0 |
23-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Honor explicit section information on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46267 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 25a0195114c4fa1e22a7b71b6d80aef48d537b7d |
18-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Revert the part of 45849 that treated weak globals
as weak globals rather than commons. While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46147 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 42c3dcfbb032a2acde040463afa1a751f8c9e421 |
18-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Revert the part of 45849 that treated weak globals
as weak globals rather than commons. While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46147 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| 3bc0850bd4beeec5b464fce8513d3c749ee413eb |
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| 48be23cd65313b055ca80acb843ed244b18cd980 |
15-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| 3d25455bc1bcf846ea3df9060bc04aee468cdcd3 |
15-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| 7047dd4d227b5fb2e5ae0cb2e7d5de1d0098ad60 |
15-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46016 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 92a609a8e853af6edc4d5660a8451950bb2e0afb |
15-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46016 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 5080f4d9919d39b367891dc51e739c571a66036c |
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename MachineInstr::setInstrDescriptor -> setDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 86bb02fda2d7f62186a316e112d77a98974520b8 |
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename MachineInstr::setInstrDescriptor -> setDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 12591d70f6c98a5c9989df2afb88e8590fc77bfa |
11-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Weak zeroes don't go in bss on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45849 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| eafd8b5511c33bdd80c66ebdaced4d6d59837ffd |
11-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Weak zeroes don't go in bss on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45849 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 9b37aaf04c633c68c9ef09d3991d9acfbef9f754 |
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
get def use info more correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| ca4e0fe76aefbdea8c5c5c215e88130bac83e242 |
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
get def use info more correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 325474e06502eb0a593f4ef5a322bab2751f16dc |
08-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 8610a3baa0f788d7f01631b18ae8fcca70cf65a7 |
08-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 5b930374090970d785c0f77c2afc6d0a24c01f39 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 0ff23966feb90618bec4d085095ffbc28426e691 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| d8529abca155e9add3d038481c9c7db119220a2b |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
|
| 0c2a4f39ad5cdb32a2c4e20f787798d8af645393 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
|
| cc8cd0cbf12c12916d4b38ef0de5be5501c8270e |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 99aa33745d9f0a255da9e56315993e68997e1e21 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 69244300b8a0112efb44b6273ecea4ca6264b8cf |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 6232760ee0d566bcf09b2f20bae65c1d6e73946c |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 9a184efddb63e9b0327cb6cfccb9130fbfe464c5 |
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 834f1ce0312e3d00d836f9560cb63182c2c4570f |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMRegisterInfo.cpp
|
| 1a1932c83d6b6fcbf089eee3f97b65a23de22a92 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMRegisterInfo.cpp
|
| 2e48a70b35635165703838fc8d3796b664207aa1 |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMRegisterInfo.cpp
|
| 6887b14d9f14d2c918e9ce18e433de9a7845a747 |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMRegisterInfo.cpp
|
| 13c6310866bc3ebfc8255a17d8ff2afb233f01cc |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove explicit isStore flags that are now inferrable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| f823faf62406bc0002ea09eb482fd36e05c08180 |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove explicit isStore flags that are now inferrable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| d94b6a16fec7d5021e3922b0e34f9ddb268d54b1 |
05-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more functionality from MRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 6690c7faaa42e02d5592367d6ca6bd3982d7fd21 |
05-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more functionality from MRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 8187543db9afdc5d465b604ce0bddea7695c78ab |
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 641055225092833197efe8e5bce01d50bcf1daae |
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| d2fd6db5816e58ea3287bef90250e044025e7bca |
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
|
| 8f2c893c01f61e358637d28c3b594a9310872d38 |
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMRegisterInfo.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
|
| 1b98919de35bee879f414e9b97b38eeb9df287bc |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
|
| 8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMRegisterInfo.cpp
|
| 6017d48252df62d121344138c5ba9241f7bd73b8 |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMRegisterInfo.cpp
|
| 9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 |
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| a96056a6649e5df71d673e058aa559b80df273ec |
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| c8bd287f3c782ae15d0d36720d874b1054dbd143 |
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
use simplified operand addition methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45437 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMRegisterInfo.cpp
|
| a18f2d12e9e1fb6b6d52721d73e94686230e7a19 |
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
use simplified operand addition methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45437 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMRegisterInfo.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMAddressingModes.h
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMFrameInfo.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMJITInfo.cpp
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMRelocations.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| 081ce940e7351e90fff829320b7dc6738a6b3815 |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMAddressingModes.h
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMFrameInfo.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMJITInfo.cpp
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMRelocations.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| fc643c5e88c596f217750dd91fcc66488dfed73d |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
remove attribution from lib Makefiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45415 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 80455b86f2c6c56b56f690db3c1fdd3a401f9df3 |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
remove attribution from lib Makefiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45415 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 6e141fd04897e5eb4925bb6351297170ebd8a756 |
13-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| e399fbbd8e53d83a50781b790d15de2a5b89373c |
13-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrVFP.td
|
| 1713d8bcfffe1ed26920a09012dbef4587930a94 |
08-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Doh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44694 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| bd08cd5dce3bf8d1835bb19653adcf097acb0a9e |
08-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Doh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44694 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 7658445fa64d2e044e84e98e19a3cbec8023f186 |
08-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a compilation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44692 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 4b181c182a31665ab8880be7049c02c8d3631bc7 |
08-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a compilation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44692 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 |
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 2af4a6c288939754c302cb397c3c334dff6def41 |
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| aee4af68ae2016afc5b4ec0c430e539c5810a766 |
02-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove redundant foldMemoryOperand variants and other code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| fd0bd3cd6b680605c609ffba12c0bbe997edd6e5 |
02-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove redundant foldMemoryOperand variants and other code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| e62f97c094dba44e4c259d20135167fa91912eea |
01-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.h
|
| ff52f082846db6a31d73cb6f02f62401e20eda6f |
01-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.h
|
| a3f61df4ff4549da3cef1ae70427a4c8ca858c69 |
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
several entries got significantly better, though they still aren't done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44382 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a1688ed618e869edb078fc96603aeb585cdef2bd |
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
several entries got significantly better, though they still aren't done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44382 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| f1b1c5ed1a91cf23cfa65a24caefce6235d2fed3 |
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
implement a trivial readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44380 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
EADME.txt
|
| 900cddb8a857e83bbae92ccc7eec11f6b68193a2 |
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
implement a trivial readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44380 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
EADME.txt
|
| 27a6c7380fa4dfc8e1837a8dd67967d063b26544 |
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| dfb947d423f6355537d1a545fb8fa4fbc6dad230 |
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b97aec663b1591e71c9ddee6dbb327d1b827eda5 |
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| f5a1153219e7c91069d2ff8299434f06d465f516 |
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| c69107ca11282a905c252d1b62091951087f13dc |
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unifacalize the CALLSEQ{START,END} stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 7173da5356af8419369d41909c301de0ce52fd36 |
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unifacalize the CALLSEQ{START,END} stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 |
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMRegisterInfo.cpp
|
| 22f8debd4e886118daaa419ba6bfa0c1ef279beb |
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
RMRegisterInfo.cpp
|
| 20ab29068d8a8ec31f26f022634f1e0bc4b1da56 |
12-Nov-2007 |
Owen Anderson <resistor@mac.com> |
Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f805308b197ba190bef81bc97ae963f7ba75aac2 |
12-Nov-2007 |
Owen Anderson <resistor@mac.com> |
Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f191c80cd79ee35e47b5a4feed98d687782dfe85 |
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
|
| 26ab1b7546fbb1a7206f132ff78d77aabea56d4a |
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
|
| cc41586b9d79532172b37e1f44a9077da4b73fc9 |
09-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6fb0676d69697f38712be6843073618583d3a3f8 |
09-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| e0cb36b9fb1e1b0de9b46eafd8dc3802122b2e73 |
08-Nov-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
[ARM] Implement __builtin_thread_pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 5a87a8ae412e4c75d072c9b3936de0d25f92fca1 |
08-Nov-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
[ARM] Implement __builtin_thread_pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| f1ba1cad387dc52f3c2c5afc665edf9caad00992 |
06-Nov-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| dd867c703a1fb12d758ab2ea45aaa0e4e6be4074 |
06-Nov-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 8699a97a2ef42d349c9b81317d55ff621c459adc |
05-Nov-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
[ARM] Fix code generation for:
static __thread struct {
int a;
int b;
} teste = {0, 0};
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43722 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 7eccd2b40188dd1481bae1458d675152447823b9 |
05-Nov-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
[ARM] Fix code generation for:
static __thread struct {
int a;
int b;
} teste = {0, 0};
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43722 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ca0ed744852a7d9625572fbb793f65e81225a3e8 |
05-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Eliminate the remaining uses of getTypeSize. This
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43688 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantIslandPass.cpp
|
| 8157ef423408bd50e6712814e7792a308b5db7d7 |
05-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Eliminate the remaining uses of getTypeSize. This
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43688 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantIslandPass.cpp
|
| e0703c84ddeb1a1276de4e38210c1127ef5df130 |
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.
New I just have to move this to a common place :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.h
|
| 948da40ac9a3c2677ecb44fcbca7a7306f36e761 |
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.
New I just have to move this to a common place :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMSubtarget.h
|
| fc05f402ea22e8a9ae465d209b65be7e857a89ff |
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.h
|
| 7afa9b19ace1d714b7f36e88388dbc4ea8c3fdbb |
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMSubtarget.h
|
| ca4571e79fc4298197c2a9521a0e855b0a280118 |
25-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Support non-POSIX hosts by removing use of strncasecmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43364 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 3fdb202b827b5282698a0480110954b36908f9a5 |
25-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Support non-POSIX hosts by removing use of strncasecmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43364 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 4102eb57bbeecbbf5b5b5122ed1ecd4cd5487878 |
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
EADME-Thumb.txt
|
| 857b89ee805e84560a48242eca2354730bd2892d |
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
EADME-Thumb.txt
|
| 7b73a5d6dead3fa765cdde8316a19ac8930cc60d |
19-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43176 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 0ec733ad5fdb07d546c0b6e9b9ae418a1aa2b47c |
19-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43176 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 3a7c33a853b03d9dcde400b9d58e02c25d9789db |
19-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Add an easy microoptimization I noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43164 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 01eb72865796b7ed946f020d8f91c60105b6c445 |
19-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Add an easy microoptimization I noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43164 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| f0a0cddbcda344a90b7217b744c78dccec71851c |
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 8fc1fa2edefe0076e298dd86c76f5325d7342f15 |
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 58184e6878fdab651bc7c9a59dab2687ca82ede2 |
18-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 812acafe223f459fc280bbe180340704ab65bf52 |
18-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| a4c791072f65b44b069a8acf17f85a3849cfb36d |
18-Oct-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Fix a misnamed parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43145 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
|
| bad085b5560ddb36bf2358c254eeab821241abe9 |
18-Oct-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Fix a misnamed parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43145 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
|
| 65a3323b0a1369067be131c3d3fe8442f5ac2df3 |
18-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
legalizing the ret operation on f64 shouldn't introduce a new
i64 bit convert needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43116 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 72d66ad57ecd65aee2abf2122b205ae5f5f1a1fc |
18-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
legalizing the ret operation on f64 shouldn't introduce a new
i64 bit convert needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43116 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 347d39f1fd8ad825a7ec5b8a3dce816723a56d42 |
14-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Revert 42908 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42960 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 477013c1dda38cf918e259e972998664008da616 |
14-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Revert 42908 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42960 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8ddde0a151c5297ae5694a4b9201b2d3fe56b196 |
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Change the names used for internal labels to use the current
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 36eb6b7103ccca77ac51754a2265340ce9a2a8d7 |
12-Oct-2007 |
Dan Gohman <djg@cray.com> |
Change the names used for internal labels to use the current
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f96e4de403453e57aea75bcac1ed99af686d33c4 |
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 2f7b198c0bf4fd2518f310f5faed165808b96d15 |
12-Oct-2007 |
Dan Gohman <djg@cray.com> |
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 525178cdbf00720ea8bce297a7d65b0cca0ab439 |
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 5a199558c23d400e3dd83a9c7cab754c77778956 |
08-Oct-2007 |
Dan Gohman <djg@cray.com> |
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
|
| 66f0f640820b61cf9db814b6d187bae9faf7279c |
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 535f993076a90e8c68f078c203b7e001f0ceb035 |
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| cb406c25973b4e88a6c10ad839ef1beeb3664715 |
03-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Use empty() member functions when that's what's being tested for instead
of comparing begin() and end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42585 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 3f7d94b6cd40a3653c000f4b2e166c82dc3e3715 |
03-Oct-2007 |
Dan Gohman <djg@cray.com> |
Use empty() member functions when that's what's being tested for instead
of comparing begin() and end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42585 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| cd8bc05102e7963a5839cfdca7785390288bc745 |
30-Sep-2007 |
Gordon Henriksen <gordonhenriksen@mac.com> |
AsmPrinters overriding getAnalysisUsage should call super.
And not super's super, either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42482 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 76e4b61dfd89698438a8b654194eb11b719dcc36 |
30-Sep-2007 |
Gordon Henriksen <gordonhenriksen@mac.com> |
AsmPrinters overriding getAnalysisUsage should call super.
And not super's super, either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42482 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 9efce638d307b2c71bd7f0258d47501661434c27 |
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| b3d91cfa10387517c305f75a8220d192f7d133cb |
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 677ccc6e8b912e1a39259952b125954820062541 |
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42316 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.h
|
| cdd820b52b570a69ac4ca251fb701300c6e1db4b |
25-Sep-2007 |
Dan Gohman <djg@cray.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42316 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.h
|
| 76a4023096fc330db11d711197388d9f3ba91cc6 |
21-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Honor user-defined section specification of a global, ignores whether its initializer is null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 65c0fbc139b210f10c7af2bb788f2d252981a62b |
21-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Honor user-defined section specification of a global, ignores whether its initializer is null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 17207ddf38b92245d6eda9e58cf9bf75f2a88e80 |
20-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enable if-conversion for ARM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42156 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| cd497f4be825a3389ab7b338c07993782afd69ff |
20-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enable if-conversion for ARM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42156 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| e71bff7405392ad5904f986724a65f965c0686e8 |
19-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Avoid referencing deleted instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 11948d6b2065509c4ad3fdae58da10bfd3b13e90 |
19-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Avoid referencing deleted instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 92dfe2001e96f6e2b6d327e8816f38033f88b295 |
14-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 38a9a9f8be9243cc958662832067ac17f7bd4558 |
14-Sep-2007 |
Dan Gohman <djg@cray.com> |
Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| fe4afb17d3370a1c3d4945d6558de544462b4ce6 |
12-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Enable indirect encoding for the personality function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 909ec5692e77f3c580135d896188f0135abe0683 |
12-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Enable indirect encoding for the personality function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 071a279e94e30d51aff3b46a4651d686982488a0 |
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 6e4d1d95040e884712107be256969625e76c0078 |
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| f7331b3dd72409e644833ecaf62a0f6db03c97ee |
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 7407a9f0ce838891356c1faf3d52e1dacf4e5365 |
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| be36798bfe473b13bcb361f44f63aeb129892a2a |
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
80 col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| cce0af5eb3131d9d7ac9ac898bcf755cb644cefb |
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
80 col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bf8ae84a21011a7263c2a4183fdfd8e5755765a1 |
10-Sep-2007 |
Chris Lattner <sabre@nondot.org> |
Add some notes about better flag handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4084d49e2baf19cf47ee90fd0a54f7d00b008ab6 |
10-Sep-2007 |
Chris Lattner <sabre@nondot.org> |
Add some notes about better flag handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 718cb665ca6ce2bc4d8e8479f46a45db91b49f86 |
07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 1636de94069d492185da2dd36859d4a1962a2eed |
07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| eaf089430e7681fcddc3465c3b33b9645273ab02 |
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| df8a831eb0f35fad163b2e45212f8154a17bbd36 |
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 8c132633c86a7e496f84e3458c47520d0cc4d938 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
Instruction formats added used to generate multiply instructions of V5TE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41629 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
|
| 85f456100c0a6dea1475c91dd358e4d9a81eb151 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
Instruction formats added used to generate multiply instructions of V5TE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41629 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.h
|
| b94e60872e97a527b090e20c7d5cb4404437a4dd |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
Unused relocation type reloc_arm_absolute removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41628 91177308-0d34-0410-b5e6-96231b3b80d8
RMRelocations.h
|
| 52530dbe53e6835b1dca46defecc38bd1bea3330 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
Unused relocation type reloc_arm_absolute removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41628 91177308-0d34-0410-b5e6-96231b3b80d8
RMRelocations.h
|
| 9c1a3827cec76ee9c489662115906939f3de5d98 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| d8dc8c5ffcd9d787ccdd8b48c1ebcee8870bfc01 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
|
| 37fb5b154cd30be540ecdd08873a9e10f27a3613 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2e07e8d2ff30dda3296e3dc9de481a84fca6bc86 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d05c04c1692d4630e43fd4f22bba37edbe701258 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
JITInfo now resolves function addrs and also relocations. It always emits a stub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41625 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 72551daeaad642f5bb9318d269bc0b7834381ef4 |
31-Aug-2007 |
Raul Herbster <raulherbster@gmail.com> |
JITInfo now resolves function addrs and also relocations. It always emits a stub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41625 91177308-0d34-0410-b5e6-96231b3b80d8
RMJITInfo.cpp
|
| 35b35c5c320a71e4611fe2101452da685f8eeda0 |
30-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.h
|
| 242a992fc30a1466f3ab7f4d14b2de9a6c954d5e |
30-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.h
|
| 0ff94f7fcc95112331ee0f4f3d31c90acb9f2952 |
07-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Initial JIT support for ARM by Raul Fernandes Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCodeEmitter.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMJITInfo.cpp
RMRelocations.h
RMTargetMachine.cpp
|
| a7b3e7c33f1ef7be844fde18dcd9e24afdc97748 |
07-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Initial JIT support for ARM by Raul Fernandes Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMCodeEmitter.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMJITInfo.cpp
RMRelocations.h
RMTargetMachine.cpp
|
| 61e729e2e9517ab2d8887bab86fb377900fa1081 |
02-Aug-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 3a78bbfeacce9988ff60210fd472cef9789abcc2 |
02-Aug-2007 |
Dan Gohman <djg@cray.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 7fc77611eff7c47e8c37fad58af637138e2a9d7a |
01-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Indexed loads each has 2 outputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1a9e67782d0a837f629e519817b77a657f0bf55f |
01-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Indexed loads each has 2 outputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f452207d202618f92cbc04bcc6251ecae0eb6d61 |
30-Jul-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
|
| 2914661badf625cb7253896dca2789ee54a58859 |
30-Jul-2007 |
Dan Gohman <djg@cray.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
|
| 36397f50343639ce9a25996f2d790c656791ab92 |
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 38947cd9adc03b30ff6d50d97279421c63b6f2f2 |
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b8275a3f6f6497889653cb2452d82a46f92b4926 |
25-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Don't ignore the return value of AsmPrinter::doInitialization and
AsmPrinter::doFinalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4a558a338dad938df33a3286eac0c64017fbcc38 |
25-Jul-2007 |
Dan Gohman <djg@cray.com> |
Don't ignore the return value of AsmPrinter::doInitialization and
AsmPrinter::doFinalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ffbaccae029ac238972e3814967260f029b6058a |
21-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
No more noResults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 37e7c75b491e50df2a7f3e9f5d872a48d85239a0 |
21-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
No more noResults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 8bd6035750f1b290832a3b1c90766d9b45ed8d6b |
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added -print-emitted-asm to print out JIT generated asm to cerr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 775472112da257a6558fb583d71aa850860dd8a1 |
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added -print-emitted-asm to print out JIT generated asm to cerr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| 64d80e3387f328d21cd9cc06464b5de7861e3f27 |
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| b783fa36e0770cbb5dc349e649499373185c21fc |
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 4558b807a2076e199bcb019f5edc9eabbc5922c1 |
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Only adjust esp around calls in presence of alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 8154094f225ccb52a058501b84c6fa0a51862ca7 |
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Only adjust esp around calls in presence of alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| f17a25c88b892d30c2b41ba7ecdfbdfb2b4be9cc |
18-Jul-2007 |
Dan Gohman <djg@cray.com> |
It's not necessary to do rounding for alloca operations when the requested
alignment is equal to the stack alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40004 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMAddressingModes.h
RMAsmPrinter.cpp
RMCodeEmitter.cpp
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMFrameInfo.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMJITInfo.cpp
RMJITInfo.h
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMRelocations.h
RMSubtarget.cpp
RMSubtarget.h
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
akefile
EADME-Thumb.txt
EADME.txt
|
| c3dbe70ce75e2fff00f6ea876ba9c39af4510d06 |
17-Jul-2007 |
Chris Lattner <sabre@nondot.org> |
no email addrs in file headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
|
| 2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 66a2a8f8782f55a9668c7f4200ff55b52fcddef6 |
12-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
ARM: make branch folder remove unconditional branches
following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
|
| 5d9c4b60204d741c213456e21b87e9af6a3dc627 |
11-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Fix hang compiling TimberWolf (allow for islands
of size other than 4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 8202010364e1bfe6111f1ce62f154499b80877fb |
11-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Didn't mean the last commit. Revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| c608ff22e79bf56b7227e56eb9e88fed2258b5c6 |
10-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| 13ab020ea08826f1b87db6ec3da63889a12e3d9d |
10-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 87bdba6d6a1684373c94df0363a3b620de6dab6c |
09-Jul-2007 |
Chris Lattner <sabre@nondot.org> |
The various "getModuleMatchQuality" implementations should return
zero if they see a target triple they don't understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 9ad6f03166b9ae169f1c9e3fe229cae1e0f94d7a |
07-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
No need for ccop anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 4b9cb7d135fbd0fbecbf8579d741e15e4b02f176 |
07-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Incorrect check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37962 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 06aae67b8315aa915f55abd5927453dbe8b11169 |
07-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Do away with ImmutablePredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| dfb2ebac29f92a533218bd576734913a89d1299d |
06-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Print the s bit if the instruction is toggled to its CPSR setting form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37932 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 04c813d00ced172d9fbd26aa610e0992846a40bd |
06-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
PredicateDefOperand -> OptionalDefOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 148b6a419fbb20e2224a1b92c499d51513b9bc27 |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Initial ARM JIT support by Raul Fernandes Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMCodeEmitter.cpp
RMJITInfo.cpp
RMJITInfo.h
RMRelocations.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| d54874a06d1bc67248fe3b5d990acd6e8a61d2ff |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a99be51bf5cdac1438069d4b01766c47704961c8 |
05-Jul-2007 |
Gabor Greif <ggreif@gmail.com> |
Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0e1d37904abbf7e8c4c478408253dd995f3040f4 |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Reflects the chanegs made to PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
|
| 16b6598325aced8a05ae8c87685d160fe3ad6e66 |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added ARM::CPSR to represent ARM CPSR status register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| ee568cf7948230b78303b86c92722c177d3a5673 |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c85e832eb7193b2a67b1159e00db8d89df714142 |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 3b5b8368f3867bc7e2fde4e12a1e0dfe62e54f1e |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added ARM::CPSR to represent ARM CPSR status register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| e644ef7b098460ce831220c780cbe25eaef3fb28 |
29-Jun-2007 |
John Criswell <criswell@uiuc.edu> |
Convert .cvsignore files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
cvsignore
|
| e2446c607611ce868857d9b853aa8703bf0da4b8 |
26-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Silence a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37737 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d45eddd214061bf12ad1e6b86497a41725e61d75 |
26-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
|
| 0819a9d386e2b690abee8ae779c8ba84639ec664 |
22-Jun-2007 |
Owen Anderson <resistor@mac.com> |
Fix the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37705 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 5411835165429dc409012adc5efaf92c4938563f |
22-Jun-2007 |
Dale Johannesen <dalej@apple.com> |
Quote complex names for Darwin X86 and ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37700 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 97e604e7d861cfdfba9fcf720854a3399729bef0 |
20-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Be more conservative of duplicating blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37669 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 277f0741c5ea123b30360c382a153df238c31cae |
19-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow predicated immediate ARM to ARM calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
|
| 82a87a01723c095176c6940bcc63d3a7c8007b4b |
19-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
|
| eaa91b0a1fc68984aae51f3c4b0cf29b38f89dac |
19-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
|
| d42e56e166761d79201f09eeb4ab782e3097bfcd |
15-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37606 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 13e8b51e3ec014c5d7ae83afdf3b8fd29c3a461d |
13-Jun-2007 |
Dale Johannesen <dalej@apple.com> |
Handle blocks with 2 unconditional branches in AnalyzeBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 |
08-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a utility routine to check for unpredicated terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 61718a6285a4f140cab530bcc07c6492902dc710 |
08-Jun-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Define AsmTransCBE for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37527 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 1fc7cb695c0278e7d5f220e2e287d68430d19e37 |
08-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARM condition code subsumission check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37517 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| f81dea45b574e8c6505e330d602c27add9358b88 |
08-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
tBcc is not a barrier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 9328c1ac66397775be850b6d2b64fa8a8f4aca6c |
07-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37484 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 2c614c5c699fed503b93e85ea0cb48811843c3c7 |
06-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mark these instructions clobbersPred. They modify the condition code register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 5e148a37d3432f83ccc4dbebe08d4f1b4717034c |
05-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Print predicate of the second instruction of the two-piece constant MI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37437 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 341dcccb4e1f190f4aee12e92c2b7c2cb68c520d |
05-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
PIC label asm printing cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37434 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c621ae7bba11f98163633bc6dde41f9e8a326a78 |
02-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
update this entry, now that Anton implemented shift/and lowering for
switches. There is one really easy isel thing here with tst we are not
getting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| c354334ac4c7854d5b8649f92339ce3bedb90c81 |
01-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 144fd1ff0f1548ec9c4e835dec19ac2d5e46e902 |
01-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Set ARM ifcvt duplication limit to 3 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| df4da14948dfbc567831f3af4f6ef913c4dd12ad |
01-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make jumptable non-predicable for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3a4205367dc845d4cd804b47e061f8281777c9da |
31-May-2007 |
Chris Lattner <sabre@nondot.org> |
Fix the asmprinter so that a globalvalue can specify an explicit alignment
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37373 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c6f2f6fbb9e6a30ab83fe47c70150444eddf34bb |
30-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| fd488edb1de9710ac6ec69f93f6494589b372433 |
30-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 62ccdbf0b3b75661bcdb20476609fece499c767f |
29-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add missing const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 69d555611aa1b7e45fc1b3719bfcb17a39dff9f3 |
23-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Hooks for predication support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 94679e66bbad22dc1a6e3e1b3f8fa9bab0db0f67 |
22-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix some -march=thumb regressions. tBR_JTr is not predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37272 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| f23b8cf239515fb09fcbbe3c4d334ca63ec6fe1b |
22-May-2007 |
Dale Johannesen <dalej@apple.com> |
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37271 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 86d4069666565b2c3b5751bc592482a0ca073bc8 |
22-May-2007 |
Dale Johannesen <dalej@apple.com> |
Add some patterns for PIC PC-relative loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5a18ebc70cadd844167b3e39e7a7a627901ab529 |
21-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| dcc50a4aeee13e5bb7aec9f6a2e5ca80ef54c40d |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| e5e7ce458a2062dd9a8b495f4d73d359e0e269de |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Silence some compilation warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9f8cbd147c0ae4ec2df0f3bbff65def0ffd784c1 |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Set ARM if-conversion block size threshold to 10 instructions for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6ae3626a4fda14e6250ac8d8ff487efb8952cdf7 |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 8dd86c14d46b2deb1e1335d495acc579d70bf60f |
17-May-2007 |
Dale Johannesen <dalej@apple.com> |
More effective breakdown of memcpy into repeated load/store. These are now
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 3f8602cf20146e9b7953c56d4fcdc586d52aa6f1 |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM::tB is also predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 02c602b333ed2a1a13a17981f3c3f2f5463d5e5c |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
PredicateInstruction returns true if the operation was successful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 75604f81b7706f7a0276c8306e944a6a6bc70aa1 |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Move if-conversion after all passes that may use register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| b5f8eff566ab35a15dcd5bf490047c7ccfcecce0 |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Removed isPredicable().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
|
| 5ada199246ec384cf4a21b4b5413703820611e3e |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| aeafca0a257f8b698a67c627c0820365cdfc85e6 |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Conditional branch is not a barrier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 2706f9771de8e90ee6379e70afedd91892bb9c8c |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37098 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 9307292ae27c125a10eabccb5a437200d831a55f |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Hooks for predication support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| 44bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4 |
15-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add PredicateOperand to all ARM instructions that have the condition field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
RMRegisterInfo.cpp
|
| 5d3d44a84815b848d4493f693a0579efcc2ce42f |
15-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix previous patch. GOTOFF can be used only when the symbol has internal
linkage or hidden visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37055 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 930d161ba23c9bd9e7dc9586742725b08a8e622d |
14-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
and used in the same module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37044 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 69642f11ed9443a0ad9c6d959739bfcbdd4f732b |
14-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Enable aliases on arm-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 42d712b3067ec14170f80d8adfc7e5ad5878132b |
08-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Switch BCC, MOVCCr, etc. to PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
|
| 356e72c4f1a90b0ff306838e8841b9b550460cd9 |
08-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix PR1390 in a better way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36916 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c4e600362e0adec4660c317e0f87e4344e76f139 |
07-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
This is no longer needed after enabling the DAG combiner xform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36909 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| 8f57667a5d79faa3bb0644b051ed28b071659fd9 |
06-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix PR1390.
Don't spill extra register to align the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| a8e9562906cf70a3e89baaf5fe6e2f4f5cf83c11 |
05-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Add a processor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
|
| 97c9bb5cc6c2f936493ae5e8f577ecbfc1f750ce |
04-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36718 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bdc9869dbfa40579236405db73897a9fd19d1ed0 |
04-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Should never see an indexed load / store with zero offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36714 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 4ac075c859ec0b03d61229bca3517a6801ac63ab |
03-May-2007 |
Dale Johannesen <dalej@apple.com> |
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrVFP.td
|
| e8e5495474d67cd5151bd88e502be3f46ace7a85 |
03-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Debug support for arm-linux.
Patch by Raul Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36690 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelLowering.cpp
RMRegisterInfo.cpp
RMTargetAsmInfo.cpp
|
| 388488d604a63fc25d5f6b2c598f7cc4499c9db5 |
03-May-2007 |
Chris Lattner <sabre@nondot.org> |
add support for printing offset from global
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36669 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0b0a9a90a423efb91dd4efdfd866ad37aa72ee8e |
03-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36663 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 1997473cf72957d0e70322e2fe6fe2ab141c58a6 |
03-May-2007 |
Devang Patel <dpatel@apple.com> |
Drop 'const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| 72939126d43901e3d922535be4e12ef8ebf31611 |
03-May-2007 |
Chris Lattner <sabre@nondot.org> |
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrVFP.td
|
| 3e15bf33e024b9df9e89351a165acfdb1dde51ed |
02-May-2007 |
Devang Patel <dpatel@apple.com> |
Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| 67cf561b7fc59e050709401de184e456440a2d52 |
02-May-2007 |
Dale Johannesen <dalej@apple.com> |
Add some support for (Darwin) code-generating directives in getInlineAsmLength.
Support is incomplete, but more accurate than gcc's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36634 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 794fd75c67a2cdc128d67342c6d88a504d186896 |
01-May-2007 |
Devang Patel <dpatel@apple.com> |
Do not use typeinfo to identify pass in pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMLoadStoreOptimizer.cpp
|
| 1b201684333c501e2f47178e1a4df68cd894c49d |
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Doh. PC displacement is between the constantpool and the add instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 97de9138217d6f76f25100df272ec1a3c4d31aad |
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
eliminateFrameIndex() change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 5c3885ce8e6a3dc69913b50fe6bdc0c89c5432d5 |
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Under normal circumstances, when a frame pointer is not required, we reserve
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36607 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 9118dbc7bd82a2f8a3c3d5fd38d3265afb6a5774 |
30-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
Remove item: thumb padding in constant islands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36586 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 23c968478ea7e9e06eb322b8042711266a3b95db |
30-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36585 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 0a1817392d3ad7ec2681e6bf495f490c443ec0b7 |
30-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Enable protected visibility on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36583 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetAsmInfo.cpp
|
| 8593e418555fdae21a070357fd8734b4069c17d0 |
29-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
Rewrite of Thumb constant islands handling (exact allowance for padding
around islands and jump tables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36573 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
|
| 8650199fbb192c054f85647843b89e1182855718 |
29-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
Make ARM-specific version of getInlineAsmLength
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36572 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| caa8055cf54c9e633b06d7d3433e5345e3ca982a |
28-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
change per review
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36519 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 25c1f9e125583fda422d11189a86bdf93a0e7386 |
28-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
Prevent Thumb code from generating ARM instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36518 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4c6d20a096ad28aa6f812c07a48268e8a6ccb8fe |
27-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
add parenthesis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36514 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 185ea1e2aad88b13c3978197851da078601afff3 |
27-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Doh. ARM::LEApcrel is a single instruction MI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36513 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| fdc9692f9763a7ffd1bbcadc01445db33fb468de |
27-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
In Thumb mode, the frame register must be R7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36512 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 64f4fa5e0eb505eec3a72041bec6b3a7f7739ded |
27-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
RMTargetAsmInfo.cpp
|
| b1df8f2750cb8df55f7e15985ef5c86f9092cbe1 |
27-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin runtime library does not have these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36505 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 768c9f725bda048b3406b6289beb586ff6e933df |
27-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Special handling of LEApcrel and tLEApcrel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36504 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| eec041a037a5dffadbc27af1d0e714e76079f06d |
27-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Back out previous check-in. Incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36503 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 33fdc983fdda96bf68f184cd44726e66a4cfacff |
27-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
tLEApcrel is a AddrModeTs, i.e. pc relative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36502 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| faa510726f4b40aa4495e60e4d341c6467e3fb01 |
26-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36483 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
|
| 6c087e5585b227f3c1d8278304c7cfbc7cd4f6e8 |
26-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Match MachineFunction::UsedPhysRegs changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 305b8a5f62c9d027f3d8a870fc12fc2abf69aeea |
25-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
remember to emit weak reference in one more case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36438 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 1e341729dd003ca33ecea4abf13134f20062c5f8 |
25-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 56c42ef3e43f8eb75c435e781d0ac8251c7588a1 |
23-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining
BBOffsets and BBSizes when adjusting conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36372 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| bd24f3f398bc26d686836dc412f3c1997953f427 |
23-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
add Align field, and use when generating function alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36371 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMachineFunctionInfo.h
|
| 24fb52da3c797eaa9dc6315ef8c4713ed556daa0 |
23-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
add isThumb (unused as yet)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36370 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 0ae4a3357a556261f25b1584a2d9914637c69e65 |
22-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Implement PIC for arm-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36324 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMISelLowering.h
|
| ba647becb98fbb01cc02aa6a522971a639ea2534 |
20-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Specify S registers as D registers' sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 93305bc4620c12042b11a5e721feda7892d2f65d |
20-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
add a crazy idea
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36273 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 267bfb553e3ab44de2d4bac2866afc6de808c3f8 |
19-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix a bug in getFrameRegister.
Reported by Raul Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36262 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 120fba91a3d894daaa9317474b51e1fed8577a83 |
18-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36222 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3c30d10b0484349d837d21490181600f5ebee6cd |
17-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36203 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bed2946a96ecb15b0b636fa74cb26ce61b1c648e |
16-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMRegisterInfo.cpp
|
| 5a3d40d88fbfe79ad7ed5802ff4fd1498c4c820b |
13-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35962 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e11529438cd825935410750881f6dd6b04806db2 |
11-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35909 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| eb13d1b710c385437f30f944de44a5b7053069f3 |
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
restore support for negative strides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35859 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 37caf8c68e71333b6d1a663efac088439681ad45 |
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove dead target hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35846 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b445d0cbb9b299ba8ec7be2494e35c501b6d3a93 |
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead target hooks, subsumed by isLegalAddressingMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| e21e39666e8a41ffd4971d8bb023b70b59297267 |
04-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implement inline asm modifier P.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35640 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0a7baa24d17be1a3f4dc5bca53bc89a30dbc24db |
04-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35639 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| ed884f3a2f7225a0ea40fc18964b6f949cac3680 |
04-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove unused constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35635 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b03eacdbf39b37a98b65b936046b22cca8215d8d |
03-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fixed a bug that causes codegen of noop like add r0, r0, #0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35627 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 3c5ad82ba2b4c1ebbed7f1c4594c245f57ae08e0 |
03-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Inverted logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35619 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| b2c594f350c13f7faa263dfeba93d81b6ed964e9 |
03-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Arm supports negative strides as well, add them. This lets us compile:
CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35609 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| d959aa421a8d14fc5aad29141f816db8f4362c7f |
02-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
fix off by 1 error in displacement computation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35602 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6e0784da77672df0263b6291490c5df5dcadd56e |
02-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
to be folded into non-store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35601 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c4e3f8e736ecea7cd44a0fae75b1b3092567cbcd |
02-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
add support for the 'w' inline asm register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35598 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 9996663fc6d50128a4897ff3568d311496e9d944 |
02-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
- Divides the comparisons in two types: comparisons that only use N and Z
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
|
| 3074d9df96b1b5fa3920672ef7555d3fbbc5bb65 |
01-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add i16 address mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35551 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c9addb74883fef318140272768422656a694341f |
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 87c6c9abb3c0c19cb172a3cf3cc3de79a03b02f7 |
29-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35480 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 5e3c203cfd460ffa60341fb555fba6162abcbe61 |
29-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35479 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 616cc663daf965695809213d8cf8e3686e5309c3 |
29-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add support for hidden visibility to darwin/arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35448 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| caaf69107ece8bd9864fed4d64e2a84fa5f8cd4b |
28-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove isLegalAddressImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| b8a93a45f8db0ff507c3833c88f24d5fcd9b2ed4 |
27-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| f6fa5ee5c201f91217c3034ddcaecb63e7d8cd5a |
27-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
findRegisterUseOperand() changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35366 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMLoadStoreOptimizer.cpp
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| fa4bce2b76c8557cfd0794beef86efe5fb0087fa |
21-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| a125cbe839398f7df475e322bdaf150c62a1c8c3 |
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35229 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8e59e163db8cd3e7b4c96e438fbedf78bff06707 |
20-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
do not share old induction variables when this would result in invalid
instructions (that would have to be split later)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 64c88d741e51281edc15dcfc27dfaa500a89d43b |
20-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
mov lr, pc
bx lr
So, the function was not called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| c70d1849b7b85b06adf7dce856b3b19028fff8f7 |
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35207 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 5603dcf21e3227e457624e9ff895f4893ca81528 |
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35206 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| bf2c8b3c96f5c885095a10b0fcb29438f92d73c2 |
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added MRegisterInfo hook to re-materialize an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 1719e13da087914ccad3906d5cf8a4e92ba386eb |
20-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35202 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 80dae195c75a3ef38854645ae3cf41f8ae835644 |
20-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
fix obvious comment bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35196 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.h
|
| 9f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5 |
19-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMInstrThumb.td
RMRegisterInfo.cpp
|
| fa775d09c6bb506cf0696e0d688cafcb74955702 |
19-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMInstrThumb.td
|
| a251570417bd49b3dfebbc7ad6b2b806aac05df4 |
19-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Constant generation instructions are re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMInstrThumb.td
|
| 368f20fda4a1cb9afdc2788a754b9ffe59afd391 |
16-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Only ARMv6 has BSWAP.
Fix MultiSource/Applications/aha test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35128 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 277074721680253b151efd49d0263a07fafbec3d |
16-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added isLegalAddressExpression(). Only allows X +/- C for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| a13fd108f2c77adc60045859f1df4923b59a9d10 |
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 961f879ed8642e63db712d0528680a48076fa760 |
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Zero is always a legal AM immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35087 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| e8308df0b9b34089bb6040f6902ba121441bdf3e |
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implement getTargetLowering() or else LSR won't be using ARM specific hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35077 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| b01fad6d19ac83f9c97eee16af438507383f36d8 |
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMISelLowering.h
|
| 1a9da0d66cbb7742e60ed957a7670a6547911de1 |
09-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35049 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 44f4fca3c02da1c3c90e99af08692003fabf2e45 |
09-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add comments about LSR / ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35048 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2265b491931554eb59edfa1c2cfbda64b2e5de1b |
09-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Unfinished work and ideas related to register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35047 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 818c085232ef44d0e5afce529c5c669e3712b43d |
09-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
apply comments from review of last patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35045 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a6bc6fc170b0fed4b1426caba1a3b58a55ca5164 |
09-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
Add some observations from CoreGraphics benchmark. Remove register
scavenging todo item, since it is now implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35044 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 23a95704949b99ca07afe45c6946d0fa26baf9f3 |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implement inline asm modifier c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35035 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b582b1b1fcbbad4295fd75f49be6dd0596df910f |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35030 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 032953d74746fa89b62e49b63a38ba6d8827b81a |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Putting more constants which do not contain relocations into .literal{4|8|16}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35026 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| bf822eb6a38d62ab8623fd860c654820e69aea6d |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change register allocation order to Dale's suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35021 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 11788fde93fb74636aa333b2910d606d2c19ba9e |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Bug fix. Not advancing the register scavenger iterator correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35020 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 98ded765c2dc2f256e9f11502ca302f2b24f31e8 |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35017 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetAsmInfo.cpp
|
| 603b83ebcdfb9c27e44c1da16f2799755e3e3022 |
07-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Only safe to use a call-clobbered or spilled callee-saved register as scratch register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35010 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| d0b82b301d700217a716526f9329bb031e0d6578 |
07-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35008 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| cb20998b3f853f8ce78485941225310697b9e5ea |
07-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM always use register scavenger. No longer reserves R12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34999 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 0ea12ec8484c45ca1394f3b2dcd39c9a34cf2ab9 |
07-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34998 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 3d06cf4584b44ea8c4a49778c2b61f8990692157 |
07-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix one more Thumb eliminateFrameIndex bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34990 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| e6257632fc2cc79a76ff0b5ba213f6ba2a7c469a |
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Register scavenging is now on by default for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34987 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| a90f3408b3aca71cd438efa2c539af041430e059 |
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make load / store optimizer use register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34986 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| cc1c427266817e0f41cbb9d0dc97a52890182040 |
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. Prepare to use register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34976 91177308-0d34-0410-b5e6-96231b3b80d8
RMLoadStoreOptimizer.cpp
|
| 140e33cfd1386b65bc936c7346d1b1cb72b26cae |
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Scavenge a register using the register scavenger when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34966 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 1d9baccc9b4d664a944f82eef9f708125e3f1552 |
06-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use new SDIselParamAttr enumeration. This removes "magick" constants
from formal attributes' flags processing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34963 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 6d7dd8ef46e9a505ddfb7d02cb2566560afec43d |
05-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS.
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34931 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 9f8e50d4ed7dcc5ca0f137830ff1185b2afa38bf |
02-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
eliminate unnecessary reset of SP in epilog on darwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34824 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c1c2de0ae7abecb4120dd28f722a2b73319b0cd8 |
01-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use a spilled free callee-saved register as scratch register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34785 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| f49407b790d8664d8ff9c103931b115ebe9cc96e |
01-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Track which callee-saved registers are spilled.
- Some code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34783 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
|
| cda067bad95654d970e14d3555f4aa685e5ebcae |
01-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Switch from std::vector<bool> to BitVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34781 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
|
| f1d6006ad60e0eb28f5089a5bb407ada6bb7ef4e |
01-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Get rid of verboten <iostream> include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34777 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b71aa2b6ca801d407c702483c412a290ab4af3b2 |
01-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
Changes requested in review of last pass. Also pulled isThumb into a
member, instead of resetting in every function that uses it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34764 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| ad78ef215485389bb5c5698fa6f1ac670f0076d8 |
01-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Doh. ARM::PC is obvious a reserved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34763 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| f1b214d3ca12f2d85f0d092b4920172bcc797bac |
28-Feb-2007 |
Dale Johannesen <dalej@apple.com> |
Add intelligence about where to break large blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34755 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| 36230cdda48edf6c634f2dcf69f9d78ac5a17377 |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make requiresRegisterScavenging determination on a per MachineFunction basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
|
| 41a4d562f73ef9899998e30c874c5549ecd0cd04 |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Temporary: make R12 available in ARM mode if RegScavenger is being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34709 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 1b051fc6a491c40cf3f926c089ad082938b653f0 |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Start making use of RegScavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34708 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 5e6df4647e15c50daea9a8a4e7f4f417a266335c |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.h
|
| 15991bf775234d4d5c25510fe8703b4751bd31d1 |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34701 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 5ef9226f30d0615558cdfc6a2b76c7a914a8e32f |
27-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34692 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| ce74de46dd2b1ca040bc5d2e17af64832bc0b633 |
25-Feb-2007 |
Dale Johannesen <dalej@apple.com> |
cosmetic changes from review of last patch. obvious
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34598 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| 598270a68d162ee28cf5033b8cef236fe7ee767f |
25-Feb-2007 |
Dale Johannesen <dalej@apple.com> |
remove crediting of Evan Cheng and me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34568 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 99c49a4b94ffabdd22f55e8274c7f92892e25559 |
25-Feb-2007 |
Dale Johannesen <dalej@apple.com> |
Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this
from README.
When no water available, use end of block if in range. (More to do here.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34563 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| acdfa445ac370cbf392234e9176c98f46bb3f672 |
23-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
bugfix: SP wasn't updated for varargs when frame pointer was eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34537 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 600c383e5c96d4b107b3e6ed4515eac25246cb02 |
23-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix stack alignment in functions with varargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34532 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 88e37ae36652546c8e409cab69a1777af63cf095 |
23-Feb-2007 |
Dale Johannesen <dalej@apple.com> |
rewrite of constant islands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34523 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
EADME.txt
|
| 04321f70f5075673934d5b1ed3353dd15d911183 |
23-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added -march=thumb; removed -enable-thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34521 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
RMTargetMachine.h
|
| ead75905813e175898677cb8c4e4cc919ad2782d |
23-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add option to turn on register scavenger; By default, spills kills the register being stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34514 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 2ad9f17fee5d6395cd8db81668853e6dbf94060b |
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| b371f457b0ea4a652a9f526ba4375c80ae542252 |
19-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| a284cbf667e11660840dc7bae3ee9eeaa3c7cbd2 |
19-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1207:
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| eceada67286f0d8081c23aedd242f4deeffa85ad |
17-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added getReservedRegs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| d2b7cec527a0efa552628378ebca7a8ca63bb45d |
14-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Generalize TargetData strings, to support more interesting forms of data.
Patch by Scott Michel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34266 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 75016059889ecf571e6159c5812dff40781ac5bb |
13-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Add space between // and the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34246 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 3630e78db9268dbe81a9369a33e49b857804f2ec |
13-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Add ABI information to ARM subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34245 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
RMTargetMachine.cpp
|
| 876eaf1135b40869f59fb27c87a7d626459e9181 |
13-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34241 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMTargetMachine.cpp
|
| e03cff6812ac41598e2bca7854985dc821a07f44 |
10-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
These vectors are frequently large. Use std::vector instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34109 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| c99ef085b90b32952b484e8843fb66ad65215b61 |
09-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add reference counting to constantpool entries. Delete the unused ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34105 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| bd8251a9a6d4f90065b52e04d15120bc111e56aa |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
isLowRegister() expects input is a physical register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34013 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 403e4a4725af21c267d4189fe88bc48bd438b08c |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Rename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34011 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 5ebd10e5ac6f7746f228da3e37729760a1903a1e |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
If sp offset will be materialized in a register. Clear the offset field of str / ldr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34010 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 8fdbe560a0bc600121f1f2de10638c7b5d58a47a |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of references to iostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34009 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMRegisterInfo.cpp
|
| 2ef02a220e3f949ebd18948ebb5bea34dc18b652 |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34000 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 8bed6c968fd7164222bc0cf4b86686c88381c3b8 |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
In thumb mode, R3 is reserved, but it can be live in to the function. If
that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33999 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
|
| 1f253d6e97f6be21210d03b748c07954313605e3 |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33998 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 7142f8755a07512d909d288f74a3f1ffa9c1411a |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
- If fp (r7) is used to reference stack objects, use [r, r] address mode.
- If there is a dynamic alloca, in the epilogue, restore the value of sp
using r7 - offset.
- Other bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33997 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| a01faf4a7ac34b2b89c93d62d3159a5c9c421149 |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33975 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 8e59ea998f1357768aa43cb00187e6c1c1a1cc7e |
07-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Spill / restore should avoid modifying the condition register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrThumb.td
RMRegisterInfo.cpp
EADME-Thumb.txt
|
| 8c1a73ad3ffbc121a251b93b0fb4e64187f90645 |
06-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Select add FI, c correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33960 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 40984d7449c80a3d0365d31f25dff451fd54f060 |
06-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33958 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 88b633165a20398d1015eec561856500fcf30d7d |
06-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
eliminateFrameIndex() bug when frame pointer is used as base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33945 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| ad0e465889d49f423436dc56d50c838df2672133 |
06-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Store val, [sp, c] must be selected to tSTRsp.
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33944 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b38cba928ee64849a950026be5e6162e48d83992 |
03-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33832 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fc4034259f8424364d8622f579335c421c9615bd |
03-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33831 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| bd5d3dbdbe46c7325545a7cb8c891c0347375451 |
03-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Branch max. displacement calculation bug.
- Add debugging info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33811 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 4642ca6589d3002861963744a157169f15d1ee90 |
03-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
bugfix: SP isn't resetted when function has FP and there is no spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33800 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| a21335dd763ab98ef3cf98e7a0573367c6dc845f |
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Another thumb large stack offset codegen bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33795 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 05cc424082f797c5820b19f29f398c9cce9b9928 |
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use MBB.empty() instead of MBB.size() for speed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33789 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1dd6a606ad59847164ef92ba82d533dc645f134c |
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Watch out for empty BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33788 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| f48ae3353eafcd9f5dd26fd9d76d87674328b78e |
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Ugh. Only meant to do this in thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33780 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 2d1222c060f56909c57c7828b6cad6a3e25017e2 |
02-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33778 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9a2ef9509e76869c3d658fb3e321d9b9e9d479d9 |
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33775 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b0636156effd9a3563d905cbbfee59826c63e2a2 |
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb does not have clz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33773 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| c33f674ca3e3f9834833d7b4840157f2c92f4e4c |
01-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33763 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 556f33c6e25b9f85abccc9568974df7ecc202ec0 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Pasto. Lots of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33762 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6f46e59d2a0e66f3646db9677258876960477f87 |
01-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix .thumb_func directive on linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33759 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b43216ee4a418257ce5530c02601b77efe86c354 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Off by one bugs in maximum displacement calculation / testing.
- In thumb mode, a new constpool island BB size should be 4 + 2 to
compensate for the potential padding due to alignment requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33753 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| e0c2b6b9a8ac874c7b57e445ff1513f0e37581f4 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
.set pc relative displacement bug: label should be moved down one instruction
to just before the add r1, pc:
Before:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
Now:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
mov r1, #PCRELV0
LPCRELL0:
add r1, pc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33744 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 736cefff8551d0f76ad5d8c726fe267eb0ee22d5 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33743 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 9312313a56ca3d4d904e8f7e9b4fe152a293eae1 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Also set alignment of stack-based structs to 4 in thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33741 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMTargetMachine.cpp
|
| 9d945f78e5d26dac6778665bd7018a8fb3fd38c5 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Special epilogue for vararg functions. We cannot do a pop to pc because
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33739 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMRegisterInfo.cpp
|
| 2021abe154e3cac523755b74fc5e62a2c9dad1fc |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Pessmistically assume the .align 2 before the first constpool entry adds
two bytes padding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33734 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 5b49ab999623a0bc3ca4f2484bd4adfcbf9eb16a |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Possible JT improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33733 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 3bf12d0460cc6dcd5ad9375be9a2b05535b002a6 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Don't emit unnecessary .align directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33729 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a2e35588c669a70fdc81426df8654fb4efc1d7f4 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Handle an interesting corner case: the constpool_entry being reference is two
instructions away, i.e. its address is equal to PC.
%r0 = tLDRpci <cp#0>
bx
CONSTPOOL_ENTRY 0 <cp#0>, 4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33728 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 7588ad478aa95a7eb109034f0496f6d5a9769103 |
01-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Don't want to add FramePtr to callee save spill list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33727 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 3548006a29ea9e5b63b53c9923fff96326fdc302 |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin ABI requires FP to point to stack slot of prev FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33724 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 11a065e599ff593acbdffebba1981c88ee0a9d4e |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33723 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| 0fa10515ee93821aab035efbd39cf7cb311d639e |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb add sp, #imm requires the immediate value be multiple of 4. For now,
change preferred alignment of short, byte, bool to 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33722 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 86eb5153594b523e0b201735e14c92785d7ba601 |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33721 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 3471b60e9586c8923800b0ce1cea042efa2675e7 |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb asm syntax does not want 's' suffix for flag setting opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33717 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| c0dbec7e1038ee60b8525eb1e8e3eaa6a839bd5b |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
When determining whether a pc relative branch / load displacement fits in the
instruction field, adjust it for PC value (4 for thumb, 8 for arm).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33711 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a9b8b8d62c67e96bc4dc2ed25298c539102f8638 |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33707 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 934536dab2585079d72b0218b3d5a2ea07795beb |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
ConstPool island bug: watch out for cases where UserMI is the last MI of the BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33706 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| b5b84f92bf5b5d075cb7fa8f67fa94d062aebfe7 |
31-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33703 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 193f8508809c5eab36181f442146cb40e0182138 |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Specify the right CC for comparison libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33702 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| b6ab2547cb4e4c7b237d88ad11316a69b111f88e |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Observe -soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33699 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 0c61584d05894a5543f690803191a8b0da05b8fc |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added Thumb constpool island support.
- Islands are inserted right after the user MI since thumb LDR cannot encode
negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33690 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 36640905e1b2b2f1179845acc46f3de02f972c8c |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
During PEI, if the immediate value of sp + offset is too large (i.e. something
that would require > 3 instructions to materialize), load the immediate from a
constpool entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33667 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c60e76d139a96cc8bb7454929172cdb992e16971 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33664 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.td
RMInstrThumb.td
|
| 5cbf985dcbc89fba3208e7baf8b6f488b06d3ec9 |
30-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
confusion with external linkage types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33663 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelLowering.cpp
|
| ad1b9a503cea6f8ab850a4b9caedbfeb6fce0bb7 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Copy and paste bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33658 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| b267ca17d1351b28d597e7807b5ed398e92d65e4 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin -static should codegen static ctors / dtors to .constructor / .destructor sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33657 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetAsmInfo.cpp
|
| c322a9ac146358c09279e59846872565a8b01b50 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Misseed thumb jumptable branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33656 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 236f677e48d45847ac10614bb9923129a028a4df |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
In thumb mode, round up stack frame size to multiple of 4 since add/sub
sp, imm instructions implicitly multiply the offset by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33653 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 5b91c7f69ac2dc19edec1dbf76e5a8667c67bd28 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb eliminateFrameIndex fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33652 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| cea117d2de0bfe422641e2ada4fef160e099a6b4 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change the operand orders to t_addrmode_s* to make it easier to morph
instructions that use these address modes to instructions that use
t_addrmode_sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33651 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrThumb.td
|
| d1b2c1e88fe4a7728ca9739b0f1c6fd90a19c5fd |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- In thumb mode, if size of MachineFunction is >= 2048, force LR to be
spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
in thumb mode so it can be clobbered if it is properly spilled / restored
in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
spill by:
push lr -> delete
pop pc -> bx lr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33650 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
|
| 225dfe973bd85e36ff16fe7a08e458f285703cc9 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use BL to implement Thumb far jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33649 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 29836c330ff33e3c6a250a89b3e78abb3a1970c9 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Factor GetInstSize() out of constpool island pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33644 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMInstrInfo.cpp
RMInstrInfo.h
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 24f7fb3267e358bb589e1856d7c9cc43db5f91d5 |
29-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33633 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| 78268b943669cd0c0e1e874e2a329fcf200bd59b |
29-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remember if LR register has been spilled in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33632 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 198529aaf123ae2431840dfa4c1b84eaebf0183b |
27-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33569 91177308-0d34-0410-b5e6-96231b3b80d8
EADME-Thumb.txt
|
| d85ac4d07966a56b3101598f29393f4532acc50f |
27-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb jumptable support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33568 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMConstantIslandPass.cpp
RMInstrThumb.td
|
| 53d7dbafc35b84859f94bbbb41254d3e3a6d9c6b |
27-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb add / sub with carry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33562 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| ea9fc58bbf88163d95986f7561a2f882daf8a97e |
27-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Some asm directives fixes for ELF.
Now we can compile llvm-gcc on arm-linux-gnueabi!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33558 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 3fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60 |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Represent tADDspi and tSUBspi as two-address instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33551 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
RMRegisterInfo.cpp
|
| 44c3b9fdd416c79f4b67cde1aecfced5921efd81 |
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
for debugging and exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33550 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| fce1765a19565954b2b4629cf214b516663e7cbc |
26-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix Data16bitsDirective for ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33549 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 43aeab68a69e443c528092b4424a498d813f96b7 |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Conditional branch being fixed up is not the last MI in the BB, there is a
unconditional branch following it. Simply invert the condition and swap
destinations if the conditional branch can reach the destination of the
unconditional branch:
beq L1
b L2
=>
bne L2
b L1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33548 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 1a92d941b3541f0c361caad499d0eb37a8339453 |
26-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
If the constant pool value is a extern weak symbol, emit the weak reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33543 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b60c02e0050ab62f0c65a644cd353598d49aac99 |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
extload -> zextload
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33542 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrThumb.td
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelLowering.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
|
| dd353b8ad747a8731a191848ff5db978a70bd0fb |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
SplitBlockBeforeInstr() insert a unconditional branch to the next BB. This
is unnecessary when we are fixing up a conditional branch since we will be
adding a unconditional branch to the destination of the original branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33517 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 7755facd76c518b09ed634f383170e8f3bcafc0d |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Need to scan the function for branches even if there aren't any constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33515 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| a0bf794eb60b6795a121efcb9ff759e9e0955772 |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Forgot to update this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33512 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| c285414988ba026d01e5d8acc07a21cd06fd5732 |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add comment, fix typo, reduce memory usage, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33510 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 3df62bde9b3f2557cccfa1f18d25b57bf0477f60 |
26-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
I am an idiot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33509 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| b1cc0528232a732b337a4ba2eb0ba64d7538f1ef |
25-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix elf object definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33502 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 743fa032a781c18a03e474e0a34f013598439ba5 |
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Doh. Skip JT branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33501 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| af5cbcb809bdbd30ebacab942994721c134d16a2 |
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added (preliminary) branch shortening capability to constantpool island pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33497 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
|
| 6318ffd7361677e3b4487025538997ee01304452 |
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Getting rid uses of evil std::set<>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33496 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMMachineFunctionInfo.h
RMRegisterInfo.h
|
| 012f2d97b78e4eb9128f1d491f2c177768dbe527 |
24-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use PC relative ldr to load from a constantpool in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33484 91177308-0d34-0410-b5e6-96231b3b80d8
RMConstantIslandPass.cpp
RMISelDAGToDAG.cpp
RMInstrThumb.td
|
| e966d6415ce3a9a6ef113ea4382131f46eb55540 |
24-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow [ fi#c, imm ] as ARM load / store addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33474 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 79d4326b00e35359d38dd9b616840b27e4fc270e |
24-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Various Thumb mode load / store isel bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33472 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c38f2bc3c29337f777c48b33daa8b1d6c76c27bf |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33470 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrThumb.td
|
| a6f567c89e5e15ab658ce798600eef7f313fe93d |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin HiddenDirective is .private_extern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33465 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 367372a30c36776e31958f0dc38306f32b80aa7c |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33460 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| dc77540d9506dc151d79b94bae88bd841880ef37 |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
|
| aa3e123ebb34620757ee1ac90e1ec593412ac258 |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM AAPCS abi (Linux, etc.) requires 8-byte double / long alignment; Mac
requires 4-bytes alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33448 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| d44ecd86e749cf15f737fa9ebaf51875b762ab11 |
22-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Double and Long preferred alignment is 4 for Darwin, 8 for Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33440 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 2576f136458bda873208399e4c8a5e21ee14b362 |
22-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use bl to call Thumb fuctions directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33433 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
|
| 515674c7b66a411db4ea2fa1f5c30cd1461d3e51 |
20-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Round up stack to multiple of alignment only if it's a leaf function without alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33401 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c1c728304731fe582afba73ddbb26b1dc59f5900 |
20-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Prologue and epilogue bugs for non-Darwin targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33390 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 75e18c403e4046057cb99accb3afc7cdf6fadd61 |
20-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM PEI code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33389 91177308-0d34-0410-b5e6-96231b3b80d8
RMMachineFunctionInfo.h
RMRegisterInfo.cpp
RMRegisterInfo.td
RMTargetMachine.cpp
|
| 34b12d24a0076d588154af9910ccaaba9b983f1a |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. Use def : pat instead of defining new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33368 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 970a419633ba41cac44ae636543f192ea632fe00 |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
isDarwin -> isTargetDarwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33366 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelLowering.cpp
RMRegisterInfo.cpp
RMTargetMachine.cpp
|
| 5be54b00bdbe1abd02dde46ca2c4b0e5aaf7b537 |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Restructure code a bit to make use of continue (simplifying things). Generalize
the .zerofill directive emission to not be darwin-specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33365 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| e433ea9dce0311d918db67e32c9822e309f8ebd2 |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin doesn't support .bss, but it does have .zerofill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33364 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 1a3771e30e48b9cc21ccdc79fc9cf37ec4104b17 |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Introduce TargetType's ELF and Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33363 91177308-0d34-0410-b5e6-96231b3b80d8
RMSubtarget.cpp
RMSubtarget.h
|
| 8e1185bd5ccc00576d2a4755f0e5ea8da5abb312 |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Modify emission of jump tables on darwin to emit an extra "l" label that
delimits the boundaries of jump tables. This lets the linker's dead code
stripping optimization do a better job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33362 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 471ffaffd86c8bd48e8769c9e0c75553235deba0 |
19-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix section definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33359 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a8e2989ece6dc46df59b0768184028257f913843 |
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMAddressingModes.h
RMAsmPrinter.cpp
RMCommon.cpp
RMCommon.h
RMConstantIslandPass.cpp
RMConstantPoolValue.cpp
RMConstantPoolValue.h
RMFrameInfo.h
RMISelDAGToDAG.cpp
RMISelLowering.cpp
RMISelLowering.h
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMInstrThumb.td
RMInstrVFP.td
RMLoadStoreOptimizer.cpp
RMMachineFunctionInfo.h
RMMul.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMSubtarget.cpp
RMSubtarget.h
RMTargetAsmInfo.cpp
RMTargetMachine.cpp
RMTargetMachine.h
akefile
EADME-Thumb.txt
EADME.txt
|
| 5293e7d5d693e2e2f8f729856d6f3596b3ee244c |
12-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Don't add or sub zero to sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33142 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| a38bbf7dd3b824aab6c290aec9e03e5cfdd028f5 |
12-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Build constants using instructions mov/orr or mvn/eor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33141 91177308-0d34-0410-b5e6-96231b3b80d8
RMCommon.cpp
RMCommon.h
RMISelDAGToDAG.cpp
RMRegisterInfo.cpp
|
| ca1f66db0d151a721a18039082afa54f5d454124 |
04-Jan-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32870 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| c2b861da18c54a4252fecba866341e1513fa18cc |
02-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| 9985f9f61e1dcffcd28caa2b6a42a1347624158d |
31-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement missing compares
patch by Lauro
bug fixed by me
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32795 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 47857812e29324a9d1560796a05b53d3a9217fd9 |
31-Dec-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR950:
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32788 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 0cc2bd12d22562acaeb3813250de2fcd30bd9e0e |
29-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32767 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| da4842e266becaca6ca4b46428c277fc5fbadc7a |
28-Dec-2006 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Define StaticCtorsSection and StaticDtorsSection for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32763 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
|
| 301009a0fca8dea601d54954eaaa8fae1e055c75 |
28-Dec-2006 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Implement SELECT_CC (f32/f64) for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 6547c5598855837c5ca830aff4e3b48eb17e1f21 |
28-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
remove duplicated line
bug noticed by Lauro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32761 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a8f9f4af54bc3048ec6aa034a5dcae9a34cef5e9 |
26-Dec-2006 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
This patch defines extloadi1 and fixes an internal compiler error on
arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32760 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1a199de81322a844faee0ea242f68fe326bbd885 |
21-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix for ARM weak symbols, patch by Lauro Ramos Venancio!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32740 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 95b2c7da5e83670881270c1cd231a240be0556d9 |
19-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
eliminate static ctors for Statistic objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32703 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 3ef39ca6a119caced345e35204e170ee3ad9aa29 |
18-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
macros -> Inline functions
Lauros's patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32656 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 15404d060ba8b604c03b9223a0f2e2abcd0fdded |
18-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
move ExtWeakSymbols to AsmPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32648 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 8897a7b02e6ccd50bbcb68133e55b54ec8a2e4e0 |
14-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
avoid using a constant table when a constant can be used inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32580 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 15f17a7c4746b8533aabf7c78bde82503ad9fc9f |
14-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
Avoid creating invalid sub/add instructions on the prolog/epilog
patch by Lauro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32577 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| a898ce687a3a835ae47548101fe847ca17d85f48 |
12-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
more general matching of the MVN instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 2426775c81b32ab0f12eb15e45001303737060c8 |
12-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
don't use "ordinary" addressing mode 1 when mvn is appropriate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32482 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f64945d83c61e540a448de0d0d23cda67c92ebe5 |
12-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
use MVN to handle small negative constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 450856d01b27518e88c738ab588765879cb8b1b6 |
12-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add mvn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32454 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4dfab986ab469744a3dfdcb0e0de5bbaa3d61c53 |
12-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32452 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 796cbd87b497ef5d27815530736babc4cf946de6 |
10-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
.align is in bits
.comm is in bytes
:-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32408 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0ec729ef2d0bf7a9563ac2f2666cff37afe8c257 |
08-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
%progbits not @progbits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32376 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 1366626e08322aaecd60704d02a5d881b0826725 |
08-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add \"aw\",@progbits" to ctors and dtors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32373 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| a43f3d4c96ef2e2e2e3639ed673b6cf8879044ca |
08-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix truncstorei1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32364 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1c411dee4f406e33d70666898f62ab9ba23bb73d |
07-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32337 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMRegisterInfo.cpp
|
| 7367d05cb713d11f8ac1e0815ac6b2eb6b17088c |
07-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
make sure that we don't use a common symbol if a section was specified
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32310 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| ac0b6ae358944ae8b2b5a11dc08f52c3ed89f2da |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Detemplatize the Statistic class. The only type it is instantiated with
is 'unsigned'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 392b1b2ef3ace82b5104ba4c9280fc7957c669d4 |
06-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
print weak references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32276 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetAsmInfo.cpp
|
| d17aa4b1f17f6d3fcd9079aef239ff16cfb5907f |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
These asm printers shouldn't use assembly/writer.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32262 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 97815c6b9c789ba741106d300f94f0c10ba6d978 |
05-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand memmove and memcpy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32226 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 462af9a2e0e3667bc35203be2d14086bf14f0a02 |
05-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add support for the "r" asm constraint
patch by Lauro Ramos Venancio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32224 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 204b0c2ca06d451479a62aeca4822f8e1a942ccf |
05-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add support for weak linkage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32222 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMMul.cpp
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| f819a4999aedd00368c850c1707e7ed0d59b4ace |
09-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement load effective address similar to the alpha backend
remove lea_addri and the now unused memri addressing mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| 0d53826f3653a789cf1491c3c40a1f4a993992b6 |
08-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6e8c6493f0db238d06549368bd647e29ff3c7821 |
08-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial implementation of addressing mode 2
TODO: fix lea_addri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| 3751844b397c18ae0814fbb076583114d788e3af |
04-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead/redundant vars
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31435 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| f05696c1b5e5b77d32574f3c03f30b53b0178fce |
03-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
revert previous patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31411 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| 115bfcb574bd75c870147616472fdf69b80048e7 |
03-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add createCFGSimplificationPass to ARMTargetMachine::addInstSelector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31400 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| e931a37a4eb3e46d73ab0379dd84173dca1214f2 |
02-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
move ARMCondCodeToString to ARMAsmPrinter.cpp
remove unused variables from lowerCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31378 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
|
| 560a8d051220ca070b6550f5ee11517fe3e14c68 |
01-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
print null values in bss
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31349 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 9dca7ad78f80328abb95b3bd8a739c02a5496477 |
01-Nov-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement zextload bool and truncstore bool
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31348 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b191e0ab51174cfb86502308f520f139daa9e4a0 |
31-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add support for calling functions when the caller has variable sized objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31312 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| c35497fc2a8b984dbacede5b75b7be74c6756948 |
30-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
All targets expand BR_JT for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7ae68ab3bccb6ef2d0e4c489f0648dc5d37ae362 |
26-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial support for frame pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMRegisterInfo.cpp
RMRegisterInfo.td
|
| 0e5e3aacbe5dc069187b94896f5844f8dfbb44c5 |
24-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::VACOPY
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31170 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 3d7d39ab1549f5ab7a929ec18a3e6481862cf247 |
24-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix warning about missing newline at end of file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31162 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
|
| 578e64a041ab2c199d37fd6346eb34b9e9c2e9ed |
24-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement uncond branch insertion, mark branches with isBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31160 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
|
| c391d16b498ff7401d815c72154f4ced1d6e212c |
23-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement STRB and STRH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31138 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| d8ed7f8cde5e56eff4692303af97aa6495c41ca4 |
23-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::MEMSET
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31137 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b83eb6447ba155342598f0fabe1f08f5baa9164a |
20-Oct-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR950:
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31063 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 2435786414ac5e3eccddc6dc8252421f627aee6a |
19-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
use Pat to implement extloadi8 and extloadi16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31052 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 20793115a85e4f9dc873b81f7bc32644519e9b20 |
19-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31049 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b97809c9a7a4ef681070ab1cbc7bd4fb18d34ba1 |
19-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
print common symbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31048 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 3692c7ac171de3b90b205b59e5ce8fd9f7755a9f |
19-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement extloadi8 and extloadi16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31047 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 6495bdd8d2702e23092a55bc82446db1768f3cf7 |
19-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand SIGN_EXTEND_INREG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31046 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4749aa4ea373e2928444974a761e14cf8c3b3f90 |
19-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand brind so that we don't have to implement jump tables right now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31045 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 71d94d8817edd01481c2a21625bcfafdb3874d0a |
18-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add blx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31037 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 70673a1a90e355d7b9aa552d673b81e5fa1d2c80 |
18-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add isTerminatortto b and bcond
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31036 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5f1b698aebbb5bb3dc349d287d5c85ab542860ec |
18-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement CallingConv::Fast as CallingConv::C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31034 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 226f8bc38c7d1916518602126c7091812265bf6b |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 04d88ffdb56858397427af5839202459de44e5a4 |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the FPUnaryOp and DFPUnaryOp classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31013 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| c01c87c8baa5e7dd1e11a3bacbd3b4e94ebe6c5d |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add FABSS and FABSD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31012 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3f3a6f6c3b6b178602a1246e62ed1e6c5d9631de |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
remove extra [] in stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31008 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 32bd5f4f6a374f9ab0fcbd2cf6a8561019a6fd56 |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial implementation of addressing mode 5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31002 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 0d479ecbb132e324da27b674fea5b232115fe964 |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the immediate to the Offset in eliminateFrameIndex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30998 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| f621abca9e423bd32a85519bc0b0b249807b2571 |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add FSTD and FSTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30996 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
EADME.txt
|
| 199dd67c50990a45876b871008cad0dad0f63b88 |
17-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add FCPYS and FCPYD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30995 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.cpp
|
| a605be69c3127a811793bcc0cbc65e9df79321ca |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add fdivs e fdivd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30988 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 0505be03adf561afbd8307516125da10dba8f0c4 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30987 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 27e469ef139e0b0b447360b0c37aeb0496b6d7d8 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
define the DFPBinOp class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30981 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a6f149d548bcd5f24f391fa0f9b196104db550dd |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the FPBinOp class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30980 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 90057aaeb7e0d2cc0d0cfd3d7dd59a86ad4ec4e6 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
define the Addr1BinOp class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30979 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 15a6c3e97629c61c8407b57289be53de9237b554 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
define the IntBinOp class and use it to implement the multiply instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30978 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| bb1e2fbc68f91a8df61eeca3a0ff2024b622e2a2 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix assembly syntax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30977 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 82c678b83ca996cc11fc48d5151c4a3ece7aa565 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement LDRB, LDRSB, LDRH and LDRSH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30976 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
EADME.txt
|
| bec2e38a9156aa35a200914a700de1e8d0810d80 |
16-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement smull and umull
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30975 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMMul.cpp
EADME.txt
|
| d2b5668208ac9c699be39408f68f4dee9deb90f0 |
14-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::BRCOND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30963 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6c5ae3edd3c32704991793f1ba7703d87df4f06d |
14-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix some fp condition codes
use non trapping comparison instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30962 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 33d06bcfd41447b94cd66126b948469d41f7f2ef |
13-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add FNEGS and FNEGD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30932 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5395538307ea22b55cd01776badbc8c4f977df63 |
13-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add SBCS and SUBS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30930 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 26a76d1024e944669a80dd86bcd0b81d7394a4f5 |
13-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement calls to functions that return long
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30929 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 42b62f3f81b0c38954dd64b37cbb3c995f84073c |
13-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement unordered floating point compares
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30928 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 65d8c1e8d49150187b8561be931abf6b83afd793 |
12-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
mark call adjustments as modifying the SP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30911 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| af9db75943c11eebd642c1645d3c3f4003fe37e3 |
11-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add properties to ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 493a7fc5c301faca1f5cd042c5f546bd008c282e |
10-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
uint <-> double conversion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30862 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 667c349febc16ec921093baedadeeab8488dbe26 |
10-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add fp sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30859 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| b47e1d033cd3519d4a50779e07563a8dc2c0a21a |
10-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add double <-> int conversion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30858 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 0d9fe764dfcacf9978680cd8bc91cc27191f8546 |
10-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
compare doubles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 4b20fbc01d6a298bb3c8c22cb76c33b366c1c1b9 |
10-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial support for fp compares. Unordered compares not implemented yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30854 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 466685d41a9ea4905b9486fea38e83802e46f196 |
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 2dc0f2b55cdcf53af2e07ef86069959aab0cc358 |
09-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add float -> double and double -> float conversion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30835 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| ecdb9f93c42e54574e1eaf121ad68b6e27f721fb |
09-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add ADDS and ADCS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30830 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 48bc9fbf191057abfa42e26517cef61a241c7516 |
09-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::SELECT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30829 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5af3a686a72a5f9fd3902606971ff6e265110f6b |
09-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30828 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ad557f9d11b942efe858a27e330a15d9f0af5dad |
09-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
expand ISD::EXTLOAD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30827 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 896f10c30995dd522eadea553780785d8cf967d6 |
09-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
most ARM targets are little endian
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30826 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| e5bbd6d75353103f0053af2f6686e70c58abe340 |
07-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement FUITOS and FUITOD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30803 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 5aca927ae68ef063b86914378749dc59646d3f52 |
07-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement FLDD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30802 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
EADME.txt
|
| d9ae778125a0be138d97254a07775bb741740ff2 |
07-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement fadds, faddd, fmuls and fmuld
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30801 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 935b1f8fce78d1a33251aec02dcd0108b8dd0366 |
06-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add optional input flag to FMRRD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30774 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 614057b843e5b27963095c42042a232e85527f02 |
06-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add support for calling functions that return double
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30771 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| af1dabef358895da483617b6f5cbd25b60b6f410 |
06-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix some bugs affecting functions with no arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30767 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1b5076887e32f9a16a1f65f3ce9abf11c31abcd7 |
06-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix the stack alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30766 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 4a408d46d4c2d9a7e5598c9a96886374ca7044f6 |
06-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add support for calling functions that have double arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30765 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 786225adf09e606c795ef68a1f789c12f37869f2 |
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make use of getStore().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 39b5a2125922810233c0c1fd52a9621a979c8c19 |
05-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
use a const ref for passing the vector to ArgumentLayout
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30756 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| a284584352df145da085b11db7891b67c0f09430 |
05-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
implement FMDRR
add support for f64 function arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30754 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 1da31ee472b9615d7329c656e2cc17c419ed7c95 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Pass the MachineFunction into EmitJumpTableInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30742 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 6f6f69950f5a36d3ae7e4d1d5b96fda204beb79a |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Use getSectionForFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30740 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| cd71da5cf05cd023d2082e2a13a2524ee7d5af3f |
03-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement floating point constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30704 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
EADME.txt
|
| 9e071f0ae3eb92c61de4860fdb12d4499b50e392 |
02-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.td
|
| 27185190e6652d4c6d70bdf1202a518e5d3f3053 |
29-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add floating point registers
implement SINT_TO_FP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.td
|
| 75645496fa9cd73d7dd1965b055ca6b7ee7a291d |
22-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30581 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ebdabda708348d54d86719a1af30e2410b5bcc0a |
21-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
more condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7246d33e2a99c3060089e550775403f6779662e7 |
21-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
if a constant can't be an immediate, add it to the constant pool
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30566 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4d4c0217587d6cd76da9690aca0be49f5508db7a |
19-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix header
add comments
untabify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30486 91177308-0d34-0410-b5e6-96231b3b80d8
RMMul.cpp
|
| 71f3b94fa846114a2ce45645ef262e230737e65e |
19-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement a MachineFunctionPass to fix the mul instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30485 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMMul.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 3ad5e5cf998841681e9d11e08eb82a94ddffd1f8 |
13-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add shifts to addressing mode 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| c356a572e34131bf767f35e3fecefae36fab744a |
12-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects MachineConstantPoolEntry changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 817e7fdb8bc3ca40fc44c1efe4fbb63855bd3d2d |
11-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement SRL and MUL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30262 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 1b3956b516e28d634e48a12074b94acca5bcc679 |
11-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30261 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7cca7c531773f763c1bddc3fefecc99ba56ed10a |
11-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
partial implementation of the ARM Addressing Mode 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| ff59d22232f47f138ed3d753975153befd1aa0c0 |
11-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30246 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| f369dd26fbc8e3e174be0773fec6bffa80fb6cd4 |
10-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Removed unnecessary Mangler creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30239 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 0a200600e777c8aac9646c9cba69693155a8142c |
08-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement shl and sra
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 4e30764d5515b09e48ebed1ee61d206d11fc2293 |
08-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the eor (xor) instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30189 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 5c2aa0a4d819039a8f31d04041f6c8056cd10fb7 |
08-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement unconditional branches
fix select.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30186 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| fde1b3bb2f15b74c713d98a79fcddaff1ac00dd1 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Remove condition on delete.
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30169 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| a0f3d17daac73c9c71aad497b298cbe82848f726 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Make target asm info a property of the target machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30162 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMTargetMachine.h
|
| 8e8de8f7765a08ab3aa4f48b302cf19ccb9740e2 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Break out target asm info into separate files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30161 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetAsmInfo.cpp
RMTargetAsmInfo.h
|
| 563321a2582851c653d0863e8e0bba3d483734f9 |
06-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Separate target specific asm properties from the asm printers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30126 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| b52b54d4af18ca3cbfa56361aea94635b2a6919e |
06-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the orr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30125 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 09e460662a8d7328da1b938d5581a6ef3740b51d |
05-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Completely eliminate def&use operands. Now a register operand is EITHER a
def operand or a use operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 3a02f020eb72cb10f7f794532ddc35e478f7e86b |
04-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add support for returning 64bit values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30103 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 1911fd4f85aebcd4d7b8f27313c5a363eebf49cb |
04-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Completely rearchitect the interface between targets and the pass manager.
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30081 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
RMTargetMachine.h
|
| c4fa386471cb1ff9d1f2acc24e2d0682e5a17b1b |
03-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify target construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30070 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| bc4cec9a62113dc7d12caa03f1a1e8a31ce60b9c |
03-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the SETULT condition code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30067 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5f450d2948ac5bd83a31fbfff89e17b0e2536a80 |
02-Sep-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add more condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
|
| 9ade218533429146731213eacb7e12060e65ff58 |
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Select() no longer require Result operand by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 755be9b3debb5ffdb21759c0213d51116a522e1b |
25-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
use @ for comments
store LR in an arbitrary stack slot
add support for writing varargs functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29876 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMFrameInfo.h
RMISelDAGToDAG.cpp
|
| cdda88cd1216c146d9ea095561467a9c83f65908 |
24-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the "eq" condition code
implement a movcond instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 6f602de3b68cc63d12554ad6ae3c98a4c436c32d |
24-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
create a generic bcond instruction that has a conditional code argument
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 687bc49d1ada3fe0a2cd3fb5c044f12d267f259f |
24-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial support for branches
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| f4d40050f1dc6488b5f706b95a2c8657f5a97c2f |
22-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add a README.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29814 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 3c000bf817f90212c8e5585f7c1981e68ee393fc |
22-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial support for select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29802 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMTargetMachine.cpp
|
| a5dfc835d4acf4316364ecc2b0c9cbaf13d08020 |
21-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the and instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29793 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| 3717ca965bcfb6c66d7e9016566be842a9cc5629 |
20-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
call computeRegisterProperties
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29780 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 5ea64fd9eb0027ad20a66ea29211eef79d8842a0 |
18-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Constify some methods. Patch provided by Anton Vayvod, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.td
|
| f3a335cedff423438789c593d58be068b124dc1e |
17-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add a "load effective address"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| ec46ea34dcc615558294e9e0dbd0dd0f2894f574 |
16-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
Declare the callee saved regs
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
RMFrameInfo.h
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
RMTargetMachine.cpp
RMTargetMachine.h
|
| 61369da0e5461047adce93f3c3f5ca1ff49707fc |
14-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
select code like
ldr rx, [ry, #offset]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29664 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| e219945348207453a2d5e21021ba3211f8f94e25 |
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 8742867f958221d4a8cbbba7eef309bfe037653c |
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
elimiante use of getNode that takes vector of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29612 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 64a752f7c7cf160f2887d0a16d5922359832c9c2 |
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| bb7b844bec6c53ac29ac4c50d7b3963e7f193efb |
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
CALLSEQ_* produces chain even if that's not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
|
| a1ab92d8b7c2d4ca0ab35b372c8eb7b66a5cbf64 |
09-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
correctly set LocalAreaOffset of TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29589 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
RMTargetMachine.cpp
|
| 7a53bd0890b0529c6dd95e97611dca7a8c4d6077 |
09-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix the spill code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29583 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMRegisterInfo.cpp
|
| 2c8cdc6c1ad78179fecfe67e7e0e250a4053c714 |
09-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix the loading of the link register in emitepilogue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29580 91177308-0d34-0410-b5e6-96231b3b80d8
RMRegisterInfo.cpp
|
| 46adf8119df362bfed7c6d71dd467527981b97da |
08-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
change the addressing mode of the str instruction to reg+imm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMRegisterInfo.cpp
|
| 1a009468175a6e123cc3f1e847c10e3e126a44db |
08-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial support for variable number of arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29567 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMRegisterInfo.cpp
|
| 2ef88a09b71f458ad415b35a1fb431c3d15d7eb1 |
08-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen isel changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 341b864c8d3868a17d5dbcdb4bac40c6586b60cf |
04-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
use a 'register pressure reducing' scheduler
make sure only one move is used in a hello world
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29520 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6312da0fc7b5cbefba2243775ed9de5c405274be |
04-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
Bug fix: always generate a RET_FLAG in LowerRET
fixes ret_null.ll and call.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29519 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| f4fda804038e8f98b597e82a8df607321369db2b |
03-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add and use ARMISD::RET_FLAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29499 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| 1ed3af11b55becb26a3485494409084a668a9232 |
01-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
start comments with #
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29451 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
|
| 06c1e7eacb11edd1671eabfc11291b7716be2608 |
01-Aug-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement LowerConstantPool and LowerGlobalAddress
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29433 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
|
| 6d581e8d1567e4e445e2cc88c790c79eb75c226a |
31-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
handle GlobalValue::InternalLinkage in doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29417 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| 2641cad180e94c0d26630d4ed455352f19be3d3e |
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove InFlightSet hack. No longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29373 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| b01c4bbb4573e0007444e218b683840e4519e0c8 |
27-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
emit global constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29344 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| fac00a93a98d43ac0d4ca514aa5a720debbd6c8b |
25-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement function calling of functions with up to 4 arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29274 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 44819cb20ab8e84fc14ea1e6fc69fb797c70a50d |
21-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implemented sub
correctly update the stack pointer in the prologue and epilogue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29244 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.cpp
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| 355746359ebca83ccb5accab0f3ffd20f0374a35 |
18-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.cpp
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| 84b19be6ab9544f72eafb11048a1121f5ea77c95 |
16-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
skeleton of a lowerCall implementation for ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| a4e64359aafaf23e440e9dc171859daef1995f1b |
11-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add the memri memory operand
this makes it possible for ldr instructions with non-zero immediate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| aefe14299a05621864e6372639f372173a96bf38 |
10-Jul-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMRegisterInfo.cpp
|
| 49e441558760cc1708778b5d0ded05d639c1e5ed |
27-Jun-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
handle the "mov reg1, reg2" case in isMoveInstr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28945 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMRegisterInfo.cpp
|
| 58421d7d0847bbb5f4cc95c647726d55c45582c0 |
18-Jun-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
initial implementation of ARMRegisterInfo::eliminateFrameIndex
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
RMInstrInfo.td
RMRegisterInfo.cpp
RMRegisterInfo.td
|
| 1790d44d0dbe3412e012be5e43b89e67064bdb86 |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Don't pass target name into TargetData anymore, it is never used or needed.
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28830 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
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| 337c4ad6e7726555b61a6a75d5172a77fe12c029 |
12-Jun-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
lower more then 4 formal arguments. The offset is currently hard coded.
implement SelectFrameIndex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28751 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 4b02367d542c7eaa429d1ff73119ae44ddb252a8 |
06-Jun-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add R0 to liveout
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28691 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
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| 85ede37ca90b5d1846f37631ed2e8b8f96000db8 |
30-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
Expand ret into "CopyToReg;BRIND"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
|
| a5135ba0c9d6d063f0479927b7b6ae26124a0fdd |
27-May-2006 |
Chris Lattner <sabre@nondot.org> |
Ignore generated files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28520 91177308-0d34-0410-b5e6-96231b3b80d8
cvsignore
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| 6848be1a27e08a89dcd4dd69f746471a608012cd |
27-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
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| a1334cdfb2afb44a1f2b952391e1b2fecb1d4bd8 |
26-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
On ARM, alignment is in bits
Add lr as a hard coded operand of bx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28494 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMInstrInfo.td
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| 2f99b6bd9601ae8d4fd248f9bb701283795c38a8 |
25-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement initial version of ARMAsmPrinter::printOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28470 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
|
| c3c1a86aa0fe3ccda2de383330b90b77aaccd710 |
25-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
port the ARM backend to use ISD::CALL instead of LowerCallTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28469 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 6a3d5a62f09d4093468525a07a0143cae0e9df41 |
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Assert if InflightSet is not cleared after instruction selecting a BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| afe358e7d46da9d29ba02fbbf81bdfb4ac4a4520 |
24-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
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| 4b442b528a50ef06cd75f0e7c41ad57426175bcc |
23-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement minimal versions of
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28431 91177308-0d34-0410-b5e6-96231b3b80d8
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
|
| d988b32abad0634df07c18629e899f256935fde7 |
20-May-2006 |
Owen Anderson <resistor@mac.com> |
Make all of the TargetMachine subclasses use the new string TargetData methods.
This is part of the on-going work on PR 761.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28414 91177308-0d34-0410-b5e6-96231b3b80d8
RMTargetMachine.cpp
|
| dc124a234a02ea6fc1061a51ade1bb7b817ddb61 |
18-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
implement movri
add a stub LowerFORMAL_ARGUMENTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
RMInstrInfo.td
RMRegisterInfo.cpp
|
| 0f3ac8d8d4ce23eb2ae6f9d850f389250874eea5 |
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
RMRegisterInfo.cpp
RMRegisterInfo.h
|
| c01d497255f0d344163178c5f827e8b73f6f04d6 |
17-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove PointerType from class Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
RM.td
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| 1c8f0536b3a19c0ff9f5a8ba039a771c4bb2bfbc |
16-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
add an abort after every assert(0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28310 91177308-0d34-0410-b5e6-96231b3b80d8
RMISelDAGToDAG.cpp
|
| 7bc59bc3952ad7842b1e079753deb32217a768a3 |
15-May-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
added a skeleton of the ARM backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
RM.h
RM.td
RMAsmPrinter.cpp
RMISelDAGToDAG.cpp
RMInstrInfo.cpp
RMInstrInfo.h
RMInstrInfo.td
RMRegisterInfo.cpp
RMRegisterInfo.h
RMRegisterInfo.td
RMTargetMachine.cpp
RMTargetMachine.h
akefile
|