History log of /external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
1b26fdbf1f01e90b803cc035b6b932cd95c76830 02-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r196046:
------------------------------------------------------------------------
r196046 | tnorthover | 2013-12-01 06:16:24 -0800 (Sun, 01 Dec 2013) | 8 lines

ARM: fix bug in -Oz stack adjustment folding

Previously, we clobbered callee-saved registers when folding an "add
sp, #N" into a "pop {rD, ...}" instruction. This change checks whether
a register we're going to add to the "pop" could actually be live
outside the function before doing so and should fix the issue.

This should fix PR18081.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
ef8c4ca252f1289ca8d0a1e6cfd96ca17fe3c5a8 07-Oct-2013 Rafael Espindola <rafael.espindola@gmail.com> Remove getEHExceptionRegister and getEHHandlerRegister.

They haven't been used for a long time. Patch by MathOnNapkins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
165a7a925d73286abfc826b3d6339843b02c09e0 27-Jun-2013 Stephen Lin <stephenwlin@gmail.com> Clarify and doxygen-ify comments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
6b97ebe9a32342207b24a5f73ebbf3070ec8d189 26-Jun-2013 Stephen Lin <stephenwlin@gmail.com> ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is not used for incompatible calling conventions.

(Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
57148c166ab232191098492633c924fad9c44ef3 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
456ca048af35163b9f52187e92a23ee0a9f059e8 20-Apr-2013 Stephen Lin <stephenwlin@gmail.com> Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
700ed80d3da5e98e05ceb90e9bfb66058581a6db 21-Feb-2013 Eli Bendersky <eliben@google.com> Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
108fb3202af6f500073cdbb7be32c25d7a273a2e 31-Jan-2013 Chad Rosier <mcrosier@apple.com> [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
f71415646053e66f8a5b63a74ac06287eeab53d5 04-Dec-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.

These functions have been replaced by TRI::getRegAllocationHints() which
provides the same capabilities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
303da1baf2a90d18a709f29f4f7cd0e1962be5f9 03-Dec-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Implement ARMBaseRegisterInfo::getRegAllocationHints().

This provides the same functionality as getRawAllocationOrder() for the
even/odd hints, but without the many constant register arrays.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
e7bd51980a1341fb60322e5922cfcc0c9b92b165 07-Nov-2012 Chad Rosier <mcrosier@apple.com> Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers. Previously, the register we being marked as implicitly defined, but
not killed. In some cases this would cause the register scavenger to spill a
dead register.

Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b1f994af589af28dead4826d2e58a0138105e452 26-Oct-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove ARMBaseRegisterInfo::isReservedReg().

It is just as easy to use MRI::isReserved() now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
f4a5a613faa1a0eca6b884a6dfe83e8b1eb957b2 26-Oct-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the canCombineSubRegIndices() target hook.

The new coalescer can already do all of this, so there is no need to
duplicate the efforts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 08-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
6a8c7bf8e72338e55f0f9583e1828f62da165d4a 23-Apr-2012 Preston Gurd <preston.gurd@intel.com> This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.

This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.

This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.

The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().

It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.

It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.

Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.

Patch by Andy Zhang!

Thanks to Jakob and Anton for their reviews.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b6632ba380cf624e60fe16b03d6e21b05dd07724 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
015f228861ef9b337366f92f637d4e8d624bb006 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store registers in callee saved register tables to reduce size of static data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
3ee7d15284f188672e9e429e9e5cf7b870698677 18-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Implement ARMBaseRegisterInfo::getCallPreservedMask().

Move ARM callee-saved lists into ARMCallingConv.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
afad0fe59a791cb4fd87fbd7ea2b1aba8d67a7af 04-Jan-2012 Evan Cheng <evan.cheng@apple.com> Fix more places which should be checking for iOS, not darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
570f9a972e02830d1ca223743dd6b4cc4fdf9549 19-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit a getMatchingSuperRegClass() implementation for every target.

Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
342e3161d9dd4fa485b47788aa0266f9c91c3832 30-Aug-2011 Evan Cheng <evan.cheng@apple.com> Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

subc
|
libcall #2
|
libcall #1
|
sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
194bd8982936c819a4b14335a4d08f28af8f3d42 17-Aug-2011 Jim Grosbach <grosbach@apple.com> Thumb parsing diagnostics for low-reg requirements on ADD and MOV.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
0e6a052331f674dd70e28af41f654a7874405eab 18-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 27-Jun-2011 Evan Cheng <evan.cheng@apple.com> Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.


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/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
dd5a8471526ceadf9bceb1a1221299b3db49c33a 17-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Rename TRI::getAllocationOrder() to getRawAllocationOrder().

Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.

The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
6e032942cf58d1c41f88609a1cec74eb74940ecd 30-May-2011 Rafael Espindola <rafael.espindola@gmail.com> Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
c9e5015dece0a1a73bec358e11bc87594831279d 26-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.

The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee 19-Apr-2011 Bob Wilson <bob.wilson@apple.com> Avoid write-after-write issue hazards for Cortex-A9.

Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.

This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
be2119e8e2bc7006cfd638a24367acbfda625d16 07-Mar-2011 Cameron Zwarich <zwarich@apple.com> Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
3daccd82d3151fa3629de430b55698a81084fc9e 05-Mar-2011 Anton Korobeynikov <asl@math.spbu.ru> Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
976ef86689ed065361a748f81c44ca3510af2202 18-Dec-2010 Bill Wendling <isanbard@gmail.com> During local stack slot allocation, the materializeFrameBaseRegister function
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
94c5ae08750f314bc3cf1bf882b686244a3927d9 28-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move more PEI-related hooks to TFI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
82f58740c76b42af8370247b23677a0318f6dde8 20-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move some more hooks to TargetFrameInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
d0c38176690e9602a93a20a43f1bd084564a8116 18-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move hasFP() and few related hooks to TargetFrameInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
8b3ca6216d62bf3f729c2e122dcfeb7c4d7500dc 18-Nov-2010 Eric Christopher <echristo@apple.com> Rewrite stack callee saved spills and restores to use push/pop instructions.
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.

Adjust all testcases accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
65a0adb5978d44c791d047cb44792785abf71e4b 15-Nov-2010 Chris Lattner <sabre@nondot.org> silence a ton of warnings from clang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
33464912237efaa0ed7060829e66b59055bdd48b 15-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
6c50119ba33bf22885d2229726c809539a85c247 11-Nov-2010 Eric Christopher <echristo@apple.com> Revert this temporarily.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
391f228e7e00f62b79ad483b801f5f58f046b7ea 11-Nov-2010 Eric Christopher <echristo@apple.com> Change the prologue and epilogue to use push/pop for the low ARM registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
a4c3c8f28d9465dc7c42eb43c2377530f1821574 15-Sep-2010 Jim Grosbach <grosbach@apple.com> move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
f1c3eb37ae96572e1df34bf980b9ecd149b5ee33 15-Sep-2010 Jim Grosbach <grosbach@apple.com> simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
merge the common cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
65482b1bb873dd820f54a24a2f34bd65f2669e5c 03-Sep-2010 Jim Grosbach <grosbach@apple.com> Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
6a8700301ca6f8f2f5f787c8d1f5206a7dfceed6 03-Sep-2010 Daniel Dunbar <daniel@zuster.org> Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.

This reverts commit 8d6e29cfda270be483abf638850311670829ee65.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
1755b3964f931bdd6fa9b4c0138f666ccfa12aca 03-Sep-2010 Jim Grosbach <grosbach@apple.com> For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.

rdar://7352504
rdar://8374540
rdar://8355680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a 27-Aug-2010 Jim Grosbach <grosbach@apple.com> Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
1ab3f16f06698596716593a30545799688acccd7 26-Aug-2010 Jim Grosbach <grosbach@apple.com> tidy up a bit. no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
3197380143cdc18837722129ac888528b9fbfc2b 24-Aug-2010 Jim Grosbach <grosbach@apple.com> Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
a273442891ae20fd8192526132e3819ea9e5eda9 24-Aug-2010 Jim Grosbach <grosbach@apple.com> Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
e2f556933e1a19cddf6d4f370e2770c0f763b025 20-Aug-2010 Jim Grosbach <grosbach@apple.com> Better handling of offsets on frame index references. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
74d803a58c7935c067397bb19afc05ec464d8159 18-Aug-2010 Jim Grosbach <grosbach@apple.com> Add hook for re-using virtual base registers for local stack slot access.
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
dc140c6e7b8350ca51aa1d408c10e25a27826e2c 18-Aug-2010 Jim Grosbach <grosbach@apple.com> Add materialization of virtual base registers for frame indices allocated into
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.

Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
8708ead5a46f4ec8f2d5f832be23381924d72b8d 17-Aug-2010 Jim Grosbach <grosbach@apple.com> Add hook to examine an instruction referencing a frame index to determine
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09 05-Aug-2010 Jim Grosbach <grosbach@apple.com> For local variables in functions with a frame pointer, use FP as a base
register for local access when it's closer to the stack slot being refererenced
than the stack pointer. Make sure to take into account any argument frame
SP adjustments that are in affect at the time.

rdar://8256090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
4dbbe3433f7339ed277af55037ff6847f484e5ab 20-Jul-2010 Chris Lattner <sabre@nondot.org> prune #includes a little.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
72852a8cfb605056d87b644d2e36b1346051413d 20-Jul-2010 Eric Christopher <echristo@apple.com> Constify some arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
18f30e6f5e80787808fe1455742452a5210afe07 02-Jun-2010 Jim Grosbach <grosbach@apple.com> Clean up 80 column violations. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
91a74da036d3a9442953ae1de3e797a50da4ccf0 02-Jun-2010 Bob Wilson <bob.wilson@apple.com> Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
20fae651816916000c47b78843f22fd259ba4216 02-Jun-2010 Rafael Espindola <rafael.espindola@gmail.com> Replace ARM's getCalleeSavedRegClasses with a simpler solution

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b990a2f249196ad3e0cc451d40a45fc2f9278eaf 15-May-2010 Evan Cheng <evan.cheng@apple.com> Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 09-Mar-2010 Jim Grosbach <grosbach@apple.com> Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
4642ad3af1cf508ac320b9afd25b065f08b36574 23-Feb-2010 Jim Grosbach <grosbach@apple.com> Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
1a2e8686f8137a1a2329952ffd1e21969ea1658c 19-Feb-2010 Bob Wilson <bob.wilson@apple.com> Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
cf43e60544041c127bb875fe4cf0d0ae96cd6c78 19-Feb-2010 Jim Grosbach <grosbach@apple.com> Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
30c6b75ac2eef548c18110a38c9798ea5314caba 27-Jan-2010 Chris Lattner <sabre@nondot.org> constify a method argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3 19-Jan-2010 Jim Grosbach <grosbach@apple.com> For aligned load/store instructions, it's only required to know whether a
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
50f8516d2dd87e6c02a46fa349b75101f9db8619 22-Nov-2009 Jim Grosbach <grosbach@apple.com> Generate more correct debug info for frame indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b9c2fd964ee7dd7823ac71db8443055e4d0f1c15 12-Nov-2009 David Greene <greened@obbligato.org> Make the MachineFunction argument of getFrameRegister const.

This also fixes a build error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
3dab2778571b5bb00b35a0adcb7011dc85158beb 27-Oct-2009 Jim Grosbach <grosbach@apple.com> Infrastructure for dynamic stack realignment on ARM. For now, this is off by
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
4f54c1293af174a8002db20faf7b4f82ba4e8514 25-Oct-2009 Evan Cheng <evan.cheng@apple.com> Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
7e831db1d4f5dc51ca6526739cf41e59895c5c20 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Enable post-pass frame index register scavenging for ARM and Thumb2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b58f498f7502e7e1833decbbbb4df771367c7341 07-Oct-2009 Jim Grosbach <grosbach@apple.com> Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
010b1b9e7b11bced0b277a4d808226ba2af3044a 15-Aug-2009 Evan Cheng <evan.cheng@apple.com> Do not use frame register to reference fixed stack objects if the function is frameless.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
98a0104014e9bb6ed89c2572f615351fd526674a 14-Aug-2009 Evan Cheng <evan.cheng@apple.com> Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
ee42fd309ee6a8febfafb97c2f3b6f2069758c5e 31-Jul-2009 Evan Cheng <evan.cheng@apple.com> When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
2cfd52c507bd5790457a171eb9bcb39019cc6860 29-Jul-2009 Chris Lattner <sabre@nondot.org> Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
6495f63945e8dbde81f03a1dc2ab421993b9a495 28-Jul-2009 Evan Cheng <evan.cheng@apple.com> - More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
30b2bdfa734d59bb7bc769dc2f06e4900a77f6f8 26-Jul-2009 Evan Cheng <evan.cheng@apple.com> Refactor. Get rid of a few more getOpcode() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
5ff58b5c3ab6df332600678798ea5c69c5e943d3 24-Jul-2009 David Goodwin <david_goodwin@apple.com> Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b53cc014d0f47b898c9daca34566c16dda6c4c1e 23-Jul-2009 David Goodwin <david_goodwin@apple.com> Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
8295d99bff6f8e3dfdfdaf1871cb72adab423f20 22-Jul-2009 Evan Cheng <evan.cheng@apple.com> Get rid one of the getRegisterNumbering. Also add D16 - D31.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
378445303b10b092a898a75131141a8259cff50b 16-Jul-2009 Evan Cheng <evan.cheng@apple.com> Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
b5619f42f4fdf347380d28357549df09b9ca3946 10-Jul-2009 Evan Cheng <evan.cheng@apple.com> 80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
77521f5232e679aa3de10aaaed2464aa91d7ff55 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Generalize opcode selection in ARMBaseRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
db5a71a8e01ed9a0d93a19176df6ea0aea510d7b 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Push methods into base class in preparation for sharing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
c140c4803dc3e10e08138670829bc0494986abe9 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Start breaking out common base functionality for register info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h