| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e1bde51d63f888e0011dfd3b9cfd78b1736d0b5d |
|
04-Oct-2013 |
Matthias Braun <matze@braunis.de> |
ARM: preserve undef flag in pseudo instruction expanders
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| bba9390fc6c0d536172c6bb4a9c93db557c1aff4 |
|
01-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/14207019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 3f4f420ab7acb10221ba971543a7eed5489fb626 |
|
28-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 |
|
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.
TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e7bd51980a1341fb60322e5922cfcc0c9b92b165 |
|
07-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers. Previously, the register we being marked as implicitly defined, but
not killed. In some cases this would cause the register scavenger to spill a
dead register.
Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 17f42e02a10bd4d43e4ba904c640224de2c48f51 |
|
27-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."
Keep the integer_insertelement test case, the new coalescer can handle
this kind of lane insertion without help from pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| aa258442b9c9f764845660a8f3233c7887e7cf6f |
|
20-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Change enum type in a static table to uint8_t instead. Saves about 700 hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 6c822eea47dbef96940819b1ea085fabc49a1e71 |
|
06-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| df1c637ac4b6f6587c037be55cafed665c732d8f |
|
10-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Remove getARMRegisterNumbering and replace with calls into
the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.
One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d628a587b654ba737b570ee0611f70a1deb58bbc |
|
15-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve <undef> flags in ARMExpandPseudo.
This probably mostly shows up in bugpoint-generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 6e6269a976baee45717265dbd12996367df6a201 |
|
20-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Transfer memory operands to the right instruction.
They need to go on the PICLDR as the verifier points out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 0e5233a9e5ee9385c6a940e3985194d77bee0bbb |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b78ca423844f19f4a838abb49b4b4fa7ae499707 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers and opcode in static tables in the target specific backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| c0fc450f0754508871bc70f21e528bf2f1520da1 |
|
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 28f08c93e75d291695ea89b9004145103292e85b |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| f1f16c832f92829f47573620c20d8420c47bde6c |
|
10-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM updating VST2 pseudo-lowering fixed vs. register update.
rdar://10663487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| f4aea8f34946d4d2b101b8e3c6db95c18be80173 |
|
23-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e6949b13997e6d31aa4719a0e80c4b6b405e42a9 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 2027379985f1cbb965be808adad5b819a66dd97f |
|
17-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve more memory operands in ARMExpandPseudo.
I don't think this affects anything but verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 60d99a5278e4a0e7116a05c01cececb07ca1362a |
|
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| bb3a2e4d0defc6854d37384d80858037dbbc5f20 |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON refactor VST2 w/ writeback instructions.
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e90ac9bce9aa6de288568df9bf6133c08534ae2f |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| a4e3c7fc4ba2d55695b0484480685698132eba20 |
|
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 096334e25ea68ac970942ecb680a82fbb8ad206c |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 all lanes, with writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 13af222bab6fdc77d8193eb38e78a9cbed1d9d1f |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 two register all lanes, no writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 4c7edb3ad8bd513c59190f6ebee9bee34af7d247 |
|
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for four-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d5ca201891d238ca2185831524a1e3f2670224df |
|
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for three-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| eaab6ef6eb12fc950f1d4371b297d9b7ca9d4c66 |
|
16-Nov-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 742c4bac07e2800275a69259296fba7c3e3f651b |
|
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Re-apply 144430, this time with the associated isel and disassmbler bits.
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 4334e032525d6c9038605f3871b945e8cbe6fab7 |
|
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VST1 w/ writeback assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| f9f5a765adf8465530fe1aced6455ca9438bb29a |
|
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM writeback vs. stride operands for VST/VLD.
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b36e03d987c843ccb731627ffd2b1db17bd72e39 |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 10b90a9bbf7dcae1568c03a03f9606f5395f2144 |
|
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor am6offset usage for VLD1.
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 224180e81b34c99d15e35a4d4de6729357c6d372 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 8e0c7697fd9b9354856074efc06eea9f6d80015c |
|
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| fea95c6bade86fcfa5bd07efdda9bd902f53be8c |
|
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
Remove the VMOVQQ pseudo instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e5038e191db82d4d92fdeec1b5bce5cae21f6d8f |
|
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| a67f14bf53737f9bb0afefa28e08c4aac6ec4804 |
|
19-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make a bunch of symbols private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 7dcd04abe0b0b1dbfb285faea2daece50f9aa502 |
|
13-Aug-2011 |
Bob Wilson <bob.wilson@apple.com> |
Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e69438fb87623dd6fdeeb99b647a46e877eb6183 |
|
29-Jul-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.
The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 152d4a4bb6b75de740b4b8a9f48abb9069d50c17 |
|
22-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 92a202213bb4c20301abf6ab64e46df3695e60bf |
|
21-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
|
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 43967a97cf9a296623e1cf5ed643e2f40b7e5766 |
|
15-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| aa4cc1a6d75f621cbc5eb1db692068db072fbecc |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| efeedceb41cc0c5ff7918cad870d5820de84b03d |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| ff97eb0cf4394090570feaa327d1237ba4b935e2 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d7d030a44796adc73a6eaa939cd17e52047734c1 |
|
29-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b58a340fa2affa0da27a46c94dd49ba079c9343c |
|
19-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not lose mem_operands while lowering VLD / VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 76706013131247121a3a153f378946a0cb0e319c |
|
05-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 15b81b51d64b04c71aa75788fcc418f52ec8b181 |
|
05-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 848b0c39b11801614c47e460248b60e8d40eb257 |
|
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 670350bb782f6268126f7f8afefe86ab05b5b23d |
|
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
There are two pseudos in this case that are Thumb mode, not one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| f219f3135d0ec939acd42801766c17fad41c0173 |
|
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize VMOVDcc and VMOVScc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3 |
|
12-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 8b8515c225c799e9df69bde8ffffa3c72cec9445 |
|
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e672ff84308434ad5517a5c6fc36e691893fca96 |
|
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize ARM MVNCCi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 3906276a8d4b308a19675d5a67b2d6ab3e3b9b6f |
|
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d4a16ad85d991ff12487b40ef248833448047ead |
|
11-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Properly pseudo-ize MOVCCr and MOVCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 |
|
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 971b83b67a9812556cdb97bb58aa96fb37af458d |
|
08-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 7de6814405ab02591235f0826b8e6d98fd76c8ba |
|
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Change VLD3/4 and VST3/4 for quad registers to not update the address register.
These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used. In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 584520e8e2c1f8cc04bc8dd4dc4ea6c390627317 |
|
23-Jan-2011 |
Ted Kremenek <kremenek@apple.com> |
Null initialize a few variables flagged by
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 53519f015e3e84e9f57b677cc8724805a6009b73 |
|
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
|
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 |
|
17-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 6b8719fd7dc527e4c1910ae49ebee61d90907c08 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121721, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e8d02539d7981c07d301d91a6a5b6ad34099b510 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 1e6f59608bf5becb3c560dd5c38c7b37c0edcbdb |
|
13-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 3a6756cb1c87908f5d04660b6ed7d464b56f78f6 |
|
13-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for 2-register Neon instructions for scalar FP.
Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 0a29c270b53f15723811783c572d06b9500a7e8f |
|
09-Dec-2010 |
Matt Beaumont-Gay <matthewbg@google.com> |
Remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 2fe813af23e682b418ecd477144fe070be325419 |
|
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove extraneous semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 045869c12ac5af2b1dd97a0dcbedab8db01fe765 |
|
09-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Style nit and whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 0062db8b4f388308f8838805f160259a48a2882e |
|
09-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Removed dead comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| a0871e79270b2a05f93c9df73bbe24c587faa94e |
|
09-Dec-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
ARM/MC/ELF TPsoft is now a proper pseudo inst.
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| eb6779c5b98383e33542207f062102e79263df16 |
|
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| c76c59840b7a4491afdcd2f35483f8d6e5ab533a |
|
06-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121021, which broke the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| ba3368ceae8d3e3f1653de4aa24f168eae8f083b |
|
06-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 4c386fc75488cf8663acf9527e335bbca1fbc0ac |
|
06-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 1ab4b211ea5165445b791277507d58dcf1e46688 |
|
02-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,
not thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 6c4c982f83eea655e0f14610d2689fad722aeb7d |
|
30-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD3-dup instructions.
The encoding for alignment in VLD4-dup instructions is still a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 86c6d80a7a20fa7decc3e914be5d1cb0f7f29a6f |
|
29-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD3-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b1dfa7a8e0c1972231bee636afd5239b009ba4da |
|
28-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD2-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 2a0e97431ecef2aa6a24a16ced207d5b53fcfc2d |
|
27-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VLD1-dup instructions (load 1 element to all lanes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 7920d96964d707a3af85332c98d95b2fabc3d5c9 |
|
19-Nov-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Avoid release build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
|
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 73fe34a3ee866867d5028f4a9afa2c3b8efebcba |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 63f3544a7f6ca09e7515d6b0e1bf9e8e884131e2 |
|
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional move of large immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 893d7fe2098cc81ba1b4ce0ed71f6f614843961f |
|
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d0c6bc220433fab06bc1507f963ea5883fdc4f69 |
|
02-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b796bbb6de19872c0c1921b8b3f05206dd33c97d |
|
01-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 8e0a3eb95784c76f3a73abf815a0143613068f72 |
|
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 100c267249d1d03c4f96eede9877a4f9f54f2247 |
|
23-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
until other LLVM projects using these are cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| dbbd99faf1d661f03a9dfc1551d7537c34d64bee |
|
21-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
The return value of this call is not used, so no point
in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| b8e67fc92b0a508e3782b782baa98a6d56d5d7ea |
|
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix backwards conditional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 8b95c3ebfbd492c2ac863df93e40c11fc2e914fd |
|
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add dynamic realignment when rematerializing the base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e4ad387a5a88dae20f0f7578e55170bbc8eee2a9 |
|
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 01b35c25deee3d4cab339e620c12c721e627d609 |
|
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use simple RegState::Define flag instead of getDefRegState(true).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 6bdc8ae2916d20740790e0618692df7dac598cd0 |
|
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
an explicit def. Make sure to capture that properly. rdar://8556556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 7032f922b12746b73d6316578b0aea2d812b07b4 |
|
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 65dc30340cf874307eae11ec1195a1cd6d27fb13 |
|
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 823611bfba4fb2c1abbba2e59d68432c6d0a9e9a |
|
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
When expanding ARM pseudo registers, copy the existing predicate operands
instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| ea606bb76b9922f67b678ea48645cdc9bfa0305b |
|
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 9d4ebc0eb80c770aab5b51ca459748a6ac8f1699 |
|
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| fe3ac088ee0a536f60b3c30ad97703d5d6cd2167 |
|
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Avoid warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| bd916c54b7989ddbab373c61eb1ed2556ca44d27 |
|
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 8466fa1842ad4f2d6fadcf5c23c15319ae96b972 |
|
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Switch all the NEON vld-lane and vst-lane instructions over to the new
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 19d644d5a9cd6699e5f9f1999deb3c77b2bbdca4 |
|
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 63569c99ec944210d0edc687d7411b5c687e97a7 |
|
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Simplify copying over operands from pseudo NEON load/store instructions.
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 656edcf138563068a2e7d52fb35f8de1375bad9a |
|
09-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| f572191fe43025bd85ab5d398a5b53305fdc6b8b |
|
03-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 82a9c8480ecd41a1351274569f8d4e4de2723cf6 |
|
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fill in a missing comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| ffde080ae615906545eb33dab30e7bc47c2ac838 |
|
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 6d1e29d2f203093e3e03f15173c0f36637d3afe3 |
|
31-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand MOVi32imm in ARM mode after regalloc. This provides
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 7e701979ad20796bc930b21de3888ccfa0d8b33d |
|
30-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
When expanding NEON VST pseudo instructions, if the original super-register
operand is killed, add it to the expanded instruction as an implicit kill
operand instead of marking the individual subregs with kill flags. This
should work better in general and also handles the case for VST3 where one
of the subregs was not referenced in the expanded instruction and so was
not marked killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| e5ce4f68c786696a96acf1f1aa5431652abb6ce7 |
|
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST1 and VST2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 01ba461af7eafc9d181a5c349487691f2e801438 |
|
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 70e48b23a3455e4689ee24cec4eb153d67223e86 |
|
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use pseudo instructions for VST1d64Q.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 709d59255a3100c7d440c93069efa1f726677a27 |
|
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 90c579de5a383cee278acc3f7e7b9d0a656e6a35 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 1f74590e9d1b9cf0f1f81a156efea73f76546e05 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 9ccaf53ada99c63737547c0235baeb8454b04e80 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 4dbbe3433f7339ed277af55037ff6847f484e5ab |
|
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
|
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 558661d2718cf5750907c449d36ff1231924a2d1 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| d929f7773812535271ae6969331f8164c1f7f3b2 |
|
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Expand VMOVQQ into a pair of VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
|
| 431300797b84600fc9b4eb8ca283277d3e0674eb |
|
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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| a4d73d01c4850dce6a951228b13dcd8e733704b4 |
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12-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a dead fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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| 46510a73e977273ec67747eb34cbdb43f815e451 |
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15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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| 7896c9f436a4eda5ec15e882a7505ba482a2fcd0 |
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03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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| 5cdc3a949af0cef7f2163f8a7acbf3049c226321 |
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24-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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| b9803a8fa65f043c96612fa9c5aeeee12739db2b |
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07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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