| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| acd79ce0ada50c7a437757d188f410d67030fbb9 |
|
10-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: correct liveness flags during ARMLoadStoreOpt
When we had a sequence like:
s1 = VLDRS [r0, 1], Q0<imp-def>
s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.
This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.
rdar://problem/15124449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3d476a80e9da0136681f69247abfbd6de986c137 |
|
04-Sep-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Swift: Only build vldm/vstm with q register aligned register lists
Unaligned vldm/vstm need more uops and therefore are slower in general on swift.
radar://14522102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 5fa2ba2769d31815f54ebf1af42f868f1486e4d0 |
|
10-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 6227d5c690504c7ada5780c00a635b282c46e275 |
|
04-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 2b7cdf09a142b7f3e9a0ec8c7044eaf89bc59caa |
|
21-Jun-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Remove a (false) dependency on the memoryoperand's value as we do not use
it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.
<rdar://problem/13978317>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d050e96133fac8565e3bb1eabe9a587dd5a6ac4d |
|
18-Apr-2013 |
Hao Liu <Hao.Liu@arm.com> |
Fix for PR14824, An ARM Load/Store Optimization bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 84581daf2058eb9d37e24a50ad3be198529bdf28 |
|
05-Apr-2013 |
Renato Golin <renato.golin@linaro.org> |
Reverting 178851 as it broke buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 992347f27131a403043a1e2f1bec4da82568df35 |
|
05-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 89becbb97423fb608a4dd85ec10c3fde4398d956 |
|
05-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instruction vldmia at incorrect position".
Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass.
It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4
But it also tracks conflicts between different register classes (e.g. D2 and S5).
For more details see:
Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824
LLVM Commits discussion:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c82fba27fe6205e5ecdc80fb53e10675db07dfff |
|
25-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
[arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores. This was already being done for loads.
Unfortunately, it is rather difficult to create a test case for this issue. It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| b300455b5817f099d64aad8f9356e0e23fa9a87e |
|
21-Feb-2013 |
Evan Cheng <evan.cheng@apple.com> |
Radar numbers don't belong in source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| be06aacaa9a270384599bbfa850b967e9996b9fb |
|
20-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to MI::copyImplicitOps().
This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.
Also add a corresponding MachineInstrBuilder method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| df1c637ac4b6f6587c037be55cafed665c732d8f |
|
10-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Remove getARMRegisterNumbering and replace with calls into
the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.
One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
|
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 95a7e80b5e6423f4daf4c674100706b0036d4fe0 |
|
24-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Nuke remnant bogus code.
r154362 was supposed to delete this bit, but obviously didn't.
rdar://11305594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 420761a0f193e87d08ee1c51b26bba23ab4bac7f |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 2d620c571cb53993b788893b6ef73a6e2805411f |
|
10-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM LDR/LDRT has the same encoding collision as STR/STRT.
Generalized logic of r154141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3ef737608ab005f320c2e20fcb3b914c677616ed |
|
06-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.
The load/store optimizer splits LDRD/STRD into two instructions when the
register pairing doesn't work out. For negative offsets in Thumb2, it uses
t2STRi8 to do that. That's fine, except for the case when the offset is in
the range [-4,-1]. In that case, we'll also form a second t2STRi8 with
the original offset plus 4, resulting in a t2STRi8 with a non-negative
offset, which ends up as if it were an STRT, which is completely bogus.
Similarly for loads.
No testcase, unfortunately, as any I've been able to construct is both large
and extremely fragile.
rdar://11193937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 892143ff70b5e7d0cb06e7c4596c232347806b17 |
|
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't kill the base register when expanding strd.
When an strd instruction doesn't get the registers it wants, it can be
expanded into two str instructions. Make sure the first str doesn't kill
the base register in the case where the base and data registers are
identical:
t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg
t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg
<rdar://problem/11101911>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| dc909bf46ba94bf123bf5c7273fa867bddffc4a2 |
|
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve implicit defs in ARMLoadStoreOptimizer.
When a number of sub-register VLRDS instructions are combined into a
VLDM, preserve any super-register implicit defs. This is required to
keep the register scavenger and machine code verifier happy.
Enable machine code verification after ARMLoadStoreOptimizer.
ARM/2012-01-26-CopyPropKills.ll was failing because of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 8d813de71e18dd73ed98e8d58407caba0265e38e |
|
28-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r153516: "Invalidate liveness in Thumb2ITBlockPass."
Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness."
These patches caused miscompilations in povray by turning off branch
folding's updating of live-in lists.
It turns out the the late scheduler depends on the live-in lists, even
if it doesn't need correct kill flags.
<rdar://problem/11139228>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 805543068eb7407d718b0359f54b342d7094d0ea |
|
27-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARMLoadStoreOptimizer invalidates register liveness.
This pass tries to update kill flags, but there are still many bugs.
Passes after the load/store optimizer don't need accurate liveness, so
don't even try.
<rdar://problem/11101911>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 0e5233a9e5ee9385c6a940e3985194d77bee0bbb |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 4ee1c5cf6c18db0fa4946437f0bca3dbb313e21b |
|
07-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed
load / store) if the ADD / SUB has a live definition of CPSR.
Bug reported by David Meyer. Alas, no test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 08c66642d70879cc479b502c048df4f5fdeaefae |
|
11-Jan-2012 |
Andrew Trick <atrick@apple.com> |
ARM Ld/St Optimizer fix.
Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits.
Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 70aaf37c11bbfffc8d3e007556da46c810e822a3 |
|
25-Nov-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 95bc85e4eefdfc1aabfde85daf752f05d2a60701 |
|
11-Nov-2011 |
Andrew Trick <atrick@apple.com> |
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
Fixes PR8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 44ee4714a8c245d4fdfd03840efcf58c3f66c6bc |
|
09-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide cpu name checking in ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3568a1051efb9a9edbd4914b04b44e9d7bc1b004 |
|
08-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| acb274baacbc104d7ef3b826b443847f11548760 |
|
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 07700d486ec790327723d2a81fe9c66b2fb52016 |
|
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9ab0f25fc194b4315db1b87d38d4024054120bf6 |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 10342123adec62151bf9060493dd13583c67ae52 |
|
13-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 19dec207fcc0f04902b7f097b7771ba7abba43fb |
|
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 793e79601f0fd68ba082fa2016018f80b2379460 |
|
26-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
|
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f6fd90910a552ad9883f031350ae517e26dfdb44 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 15993f83a419950f06d2879d6701530ae6449317 |
|
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 7bb1c4054986e51682ff89170c740cc16b921236 |
|
25-May-2011 |
Eric Christopher <echristo@apple.com> |
Clean up comment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 955db42568ae61c9f381a5af3e354d4270d06d92 |
|
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d7d030a44796adc73a6eaa939cd17e52047734c1 |
|
29-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 61f3cf3bc9c4db657eda5a4b9f4f8079e65aba8f |
|
06-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some code for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d0cfc99b308a805ffc130cde7317a0b0c626348f |
|
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9eae80051b6f6f5564b725221b2163a1f0d83672 |
|
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Add safety check that didn't show up in testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 848b0c39b11801614c47e460248b60e8d40eb257 |
|
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 019195229693c1829e6ed5a3f57209728fdcba8f |
|
15-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 79bb6dd363fd0a23040910b32d69a282063521bd |
|
15-Feb-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 4e97e8ee5748a92326078d744f5fc2b581a7b5b0 |
|
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Move code for OffsetCompare struct closer to where it is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f7ca976e74eafeeab0e9097f0fb07d6bb447415b |
|
13-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a few more places that should use MBB::getLastNonDebugInstr().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c36b7069b42bece963b7e6adf020353ce990ef76 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 6819dbb6f86f519130edf22ac3a30fa53b01fa45 |
|
06-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
PR8921: LDM/POP do not support interworking prior to v5t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 707120047e0107cb15dd4bbb31613df129b13c7a |
|
18-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Missed the _RET versions of LDMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| df8d94da01ccae58c93b03a5fb93fa1f05799c2f |
|
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add missing opcodes now that this function's used in more than one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| baa45f7298c266f0f89b17e50e9d98709dde84d7 |
|
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert r119109 for now. It's breaking 176.gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 2567eec4233d58a2a0cbdcafca9420452689b395 |
|
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The machine instruction no longer encodes the submode as a separate operand. We
should get the submode from the load/store multiple instruction's opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 73fe34a3ee866867d5028f4a9afa2c3b8efebcba |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| fbc8c67992d8c8b0f4ea07b29cf31a4f0c1b28fe |
|
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 7e3383c007f53b3a00675af225e428cb66ddf404 |
|
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f85dd04bfaba4b7d57833d576127439628cb2931 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3e5561247202bae994dd259a2d8dc4eff8f799f3 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 0eb7d06ab12bd66d04ea2329f71ceb2e8022f83a |
|
26-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| b179b46cc558c720d23a066c768bad71f975eb93 |
|
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Transfer implicit ops when forming load multiple and return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 7122ba7efb5430d724ed3a0ac86fa7f7185b43ba |
|
29-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| a4c3c8f28d9465dc7c42eb43c2377530f1821574 |
|
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 979927ab26a1832ee2ecd1edb17d50184756f474 |
|
10-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Calculate the number of VLDM/VSTM registers by subtracting the number of
fixed operands from the total number of operands (including the variadic ones).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| efe7d9a12f441a256d67c4e4da494dcefca678a5 |
|
10-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 253627967454246d347a5038ec971f6738f77f07 |
|
30-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remember to clear the shadow kill flag at the same time as clearing the real
kill flag.
This could cause duplicate kill flags when the same register was used twice in a
continuous sequence of STRs.
There is no small test case. <rdar://problem/8218046>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 14805e2afd5aa754e13fd5bb99365ffe972e9696 |
|
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
When merging Thumb2 loads/stores, do not give up when the offset is one of
the special values that for ARM would be used with IB or DA modes. Fall
through and consider materializing a new base address is it would be
profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d4bfd54ec2947e73ab152c3c548e4dd4beb700ba |
|
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3d38e8364a542abab6ca3d3aed658cf60d3112b4 |
|
27-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Unsigned value cannot be < 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 90c579de5a383cee278acc3f7e7b9d0a656e6a35 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 1f74590e9d1b9cf0f1f81a156efea73f76546e05 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9ccaf53ada99c63737547c0235baeb8454b04e80 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 628a79771ba6d293ba7b6f2615f022e1ae9c7c49 |
|
29-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
When no memoperands are present, assume unaligned, volatile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| fe60104ac97f3a8736dcfbfdf9547c7b7cc7b951 |
|
22-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Use pre-increment instead of post-increment when the result is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d95ea2da28901ca6e81645e444e528d66350d781 |
|
21-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 400c95fe3802821815c69077e48c8fd276ec6494 |
|
15-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Make sure to skip dbg_value instructions when finding an insertion point for
the combined load/store instruction. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| db03adb34615331c6ef55ebbd80d8bc750deefe0 |
|
10-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 6335ac67b60c69c7314b1fb16721ae4a51043fc0 |
|
09-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix copy/paste/modify think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 8af44b687b0ee552b696361e1ab4b2c178ff6f9e |
|
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Another fix to prevent debug info from affecting codegen. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 958e4e1967838766d327f1112e5b4900be939275 |
|
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
more dbg_value adjustments so debug info doesn't affect codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d089a7ac70397ea41fe6128639dc54b8e273ed60 |
|
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3de755bb407f91c494ae675fa6408a29b1954a52 |
|
04-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the ARM load-store optimizer to deal with dbg_value instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
|
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| ae541aad5c36cb3e4256514447d1f81e253079c7 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers for LLVM IR pointers in CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9a52d0c352c852dc9517430442afc54f53e1d4dd |
|
26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
vldm/vstm can only do up to 16 double-word registers at a time.
Radar 7797856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c88d0722931b8442cd347bd530e2182d164c82c6 |
|
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6652: Use LDM to restore PC to the return address on ARMv4.
Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 2d357f6b44159c59dbb58e03a22f94312696d064 |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant writeback flag in ARM addressing mode 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| ab3460519e8013cdba33a416cefd55dfb418999c |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the writeback flag from ARM's address mode 4. Now that we have separate
instructions for ld/st with writeback, the flag is completely redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 8d95e0be13079339c2b84f245fb1665953e2bc77 |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap a long line and add some parens to be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 815baebe1c8dc02accf128ae10dff9a1742d3244 |
|
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3943ac38c946aaac21dbe686978d098770d7679e |
|
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine the code to build VLDM and VSTM instructions, since they are
mostly the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e4193b20fd30e59c389814835ed2f6b3bc3b225c |
|
12-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Tidy up. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| bbf39b0fd9c83f1d46ca5f858e66de66fb64ec98 |
|
04-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9e6396d05ee43858f04b0f52eb7da6240845f530 |
|
24-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3f7aa79c2a46d525cf0468ad74ef2395246a309f |
|
12-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 069e100f9a79a63db177a521fd790f4d77d1209c |
|
14-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't fold insufficiently aligned ldr/str into ldm/stm instructions.
An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.
This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.
Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 1dbc38f52e2d6436ba79048013e42d96187993d8 |
|
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move kill flags when the same register occurs more than once in a sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 158a2263bd221a6920c6c7f7f96d6272344efb8f |
|
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle undef operands properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 6528966eaeaf38244ce165ef7c80326aa34a55ca |
|
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make insert position available to MergeOpsUpdate.
Rearrange arguments.
No functional changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3063aed8d29cf2418fc1c3022a3dd9c8de0e4922 |
|
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Perform kill flag calculations in new method. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f8e33e513f2620ea30fda7f17bc227729b7621b8 |
|
23-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move repeated code to a new method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| cabdd7425d30f7eb659ecb0cc5efbc4052dd78a8 |
|
19-Dec-2009 |
Douglas Gregor <dgregor@apple.com> |
Fix a bunch of little errors that Clang complains about when its being pedantic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 7896c9f436a4eda5ec15e882a7505ba482a2fcd0 |
|
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 0cd22dd7383111192571884eb941ac2ccb668025 |
|
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 |
|
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| faf93aa23390389375b8e52f0dd1c3727ed07ee8 |
|
22-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d20d6586759fe7a53ec8b1dde80622cda49e31b8 |
|
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| fa1be5d99153a4709740ce5aabba3793e9f77982 |
|
29-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e298ab26b11cf6e278b4876bbc5b890e234d4029 |
|
27-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable pre-regalloc load / store multiple pass for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 8f05c1004a642ba79c609b40cb3b6524d810b5f3 |
|
26-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| eef490f45919c8f279e40b8b5ef09f612ec6ce2c |
|
25-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up and prepare for Thumb2 support. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e11a8f565c6a019ddc54667227be9c4d8f117473 |
|
11-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Update register class references to use the global constant ARM::*RegisterClass names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c0823fe7c679ca8f7d1667a310c2fca97b9402d5 |
|
18-Aug-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify RegScavenger::FindUnusedReg.
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
|
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 764ab52dd80310a205c9888bf166d09dab858f90 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 8fb903604e83dfd63659c919042bf2bfed3c940f |
|
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 861986401e05e437cb33bfd8320d510b956fe41e |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9e7a312391cb955bfc148d15a69adcaf7cc3ae50 |
|
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| eb084d16712ededa4486e1dd05ba98aa3d40646c |
|
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 27934da97bcb7a6a4949dfc0c449d99f43077e98 |
|
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Load / store multiple pass fixes for Thumb2. Not enabled yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 446c428bf394b7113b0f18cbacb5e87b4efd1e14 |
|
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9c06178e355be69e313820d31878022bc882c2db |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove a bogus assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 45032f28013aa69d07bf859da9d976947910f059 |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e7cbe4118b7ddf05032ff8772a98c51e1637bb5c |
|
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| ab7c09b6b6f4516a631fd6788918c237c83939af |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| ae69a2a12bd0af3fa81957f7896d1a54ad69dbb2 |
|
20-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable arm pre-allocation load / store multiple optimization pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 974fe5d69187bdf33b0e111ff72e965431df4191 |
|
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4 |
|
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 675860758ec8926f9803840615366931aca7f8d8 |
|
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d780f357941fc587d36d141bab3d78d6ff972dd4 |
|
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 7f044287388843d1c094a3c0b8beef47ea403ef6 |
|
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Silence a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 358dec51804ee52e47ea3a47c9248086e458ad7c |
|
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e7d6df73530a98a5cc5f69ddfd17073b464caa57 |
|
13-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 925492279ae7d93180ebdd689c87cd58522e68f5 |
|
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 87d59e49e9008767896c4c8c80efdc172f1cbd18 |
|
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
When merging multiple load / store instructions. Use the DebugLoc of the first one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 5ba71887f918a9da82140210494608df020dcbd5 |
|
05-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up: return vector by reference rather than by value. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 1488326156741063fa7a23e1638c13e81d167e22 |
|
04-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 70fd60bd57250799672378fa2f7c5e804cb3d98d |
|
03-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily revert 72756 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9d5fb981b0ebc00e068b9bcb4df7388a8ea94b71 |
|
03-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fold preceding / trailing base inc / dec into the single load / store as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
|
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| b67284057ee130114055309eabe0bcd1af13777d |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc versions of BuildMI from ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| ae73dc1448d25b02cabc7c64c86c64371453dda8 |
|
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Tidy up several unbeseeming casts from pointer to intptr_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 5080f4d9919d39b367891dc51e739c571a66036c |
|
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename MachineInstr::setInstrDescriptor -> setDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 69244300b8a0112efb44b6273ecea4ca6264b8cf |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 |
|
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| e71bff7405392ad5904f986724a65f965c0686e8 |
|
19-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Avoid referencing deleted instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 13ab020ea08826f1b87db6ec3da63889a12e3d9d |
|
10-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 0e1d37904abbf7e8c4c478408253dd995f3040f4 |
|
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Reflects the chanegs made to PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 62ccdbf0b3b75661bcdb20476609fece499c767f |
|
29-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add missing const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 44bec52b1b7e9a3ac1efbae90db240b8c1ca2ad4 |
|
15-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add PredicateOperand to all ARM instructions that have the condition field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 1997473cf72957d0e70322e2fe6fe2ab141c58a6 |
|
03-May-2007 |
Devang Patel <dpatel@apple.com> |
Drop 'const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 3e15bf33e024b9df9e89351a165acfdb1dde51ed |
|
02-May-2007 |
Devang Patel <dpatel@apple.com> |
Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 794fd75c67a2cdc128d67342c6d88a504d186896 |
|
01-May-2007 |
Devang Patel <dpatel@apple.com> |
Do not use typeinfo to identify pass in pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| faa510726f4b40aa4495e60e4d341c6467e3fb01 |
|
26-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| f6fa5ee5c201f91217c3034ddcaecb63e7d8cd5a |
|
27-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
findRegisterUseOperand() changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 11788fde93fb74636aa333b2910d606d2c19ba9e |
|
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Bug fix. Not advancing the register scavenger iterator correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 603b83ebcdfb9c27e44c1da16f2799755e3e3022 |
|
07-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Only safe to use a call-clobbered or spilled callee-saved register as scratch register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| 0ea12ec8484c45ca1394f3b2dcd39c9a34cf2ab9 |
|
07-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| a90f3408b3aca71cd438efa2c539af041430e059 |
|
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make load / store optimizer use register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| cc1c427266817e0f41cbb9d0dc97a52890182040 |
|
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. Prepare to use register scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34976 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|
| a8e2989ece6dc46df59b0768184028257f913843 |
|
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
|