| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 1b26fdbf1f01e90b803cc035b6b932cd95c76830 |
|
02-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196046:
------------------------------------------------------------------------
r196046 | tnorthover | 2013-12-01 06:16:24 -0800 (Sun, 01 Dec 2013) | 8 lines
ARM: fix bug in -Oz stack adjustment folding
Previously, we clobbered callee-saved registers when folding an "add
sp, #N" into a "pop {rD, ...}" instruction. This change checks whether
a register we're going to add to the "pop" could actually be live
outside the function before doing so and should fix the issue.
This should fix PR18081.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 323ac85d6ad7ba5d9593d8e151d879bd91d82e08 |
|
08-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fold prologue/epilogue sp updates into push/pop for code size
ARM prologues usually look like:
push {r7, lr}
sub sp, sp, #4
If code size is extremely important, this can be optimised to the single
instruction:
push {r6, r7, lr}
where we don't actually care about the contents of r6, but pushing it subtracts
4 from sp as a side effect.
This should implement such a conversion, predicated on the "minsize" function
attribute (-Oz) since I've yet to find any code it actually makes faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| e53abc20724ddde4e91467671328b531361a734f |
|
05-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove unnecessary state-tracking during frame lowering.
ResolveFrameIndex had what appeared to be a very nasty hack for when the
frame-index referred to a callee-saved register. In this case it "adjusted" the
offset so that the address was correct if (and only if) the MachineInstr
immediately followed the respective push.
This "worked" for all forms of GPR & DPR but was only ever used to set the
frame pointer itself, and once this was put in a more sensible location the
entire state-tracking machinery it relied on became redundant. So I stripped
it.
The only wrinkle is that "add r7, sp, #0" might theoretically be slower (need
an actual ALU slot) compared to "mov r7, sp" so I added a micro-optimisation
that also makes emitARMRegUpdate and emitT2RegUpdate also work when NumBytes ==
0.
No test changes since there shouldn't be any functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 083bc97344d618884ef04bc1ba1fc4ddf14d867d |
|
20-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:
Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ...
FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.
We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.
This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| f65e4932f83ac0c36594d97fca73dc9a9fd26672 |
|
30-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Refactoring patch.
1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong.
This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method.
2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed.
3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
|
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| af3a5420aeb421e83694745c53141683caa123cb |
|
20-Feb-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix thumbv5e frame lowering assertion failure.
It is possible that frame pointer is not found in the
callee saved info, thus FramePtrSpillFI may be incorrect
if we don't check the result of hasFP(MF).
Besides, if we enable the stack coloring algorithm, there
will be an assertion to ensure the slot is live. But in
the test case, %var1 is not live in the prologue of the
function, and we will get the assertion failure.
Note: There is similar code in ARMFrameLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| be06aacaa9a270384599bbfa850b967e9996b9fb |
|
20-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to MI::copyImplicitOps().
This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.
Also add a corresponding MachineInstrBuilder method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| c1f6f42049696e7357fb4837e1b25dabbaed3fe6 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes to match coding standards. Fix an issue or two exposed by that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 79aa048d2102a7d4c8abbba82b4b8a41dbc32214 |
|
08-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to transfer implicit uses of return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147752 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| ccec74738d0fc34f4bc2ac6909324e62705f1c38 |
|
07-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug is
exposed with an upcoming change will would delete the copy to return register
because there is no use! It's amazing anything works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| afad0fe59a791cb4fd87fbd7ea2b1aba8d67a7af |
|
04-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix more places which should be checking for iOS, not darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 6690bca623d1f6405b95db5b1760f7ba8436e3fb |
|
20-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| fe04757f5e06ab15208ac0a2ab8d7e83c62b9f0d |
|
18-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for dynamic stack realignment when in thumb1 mode.
rdar://10288916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| d73462a1c9e9abae6d404c7830224814ef293f0d |
|
15-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Thumb1 does not support dynamic stack realignment.
rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 2bfaf521aed6d486b2d80dbf12b84b456100cb47 |
|
01-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
to appease nightly testers. Not quite there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 52490411259ccc34b8c59f3532e78442a46fffd7 |
|
01-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| b04546ff5b1a7a03eec1076900c945223bf494cc |
|
13-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 5b81584f7403ffdb9cc6babaaeb0411c080e0f81 |
|
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 25e6d48220330d17875d0ae0ad6a45597d5ac36c |
|
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 63b46faeb8acae9b7e5f865b7417dc00b9b9dad3 |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 74472b4bf963c424da04f42dffdb94c85ef964bc |
|
29-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Refactor away tSpill and tRestore pseudos in ARM backend.
The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 7980f61f5ff408b947474cd1c3715896d28ea578 |
|
13-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix coordination for using R4 in Thumb1 as a scratch for SP restore.
The logic for reserving R4 for use as a scratch needs to match that for
actually using it. Also, it's not necessary for immediate <=508, so adjust
the value checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 3daccd82d3151fa3629de430b55698a81084fc9e |
|
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 |
|
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 4f28c1c71450c711e96aa283de53739d8b4504cd |
|
13-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach frame lowering to ignore debug values after the terminators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 94bb7b561c16878ae442adeb13dd42140b55d027 |
|
11-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Even if we don't have 7 bytes of stack space we may need to save and
restore the stack pointer from the frame pointer on thumbv6.
Fixes rdar://8819685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
|