| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
ndroid.mk
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
CTargetDesc/Android.mk
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsABIFlagsSection.cpp
CTargetDesc/MipsABIFlagsSection.h
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsAsmBackend.h
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCAsmInfo.cpp
CTargetDesc/MipsMCCodeEmitter.cpp
CTargetDesc/MipsMCCodeEmitter.h
CTargetDesc/MipsMCExpr.cpp
CTargetDesc/MipsMCExpr.h
CTargetDesc/MipsMCTargetDesc.cpp
CTargetDesc/MipsNaClELFStreamer.cpp
CTargetDesc/MipsTargetStreamer.cpp
icroMipsInstrFPU.td
icroMipsInstrInfo.td
ips.td
ips16FrameLowering.cpp
ips16FrameLowering.h
ips16ISelDAGToDAG.cpp
ips16ISelLowering.cpp
ips16ISelLowering.h
ips16InstrInfo.td
ips32r6InstrFormats.td
ips32r6InstrInfo.td
ips64InstrInfo.td
ips64r6InstrInfo.td
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsCallingConv.td
ipsCodeEmitter.cpp
ipsCondMov.td
ipsDSPInstrFormats.td
ipsDelaySlotFiller.cpp
ipsFastISel.cpp
ipsFrameLowering.h
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrFPU.td
ipsInstrFormats.td
ipsInstrInfo.td
ipsLongBranch.cpp
ipsMSAInstrFormats.td
ipsMachineFunction.h
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEFrameLowering.h
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
ipsSEISelLowering.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsSelectionDAGInfo.cpp
ipsSelectionDAGInfo.h
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
ipsTargetMachine.h
ipsTargetStreamer.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
ndroid.mk
smParser/LLVMBuild.txt
smParser/MipsAsmParser.cpp
MakeLists.txt
isassembler/LLVMBuild.txt
isassembler/MipsDisassembler.cpp
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsAsmBackend.h
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCAsmInfo.h
CTargetDesc/MipsMCCodeEmitter.cpp
CTargetDesc/MipsMCCodeEmitter.h
CTargetDesc/MipsMCExpr.cpp
CTargetDesc/MipsMCExpr.h
CTargetDesc/MipsMCNaCl.h
CTargetDesc/MipsMCTargetDesc.cpp
CTargetDesc/MipsNaClELFStreamer.cpp
CTargetDesc/MipsTargetStreamer.cpp
akefile
icroMipsInstrFPU.td
icroMipsInstrInfo.td
ips.td
ips16FrameLowering.cpp
ips16FrameLowering.h
ips16HardFloat.cpp
ips16HardFloat.h
ips16HardFloatInfo.cpp
ips16ISelDAGToDAG.cpp
ips16ISelDAGToDAG.h
ips16ISelLowering.cpp
ips16ISelLowering.h
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ips32r6InstrFormats.td
ips32r6InstrInfo.td
ips64InstrInfo.td
ips64r6InstrInfo.td
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsCallingConv.td
ipsCodeEmitter.cpp
ipsCondMov.td
ipsConstantIslandPass.cpp
ipsDelaySlotFiller.cpp
ipsFastISel.cpp
ipsFrameLowering.cpp
ipsFrameLowering.h
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrFPU.td
ipsInstrFormats.td
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsInstrInfo.td
ipsJITInfo.cpp
ipsJITInfo.h
ipsLongBranch.cpp
ipsMCInstLower.cpp
ipsMCInstLower.h
ipsMSAInstrInfo.td
ipsMachineFunction.cpp
ipsMachineFunction.h
ipsModuleISelDAGToDAG.cpp
ipsModuleISelDAGToDAG.h
ipsOptimizePICCall.cpp
ipsOs16.cpp
ipsOs16.h
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEFrameLowering.h
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
ipsSEISelLowering.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
ipsSelectionDAGInfo.cpp
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
ipsTargetMachine.h
ipsTargetStreamer.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
ndroid.mk
smParser/Android.mk
smParser/CMakeLists.txt
smParser/MipsAsmParser.cpp
MakeLists.txt
isassembler/Android.mk
isassembler/CMakeLists.txt
isassembler/MipsDisassembler.cpp
nstPrinter/Android.mk
nstPrinter/CMakeLists.txt
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
LVMBuild.txt
CTargetDesc/Android.mk
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsAsmBackend.h
CTargetDesc/MipsBaseInfo.h
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsELFStreamer.h
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
CTargetDesc/MipsMCCodeEmitter.h
CTargetDesc/MipsMCExpr.cpp
CTargetDesc/MipsMCExpr.h
CTargetDesc/MipsMCNaCl.h
CTargetDesc/MipsMCTargetDesc.cpp
CTargetDesc/MipsMCTargetDesc.h
CTargetDesc/MipsNaClELFStreamer.cpp
CTargetDesc/MipsReginfo.cpp
CTargetDesc/MipsReginfo.h
CTargetDesc/MipsTargetStreamer.cpp
SA.txt
icroMipsInstrFPU.td
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ips.h
ips.td
ips16FrameLowering.cpp
ips16HardFloat.cpp
ips16HardFloatInfo.cpp
ips16HardFloatInfo.h
ips16ISelDAGToDAG.cpp
ips16ISelLowering.cpp
ips16ISelLowering.h
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
ips16RegisterInfo.cpp
ips64InstrInfo.td
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsCallingConv.td
ipsCodeEmitter.cpp
ipsCondMov.td
ipsConstantIslandPass.cpp
ipsDelaySlotFiller.cpp
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrFPU.td
ipsInstrFormats.td
ipsInstrInfo.td
ipsLongBranch.cpp
ipsMCInstLower.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsMachineFunction.h
ipsOptimizePICCall.cpp
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
ipsSEISelLowering.h
ipsSEInstrInfo.cpp
ipsSERegisterInfo.cpp
ipsSchedule.td
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
ipsTargetObjectFile.cpp
ipsTargetObjectFile.h
ipsTargetStreamer.h
argetInfo/Android.mk
argetInfo/CMakeLists.txt
argetInfo/LLVMBuild.txt
|
| bd3e4ce9cfa61bcc0176ac17a06f0904cb854a9a |
19-Feb-2014 |
Colin Cross <ccross@android.com> |
am b7485134: am 449fc261: Merge "llvm: convert makefiles to support multilib build"
* commit 'b7485134a2cbecc47904988b4cfde24019ac4fa1':
llvm: convert makefiles to support multilib build
|
| 373aa5c665fe6df6b9c5586d397dc3617f25aab5 |
07-Feb-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to 3.4.
Update config.h files.
Add RS SubtargetFeature for +long64 on ARM devices.
Adjust Android.mk for added/removed files:
+ Delinearization.cpp
- PathNumbering.cpp
- PathProfileInfo.cpp
- PathProfileVerifier.cpp
- ProfileDataLoader.cpp
- ProfileDataLoaderPass.cpp
- ProfileEstimatorPass.cpp
- ProfileInfo.cpp
- ProfileInfoLoader.cpp
- ProfileInfoLoaderPass.cpp
- ProfileVerifierPass.cpp
+ LiveRegUnits.cpp
- ShrinkWrapping.cpp
+ StackMaps.cpp
- StrongPHIElimination.cpp
+ DIEHash.cpp
+ LegacyPassManager.cpp
+ ELF.cpp
+ Unicode.cpp
- MipsOptimizeMathLibCalls.cpp
- MipsELFStreamer.cpp
+ MipsTargetStreamer.cpp
- EdgeProfiling.cpp
+ DataFlowSanitizer.cpp
+ DebugIR.cpp
- OptimalEdgeProfiling.cpp
- PathProfiling.cpp
- ProfilingUtils.cpp
- BasicBlockPlacement.cpp
+ LoopRerollPass.cpp
+ PartiallyInlineLibCalls.cpp
+ SampleProfile.cpp
+ GlobalStatus.cpp
Change-Id: I17dcf0bf53a1720acd8226ae3e30d84993562a91
ndroid.mk
CTargetDesc/Android.mk
|
| ce9904c6ea8fd669978a8eefb854b330eb9828ff |
12-Feb-2014 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/release_34' into merge-20140211
Conflicts:
lib/Linker/LinkModules.cpp
lib/Support/Unix/Signals.inc
Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
|
| b7325c318ecf01d4c82391c1f0a63090c8de0144 |
05-Feb-2014 |
Colin Cross <ccross@android.com> |
llvm: convert makefiles to support multilib build
Convert makefiles to allow for building two architectures at the
same time. This will also cause make checkbuild to build the target
libraries for all supported architectures.
Change-Id: Ia5e6fe5b1186a67753faafd3532ed4cb280a8b10
ndroid.mk
isassembler/Android.mk
CTargetDesc/Android.mk
argetInfo/Android.mk
|
| 102f231863034e18863333bf850f8037b46e6947 |
01-Dec-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Merged r195973:
------------------------------------------------------------------------
r195973 | dsanders | 2013-11-30 13:47:57 +0000 (Sat, 30 Nov 2013) | 5 lines
[mips][msa] MSA loads and stores have a 10-bit offset. Account for this when lowering FrameIndex.
This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s
when the stack frame is between 512 and 32,768 bytes in size.
------------------------------------------------------------------------
Review of this commit by Matheus Almeida revealed that it is still possible to
emit invalid code (when the offset is not a multiple of the element size).
However, we agreed that this commit still represents an improvement since it
fixes many cases that previously emitted invalid code, and does not cause any
cases that previously emitted valid code to emit invalid code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196049 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSERegisterInfo.cpp
|
| ff4b604f961aa9b9ec2f05a5c31885b19fa636e4 |
01-Dec-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Merged r195972:
------------------------------------------------------------------------
r195972 | dsanders | 2013-11-30 13:15:21 +0000 (Sat, 30 Nov 2013) | 5 lines
[mips][msa] A small refactor to reduce patch noise in my next commit
No functional change. An if-statement has been split into two nested if-statements.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196047 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSERegisterInfo.cpp
|
| 88fc0183be1b1fc94375421c48f8e0ef6fa9139e |
01-Dec-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Merged from r195975 and r195976.
------------------------------------------------------------------------
r195975 | zjovanovic | 2013-11-30 19:12:28 +0000 (Sat, 30 Nov 2013) | 1 line
Fixed issue with microMIPS long branch.
------------------------------------------------------------------------
r195976 | zjovanovic | 2013-11-30 19:13:15 +0000 (Sat, 30 Nov 2013) | 1 line
Test case for issue with microMIPS long branch.
------------------------------------------------------------------------
To expand on those commit messages:
The immediate in a MIPS branch is multiplied by the instruction size before use
as an offset. For many MIPS ISA's this is 4 bytes, but for microMIPS it is 2
bytes. This commit corrects the scale factor used for microMIPS so that attempts
to use large offsets result in a valid sequence of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196043 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| 9f71b97c0cd7ff930164fafe8d6d5b5a9b871c86 |
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195456:
------------------------------------------------------------------------
r195456 | dsanders | 2013-11-22 05:22:52 -0800 (Fri, 22 Nov 2013) | 4 lines
Fix typo in a comment added in r195455.
Credit to Matheus Almeida for spotting it.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195743 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 876f8f123e9a52bf8e970f9e04b93700380b5dbf |
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195444:
------------------------------------------------------------------------
r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines
[mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.
Fixes an instruction selection failure detected by llvm-stress.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195742 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 1184bebd31edac189a2c129ba93795b66cf4876d |
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195364:
------------------------------------------------------------------------
r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines
[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.
Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.
In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195741 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 9148c5d5495a25e8479f6a58e57f7058da1b4871 |
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195343:
------------------------------------------------------------------------
r195343 | dsanders | 2013-11-21 03:40:14 -0800 (Thu, 21 Nov 2013) | 5 lines
[mips][msa/dsp] Only do DSP combines if DSP is enabled.
Fixes a crash (null pointer dereferenced) when MSA is enabled.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195740 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| a87a147ee7bb9adb4caea631ff0ba7e66bb9b0b5 |
20-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195152:
------------------------------------------------------------------------
r195152 | jacksprat | 2013-11-19 12:53:28 -0800 (Tue, 19 Nov 2013) | 1 line
reverts 195057 per request
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195220 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsMCTargetDesc.cpp
CTargetDesc/MipsTargetStreamer.cpp
ipsAsmPrinter.cpp
ipsTargetStreamer.h
|
| e40e68add7f17f6ad5cd5e85ea44b149f6935147 |
19-Nov-2013 |
Eric Christopher <echristo@gmail.com> |
Remove unused special member functions and reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195077 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsTargetStreamer.cpp
ipsTargetStreamer.h
|
| 15602d786beee8308af765ade2e6debde2b81ad2 |
19-Nov-2013 |
Eric Christopher <echristo@gmail.com> |
Fix previous commit and fully remove variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195076 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCTargetDesc.cpp
CTargetDesc/MipsTargetStreamer.cpp
ipsTargetStreamer.h
|
| 2a4888b347ec1e7f69dcf2dcad0d7fd7baef50c5 |
19-Nov-2013 |
Eric Christopher <echristo@gmail.com> |
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195075 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetStreamer.h
|
| e53969b4758274ee833ce3acef37134bcf6554ea |
19-Nov-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] Support for MicroMips STO refactoring.
No true functional changes.
Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.
Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.
XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsTargetStreamer.cpp
ipsAsmPrinter.cpp
ipsTargetStreamer.h
|
| 354362524a72b3fa43a6c09380b7ae3b2380cbba |
19-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsTargetStreamer.h
|
| 4c1625b3cb23745dba38e205b20e7b63954d8067 |
19-Nov-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] MipsTargetStreamer refactoring.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195057 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsMCTargetDesc.cpp
CTargetDesc/MipsTargetStreamer.cpp
ipsTargetStreamer.h
|
| 23427207ea575f57b571cf5aad1effb1f97e7ee1 |
18-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)
Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelDAGToDAG.cpp
ipsSEInstrInfo.cpp
|
| 26651c7a6602626cf13ff3cda13f3ec2401bf790 |
18-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 95adf91f29980e374bf094e15bc3f2764ef9baf4 |
18-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
CTargetDesc/MipsMCCodeEmitter.cpp
ipsCodeEmitter.cpp
ipsMSAInstrInfo.td
|
| b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 |
18-Nov-2013 |
Alexey Samsonov <samsonov@google.com> |
Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCTargetDesc.cpp
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsTargetStreamer.h
|
| 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 |
15-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCTargetDesc.cpp
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsTargetStreamer.h
|
| cb85ded9980644fc6a3ff7d8e4dc56351adcc114 |
15-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of using a long-winded equivalent.
Now that getConstant(-1, MVT::v2i64) works correctly on MIPS32 we can use
SelectionDAG::getNOT() to produce the bitmask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194819 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| ea28aafa83fc2b6dd632041278c9a18e5a2b2b41 |
15-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 type
Summary:
When getConstant() is called for an expanded vector type, it is split into
multiple scalar constants which are then combined using appropriate build_vector
and bitcast operations.
In addition to the usual big/little endian differences, the case where the
element-order of the vector does not have the same endianness as the elements
themselves is also accounted for. For example, for v4i32 on big-endian MIPS,
the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is
<0123,4567,89AB,CDEF>.
Handling this case turns out to be a nop since getConstant() returns a splatted
vector (so reversing the element order doesn't change the value)
This fixes a number of cases in MIPS MSA where calling getConstant() during
operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF
into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger
differences between illegal and legal types such as legalizing v2i64 into v8i16.
lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling
getConstant() so this function has been updated in the same patch.
For the sake of transparency, the steps I've taken since the review are:
* Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed
that the MIPS tests were falsely passing because a polymorphic function was
not actually polymorphic in the reviewed patch.
* Fixed the tests that were now failing. This involved deleting the code to
handle the MIPS MSA element-order (which was previously doing an byte-order
swap instead of an element-order swap). This left
isVectorEltOrderLittleEndian() unused and it was deleted.
* Fixed build failures caused by rebasing beyond r194467-r194472. These build
failures involved the bset, bneg, and bclr instructions added in these commits
using lowerMSASplatImm() in a way that was no longer valid after this patch.
Some of these were fixed by calling SelectionDAG::getConstant() instead,
others were fixed by a new function getBuildVectorSplat() that provided the
removed functionality of lowerMSASplatImm() in a more sensible way.
Reviewers: bkramer
Reviewed By: bkramer
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 42cb3abaddfcff16ab18b114c3de034839c85e05 |
15-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Use instr mapping for microMIPS in llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
ipsInstrInfo.td
|
| 1703a714954f9ef0c32415423e2a1e15b152e711 |
15-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range.
Since there is not direct object emitter at this time, it does not
have any material affect because the assembler sorts this out. But we
need to know for the actual constant island work. We track the difference
by putting # 16 inst in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| 5aeb5e530e11a1473ecddb126b72cd4e37fada81 |
14-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Take care of long short branch immediate instructions for mips16 in
constant islands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194630 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| c0fad4d9fdb1aebe029bcb54311fad7059b1a9e5 |
13-Nov-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Fix bug in .gpword directive parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 1206f1968b0886ab41739aebe113dd4813f3fc46 |
13-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS trap instruction with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| c7ebe502765fecc2af047ced115845936e8ed58e |
13-Nov-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 6c242d385b44d063a8a9d4690e5a9d8fdd72ef35 |
13-Nov-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Mips16InstrInfo.cpp: Use <cctype> instead of <ctype.h>
Also, prune <stdlib.h>, seems stray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194557 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
|
| 4df21b14675954ba951ad118d1dc4a4021650078 |
13-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Allow the code which returns the length for inline assembler to know
specifically about the .space directive. This allows us to force large
blocks of code to appear in test cases for things like constant islands
without having to make giant test cases to force things like long
branches to take effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194555 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ipsConstantIslandPass.cpp
|
| 714e04b84ac5c2342f468aa55953694e4cdf3834 |
12-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix a bug in function CC_MipsO32_FP64. The second double precision
argument was not being passed in $f14.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| d4765aa047c43dc0ce2c4a6a3ccdb91b8fa73c51 |
12-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Revert part of r194510 that was accidentally committed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194511 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 0a227ad4d5e12ca90fd937bf2b05d8bca291a1ad |
12-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix and re-enable a test case that has been disabled for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 9e2838e29b0820afc35f6ef2d465d4aca9ed402a |
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
asm ("ldi.w %w0, 1", "=f"(result));
Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.
MSA registers (including control registers) are supported in clobber lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsISelLowering.cpp
|
| 92e94a2ee44aefda151125fdb62bf9d5b54edfb2 |
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Fix buildbot failures caused by an unused variable when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194472 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| bb47fd04c9b1616c0371eb2c488c5f0f665c25f8 |
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
SA.txt
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsMSAInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
|
| aee7825762830536956b9e634fd7ffd59396984d |
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| c6d4d667a8a56b341fac949153ec5939857445df |
12-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Change the default branch instruction to be the 16 bit variety for mips16.
This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
ipsConstantIslandPass.cpp
|
| 5635de519acc30856ac3081559b507679348ad26 |
11-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Partially revert r193641. Stack alignment should not be determined by
the floating point register mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSubtarget.h
|
| 50d3b27f431a213a53a0240849a8ce65dc46c8a5 |
10-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Mostly finish up constant islands port for Mips for load constants.
Still need to finish the branch part. Still lots more review of the code,
clean up and testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194337 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| 95830221bd4877816adc6707eb34ca68c5a515d2 |
09-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| de712386cdde314ee18ea44b733d48a30d63de10 |
08-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 9f471750fa6f34120d4758d5d14f54f899e34a54 |
07-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 1101cde7707b4dda9385ac399b2ff83e0ef494cd |
07-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Disable some code that is causing some warnings. It's in the process
of being converted and this path is not relevant to anything at this time
so I have just disabled it for a few days while I'm at the LLVM conference
and don't have time to complete it or properly fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194201 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| 2263a2ca72e21206d45a69532004a0b17881e733 |
06-Nov-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 7851bc1871dcb7c31b603b17cf975ae0b55f4c30 |
06-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Fix definition for Mips16 pc relative load word instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194126 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| c9080b7bc9fa7acb8cfe65e22b40697ef8286c27 |
06-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Get rid of current calculation function and adjustment scheme
from MipsConstantIslands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194108 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| 14cfb10174fa443074c235a207d290a9816392f8 |
05-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Get rid of all references to soimm in MipsConstantIslands pass because
we don't have such an operand.
Suprisingly enough, this is never actually accounted for in the
ARM version when determining offset ranges. In both places there is the
comment:
- // FIXME: Make use full range of soimm values.
(soimm = shift operand immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194101 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| 1fa282d63538477d686015ad1883fa44d5e12605 |
05-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Cleanup getUserOffset. Issues related to inline assembler length and
alignment will be handled differently than in ARM constant islands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194096 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| a2e6e6bcf8cc37ad91b130b9d02d9fe951fbb4d1 |
05-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Remove the word "thumb" from comments. Remove also an incorrect
command regarding the porting from the ARM version (was an old comment).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194066 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| c0e9800d45a2a08c95005385352a0ec9d6271498 |
05-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Fix r194019 as requested by Eric Christopher.
Submit the basic port of the rest of ARM constant islands code to Mips.
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose. When everything
has been completed I will summarize the port and notify people that
are knowledgable regarding the ARM Constant Islands code so they can
review it in it's entirety if they wish.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194053 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsConstantIslandPass.cpp
|
| 225f35a87ceb12adc29c4232749f3d44d86a1765 |
05-Nov-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Revert r194019 to r194021, "Submit the basic port of the rest of ARM constant islands code to Mips."
It broke -Asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194026 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsConstantIslandPass.cpp
|
| ba29378fdc8aa184c0d7fa08022790b7ec7d8acf |
04-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Make sure we don't get a warning from this variable that is only used
when compiling with DEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194021 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| 1ef90831229a586c2421be4ae9f1e990312a4f95 |
04-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Submit the basic port of the rest of ARM constant islands code to Mips.
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194019 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsConstantIslandPass.cpp
|
| 5c042162beb3c2dd556e00aab84c4278a69cd5b1 |
04-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ips64InstrInfo.td
ipsCodeEmitter.cpp
ipsInstrFormats.td
ipsInstrInfo.td
|
| 75ac8df380e2bad6b7e0798641b8b1805a393339 |
30-Oct-2013 |
Hans Wennborg <hans@hanshq.net> |
Add #include of raw_ostream.h to MipsSEISelLowering.cpp
Fixing this Windows build error:
..\lib\Target\Mips\MipsSEISelLowering.cpp(997) : error C2027: use of undefined type 'llvm::raw_ostream'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193696 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 02fbffd4e8e1a28539b302e4de84203814898153 |
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| c385709d8397ca1535481c04564b67d07c66c619 |
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).
These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.
bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
values is an uimm8, rather than when the condition is a uimm8 (which is
covered by bmnzi.b)
compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
is the same operation (see MSA.txt).
i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
distinguishable from bmnzi.b.
vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
MSA.txt).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
SA.txt
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de |
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.
It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().
Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
SA.txt
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsMSAInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
|
| a7c3cac87118c3e409a7fc889090c5ffe242985e |
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECT
(or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b).
where $mask is a constant splat. This allows bitwise operations to make use
of bsel.
It's also a stepping stone towards matching bins[lr], and bins[lr]i from
normal IR.
Two sets of similar tests have been added in this commit. The bsel_* functions
test the case where binsri cannot be used. The binsr_*_i functions will
start to use the binsri instruction in the next commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| aed9334acfdd8fa7548dc540fe865a5a641cb208 |
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips] MipsSETargetLowering now reports DAGCombiner changes when using -debug-only=mips-isel
No test since -debug output is intended for developers and not end-users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193681 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 57cd3bc4064bd71eb6572d3cba5e23471ab25863 |
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics)
splat.d is implemented but this subtest is currently disabled. This is because
it is difficult to match the appropriate IR on MIPS32. There is a patch under
review that should help with this so I hope to enable the subtest soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193680 91177308-0d34-0410-b5e6-96231b3b80d8
SA.txt
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 99a43d3b8f5cf86b333055a56220c6965fd9ece4 |
30-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Compute stack alignment on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193673 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsSubtarget.cpp
ipsSubtarget.h
|
| 615a279f81e08e9c63fd5e411b33d39bfe593314 |
29-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Align the stack to 16-bytes for mfp64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ips16FrameLowering.h
ipsSEFrameLowering.h
ipsSubtarget.cpp
ipsSubtarget.h
|
| ffc7dca885151ed42642c2d6733e8db75d276621 |
29-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a helper getSymbol to AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsMCInstLower.cpp
|
| 1aaf43c2a2ec0fd4c8dbfe56558237219c5f8af7 |
29-Oct-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ips64InstrInfo.td
ipsCodeEmitter.cpp
ipsInstrFormats.td
ipsInstrInfo.td
|
| a300b1cc29020b7dfaf7bfe443d38af8fbec7433 |
29-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
The asm printer has a mangler. Use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193618 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsMCInstLower.cpp
ipsMCInstLower.h
|
| 5956bed6992577d2899b81498b1703e07efc2057 |
28-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify LowerFormalArguments using getRegClassFor.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193540 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 1fe9069d53f586963d61523f7c5a7d41d80a9d8b |
28-Oct-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Prune utf8 chars in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193512 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| f3ad5745681ece7af3027fd2f82fadb0247242e8 |
28-Oct-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Prune trailing linefeeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193511 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| cb2280e4c7c5a07104306cc73265ff64fa8dd973 |
27-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
Make first substantial checkin of my port of ARM constant islands code to Mips.
Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193509 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsConstantIslandPass.cpp
ipsInstrInfo.cpp
ipsInstrInfo.td
ipsSubtarget.cpp
ipsSubtarget.h
|
| 0082717cb537e2d1424f755a49510fa9f9e67071 |
23-Oct-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS relocations 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193247 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
|
| f7b6bac2629c09b5dcdf9dd926c02490d2c81cd2 |
23-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for the LSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193240 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 09c7f4026afa46ca7ca67d47179013a340a5e944 |
23-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 5cb5ff8b1478ed413a9e9fae43b1496f5a97a2dc |
22-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).
List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193157 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 348da8d6b5e002c3698c37aca26c508bc60a05bb |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for LD/ST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| b14ad465492c472033e9ded65ab40e4a9c2c451a |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for LDI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193081 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| f6d4cff9b1cf1e3b57592d6a0e40f0026813aa7c |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for MOVE.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193080 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 006cff8d7b60ddf632f8642f01693dace7827d8b |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon
as GAS starts accepting them by name as that would make the assembly easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsRegisterInfo.td
|
| cebd4010222f28bb68c217047fd0b2c90498f7ca |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of SPLAT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193077 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| f89f66e61b26974bb73b5832d5825091873b51dc |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to
slide left the source array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 52244da7f2b3def646900520668b859343b84a33 |
17-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added lsa instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| db8a16252b9d29bd7a3442d5c3bad0398dd85908 |
17-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Removed ldx.[bhwd] and stx.[bhwd].
These were present in a previous version of the MSA spec but are not
present in the published version. There is no hardware that uses these
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192888 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| ed785629be5a1ad689e2aa4e125781419d824938 |
17-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq.
Define these three instructions in alphabetical order (like the rest of the
file).
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192880 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 06957f43f6051901590b318c10b1a0a5c7f898d4 |
16-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCAsmInfoELF class and factor some code into it.
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCAsmInfo.cpp
CTargetDesc/MipsMCAsmInfo.h
|
| 62e87cb2415b305ca9b888a2338a6af59e74005d |
15-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for build_vector for v4f32 and v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 2ef99c5dff1ab9612f2d65e38f725d809672d2fd |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| 397f6da28cc889597e8c267e15154f1f70a0922a |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use predicates to guard instructions using accumulator registers instead
of relying on AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192665 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
|
| adb1297d49dd345821d7aa91057a0b22e6209a16 |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename isel nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
|
| 89fee2ff928254f21cc9be358e1d8d4498fa0aee |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Transfer kill flag to the newly created operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192662 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| b00491341778776a4d994846ca2f7fafe79c161d |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set HI/LO registers' HWEncoding field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192661 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| b6ed641c719e3f370b0e9120823b349993c3494b |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unnecessary code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192660 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 9672a89c71f7b368455ed193bc23566f3bd4ed2b |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| e89c50acc8312c6cd4d3bdbf50e02ba88e54a663 |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 01436ba3066b99547c1138edf5c36ef2ad467e71 |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 29adbe8464f74f17a7cf977ce21ef88d88d28b14 |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 45ecbfc8e58923131068dced0cf89348ac61208f |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 7f0125ba1950b8d7e32023fcada85c5adca1cd5a |
12-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
For Mips16, start to consolidate all forms of 32 bit literal loading so that
they can be better handled and optimized in the Mips16 constant island code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 5af763cb2ad96f557f88acdb11a710e7c7256800 |
11-Oct-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 21d60f02c36c2362899109239d16824caa56d8ab |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
This reverts 192447 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| abba71663eeebbea725eded5e23f273147824ed2 |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
This reverts r192449 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 62a69eee5ad951502de28871ef27bb64dbf5508f |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 6f36ea5c4778ac0519d821798b94aaac92ec1389 |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed.
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
general purpose register. The changes to parseMSARegs reflect that requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| a6e253ddd0f757101fe97105d60a1e098ca5f33c |
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 4fa2c32220405ac32838e45d91392a83fae70bb0 |
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| c879eabcc25c4099a50939ed0bca86471201b183 |
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| b9bee10b2158253e222eb8dd5f0ae0452740ace3 |
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 25dafa388a1b8052e4817c5d6378b3408b80744e |
10-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not generate INS/EXT nodes if target does not have support for
ins/ext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsSubtarget.h
|
| 78f8339f351c95cb6ed739b7e62f01ccc2716144 |
08-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
Add fabsf to the list of inlined functions; otherwise
Mips16 will try and create a stub for it and this will
result in a link error because that function does not exist in libc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192223 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 3e6a3becd5099bc922d166b1147995a03b3aeca8 |
08-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify and optimize code.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192213 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
ipsMachineFunction.cpp
|
| b359bda93d410623bbbc96dc9968d94447169a79 |
08-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
Let rotr and bswap be handled by expansion for Mips16 since we don't
have native instructions for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
|
| 320296a4cfe414ce59f406b8a5ce15272f563103 |
08-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.
The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.
I will send an email to llvmdev with instructions on how to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsMCTargetDesc.cpp
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsTargetStreamer.h
|
| 42be15fcbeedaa67c4b5f4b19eb273749ae36465 |
07-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
Add Mips16 patterns for sign extend byte and sign extend halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192130 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 116189a997a71d0e63db64ef4c6c3906078d94cf |
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Coding style clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192125 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
ipsISelLowering.cpp
|
| c746503425fc04e25af680d244f9f351675210d5 |
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Disable tail merging when long branch pass is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192124 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
|
| 96ba8cb9b2b1087abeaaf1ede246b56ee788028b |
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define method MipsSubtarget::enableLongBranchPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192122 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSubtarget.h
ipsTargetMachine.cpp
|
| 243702b95a471ffb7d2374dfad3d7f8b11bee7e7 |
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrInfo.td
ipsSEFrameLowering.cpp
ipsSEISelLowering.cpp
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| ef8c4ca252f1289ca8d0a1e6cfd96ca17fe3c5a8 |
07-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove getEHExceptionRegister and getEHHandlerRegister.
They haven't been used for a long time. Patch by MathOnNapkins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
ipsRegisterInfo.h
|
| 5e195a4c8d8cd4498ab7e0aa16a3b6f273daf457 |
05-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.
The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.
It was never the intention that targets would keep doing things like
if (hasRawTextSupport())
Set flags in one way.
else
Set flags in another way.
When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.
This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.
The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.
I will also try to implement a target streamer interface, so that we can
move this out of the common code.
In summary, for any new work, two rules of the thumb are
* Don't use "llc -filetype=obj" in tests.
* Don't add calls to hasRawTextSupport.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsELFStreamer.h
CTargetDesc/MipsMCTargetDesc.cpp
ipsAsmPrinter.cpp
|
| 596654bd100b64cc20ef7476f5f95899bd7afdec |
05-Oct-2013 |
Jack Carter <jack.carter@imgtec.com> |
forgot to remove this file as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191993 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmFlags.h
|
| 6d389f5ebae9aa08309c5795234cf155054b6b39 |
05-Oct-2013 |
Jack Carter <jack.carter@imgtec.com> |
reverting per request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191992 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsELFStreamer.h
ipsAsmPrinter.cpp
|
| 5404ed811de113a21c99366c43b1209f3ba40c62 |
05-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
Support tblockaddr for static compilation in Mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191986 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 8e48edcf3dd7dea9fec58b05a6ace6fbd0260d7c |
04-Oct-2013 |
Jack Carter <jack.carter@imgtec.com> |
[MC][AsmParser] Hook for post assembly file processing
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.
Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".
To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).
This patch will allow other targets the same functionality.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191982 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmFlags.h
smParser/MipsAsmParser.cpp
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsELFStreamer.h
ipsAsmPrinter.cpp
|
| 60ccc3b0ece748b6d0b6bb51ccd1c4e31d334424 |
04-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191978 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| 5537013350006f34ca74c3b6e4c0799e8219753e |
01-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
Test commit. Updated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191748 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
|
| 7f768e03684514ea9ebabed93694521f9ffab28f |
01-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| d59ad8a8013fd76177fb61c741562af3024d34cd |
01-Oct-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsInstrInfo.td
|
| bdf8015cffb1860776e5a5f28014b023a32ab1bc |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| b0247157c6d44363c36cffd0aeea0e2fa83d9335 |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 70f556140fca702ef6062b0c46b032908b9ae2a5 |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 2641f5e412ba84255d8b97f5098e3f57bf990ff1 |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 3f4f420ab7acb10221ba971543a7eed5489fb626 |
28-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAnalyzeImmediate.h
ipsInstrInfo.td
|
| ba1bc60542a1a4c7ade1a563465328a3fdde1fc7 |
28-Sep-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191597 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMachineFunction.cpp
|
| 6ff59a16a05d43fdda587ce600b5b42a63cf3d33 |
28-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.
Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:
1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25 // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25 // jump to lazy-binding stub again.
With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:
1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25 // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25 // directly jump to func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ipsDelaySlotFiller.cpp
ipsISelLowering.cpp
ipsISelLowering.h
|
| 479a778590483bb3e2ca48537ed9eb7b15270ad6 |
28-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a derived class of PseudoSourceValue that represents a GOT entry
resolved by lazy-binding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191578 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMachineFunction.cpp
ipsMachineFunction.h
|
| 200a7434f6abc1e469fdf1ee547bc3fe4fbfcc02 |
27-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ipsISelLowering.cpp
ipsISelLowering.h
|
| 4d835f1cbe5d8c5f6cea4040bea9b180927a1c05 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 9f30d43122dce961ae1625c2c429bf74bf292324 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| e8eafdb67685d4f5d52ab0dce2339c37e39cdc44 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
SA.txt
ipsSEISelLowering.cpp
|
| b0922655166aeef6c54c7b4d31d1ccaecf492e2e |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191517 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 37469a132988eb0c888f6a8a205b2aca510e14f8 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| b4691b495d867a863aa12de57d45bc6a93e4df78 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| e1b1a684dd1459a40b9ee1f46eb865ba9e2133c1 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for MSA registers to copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
|
| c8a1fa77a73e7c885035421712ceba951f9024cb |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
SA.txt
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsMSAInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
|
| 9c0f5ed594367daeab784a82674fa3c14ee508d9 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added MSA.txt to describe instruction selection quirks.
This file contains notes about the instruction selection for MSA. For example,
it notes that ilvl.d is cannot be selected because ilvev.d covers the same
cases and is selected instead of ilvl.d.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191507 91177308-0d34-0410-b5e6-96231b3b80d8
SA.txt
|
| ba616ef0236a11239a0a2c174627dcdc4ab63434 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Tidy up
lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.
lowerMSASplat now takes its callers SDLoc instead of making a new one.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191503 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| f1ef27e6e308435035ffec112a6474ed5e009484 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSubtarget.cpp
|
| d2a31a124f3bebbdfc4d886afe33a116893aa689 |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 86f309b4d1426b54f23d6ba53d3f5c8a1aa3985b |
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders
Reviewed By: dsanders
Differential Revision: http://llvm-reviews.chandlerc.com/D1755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 1327c089221da78b1bfd61067162023e520085ed |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191461 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 00a5b53e148cd0c840650504fcd6e92dee132c1a |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
This does not affect any of the existing output.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191460 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 9fa81ab83898314d1a6608e8303dc57253292796 |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| afee613bf390b255eef9cd46fd336fecc7663a1a |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
Internal changes only.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191414 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 4167b88cf5754597e5a7e53aa0cbba26c18b6162 |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 42d9ca629934d0c20ac19949399ce4faa9a7bbb3 |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.
Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsRegisterInfo.td
|
| 825e5583b6c3161bb02074dc48cd07dafdf9545c |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
This only changes internal encodings and doesn't affect output.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191411 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 55d016886cc695aa14dfa3cc8b9e1d602cca149c |
25-Sep-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a bad typo in the inline assembly code for mips16 pic fp stubs
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| e36a62c23d332658e4513d67eedb392b9c27f470 |
25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r191350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191353 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ipsISelLowering.cpp
ipsISelLowering.h
|
| d47aa3adbef5ee2343b61c96292454f3a5b77dbc |
25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move public functions to the beginning of the class definition.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191352 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMachineFunction.h
|
| 793803449870a661c1a09e400df9b04492772196 |
25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define getTargetNode as a template function.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191350 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ipsISelLowering.cpp
ipsISelLowering.h
|
| 3706eda52c4565016959902a3f5aaf7271516286 |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| f515964d36834ec918fe831029bc72ccdcec34d3 |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 93d995719e2459a6e9ccdb2c93a8ede8fa88c899 |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 7e0df9aa2966d0462e34511524a4958e226b74ee |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp
This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).
There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.
compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
|
| ad16ddeb8e07a259d17ef203c9f443f816f6ae7b |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations.
The resulting code is the same length, but doesnt cause memory traffic or latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191297 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 421dcc59212a73b82141caa2c94ea340a7b34deb |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)
This covers the case where fmax_a can be used to implement ISD::FABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 930f2b51084c6dac1238b8b0f8dd11f40f619694 |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Line wrapping.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191295 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| c998bc98439e21bc8c3838d6353475eacfb8494e |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 89d13c1b380218d381be035eb5e4d83dcbc391cc |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 38a10ff063971c2f7f7384cceba3253bca32e27a |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics)
This required correcting the definition of the bsel and bseli intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| ae1fb8fc19dcfd2f0e33a36f40d687b08dcc9a6b |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics)
MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| cfb1e1703130809043a7b020b4cdfa04b59fa8ec |
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| f2058addc2aa221d0fd744180a2c04a38ebddcd0 |
24-Sep-2013 |
Reed Kotler <rkotler@mips.com> |
Make nomips16 mask not repeat if it ends with a '.'.
This mask is purely for debugging and testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191231 91177308-0d34-0410-b5e6-96231b3b80d8
ipsOs16.cpp
|
| e0187e51a17f2081d6a72a57e0fbba8ce38d9410 |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191203 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 9a1aaeb012e593fba977015c5d8b6b1aa41a908c |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| a399d698a84ffd22c7d1f121c24cbc147c6f4e06 |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 915432ca1306d10453c9eb523cbc4b257642f62a |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 4e812c1f4a723f0fa0e8714610e08be593c759b8 |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191194 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 57ebcb28a63d8646fd8fd69cfd9e6766066e342f |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Partially revert r191192: Fix -Wunused-variable error when assertions are disabled and -Werror is in use.
An unrelated change crept in because 'svn revert' isn't recursive by default.
The unrelated changes have been reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191193 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 912fde24089094a953dfb802c69f4b0d83c7925c |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Fix -Wunused-variable error when assertions are disabled and -Werror is in use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191192 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 |
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).
Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
|
| ed7fd711a1917a31714d3f9a41210916be450079 |
21-Sep-2013 |
Reed Kotler <rkotler@mips.com> |
Set .reorder for the stub so that gas takes care of delay slot processing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191125 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 6b2448326f8faa9149616a541d4c0d72b9d526e6 |
20-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] MUL should clobber HI0 and LO0.
I cannot think of a test case that reliably triggers this bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191109 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| c1fe3e3b330d9404530abc2fbbd0f6d1fa64ce01 |
19-Sep-2013 |
Reed Kotler <rkotler@mips.com> |
Fix two issues regarding Got pointer (GP) setup.
1) make sure that the first two instructions of the sequence cannot
separate from each other. The linker requires that they be sequential.
If they get separated, it can still work but it will not work in all
cases because the first of the instructions mostly involves the hi part
of the pc relative offset and that part changes slowly. You would have
to be at the right boundary for this to matter.
2) make sure that this sequence begins on a longword boundary.
There appears to be a bug in binutils which makes some of these calculations
get messed up if the instruction sequence does not begin on a longword
boundary. This is being investigated with the appropriate binutils folks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelDAGToDAG.cpp
ips16InstrInfo.td
|
| e925f7dbbf497412cd0cc3f67b9b96fed0cc3712 |
16-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsInstrFPU.td
ipsRegisterInfo.td
|
| 6febf857f690665bc33b84c957cdefb39a27f63d |
15-Sep-2013 |
Reed Kotler <rkotler@mips.com> |
Expand the mask capability for deciding which functions are mips16 and mips32
so it can be better used for general interoperability testing between mips32
and mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190762 91177308-0d34-0410-b5e6-96231b3b80d8
ipsOs16.cpp
|
| dcc425c6301c088b4c0598696de50c01fbca5733 |
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Fixed bug when generating Load Upper Immediate microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| ab48d10effb223de0c9516ccae616a80fef27df8 |
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS DIV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ipsInstrInfo.td
|
| 47b33528d1b4298bf8cc5dcca8b531dfd0e704bb |
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for misc microMIPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 906ae15d5fa5784595273228b33e16ca16a0431d |
13-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Test commit to verify that commit access works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190676 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelDAGToDAG.cpp
|
| 715d98d657491b3fb8ea0e14643e9801b2f9628c |
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| f2eb1e4286bf397d60a37e6f288ac81e644a3258 |
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 2ac128292150c7ebb469d137877eaa3c6d26a8bb |
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| ece929d6234b73ea248b7a5e89f915613ad748ea |
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| 68831cbd417b7e4c47b565038a4fe9a1269d5d50 |
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
|
| ddfbd5805478cf108156bb0159b7495d2b236f7e |
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 8857294192bdc1992d60a14a6ff6c519ddee63e3 |
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| ae43dac30037395cce2b54af0a02500985813183 |
11-Sep-2013 |
Eli Friedman <eli.friedman@gmail.com> |
Fix unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190448 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 436f64567ceb0b45e6b5b680fa09485002094830 |
10-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
The dotp_[su].b instructions never existed in any revision of the MSA spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| b15da6dc09fdf2699146cd4317f3a43e70397553 |
10-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 798cdc6af1bf2877a941bba4587e6bf72f5d140d |
10-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Remove obsolete code from MipsAsmParser.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190396 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 2dd3afc5e600b4585e4c2cd08f9a35fd1cf0df61 |
09-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] When double precision loads and stores are split into two i32 loads and
stores, make sure the load or store that accesses the higher half does not have
an alignment that is larger than the offset from the original address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190318 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| c3cee57f7d20f69a84fd88464ed8cf050e63c7ad |
09-Sep-2013 |
Bill Wendling <isanbard@gmail.com> |
Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.
Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.
<rdar://problem/13623355>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsMCTargetDesc.h
|
| 3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.h
ipsInstrFPU.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| d65d2fde4eadcb40e80b361e4cf244c02dcc670b |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Place parentheses around && to silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190234 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
|
| 1abf0afdd4d8e9d58518a878f30b9eede81303cc |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of instruction "drotr32" (double rotate right plus 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
ips64InstrInfo.td
|
| 69f8e0935af16622ca13d26e6a66464d3c1f3da4 |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ips16InstrInfo.td
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsInstrInfo.td
ipsMSAInstrInfo.td
|
| 997c5dead83fc237280888696e1fa719563fc7f1 |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190224 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
ipsInstrInfo.td
|
| cd3c1b9af9c79bd128a4811570269022a8183408 |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unused classes and defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190221 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
ipsCodeEmitter.cpp
ipsInstrFormats.td
ipsInstrInfo.td
|
| 77e1ebd18fc558620b97fe38f3ebbf825533655f |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set instruction itineraries of loads, stores and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsCondMov.td
ipsInstrInfo.td
|
| a86062c4b12fc2b9ee339ca8c54bcef3447f713c |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190156 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 5cb39b22fb248b59d7aa37603083ba7d1b0f7f2c |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190155 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 638382e6f169649eb86fa47a6ea25dd932f07689 |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ipsInstrInfo.td
|
| 3aaa3e31aa35164fa54474bcf3a2c2df5ab8b375 |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190153 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| dadd1fba3280295936f556acbdc3fbb68b496bad |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 9e935a77a59fc14acf1936165f235342b741e34a |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190151 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| b9987d1aa14d8ee91bb0acd113ac21fb322f3efd |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190150 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| bf7f7b5e0eae40bb47a410c90f9f0885c0f38b2c |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsCondMov.td
ipsInstrFormats.td
|
| 888497d8a2927ddab38667d54d574c3cadeef1e5 |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190146 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 6976d75415fdbdcd4cef52e0c9a20000dbb17db7 |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190145 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| a674463aac1d0b5d039da11045ccfab5e849b886 |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS disassembler and disassembler make check tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
icroMipsInstrInfo.td
|
| 99d02d13259620d175986bf9c7e1c07b2640163d |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| d31c238372b2ddba147a012f457cae896e6e828f |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190142 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 7d3da67611e9ce7541a8987dcb7964f69de071aa |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190141 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| bfb9bab2434e3a8c4452708995a7f5d4f5a3b20e |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190140 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| e3273b327555df6489640d2195b52b6317c88844 |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190134 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| cc538affd270c81d12285e6addcd261086beec2b |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190133 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 3f1acd55a8ad249926bc80916bb20f0b77798cb5 |
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190131 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| b83c66eb5e1efb8a1b2b204fc67fe7d11e938248 |
01-Sep-2013 |
Reed Kotler <rkotler@mips.com> |
Make sure we don't generate stubs for any of these functions because they
don't exist in libc. This is really not the right way to solve this problem;
but it's not clear to me at this time exactly what is the right way.
If we create stubs here, they will cause link errors because these functions
do not exist in libc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189727 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| c673f9c6fecb0f828845ada7ea5458f66f896283 |
30-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a problem with dual mips16/mips32 mode. When the underlying processor
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
ipsISelLowering.cpp
ipsSEISelLowering.cpp
ipsSubtarget.cpp
ipsSubtarget.h
|
| 3c380d5e28f86984b147fcd424736c498773f37e |
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.
Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 |
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added load/store intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsInstrInfo.td
ipsMSAInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| abbcf3bd47ad8ffa70f48ebd924f99fff5c22131 |
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added move.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsSEISelDAGToDAG.cpp
|
| a6c3a4ee76ef8464d3c83472e15af521ade7eeb4 |
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added cfcmsa, and ctcmsa
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEInstrInfo.cpp
|
| f00539cc5a5e66ce6b7ce3779b00fd381e2d2dee |
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| a796d90c0ed7ebd5d58fced43c60afc2e9bf6225 |
28-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsDSPInstrInfo.td
ipsInstrFPU.td
ipsInstrInfo.td
|
| bf19dba2d4c7927832d3037c15e0101afb730415 |
28-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up definitions of move word from/to coprocessor instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189431 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 6d55dfaf9124c3e5e54190090478d2f6384a51d4 |
28-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isAllocatable and CoveredBySubRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189430 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| b0bb2d6636ed7b1d089a37b3cf7913d06bb49f37 |
27-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
Changed comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189396 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 62f61bf9077418801be5e2039333727079819844 |
27-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added spill/reload support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189332 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
|
| c9617b9a9dfcb550adcf06f83a58a5e522414cc1 |
27-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added bitconverts for vector types for big and little-endian
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
ipsMSAInstrInfo.td
|
| e4bf77a1282bfdacb61bae192fdf79a696be780a |
26-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements trap instructions for mips. The test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 5e5c3069cd92741852f10a7395133d6d79c5bce7 |
25-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Start to add the LLVM builtins to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted
Resubmit this patch. The target triple needs to be added to the test so that
clang does not tell the backend the wrong target when the host is BSD. There
is a clang bug in here somewhere that I need to track down. At Mips this
has been filed internally as a bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189186 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 0570be84048b4c2a979923c583054de147590016 |
24-Aug-2013 |
Shuxin Yang <shuxin.llvm@gmail.com> |
Revert 189161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189176 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| cbbd1eeecb2bf49915c4bd0e20b1e9bad8696ada |
24-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Start to add the builtind to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189161 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| a8a7099c1849fcbb4a68642a292fd0250aa46505 |
23-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
Turn MipsOptimizeMathLibCalls into a target-independent scalar transform
...so that it can be used for z too. Most of the code is the same.
The only real change is to use TargetTransformInfo to test when a sqrt
instruction is available.
The pass is opt-in because at the moment it only handles sqrt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189097 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips.h
ipsOptimizeMathLibCalls.cpp
ipsTargetMachine.cpp
|
| c73488a38ecb26340604706003e84cff7bd48ddf |
23-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
ipsRegisterInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 187dedf21d268aecac6d95211de0c496299fdd13 |
21-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.
I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.
This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188896 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| 099e5328fcfae96b406782d636fe02a4ecad4552 |
21-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Define registers using foreach
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188893 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| d22b327b3d8fafade61fa2b4aaba5c9f3ee10d4d |
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[micromips] Print instruction alias "not" if the last operand of a nor is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188851 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
|
| b1f4f120a50c392c85c6b4388d63e36251fce279 |
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add support for mfhc1 and mthc1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| ad341d48f0fc131d1c31a0c824736e70c34e0476 |
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.
Test case will be added when support for mfhc1 and mthc1 is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCallingConv.td
ipsISelLowering.cpp
ipsISelLowering.h
ipsRegisterInfo.cpp
ipsSEISelLowering.cpp
ipsSubtarget.h
|
| c89cb45ecb861aa599a8b1c735b0ce4cd73e1397 |
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove predicates that were incorrectly or unnecessarily added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsCallingConv.td
ipsInstrFPU.td
|
| 3531db14c61957e7ad00ce972e9685864c3887da |
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsInstrFPU.td
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
|
| a98a486ad194c38293efcc5359d6ed2493f950dc |
20-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsInstrFPU.td
ipsInstrInfo.td
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
|
| 0323d4b169279414862174f38ae04add6b747a60 |
20-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188826 91177308-0d34-0410-b5e6-96231b3b80d8
ipsOs16.cpp
|
| 93877b3cbcefc0f281b744b135d609d35c3f119c |
20-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ipsInstrInfo.td
|
| c5158b869bbde7b08c486c6f326bd1c701367c98 |
20-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 6ef333501eb917cbd79a51c84294051a1a257a0b |
20-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added insve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| c149fbbe279ef623e6067304fd08dc1a62d74f7d |
20-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
|
| 1e09ed13893ad9d463c6c08c996170bac6e60449 |
19-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188690 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
|
| 1edd1a336a79c4cb804d32cb492738549154c69c |
18-Aug-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove unused stdio.h includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188626 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
|
| 80f60610826158dcbfbeb5c235ca0ea673d23281 |
17-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a subtle difference between running clang vs llc for mips16.
This regards how mips16 is viewed. It's not really a target type but
there has always been a target for it in the td files. It's more properly
-mcpu=mips32 -mattr=+mips16 . This is how clang treats it but we have
always had the -mcpu=mips16 which I probably should delete now but it will
require updating all the .ll test cases for mips16. In this case it changed
how we decide if we have a count bits instruction and whether instruction
lowering should then expand ctlz. Now that we have dual mode compilation,
-mattr=+mips16 really just indicates the inital processor mode that
we are compiling for. (It is also possible to have -mcpu=64 -mattr=+mips16
but as far as I know, nobody has even built such a processor, though there
is an architecture manual for this).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188586 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSubtarget.cpp
|
| ea549a847d87cb8ce46f6a45b24ae888db697a07 |
16-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Reverted test commit (r188556)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188557 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 1dbfa36ba1e2f6e4630b5f41254e307f81cece80 |
16-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Test commit. Just a blank line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188556 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| 6f297afb7ea6ab53be1feae4a335e7b1cb7a1f02 |
16-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements wait instruction for mips. Examples are added in test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188537 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| bd71eea899d579deb1fcee02944f955a4708091a |
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (madd_q to xori)
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| d0f99639c16ddad697db30e75643ae4cc52c3e80 |
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (fadd to ftq)
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMSAInstrInfo.td
|
| e2a9376b1bd2204ea6f56a35b762e28e0ef4e35a |
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsRegisterInfo.td
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 899ee589f5182a35495f068ae15b5f2b5ff4ef8a |
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix bug in parsing accumulator registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188344 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 88373c29fe9d0b498ed21c3d29129f31806d7ec8 |
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use register operands instead of register classes in DSP instruction
definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188343 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsDSPInstrInfo.td
ipsRegisterInfo.td
|
| 7d6355226c60cd5ac7e1c916b17fee1a2b30a871 |
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename DSPRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsDSPInstrInfo.td
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEISelLowering.cpp
|
| cbaf6d0cc3d3f363f269346817a90d3cbc8d1084 |
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename HIRegs and LORegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
icroMipsInstrInfo.td
ips16InstrInfo.cpp
ips16InstrInfo.td
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsInstrInfo.td
ipsRegisterInfo.td
ipsSEInstrInfo.cpp
|
| bfb07b1054b653661306848e695b34e79289a15b |
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Properly parse registers that appear in inline-asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 3f70e908c3d9de7acea462719ebf36dca1560f9c |
13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsInstrInfo.td
ipsMSAInstrFormats.td
ipsMSAInstrInfo.td
ipsRegisterInfo.td
ipsSEISelLowering.cpp
ipsSubtarget.cpp
ipsSubtarget.h
|
| da0860f78e6e43aca3333a7815b2f9bc0f8dfac0 |
13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsCodeEmitter.cpp
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
|
| bd980e5569d085ab73e351ec9fca8b698e06d44f |
13-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch introduces changes to MipsAsmParser register parsing routines. The code now follows more deterministic path and makes the code more efficient and easier to maintain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188264 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 809313970fc98bba6f36a332adfa3e5fef4110b3 |
12-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements ei and di instructions for mips. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 674c91bb6e704fecd905a226daef079717e7a8c1 |
12-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove global construction. const char* is sufficient here.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188158 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 5e4b95b3fe908f89aa512b6e9921fe49aadd759b |
11-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Don't generate floating point stubs for mips16 code if the function
is actually an instrinsic that will not occur in libc. This list here
is not exhaustive but fixes the one places in test-suite where this occurs.
I have filed a bug against myself to research the full list and add them
to the array of such cases. In the future, actual stub generation will occur
in a later phase and we won't need this code because we will know at that time
during the compilation that in fact no helper function was even needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188149 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 76ba4f5275a8bd908275076b50f51f3aa9a5d4e2 |
11-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Incorrect JAL instruction attributes caused the optimizer to make a wrong
instruction move. Just affects static relocation. -static works fine now
with mips16 for the most part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188143 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 1e07de352947aaf2f9137113cc594d8204da2b77 |
09-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Add another intrinsic that LLVM gives an incorrect prototype to.
I need to go through all the runtime routine list and see if there
are any more I need to add for mips16 floating point. Prototypes must
be correct or else I don't know to add a helper function call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188106 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
|
| d12fce1a27c30292dcd5f5bc10d4ba6e742888be |
09-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips ELF: MicroMips direct object Little endian support.
Test included.
Patch by Zoran Jovanovich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188024 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 491d04969d9f29ed891c73238648853954ba4f81 |
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ips64InstrInfo.td
ipsCondMov.td
ipsDSPInstrInfo.td
ipsInstrFPU.td
ipsInstrInfo.td
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.h
ipsSEInstrInfo.cpp
|
| 7af40bfa6614896913e0953bfe850d8c1ef0e593 |
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Mark pseudo instructions as code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188017 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
|
| 94a88c49b0e87ee8c911669ff6c6bbd31b912542 |
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete register class HWRegs64.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ips64InstrInfo.td
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEISelDAGToDAG.cpp
|
| fab2daa4a1127ecb217abe2b07c1769122b6fee1 |
08-Aug-2013 |
Stephen Hines <srhines@google.com> |
Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807
Conflicts:
lib/Archive/ArchiveReader.cpp
lib/Support/Unix/PathV2.inc
Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
|
| 51c9043f3bc215bb3026486e5e1ef5989a8d8d8b |
07-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Create a pattern for the "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187863 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrFormats.td
ips16InstrInfo.td
|
| 040ef013acf3e4ceed7fb052e00f2e0b7cd7650a |
07-Aug-2013 |
David Blaikie <dblaikie@gmail.com> |
Remove unused functions introduced in r172685 to unbreak the Clang -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187838 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 1858786285139b87961d9ca08de91dcd59364afb |
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
icroMipsInstrInfo.td
ips16ISelLowering.cpp
ips16InstrInfo.cpp
ips16InstrInfo.td
ips64InstrInfo.td
ipsAsmPrinter.cpp
ipsCondMov.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsInstrFPU.td
ipsInstrInfo.td
ipsMachineFunction.cpp
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
ipsSEInstrInfo.cpp
ipsSERegisterInfo.cpp
ipsSubtarget.cpp
|
| 6b034bb3ae3f6e1f3831bfc24f90e84b9578944c |
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
instructions defined in MipsInstrInfo.td as codegen-only instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ips64InstrInfo.td
ipsCondMov.td
|
| 014096e4d5e65309ca71d0e63327f5386ddf16fb |
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
ips64InstrInfo.td
ipsInstrInfo.td
|
| a1fe9ef62e18dcb30cdee62a2fad82d05791d359 |
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
nstPrinter/MipsInstPrinter.cpp
icroMipsInstrInfo.td
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsInstrInfo.td
ipsRegisterInfo.td
|
| 8e1d64666f493e4994b26a390bec1290a5d94b96 |
06-Aug-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 25278aa26fa498e41830946b2138f01473269df2 |
05-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Add the saving of S2. This is needed for some of the floating point
helper functions. This can be optimized out later when the remaining
parts of the helper function work is moved into the Mips16HardFloat pass.
For now it forces us to use the 32 bit save/restore instructions instead
of the 16 bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187712 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16InstrInfo.td
|
| 8a7f9de9d42e5817167e374dd61408dcac31a102 |
04-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Clean up code for Mips16 large frame handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
ips16RegisterInfo.cpp
ipsRegisterInfo.cpp
ipsRegisterInfo.td
|
| bc2160f7c90efffdd62587f1c978ba68b809ef35 |
04-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Stop leaking register infos in the disassemblers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187695 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 5e795097b081390a7172beeffad7e65c5150214f |
02-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Expand vector truncating stores and extending loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187667 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| ddbdeefa286374a1f036d5e80987306749d3f729 |
02-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
remove lines that are setting DecoderNamespace for pseudo atomic instructions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| b1fa7d4d26533bdd021c3269d14c30eb6096fb7a |
01-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Fix some issues with Mips16 floating when certain intrinsics are present.
This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187613 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
|
| 588f408b95c83e9b59c0777925d2ae70ac445fae |
01-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsInstrFormats.td
|
| f71698747e07145657bd8595162439da40ebd749 |
01-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Fix some misc. issues with Mips16 fp stubs.
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| d49475bebca630cd1be535eed2b3c4964209c30a |
01-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Add an omitted IsCall=1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187553 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 782638aa0d18f7db7970eb0d8dded84fe7f0c450 |
31-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename instruction DANDi to ANDi64.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
|
| 52b7321a48ae6f1a4f8f56047196d49fdb19ac16 |
31-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define instruction itineraries IIArith and IILogic.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ips64InstrInfo.td
ipsCondMov.td
ipsInstrInfo.td
ipsSchedule.td
|
| 80bec28b6645676a7cd9408d780b4c805774ef42 |
30-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete instruction format for "bal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187443 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
|
| 8838da6587e60a248b07d4db0e874429ad4e9747 |
30-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
turns "bal" into "bgezal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
ipsInstrInfo.td
|
| b67775df0cc702cd94408200ff2d58cf83f1334a |
30-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsCondMov.td
ipsInstrFPU.td
ipsRegisterInfo.td
|
| c0fa31d51bdb255a481a287ab6492461ba5f2458 |
29-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add comment and simplify function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187371 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
|
| 9758562aa706a5a20a9d833074e733ed544db776 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Implement llvm.trap intrinsic.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsInstrInfo.td
|
| 407883b69b3bc10ebf053f5922d877b2e786d124 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
ipsISelLowering.cpp
ipsInstrFPU.td
ipsInstrFormats.td
|
| 83d8ef133b121b7e752e7468cb1e0e5e3b636aee |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP branch instructions to have explicit FP condition code register
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
nstPrinter/MipsInstPrinter.cpp
ipsISelLowering.cpp
ipsInstrFPU.td
ipsInstrFormats.td
|
| 0fc641df377bf6ea88bbc28b377f6a0810dfa220 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Increase the number of floating point condition code registers to eight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| 9955cb931b287bec91313a4b185fa965fb71f559 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix floating point branch, comparison, and conditional move instructions
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
ipsInstrFPU.td
|
| d6a7ea27361a64228e5afaf99d2ef3609a63cd3e |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete register print method MipsInstPrinter::printCPURegs that is not
needed. The generic method printOperand will do.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187231 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
ipsRegisterInfo.td
|
| 9b06dd6ca25fd1f8d2cf9227fdffc304c9f51564 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
|
| 94ce6dadd131ca80adf2ba05391f689684540601 |
24-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFail
when there wasn't a match. This behavior is consistent with other register
parsing methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187063 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 959d2f70fb64601a5f73c2ebab1ff2f4ccd9c659 |
24-Jul-2013 |
Petar Jovanovic <petar.jovanovic@imgtec.com> |
[test commit] Minor comment change.
Testing commit access credentials.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187032 91177308-0d34-0410-b5e6-96231b3b80d8
ipsJITInfo.cpp
|
| f63ef914b67593e4b20a0b85e889380c20b41f55 |
24-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Split generated asm mnemonic matching table into a separate table for each asm variant.
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187026 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 9a05b98ef9ec58c52f35ce04677f24ef62a79701 |
22-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 0b926427670de6e0ed855ef93f220a3f51ed1eab |
22-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
ipsSEInstrInfo.cpp
|
| da218210f7371cd47a43252756e03b6a03a6b06d |
19-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsSEInstrInfo.cpp
|
| 764f6f51257a0669acc58c8e5b4b802a29069302 |
18-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 27d0c68617dee9c60efbc179c31b4a1bd28daa34 |
17-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use "foreach" loop to make register definitions more concise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186528 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| fce9279ac0265fd5ea637dd30253bad26f4273da |
17-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186512 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 16f385f90f481195bfcf6b139ced4cee033bb887 |
17-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 17c95a217d359a48a95b35730829e870fe8491eb |
16-Jul-2013 |
Juergen Ributzka <juergen@apple.com> |
Test commit to verify write access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186429 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| ab42fc66b1d4d7c57344de3cf266494ad8518787 |
16-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Fixing a buildbot failure:unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186403 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 088483627720acb58c96951b7b634f67312c7272 |
16-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsCondMov.td
ipsInstrFPU.td
ipsInstrFormats.td
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 434c0bd2a5c3c7ebaa8ca10dd7e4fdb1f25e92a0 |
13-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Implement MipsTargetMachine::getInstrItineraryData().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186227 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSubtarget.h
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| ae24f7d3c6770fb32eb1f6215bab1fc92cbe2d94 |
13-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add instruction itinerary classes for mult, seb and slt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
ipsSchedule.td
|
| dd51a0c1e0b3cce8093244533b3505668d16f218 |
12-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 296c1534b4ad835c6d9280145b63ca2b25831228 |
10-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Reverting commit r185999 due to buildboot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186000 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 2ec5933eae2e889225d33bd2f93a35926e958c95 |
10-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 6227d5c690504c7ada5780c00a635b282c46e275 |
04-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 365ef0b197d7c841f8e501da64296df65be4ca23 |
03-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
ipsISelLowering.h
|
| a66aacf6d7e57b21dcd9e866d28749567cfba74b |
02-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFPU.td
ipsInstrInfo.td
ipsSchedule.td
|
| 5112243aec9486a669d44b72e6648e8a920c9931 |
01-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsInstrInfo.td
|
| db8e0bbedb46c9f781f8a32728b1019f34089ed8 |
01-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| 096c0a03313ea43a1e4035645b02bf99fd35801a |
27-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 842cfc91f29f6446bb675891f7abc127f9fbe768 |
26-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not emit ".option pic0" if target is mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185012 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 9a308df027b60057d0fe3ba7a3ee9648f6677879 |
26-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Improve code generation for constant multiplication using shifts, adds and
subs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 90b1086b93708149ed7a3749e2eeccea264a037d |
24-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsInstrFPU.td
ipsRegisterInfo.td
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 7231625f75b4da1c87deb833cd9cad6c5ee95d95 |
20-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| ba54bca472a15d0657e1b88776f7069042b60b4e |
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelDAGToDAG.cpp
ipsISelDAGToDAG.cpp
ipsSEISelDAGToDAG.cpp
|
| dd5fe2ffc6f564192876065d2617ecbc18d03f23 |
19-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184292 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsRegisterInfo.td
|
| 571dd98ea4d6bf911c3b46a20ca3b5e3b341b21f |
18-Jun-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips ELF: Mark object file as ABI compliant
When producing objects that are abi compliant we are
marking neither the object file nor the assembly file
correctly and thus generate warnings.
We need to set the EF_CPIC flag in the ELF header when
generating direct object.
Note that the warning is only generated when compiling without PIC.
When compiling with clang the warning will be suppressed by supplying:
-Wa,-mno-shared -Wa,-call_nonpic
Also the following directive should also be added:
.option pic0
when compiling without PIC, This eliminates the need for supplying:
-mno-shared -call_nonpic
on the assembler command line.
Patch by Douglas Gilmore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184220 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.cpp
ipsAsmPrinter.cpp
|
| 99cb622041a0839c7dfcf0263c5102a305a0fdb5 |
18-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsMCCodeEmitter.cpp
ips16FrameLowering.cpp
ipsSEFrameLowering.cpp
|
| 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 |
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsInstrInfo.cpp
ipsInstrInfo.h
|
| 9151f6474c0c3c696e75a12a605c48f54da4665f |
12-Jun-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r183849.
s/LLVM_HOSTTRIPLE/LLVM_HOST_TRIPLE
Add #include<ctype.h> to LinkModules.cpp for isdigit().
Add missing libLLVMObject to llc dependencies.
Android.mk updates:
Remove Linker.cpp
Remove JITDwarfEmitter.cpp
Remove MipsDirectObjLower.cpp
Add MCExternalSymbolizer.cpp
Add MCRelocationInfo.cpp
Add MCSymbolizer.cpp
Add ARMMachORelocationInfo.cpp
Add Mips16HardFloat.cpp
Add MipsOptimizeMathLibCalls.cpp
Add X86ELFRelocationInfo.cpp
Add X86MachORelocationInfo.cpp
Change-Id: I3f3dbc2b62e89ef9e303f5456c6a99f0937f6981
ndroid.mk
CTargetDesc/Android.mk
|
| 90cd06e90be1db06bc4812ae9ec96b6638847285 |
13-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Mips: Remove global set.
Backends shouldn't retain any global state. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183927 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ips16ISelLowering.h
|
| 1878f9a7874b1ff569d745c0269f49d3daf7203d |
12-Jun-2013 |
Stephen Hines <srhines@google.com> |
Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612
|
| 0001acc13cd751a8bc6049abb7afbc9161d096d0 |
12-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix CMakeLists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183804 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 45137f954f976ea75282f7b4b2dac5777837840f |
12-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add an IR transformation pass that optimizes calls to sqrt.
The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183802 91177308-0d34-0410-b5e6-96231b3b80d8
ips.h
ipsOptimizeMathLibCalls.cpp
ipsTargetMachine.cpp
|
| 4cef3d818183aafc1b3adfad4140483d9ad1ad86 |
11-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use function TargetInstrInfo::getRegClass.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183767 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| b0ee97a366a07c05b2c8ab314e29f5e72a9b7bfb |
10-Jun-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a regression I introduced when I expanded the complex pseudos in
the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183633 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ips16ISelLowering.h
|
| 7462a875d9ca4cf7ab30829152175f7448757943 |
08-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use a helper function which compares the size of the source and
destination operands of an instruction.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183596 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| 41e632d9e1a55d36cb08b0551ad82a13d9137a5e |
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ipsCodeEmitter.cpp
ipsConstantIslandPass.cpp
ipsDelaySlotFiller.cpp
ipsLongBranch.cpp
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| 6a2e7ac0b6647a409394e58b385e579ea62b5cba |
06-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelDAGToDAG.cpp
ipsISelDAGToDAG.cpp
ipsSEISelDAGToDAG.cpp
|
| 8270e68c560fce9dd457ec815e6dd141eacadb2e |
05-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] brcond + setgt/setugt instruction selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 164de543917ca82df431c4453e7c9d94580b4d06 |
04-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183215 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 23ed37a6b76e79272194fb46597f7280661b828f |
01-Jun-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| affed7e11d9107285b1a9ffa2cf78a141fa27a3d |
31-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Big-endian code generation for atomic instructions.
Patch by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182984 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| c57905ef4dfc7a8b573efbf8e0a1f9580d98bfe8 |
29-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Improve set register alias handling
This patch solves the problem of numeric register values not being accepted:
../set_alias.s:1:11: error: expected valid expression after comma
.set r4,$4
^
The parsing of .set directive is changed and handling of symbols in code
as well to enable this feature.
The test example is added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182807 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 078bdc6cbb572fffc9e39fbaa8052794b93ecf48 |
28-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make helper functions static.
And remove header and cpp file that are empty after that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182746 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsDirectObjLower.cpp
CTargetDesc/MipsDirectObjLower.h
CTargetDesc/MipsMCCodeEmitter.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelDAGToDAG.cpp
ips16ISelDAGToDAG.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAnalyzeImmediate.cpp
ipsISelLowering.cpp
|
| 49a6a8d8f2994249c81b7914b07015714748a55c |
24-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.
Defines away PR16132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 6c1301ba8c017e39123e41a3cb5fb6984c0b4766 |
22-May-2013 |
Reed Kotler <rkotler@mips.com> |
Mips16 does not use register scavenger from TargetRegisterInfo. It allocates
a RegScavenger object on it's own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182430 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
|
| 2591b5c6c3e07e40d3e39f614aba4a927c43bd9f |
21-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename option to make it compatible with gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182397 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 1d4d32398ddb19520b2a84acae3b7807ad74602b |
21-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add instruction selection patterns for blez and bgez.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| bf00bf9ad2f07c5c06986930842ace28b8fb2518 |
21-May-2013 |
Reed Kotler <rkotler@mips.com> |
Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.
As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182343 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
|
| 1aeb13bd9cbc1be096af7d4f9da9d5fa566f606b |
20-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add (setne $lhs, 0) instruction selection pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| f894199a14fff1399f6ee9d78c6a601d86649155 |
20-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsISelLowering.cpp
ipsInstrFormats.td
ipsInstrInfo.td
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| ae7e7cb3d3ec657b7e6dd94cf036cdc65c182f59 |
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
Previously, three instructions were needed:
trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)
Now we need only two:
trunc.w.s $f0, $f2
swc1 $f0, 0($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrFPU.td
|
| 6b67ffd68bb2e555b1b512a809f3c82c68f3debe |
16-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove addFrameMove.
Now that we have good testing, remove addFrameMove and create cfi
instructions directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182052 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ipsSEFrameLowering.cpp
|
| 63451435402d9c401475596b6e741b5bbaad0bbd |
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Factor out unaligned store lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182050 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| e351865b65e92bea8ceeb32ad757d783d0ecea0f |
16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add TwoOperandConstraint definitions
This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.
This way all instructions that inherit ArithLogicI class
have the same macro defined.
The usage examples are added to test files.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| d761004bfd61c96ad650b82ab262e220530ea6d9 |
16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips td file formatting: white space and long lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182047 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrInfo.td
ips16InstrFormats.td
ipsCallingConv.td
ipsInstrInfo.td
|
| 02e168003f45cf8e0a277c6b8c85c1a3032b1dec |
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Test case for r182042. Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182044 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.h
|
| ec4db6ab5f64318b1aa2351f7e710569869193e9 |
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
invalid instruction sequence.
Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.
mtc1 $f4, $4 # int-to-fp move instruction.
mov.s $f2, $f4 # move contents of $f4 to $f2.
cvt.s.w $f0, $f2 # int-to-fp conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| 3209baefd4ab8242563118c37d8357bd9de6b421 |
16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add branch macro definitions
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| afcca55ff9475cdb97ec576847fc676e95397fb4 |
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
|
| f4037688242aad3109fdfd42b50df56b4a613c02 |
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unused enum value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182035 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 1a2265bc01b4d9bd53a79a5304993af2718e5663 |
16-May-2013 |
Reed Kotler <rkotler@mips.com> |
Patch number 2 for mips16/32 floating point interoperability stubs.
This creates stubs that help Mips32 functions call Mips16
functions which have floating point parameters that are normally passed
in floating point registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181972 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 0b95db8f2654cd19c029d024d931013bb7ecc14d |
14-May-2013 |
Reed Kotler <rkotler@mips.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181759 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| 5427aa88d5930655ef9e958446489acc1bf9a160 |
14-May-2013 |
Reed Kotler <rkotler@mips.com> |
Removed an unnamed namespace and forgot to make two of the functions inside
"static".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| eafa96485a6c3ce0de4f511ed080a64a7a44f2bb |
14-May-2013 |
Reed Kotler <rkotler@mips.com> |
This is the first of three patches which creates stubs used for
Mips16/32 floating point interoperability.
When Mips16 code calls external functions that would normally have some
of its parameters or return values passed in floating point registers,
it needs (Mips32) helper functions to do this because while in Mips16 mode
there is no ability to access the floating point registers.
In Pic mode, this is done with a set of predefined functions in libc.
This case is already handled in llvm for Mips16.
In static relocation mode, for efficiency reasons, the compiler generates
stubs that the linker will use if it turns out that the external function
is a Mips32 function. (If it's Mips16, then it does not need the helper
stubs).
These stubs are identically named and the linker knows about these tricks
and will not create multiple copies and will delete them if they are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8
ips16HardFloat.cpp
|
| f4a1377322a9234c17b1d324c47248bdb5f62158 |
13-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 42f562a1694d24b41f36bbb4d4a086a2a470c625 |
13-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add option -mno-ldc1-sdc1.
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| 151687cb8c4fc65fefcd8964a0c3d77680e90a5c |
13-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a helper function which creates an instruction with the same
operands as the prototype instruction but with a different opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
ipsInstrInfo.h
|
| 6daba286836e6fb2351e7ebc248e18a5c80e8a31 |
13-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename functions. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsLongBranch.cpp
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCTargetDesc.cpp
ipsTargetMachine.cpp
|
| d84ccfaf50c7843f31ffc74a8a8e33f779453d6e |
11-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change getFrameMoves to return a const reference.
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ipsSEFrameLowering.cpp
|
| 46090914b783b632618268f2a5c99aab83732688 |
11-May-2013 |
Reed Kotler <rkotler@mips.com> |
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips16HardFloat.cpp
ips16HardFloat.h
ips16ISelLowering.cpp
ipsCallingConv.td
ipsISelLowering.cpp
ipsISelLowering.h
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
|
| 6e53180db120b30f600ac31611a9dd47ef7f4921 |
10-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCAsmInfo.cpp
CTargetDesc/MipsMCAsmInfo.h
CTargetDesc/MipsMCTargetDesc.cpp
|
| b637b9f89e88e8c1ffe147634c1b2b297fb6edeb |
08-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add instruction selection pattern for (seteq $LHS, 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181459 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 9dbeb69a345d12b15571769cfacf1d5e1a7ce378 |
03-May-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r180947.
Change-Id: Ic9e7daa7ef3789298c49a7b308af92115f5d682d
ndroid.mk
|
| 2bb955a6931580c9bb0472aa29b3fbbabe263295 |
04-May-2013 |
Reed Kotler <rkotler@mips.com> |
Remove some uneeded pseudos in the presence of the naked function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| a2b2200ff8684ba23c64b24c0128a78f4b6e3c73 |
03-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Split the DSP control register and define one register for each field of
its fields.
This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsRegisterInfo.cpp
ipsRegisterInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
|
| 38578c4919ea18ceb27e29988b2d857afe6215bf |
03-May-2013 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/master' into merge-20130502
Conflicts:
lib/Support/Unix/Signals.inc
unittests/Transforms/Utils/Cloning.cpp
Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
|
| 99ad6ac65e8c97a0d3c9d884285dda01f793b7d1 |
03-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Handle reading, writing or copying of ccond field of DSP control
register.
- Define pseudo instructions which store or load ccond field of the DSP
control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
|
| e2e80cbdcfc5e69fd59715f9dcde3154cffa8169 |
02-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[mips] Fix the head Mips16RegisterInfo.cpp comment
...aka a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
|
| f9a5e7e4e9ca91111b15d97fe7461c9061931ff7 |
02-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename class and functions. Simplify code.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180897 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEFrameLowering.cpp
|
| c147c1b994e1187cb471cdb7ee05f5f875eff4e0 |
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix handling of instructions which copy to/from accumulator registers.
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsInstrInfo.td
ipsRegisterInfo.td
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
|
| cd6c57917db22a3913a2cdbadfa79fed3547bdec |
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Instruction selection patterns for DSP-ASE vector select and compare
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
ipsRegisterInfo.td
ipsSEISelLowering.cpp
|
| 13ec4812fc733c37bb3329982bc044d186e0bea2 |
30-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify code.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180807 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| b0caf5ff64962fd9ff2977d7c31d6bb88fb8a8a5 |
30-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clear isCommutable bit of instructions which are not commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180801 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
|
| 97265a48895a2cda7f04e47bfe935c4fdd71f8ae |
26-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: .set reorder support
Mips have delayslots for certain instructions
like jumps and branches. These are instructions
that follow the branch or jump and are executed
before the jump or branch is completed.
Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.
The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.
For backwards compatibility we need to support
.set reorder and have it be the default behavior in the
assembler.
Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 089741479be03b625f5a8cc52e750b4e532338c6 |
25-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definitions of micromips load and store instructions.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 385de773033080503491919dc50be7203552247b |
25-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definitions of micromips shift instructions.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180238 91177308-0d34-0410-b5e6-96231b3b80d8
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| e311b00a912b9f1a1e8fc1d28b2e58a015d250ec |
23-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Compare splat value with element size instead of calling isUIntN.
No intended changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180130 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| b109ea8245e2948ea6d06a6e6cbab7c6788da211 |
22-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180040 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ipsOs16.cpp
ipsSEISelLowering.cpp
|
| d597263b9442923bacc24f26a8510fb69f992864 |
22-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsSEISelLowering.cpp
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
ipsISelLowering.cpp
ipsISelLowering.h
ipsSEISelLowering.cpp
|
| 97a62bf2a4a2d141aad8af3531c3b69934f134c1 |
20-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Instruction selection patterns for DSP-ASE vector shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
ipsSEISelLowering.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelDAGToDAG.cpp
ipsSEISelDAGToDAG.cpp
|
| f530aff9de2738db0e3471b259ff0b577a6603e6 |
19-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] First patch which adds support for micromips.
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
icroMipsInstrFormats.td
icroMipsInstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 8d99ec574849ca8266e6491ceafee6c6029692b3 |
19-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
operand type to uimm16.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 2fbe90cf93fcb153ac1d651c764785c9b09887f6 |
18-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179741 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 26aef5b7d64e2dd2ed49123baf1e1075b648824f |
18-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] DSP-ASE move from HI/LO register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
ipsRegisterInfo.td
|
| 86924b4182537745659f2660244f3402c1e1ca4d |
18-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: formatting and comment changes.
This patch should not have any functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179737 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| ce47d5ba8cf7e30cbf0d6b80d3f7d10916c7fe31 |
17-Apr-2013 |
Evgeniy Stepanov <eugeni.stepanov@gmail.com> |
Fix -Werror build.
Broken in r179657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179669 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 8afc8b7e63d5ce2d027e92934d16b19e5ba2db59 |
17-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Enable handling of nested expressions
This patch allows the Mips assembler to parse and emit nested
expressions as instruction operands. It also extends the
expansion of memory instructions when an offset is given as
an expression.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179657 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsMCCodeEmitter.cpp
|
| b8145e3881872fffbac15693c94536446f060330 |
16-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Explicit floating point condition register recognition.
This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.
Corresponding test cases have been added.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 4e0980af2e9eda80cbd82895167e650d83ffe087 |
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 3d60241c3e86973be281660bc5971c3a46cfdc47 |
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Reapply r179420 and r179421.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
|
| bf308cedce5caca4c73e558611a1c8c48687d62e |
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Override TargetLoweringBase::isShuffleMaskLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179433 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.h
|
| d35d5bdfc41ff401f938e49e844d707462405428 |
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r179420 and r179421.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
|
| 6d224459f42fd1e2a57479b6b60e55053dce38d7 |
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Instruction selection patterns for carry-setting and using add
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
|
| 9367b8d4f254d9e5cccb15334cc1a969c5be0d31 |
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsSEISelLowering.cpp
|
| fc82e4db13b46b2f14f5895d2a0b33524d55d06a |
11-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selects
multiply instructions in MipsSEDAGToDAGISel.
This patch was supposed to be part of r178403.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179314 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
|
| fee62c167b1f731998ff4d315830154d17ec6f85 |
11-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.
- Rename function.
- Pass iterator by value.
- Remove header include.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
|
| 74adad6de8cf947257a53bb08364fa0f4f71b10e |
10-Apr-2013 |
Reed Kotler <rkotler@mips.com> |
This is for an experimental option -mips-os16. The idea is to compile all
Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this
would happen as long as floating point instructions are not needed.
Probably it would also make sense to compile as mips32 if atomic operations
are needed too. There may be other cases too.
A module pass prescans the IR and adds the mips16 or nomips16 attribute
to functions depending on the functions needs.
Mips 16 mode can result in a 40% code compression by utililizing 16 bit
encoding of many instructions.
The hope is for this to replace the traditional gcc way of dealing with
Mips16 code using floating point which involves essentially using soft float
but with a library implemented using mips32 floating point. This gcc
method also requires creating stubs so that Mips32 code can interact with
these Mips 16 functions that have floating point needs. My conjecture is
that in reality this traditional gcc method would never win over this
new method.
I will be implementing the traditional gcc method also. Some of it is already
done but I needed to do the stubs to finish the work and those required
this mips16/32 mixed mode capability.
I have more ideas for to make this new method much better and I think the old
method will just live in llvm for anyone that needs the backward compatibility
but I don't for what reason that would be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179185 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ipsOs16.cpp
ipsOs16.h
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
|
| a9a5c537ad0bf5ab68ed79c163500a4fcb3fc3ff |
10-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips specific inline asm operand modifier 'D'
Modifier 'D' is to use the second word of a double integer.
We had previously implemented the pure register varient of
the modifier and this patch implements the memory reference.
#include "stdio.h"
int b[8] = {0,1,2,3,4,5,6,7};
void main()
{
int i;
// The first word. Notice, no 'D'
{asm (
"lw %0,%1;"
: "=r" (i)
: "m" (*(b+4))
);}
printf("%d\n",i);
// The second word
{asm (
"lw %0,%D1;"
: "=r" (i)
: "m" (*(b+4))
);}
printf("%d\n",i);
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| a430cb613b6e93c05f128b04323c57acfd08686d |
09-Apr-2013 |
Reed Kotler <rkotler@mips.com> |
This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.
Because this patch is somewhat involved I have provide an overview of the
key pieces of it.
The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.
Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info,
instruction info and instruction selection classes.
Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).
When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.
When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.
In addition, MipsAsmPrinter needs to be reset on a function basis.
The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips16ISelDAGToDAG.cpp
ips16ISelDAGToDAG.h
ipsAsmPrinter.cpp
ipsConstantIslandPass.cpp
ipsLongBranch.cpp
ipsModuleISelDAGToDAG.cpp
ipsModuleISelDAGToDAG.h
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
ipsSEISelLowering.cpp
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 67fdafe1cd2c25aa1d245b4becf93324c08ec93e |
03-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Small update to the implementation of eh.return for Mips.
This patch initializes t9 to the handler address, but only if the relocation
model is pic. This handles the case where handler to which eh.return jumps
points to the start of the function.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
|
| c227c4675e7395342182492e99c0696c5d9997af |
03-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.
This patch fixes the following two tests which have been failing on
llvm-mips-linux builder since r178403:
LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll
LLVM :: Analysis/Profiling/load-branch-weights-loops.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178584 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| fd2cd0db97d78e10288bdf0fb915296c68294237 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add patterns for DSP indexed load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
|
| 175f0fd99aaa66fd4268d0f3ff73d6b76332c99f |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define reg+imm load/store pattern templates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrInfo.td
|
| 2c2c33a167c82db9abd9b6173c1cdfdaa40c2071 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsDSPInstrInfo.td
ipsISelLowering.cpp
|
| 7e287bfb58e63c4e1068e49e8e1b714f3b9703bc |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| d593a77b4cf3b81cd657e351e47cad25ee037ce1 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.
We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| f5926fd844a84adcf1ae4f193146f2877997b82c |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ips64InstrInfo.td
ipsISelLowering.cpp
ipsInstrInfo.td
ipsSEISelDAGToDAG.cpp
ipsSEISelLowering.cpp
ipsSEISelLowering.h
|
| 9cf0724cc3a570fe64146fda7518cef5c740e988 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 2459afe69791ea04f2a060a2acc7104242844ace |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| dd958925b0064981f4894ab5b8f37b02faa0c759 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| cbcdcfbda5c60d5ac7a492ef8f90b325b6026bd1 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.h
|
| 8f4d3800a7e6f546279bc7b7f418693fc7484d54 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
|
| d6a77822a98b9b5329916e994aac3a19c540be43 |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.
The code makes use of register's scavenger's capability to spill multiple
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178391 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEFrameLowering.cpp
|
| 2cd7d3f9ce034ecc4ef4d6fa8fc7dac06f0c708f |
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define pseudo instructions for spilling and copying accumulator
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsDSPInstrInfo.td
ipsInstrInfo.td
|
| 5114226c1896f250be8881adf67d55a7e54b50fc |
29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a function which returns the GPR register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178359 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ipsRegisterInfo.h
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| fda56e54cd303894c8c6d4be7527d178d1a980cf |
29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Change type of accumulator registers to Untyped. Add two more accumulator
register classes for Mips64 and DSP-ASE.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178328 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| c713e996d305df99cc7fc58c9d8dc1f5fa00518d |
29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ipsInstrInfo.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
|
| 8c0b9b03fe0198504c0c5645b4331aa23fb16b04 |
29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add parameter Alignment to MipsFrameLowering's constructor.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178326 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.h
ipsFrameLowering.h
ipsSEFrameLowering.h
|
| af7da5cb993d1a2afad4816fe22c497d5adbef91 |
29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 94fcfaf3a9f1179edb3b8053fe7b23eab6fb83bb |
29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs
This patch provides alias definitions in td files and test cases to show the usage.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 0c8f21afbd31e796c18a6a59b9f1039a71145c96 |
25-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177899 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| dc3beb90178fc316f63790812b22201884eaa017 |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.
To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.
In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEFrameLowering.cpp
|
| d3107fbc54a5b5156f0aabc8788724f1469eb9df |
22-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
Fix the invalid opcode for Mips branch instructions in the assembler
For mips a branch an 18-bit signed offset (the 16-bit
offset field shifted left 2 bits) is added to the
address of the instruction following the branch
(not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
Previously, the code generator did not perform the
shift of the immediate branch offset which resulted
in wrong instruction opcode. This patch fixes the issue.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 25df6a93f3324bd30f44dcb95fd17aff0a92d438 |
22-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
This patch that enables the Mips assembler to use symbols for offset for instructions
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsInstrInfo.td
|
| c91b5e197bb41ccb2f9f78b6176e61c848df9e15 |
21-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
This patch enables the Mips .set directive to define aliases
The .set directive in the Mips the assembler can be
used to set the value of a symbol to an expression.
This changes the symbol's value and type to conform
to the expression's.
Syntax: .set symbol, expression
This patch implements the parsing of the above syntax
and enables the parser to use defined symbols when
parsing operands.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| d212f3fdfcfd01d5bc24ac4614b7e23478432f80 |
19-Mar-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r177342.
Change-Id: Ie489c8fab15789330f6ac968087ba14953dfacca
ndroid.mk
|
| 2d4629c5d7dcc6582fa7b85a517744f1a3654eba |
19-Mar-2013 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge_2013_03_18
|
| a286fc065a5bc846d73c8407a534a1d3c1d70b59 |
15-Mar-2013 |
Eric Christopher <echristo@gmail.com> |
Silence anonymous type in anonymous union warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| cacff672dd532d882727a51e73c96f19fde45828 |
15-Mar-2013 |
David Blaikie <dblaikie@gmail.com> |
Remove some unused variables to clean the Clang -Werror build
(these were added in r177089)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
|
| 7abc88bc83d2b1a0e576fa5cf92de5017d90a792 |
15-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isAllocatable bit of unallocatable register classes to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| f8b0a08b6a2e2f4eacdb05eae9a8dd704b692b55 |
14-Mar-2013 |
Reed Kotler <rkotler@mips.com> |
Add a new method which enables one to change register classes.
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup.
Normally you need to add register classes and then call
computeRegisterProperties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelLowering.cpp
|
| 3080d23fde4981835d8a7faf46c152441fadb11f |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Provide the register scavenger to processFunctionBeforeFrameFinalized
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.
This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.h
|
| 042b79625f315da6378d06b5480b15894d6b06b1 |
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix filename in comment and delete unnecessary lines of code.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelLowering.cpp
|
| 862146b6077f017faa2b2113768e723891a06494 |
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Add back lines which were accidentally deleted in CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 275f354d6d459f4bcfb3d3e8b5b7f3ed08585940 |
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define function MipsSEDAGToDAGISel::selectAddESubE.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
|
| f283512d72757aac5bedcb270f9199194e6a12c0 |
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename functions and variables to start with proper case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
ips16ISelDAGToDAG.cpp
ips16ISelDAGToDAG.h
ips16InstrInfo.td
ipsISelDAGToDAG.cpp
ipsISelDAGToDAG.h
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
|
| 1d905668ddaab127eb6f9668b6314afbef7bee20 |
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Add header file MipsISelDAGToDAG.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.h
|
| 554d9312b284265f91ac5ee5bf0351d446f669b1 |
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
mips16 and MipsSEDAGToDAGISel is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips16ISelDAGToDAG.cpp
ips16ISelDAGToDAG.h
ipsISelDAGToDAG.cpp
ipsSEISelDAGToDAG.cpp
ipsSEISelDAGToDAG.h
|
| 5ac065a79767cc112eba63136183b7103765d0d3 |
13-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
mips16 and MipsSETargetLowering is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips16ISelLowering.cpp
ips16ISelLowering.h
ipsISelLowering.cpp
ipsISelLowering.h
ipsSEISelLowering.cpp
ipsSEISelLowering.h
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| f635ef401786c84df32090251a8cf45981ecca33 |
12-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename function and variable names to start with proper case. Fix typos.
Delete commented-out code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176844 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.h
ipsISelLowering.cpp
ipsISelLowering.h
|
| 3ef5383b3537a420c5e2ab3e657c378e5185549d |
08-Mar-2013 |
Tom Stellard <thomas.stellard@amd.com> |
DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.
v2:
- Expand more BR_CC value types for NVPTX
v3:
- Expand correct BR_CC value types for Hexagon, Mips, and XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| b7656a9cc4bf36752df38e7c02b910c9390b9c39 |
06-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Custom-legalize BR_JT.
In N64-static, GOT address is needed to compute the branch address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 2123c1c0de9e6006dfffe9123b4b992703202e3e |
06-Mar-2013 |
Stephen Hines <srhines@google.com> |
Update build rules for LLVM merge to version 176139.
Change-Id: Ibb71ad9a6a2ed05dbf87f249ac42b1355e3fa41a
CTargetDesc/Android.mk
|
| 5adb136be579e8fff3734461580cb34d1d2983b8 |
06-Mar-2013 |
Stephen Hines <srhines@google.com> |
Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226
Conflicts:
include/llvm/Support/ELF.h
lib/Support/DeltaAlgorithm.cpp
Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
|
| 5ffd24c49f6d78c166ee357424bf4e20f61af6bc |
06-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove android calling convention.
This calling convention was added just to handle functions which return vector
of floats. The fix committed in r165585 solves the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsCallingConv.td
ipsSubtarget.cpp
ipsSubtarget.h
|
| 1e3e869899468de2210f9777905340d907c814c6 |
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets
returned in registers $2 and $4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCallingConv.td
ipsISelLowering.cpp
|
| 7433b2e1142a46c1dbb491d91e0175cb9ce83167 |
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
handle fp128 returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| cb2eafdfa358ae8a1e1f9ae39d8c72cd4d446da1 |
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating
point registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 5fdee6d2b5a72a826bf6db47c319ddac08cd9f57 |
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Correct handling of fp128 (long double) formals and read long double
parameters from floating point registers if target is mips64 hard float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 1ae08e007784a0708d6dae9c37b84bb62d5e1282 |
04-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Print move instructions.
"move $4, $5" is printed instead of "or $4, $5, $zero".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 0b9675d631a33ecde9e11febea48a2c6551bfeec |
04-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| b3ea880a706cde45818e1a0f5b162358ac8bb5bd |
04-Mar-2013 |
Jia Liu <proljc@gmail.com> |
Mips ISD typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176426 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| ee767fe2d2d742630d2fd40f91f3c54e35cc0668 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:
(select (setgt a, Constant), T, F)
The pattern above effectively turns into this:
(conditional-move (setlt a, Constant + 1), F, T)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
ipsISelDAGToDAG.cpp
ipsInstrInfo.td
|
| 079a0ff1967c1dcba99d5dcd4b0e0bcaabc082d6 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176380 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
|
| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.h
|
| aa49f35240554a78318fe15f375632a66ece5e1f |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove unused option. Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176330 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 1f0aca857b899b397a9d82bb21cb1ca819419a90 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add the capability to search delay slot filling instructions in
successor basic blocks.
Currently this is off by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176329 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 888e8fefd22550ccfa496c3c1e02bd2ac036263b |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not add SecondLastInst to list BranchInstrs if there is only one
terminator.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176326 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
|
| d0a4b60df146b8c51555a752fed1530999ecbe64 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define an overloaded version of function MipsInstrInfo::AnalyzeBranchAdd.
This function will be used later when the capability to search delay slot
filling instructions in successor blocks is added. No intended functionality
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176325 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
ipsInstrInfo.h
|
| b8bc8cc3b0e0d2811b3326d49835e8a1edb1ef61 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add options to disable searching backward and in successor blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176321 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| e760675b0ed8d7adcc2c991a2d645d2b538a5ab3 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add capability to search in the forward direction for instructions that
can fill the delay slot.
Currently, this is off by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176320 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 1f7330b16239f50daee57dbf53b20fbacd028ee4 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define helper function searchRange
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176318 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 49d58723d2f8d4578c07b37cf636a81b8b8a24a5 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename function findDelayInstr to searchBackward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176317 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| a56f411961c41d8b4f6ffc62c95c5fc95fbac8c8 |
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define class MemDefsUses.
This class tracks dependence between memory instructions using underlying
objects of memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176313 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| c1a2caf870ab37d887cb89f21ca59a2efde88928 |
27-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Fix cut/paste error in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176165 91177308-0d34-0410-b5e6-96231b3b80d8
ipsConstantIslandPass.cpp
|
| d056dc0aae141d79131c6d537cf2add42922fb97 |
27-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Add the skeleton for the Mips constant island pass.
It will only be used for Mips 16 at this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176161 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips.h
ipsConstantIslandPass.cpp
ipsTargetMachine.cpp
|
| 70cdcd5114b30c4983ff158278422ea129bd27bb |
26-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use class RegDefsUses to track register defs and uses.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176070 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| de89ecd011c453108c7641f44360f3a93af90206 |
25-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176007 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 29cb2591f9f7ec948e7b0e719b1db6cef99010d0 |
25-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make psuedo FEXT_T8I816_ins into a custom emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176002 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 459d35cb7975804048684261f2358eedbd2209c1 |
24-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make psuedo FEXT_T8I816_ins a custom inserter. It should be expanded
as early as possible; which means during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175984 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| e7c67492ddc503802128ff20853a23a644f082f9 |
24-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Add new base instruction def for cmpi, cmp, slt and sltu so that def/uses
proper. Fixed this already a few days ago for slti.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175975 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 50354a3f4a5c9e3689d502a935430f2a57a44af2 |
23-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos/macros for Selt. This is the last of the complex
macros.The rest is some small misc. stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 606893294095e214f50937e8f8e9770efaab07a7 |
22-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Emit call16 operator instead of got_disp. The former allows lazy binding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175920 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 00ddc5a7274fb4131f1a724bc350fd756156a80f |
22-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refers
to the immediate operand of sli or cmp function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175865 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 7617d032ae12ba96ad65f37d91274e6f8c14e690 |
22-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand mips16 SelT form pseudso/macros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175862 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16FrameLowering.h
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ipsSEFrameLowering.cpp
ipsSEFrameLowering.h
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| ffbe432595c78ba28c8a9d200bf92996eed5e5d9 |
21-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175718 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 77217229ba1bbc92f3a53099fa91bcdaa7797da8 |
21-Feb-2013 |
Jack Carter <jcarter@mips.com> |
Mips specific standalone assembler addressing mode %hi and %lo.
The constructs %hi() and %lo() represent the high and low 16
bits of the address.
Because the 16 bit offset field of an LW instruction is
interpreted as signed, if bit 15 of the low part is 1 then the
low part will act as a negative and 1 needs to be added to the
high part.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175707 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 99e98551bf8719764f9345ce856118f3f1a9c441 |
21-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips specific standalone assembler directive "set at".
This directive changes the general purpose register
that the assembler will use when given the symbolic
register name $at.
This does not include negative testing. That will come
in a future patch.
A side affect of this patch recognizes the different
GPR register names for temporaries between old abi
and new abi so a test case for that is included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175686 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| cb2ae3d98e3bb36e5813f8f69b00d39efd026dcd |
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
MCParser: Update method names per coding guidelines.
s/AddDirectiveHandler/addDirectiveHandler/
s/ParseMSInlineAsm/parseMSInlineAsm/
s/ParseIdentifier/parseIdentifier/
s/ParseStringToEndOfStatement/parseStringToEndOfStatement/
s/ParseEscapedString/parseEscapedString/
s/EatToEndOfStatement/eatToEndOfStatement/
s/ParseExpression/parseExpression/
s/ParseParenExpression/parseParenExpression/
s/ParseAbsoluteExpression/parseAbsoluteExpression/
s/CheckForValidSection/checkForValidSection/
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175675 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 5f645953555cee528cd1c0d6faa16d9b89ebba48 |
20-Feb-2013 |
David Blaikie <dblaikie@gmail.com> |
Fix the (clang -Werror) build by removing an unused member variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175607 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 65692c809efa46337bf80f12b1795e785a6e7207 |
20-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
|
| 5cdeca8b1d726790fe9687bc4a4d615d299bc151 |
19-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips (o32 abi) specific e_header setting.
EF_MIPS_ABI_O32 needs to be set in the
ELF header flags for o32 abi output.
Contributer: Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175569 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.cpp
|
| c989c61798783f99abe7f8c27baf76bd2aea5067 |
19-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips (Mips16) specific e_header setting.
EF_MIPS_ARCH_ASE_M16 needs to be set in the
ELF header flags for Mips16.
Contributer: Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175566 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.cpp
|
| ccb3c9c2702f548fd0a7d60a622e6f4fdf0940e7 |
19-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips (MicroMips) specific STO handling .
The st_other field settig for STO_MIPS_MICROMIPS
Contributer: Zoran Jovanovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175564 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsELFStreamer.h
CTargetDesc/MipsMCCodeEmitter.cpp
ipsAsmPrinter.cpp
|
| 8a20844e277d1f51600134589aeb9ca88d9ca25d |
19-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| f80167520740cbd9b73ead4fa524533532c5538e |
19-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
|
| bb01b3cb936f110fc20700b4c4447e3e7214cab3 |
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175420 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
|
| 139748f1c180d4f2d55f31b321e9cfe87b06eb64 |
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175419 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| dabfebb5c61e49ab23c5828953506d965bcf7401 |
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudo/macro BteqzT8SltX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
|
| a8601bb4ffc5a3d7668cfadcd884e5400c526231 |
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand macro/pseudo BteqzT8CmpX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175416 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
|
| da4afa72f7cbe2801f3876eda33416aa3ba42987 |
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
|
| 5be5fa468acc4948b8f4d7f5e945d77a53e40bb8 |
17-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Clean up mips16 td file in preparation for massive pseudo lowering work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175379 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 2de893210b0d4178edb4e3f2a965d57e97410341 |
16-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
One more try to make this look nice. I have lots of pseudo lowering
as well as 16/32 bit variants to do and so I want this to look nice
when I do it. I've been experimenting with this. No new test cases
are needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175369 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
|
| 6a0da011e42e553d497fce2059f43401e854b99d |
16-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Use a different scheme to chose 16/32 variants. This scheme is more
consistent with how BuildMI works. No new tests needed. All should work
the same as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175342 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
|
| abbf9df7f42e8e3e95b02b16ebbc6a0684bb4f6d |
16-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove SDNPWantParent from the list of SDNodeProperties.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175325 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
ipsInstrInfo.td
|
| ffd28a44f04ab2de5a7092fbd5ff17af79f56e28 |
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up class MipsCCInfo.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175310 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| dc2f79274021a590d6b72acd741117068c3e49bd |
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Split SelectAddr, which was used to match address patterns, into two
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
ipsInstrFPU.td
ipsInstrInfo.td
|
| 79cd4118090a3c0bc80cafc699a51abf1d6299f3 |
15-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Remove a final dependency on the form field in tablegen; which is a remnant
of the old jit and which we don't intend to support in mips16 or micromips.
This dependency is for the testing of whether an instruction is a pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175297 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
ipsAsmPrinter.cpp
|
| 5cf38fd7633bee4a0ff627593cc1fd63ab0868d8 |
15-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| d977aacf990d241d0224d20518f631a928c1b1a8 |
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Disallow moving load/store instructions past volatile instructions.
Unfortunately, I wasn't able to create a test case that demonstrates the
problem I was trying to fix with this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175226 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| cd7319dc5f91ac81ab9d8505f34937e91bfcf65d |
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Replace usage of SmallSet with BitVector, which is used to keep track of
defined and used registers. Also add a few helper functions to simplify the
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175224 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 90db35a3e7d24ad81aa0ce6b641186faed033cdc |
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix comments and coding style violations. Declare functions to be const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175222 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| eba97c573f08332c9c9d1875c304cce1bea2e28e |
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify code in function Filler::findDelayInstr.
1. Define and use function terminateSearch.
2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator.
3. Delete the line which checks whether an instruction is a pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175219 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 38f85c5b9f2e2a7e1364ce44b6b8cd1ec0ffb0b3 |
14-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Remove the form field from Mips16 instruction formats and set things
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ips16InstrFormats.td
ips16InstrInfo.td
|
| 6b9d4617800d9450825f8a4b122a9aeb76f2795f |
13-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
|
| 80806961035807d1b9566cdd34233c1b4cf49282 |
13-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make jumptables work for -static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| b4b4fa80bab1387e50c5f1b08e1141f853d35204 |
11-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Expand pseudo instructions before they are emitted in
MipsCodeEmitter.cpp.
JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not
called when the old JIT is used.
This fixes the following tests which have been failing on
llvm-mips-linux builder:
LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll
LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll
LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll
LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll
LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
LLVM :: ExecutionEngine__hello2.ll
LLVM :: ExecutionEngine__stubs.ll
LLVM :: ExecutionEngine__test-branch.ll
LLVM :: ExecutionEngine__test-call.ll
LLVM :: ExecutionEngine__test-common-symbols.ll
LLVM :: ExecutionEngine__test-loadstore.ll
LLVM :: ExecutionEngine__test-loop.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174912 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| 1b235a26f530623d07b49ab861fcd4adb4e62b4f |
11-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174907 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| b2d1275188c997e279293afc031a88e03871f9e0 |
08-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is
important as well as for other passes which need an accurate count of
program size. There will be other similar putbacks to this for various
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsInstrInfo.td
|
| 61b97b8c1721ba45e5c10ca307ceebe1efdf72a9 |
08-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16RegisterInfo.cpp
|
| 5dd41c95f3075fc5c01cfb6822a66ac584fcc8c7 |
07-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make Filler a class and reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174666 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 0c66403efdf88ff4f247b6a9f45339bb3a893235 |
07-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 24b339dcdc2411bc3305e6f58964caa393fd9ea0 |
07-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make sure we call externals from libraries properly when -static.
For example, when we are doing mips16 hard float or soft float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 6e3443eed44a463bdbc9d2e01f01b85f07d5ca40 |
07-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Enable jumps when in -static mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 6c59c9f57c8428e477ed592ee3537323d287d96f |
06-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174546 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsInstrFormats.td
ipsInstrInfo.td
|
| baabdecbb9bf5b32fa81b1e2830ab13076d549f1 |
05-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not use function CC_MipsN_VarArg unless the function being analyzed
is a vararg function.
The original code was examining flag OutputArg::IsFixed to determine whether
CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this
flag is often set to false when the function being analyzed is a non-variadic
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174442 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| d07359667118ab1e889c3b9163b5e6a12414c38b |
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to Mips return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174410 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsInstrInfo.td
|
| 7304702ef99f98897d15baae0eede55f294bc602 |
05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the Mips ELF header flag for
MicroMips architectures.
Contributer: Zoran Jovanovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174360 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.cpp
ips.td
ipsSubtarget.cpp
ipsSubtarget.h
|
| 37ef65b9c1b93c386d13089d9ace6a1cc00e82dc |
05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
ips64InstrInfo.td
ipsInstrInfo.td
|
| 9c5b94b6be08afe22b576d007353a0002603cef1 |
05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch changes a static_cast to dyn_cast
for MipsELFStreamer objects.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174354 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.h
ipsAsmPrinter.cpp
|
| 63f331235513a6f562ab4b2809b497c518b132e9 |
02-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Start static relocation implementation for mips16.
This checkin makes hello world work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174264 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsInstrInfo.td
|
| 108fb3202af6f500073cdbb7be32c25d7a273a2e |
31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
ipsRegisterInfo.h
|
| d7800dfba255305941d81a6b8b30cb37ef50f5ef |
30-Jan-2013 |
David Blaikie <dblaikie@gmail.com> |
Removing initializer for the field removed in r173887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173888 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.h
|
| 84fb9633caf6dc5b63ca98fd4d92e6086ab146d0 |
30-Jan-2013 |
David Blaikie <dblaikie@gmail.com> |
Remove unused variable (introduced in r173884) to clear clang -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173887 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.h
|
| cbaf2ac072369f67536485bcc00e7de1f1202679 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
Forgot to add new file to CMakeLists
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173886 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
|
| dba14301f0098f9fc5c0d244bf334f55a6a21960 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch implements runtime Mips specific
setting of ELF header e_flags.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFStreamer.cpp
CTargetDesc/MipsELFStreamer.h
CTargetDesc/MipsMCTargetDesc.cpp
ipsAsmPrinter.cpp
ipsSubtarget.cpp
ipsSubtarget.h
|
| 9a7bf438b50fed2c77f0e2bc835defa5b4728f82 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch reworks how llvm targets set
and update ELF header e_flags.
Currently gathering information such as symbol,
section and data is done by collecting it in an
MCAssembler object. From MCAssembler and MCAsmLayout
objects ELFObjectWriter::WriteObject() forms and
streams out the ELF object file.
This patch just adds a few members to the MCAssember
class to store and access the e_flag settings. It
allows for runtime additions to the e_flag by
assembler directives. The standalone assembler can
get to MCAssembler from getParser().getStreamer().getAssembler().
This patch is the generic infrastructure and will be
followed by patches for ARM and Mips for their target
specific use.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFObjectWriter.cpp
|
| 544cc21cf4807116251a699d8b1d3d4bace21597 |
30-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Lower EH_RETURN.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrInfo.td
ipsMachineFunction.cpp
ipsMachineFunction.h
ipsSEFrameLowering.cpp
ipsSEFrameLowering.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsSERegisterInfo.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 52dd806ed9c656c1b4fd073c8e086b563104f601 |
28-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove addToNoHelperNeeded function that was left unused after r173649. Fixes a -Wunused warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173664 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| bc49cf73079c1223fba5046047517fc3c00d5284 |
28-Jan-2013 |
Reed Kotler <rkotler@mips.com> |
Make some code a little simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173649 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| d07c64dce67595e9b27e039c558800b7499df7c7 |
26-Jan-2013 |
Reed Kotler <rkotler@mips.com> |
fix use of std::std. it's ordered set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173563 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 801c5838830d190a6b0d8e462bd43805f66ba50f |
25-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch implements parsing the .word
directive for the Mips assembler.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| d2047c60013a1a48cc3cef88003633463285b9ee |
25-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
|
| b3105b9a9bb318672364b3d63e07b6325c3be3d7 |
24-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsISelLowering.cpp: Fill unreachable paths to fix warnings. [-Wsometimes-uninitialized]
FIXME: Could they, unreachable(s), be removed?
FIXME: I could prefer the coding standards...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173325 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 00cdf602ae73e039c5d5244bae4bffb5e6455096 |
24-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsISelLowering.cpp: Fix a warning, take two. [-Wunused-variable]
...and fix a typo, s/#ifdef/#ifndef/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173324 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| d5a336cdb5ed691b0288c8d4aa4c5b1899b7e39b |
24-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsISelLowering.cpp: Fix a warning. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173323 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 8453b3f66a3c3200ea828491ef5cf162db9ccfb2 |
24-Jan-2013 |
Reed Kotler <rkotler@mips.com> |
The next phase of Mips16 hard float implementation.
Allow Mips16 routines to call Mips32 routines that have abi requirements
that either arguments or return values are passed in floating point
registers. This handles only the pic case. We have not done non pic
for Mips16 yet in any form.
The libm functions are Mips32, so with this addition we have a complete
Mips16 hard float implementation.
We still are not able to complete mix Mip16 and Mips32 with hard float.
That will be the next phase which will have several steps. For Mips32
to freely call Mips16 some stub functions must be created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| e752feee5228bfa33acee35ef9c606ce12f0f173 |
23-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and explicitly set this in every target that needs to change it from the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173270 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCAsmInfo.cpp
|
| a88322c283a001019bd5cd4ddeafc425cc4d00af |
22-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Implement MipsRegisterInfo::getRegPressureLimit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
ipsRegisterInfo.h
|
| bf6a77b98715012c0fa3bdbb3ba55fa7c24c1548 |
22-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up code in MipsTargetLowering::LowerCall. No functional change
intended
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173189 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 3aef70314b053a1df4f85ca4a6f3890d06ebbdd6 |
09-Jan-2013 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to r171905.
Android.mk
lib/Analysis/Android.mk
lib/CodeGen/Android.mk
lib/CodeGen/MachineScheduler.cpp - specify std::pop_heap()
lib/IR/Android.mk - new from lib/VMCore
lib/MC/Android.mk
lib/MC/MCAssembler.cpp - put back pointer param (from reference).
lib/Support/DeltaAlgorithm.cpp - iterator -> const_iterator !
lib/TableGen/Android.mk
lib/Target/ARM/ARMJITInfo.cpp - Removed unused legacy JIT changes
lib/Target/ARM/Android.mk
lib/Target/ARM/AsmParser/Android.mk
lib/Target/ARM/Disassembler/Android.mk
lib/Target/ARM/MCTargetDesc/Android.mk
lib/Target/Android.mk
lib/Target/Mips/Android.mk
lib/Target/Mips/Disassembler/Android.mk
lib/Target/Mips/MCTargetDesc/Android.mk
lib/Target/X86/Android.mk
lib/Target/X86/AsmParser/Android.mk
lib/Target/X86/Disassembler/Android.mk
lib/Transforms/IPO/Android.mk
lib/Transforms/Instrumentation/Android.mk
lib/Transforms/Scalar/Android.mk
lib/Transforms/Utils/Android.mk
lib/Transforms/Vectorize/Android.mk
lib/VMCore/Android.mk - moved to lib/IR
llvm-gen-intrinsics.mk - new Intrinsics.td location
utils/TableGen/Android.mk
Change-Id: Ifebdb1716c372fd917a844c44be9d10df66434b0
ndroid.mk
isassembler/Android.mk
CTargetDesc/Android.mk
|
| 059800f9e3fee2852672f846d91a2da14da7783a |
21-Jan-2013 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/master' into merge-llvm
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/MC/MCAssembler.cpp
lib/Support/Atomic.cpp
lib/Support/Memory.cpp
lib/Target/ARM/ARMJITInfo.cpp
Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
|
| e11dda8631f1e65417971ee0c2f7a661fc7d0fd7 |
19-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and
blank spaces at end of lines.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172882 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/LLVMBuild.txt
isassembler/Makefile
ips16InstrInfo.cpp
ips16InstrInfo.td
ipsInstrInfo.td
ipsLongBranch.cpp
|
| c91cbb9b0c90a480299cc7deaef166d47a61d9df |
18-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.
Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.
The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.
This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172847 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsReginfo.cpp
CTargetDesc/MipsReginfo.h
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsSubtarget.h
ipsTargetObjectFile.cpp
ipsTargetObjectFile.h
|
| e72fac60e3dbcf14ec68cedc1e86feafec1652eb |
18-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Removal of redundant code and formatting fixes.
Contributers: Jack Carter/Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| c147b678206db510336ee95c3b55dc9c0ff19595 |
17-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| 457ee1a12e2c52624af7fdb81cf938f6d8d96572 |
16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
reverting 172579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| 490c7d97737ea7719efcea7321d3cfa3984b0027 |
16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
Akira,
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| 096d617796228293810cb0443c6617b33c5afdc5 |
15-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch fixes a Mips specific bug where
we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.
The bug was exposed by the SingleSourcetest case
DuffsDevice.c.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172496 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFObjectWriter.cpp
|
| 953cbfcd26fa59d80c8d9ca749b5dd8ef901d11a |
14-Jan-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Improve r172471: avoid all those extra casts on the lines nearby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172481 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| b398cae1e501069c48456a4bfdf8bbf549aa9746 |
14-Jan-2013 |
David Greene <greened@obbligato.org> |
Fix Casting
Fix a casting-away-const compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172471 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| edaf85606d7ac8368dd7fa0e9fd4042e523a6e3a |
12-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172319 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| a96a96cefaa3196bde76a7bda8e57c95893f723b |
12-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsAsmParser: Try to unbreak tests to add extra check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172315 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| ec3199f675b17b12fd779df557c6bff25aa4e862 |
12-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
nstPrinter/MipsInstPrinter.cpp
nstPrinter/MipsInstPrinter.h
ips64InstrInfo.td
ipsInstrFPU.td
ipsInstrInfo.td
ipsRegisterInfo.td
|
| 4a50e53e53816076584c957741cb430899271726 |
08-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch produces the correct addend value for
an R_MIPS_GPREL16 relocation.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171882 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
|
| 26853a5d1c39c3e4ddab3dc9f3d1f97815d974d2 |
08-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch produces the correct pointer size
value in the 64 bit .eh_frame section.
It doesn't however allow exception handling to work
yet since it depends on the correct relocation model
being set in the ELF header flags.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171881 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCAsmInfo.cpp
|
| 251040bc18eedfa56d01fe92836e55cfd8c5d990 |
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
|
| 3ebe59c892051375623fea55e977ff559fdb3323 |
07-Jan-2013 |
Jordan Rose <jordan_rose@apple.com> |
Change SMRange to be half-open (exclusive end) instead of closed (inclusive)
This is necessary not only for representing empty ranges, but for handling
multibyte characters in the input. (If the end pointer in a range refers to
a multibyte character, should it point to the beginning or the end of the
character in a char array?) Some of the code in the asm parsers was already
assuming this anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171765 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 71ab7a79a74ebb3dad1aac02c5a5c7c2c20b547f |
07-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 3f0ef85f44e6af948e3048b3368c7e81cf227a8f |
05-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix data layout string. Add 64 to the list of native integer widths
and add stack alignment information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171587 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
|
| e13f441e002b95bb64d883d173f6aff9615556fd |
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] MipsTargetLowering::getSetCCResultType should return a vector type if
vectors are being compared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171517 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b |
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.h
ips16RegisterInfo.h
ips64InstrInfo.td
ipsInstrFormats.td
|
| f53b78f5bf28dff9536687245239f6aa200add86 |
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and
shift_rotate_imm64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171513 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 63723e5bf8bc1e5b699733cb79992b720b20f0d5 |
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171511 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
|
| 5f560bb2ebd9b489750fafd0c2d7c5136d18c622 |
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor instructions which move data from or to coprocessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171510 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16RegisterInfo.cpp
ipsAsmPrinter.cpp
ipsCodeEmitter.cpp
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsJITInfo.cpp
ipsLongBranch.cpp
ipsMachineFunction.cpp
ipsRegisterInfo.cpp
ipsSEFrameLowering.cpp
ipsSERegisterInfo.cpp
ipsTargetMachine.h
ipsTargetObjectFile.cpp
argetInfo/MipsTargetInfo.cpp
|
| 58a2cbef4aac9ee7d530dfb690c78d6fc11a2371 |
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.
Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
|
| dbf51ee4596791d8cf38538b80805b2c3a577836 |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| e8bc10b902f15eb4a12b810d5ab06a2755e7f990 |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor SYNC and multiply/divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| aa7c9cd1814ad080c7f8e5c2c4434c206e0ea66d |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor BAL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170954 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 189225369446136f82e080dbdcab3a0fa63c71ac |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 6a8309e62afd88fbea4f1c39121de6dc4dc0d899 |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 0a57dc1d147bbd091adf89ace10482ceb912c552 |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor load/store left/right and load-link and store-conditional
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 16164657d88c50be59a3fbff035ded786a98cf7f |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 5f5770baae0bd586410c11e0be1f634415d41186 |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove unnecessary isPseudo parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170947 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 8e719fac46c3c79dedfde86bf439819444223537 |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor LUI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 35242e27c578da3915451079b5bdd7b9a89ed77c |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor count leading zero or one instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 8aaed99a99fcb879be2ed9bbc25a68c2e8558960 |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor sign-extension-in-register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 7de001b97e1087b393efc90f7b10ffedd4f66fed |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor instructions which copy from and to HI/LO registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 2a732ec272e3bab004a47abb452ad47bc4eb8c7b |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor logical NOR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170937 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| a8215f4ec21188f3a793672202f20dbb93c8e5e8 |
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move instruction definitions in MipsInstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170936 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| a40ba2b3b2c909c366e5479d4e51ed35a0ada934 |
21-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
Call llvm_unreachable instead of assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170822 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
|
| 27210d215a9ab0384ea662bdacdf0c52bafe665e |
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
Implement cfi_def_cfa_offset. "Make check" test case for this comming in the
next few days but it's already tested a lot from test-suite and works fine.
This patch completes almost 100% pass of test-suite for mips 16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170674 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
|
| 0fd831325006d3d3f73022b4908ceacfbf7aa262 |
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
There is one more patch to finish large frames. Make sure we assert
on code that has large frames which will not yet compile correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170673 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
ipsInstrInfo.td
|
| bacbf1c2cb58af7d839027768a7a67e117a6cc5f |
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
set register class properly for mips16 here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170669 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| c28ee9622a4348c9d7a18d34fecc029f5817a5e2 |
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
This assert is overly restrictive and does not work for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170667 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 1f23239c5bdbeb45a612238acd48bb497b3cce15 |
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
Turn on register scavenger for Mips 16
We use an unused Mips 32 register for the emergency slot
instead of using the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170665 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
ips16RegisterInfo.h
|
| 9bf571fe2c24305aee6a930ed3b2561f6d4ff237 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| c23061547de868c5971e1f7a12bc54a37a59a53f |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor unconditional branch instruction. Separate encoding information
from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170663 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 1e7739f6140da773b6e998525d7900fa82670f00 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
ipsInstrFPU.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 77e85f367c4f69fb95a88419aba1eef2cbab6800 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete definition of CPRESTORE instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170660 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 5c5402564515ad87425af9881619545c096b84b9 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| c4889013553a4e407e110d1f76d9b6cf1396e702 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| cef95f702a5586781e5f812078a5c57f6f0e962b |
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
|
| 68fe665b9a878b4a19e005ad9a8c92c402ecd320 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy
physical register $r1 to $r0.
GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.
Original patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSEInstrInfo.cpp
|
| 2427773f2f18a2dd630428d7df927a5cdf4280f1 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Change the order of template parameters. Move the default parameters to
the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 0dad34a9bf850132e9ec84397f13604143c3aeff |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor shift immediate instructions. Separate encoding information
from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 23a3da0113600a2c3204f766cbc51d68a8ed4d94 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| c9e30ea42c428ca3ccf9d70a88c4171c6be71f41 |
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 759e3fa641d0ad01012d16d913015c9f69c8d2ab |
19-Dec-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove edis - the enhanced disassembler. Fixes PR14654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
isassembler/MipsDisassembler.cpp
akefile
|
| 95f475f2ecc5fd0f1db2f5c249723010abc5259e |
19-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
Add some missing Defs and Uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170493 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 2c3a4641a7785da78839caf574277df9cd93b52c |
16-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
This patch is needed to make c++ exceptions work for mips16.
Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.
If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.
The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.
In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.
This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.
lab1: ; this will cause the lower order bit to be added
lab2=. ; this will not cause the lower order bit to be added
In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.
To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.
For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX"
labels.
Mips overrides the debug label suffix from ":" to "=." .
This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.
Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170279 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCAsmInfo.cpp
|
| ed23fa8e55f5a58741c20c601410c2822d00f066 |
15-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
This code implements most of mips16 hardfloat as it is done by gcc.
In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.
I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.
The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170259 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| a61b17c18a67f1b3faef2f2108379c4337ce9bb7 |
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170104 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| ed185daba7432e9df717f0199336889784b10da3 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not copy GOT address to register $gp if the function being called has
internal linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170092 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| c567b1cd0d6bf973a21df4b5c8cae37e5e7518f8 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete all floating point instruction classes that are no longer used.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
ipsInstrFPU.td
ipsInstrFormats.td
|
| 5c3739927900af1bf5f5cdcbb3ebead2d89cd943 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point conditional move instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170080 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCondMov.td
ipsInstrFormats.td
|
| b573539c6b47d020ade2e41c0ff3afcd00f294f4 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point comparison instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170077 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 89828a6a563426edda0e30384997b2b24be6bb12 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point branch instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170076 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 2b1a50cfdb2db28605fc9834310890160c29be4f |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point indexed load and store instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170075 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| b2c68ddaaba55c417679d3ed466ebd403d991cec |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point multiply-add/sub instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170073 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 6f94eb3512ebc7b279451d26427153d9300a6a14 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point load and store instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170072 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| be9f72d2d8ab4a785cf788c5d9c5092b0fc02bfc |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of move from/to coprocessor instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170071 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 4b921416b4a702705a83a4288d217017512a7634 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of two register operand floating point instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170069 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 82fdad75f7efa9d15261068e1bb3691f10fb3d36 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of three register operand floating point instructions
and separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170066 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 10bd7264598a806aced15d0b7a3a5fc6803112a1 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move classes that do not belong in MipsInstrFormats.td into
MipsInstrFPU.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170061 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 2f3e06399a703a20f544a0029a11e9a484d4cead |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isCommutable flag in a more explicit way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170060 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
|
| 1c88a8d978e5cbcbd270f7a742bfe690ed798e0e |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170057 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
|
| 625cb5ac72f1e23e1dfbb9600a5183a9a072c74a |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove single-precision floating point instruction from multiclass
FFR2P_M.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170055 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| 0232064e6f85a7c8e3815fd7decceba5bba2af26 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move class IsCommutable into MipsInstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170054 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
|
| 6085780a91c722839b3f9f2dca33b974a083df82 |
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove single-precision floating point instructions from multiclasses
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170053 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrFormats.td
|
| de99993a301e895273084d3df45cdf54d2f2ef91 |
12-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix a memory leak bug report by NAKAMURA Takumi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170012 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.h
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 7d34267df63e23be1957f738de783c145febb7af |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 8163ca76f0b0d336c5436364ffb3b85be1162e7a |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| d181342eee9eed65e5428a33646288345cdbdd7a |
11-Dec-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
[CMake] Remove dependencies to intrinsics_gen I introduced in r169724.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169819 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/CMakeLists.txt
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| e8068692f924a1577075bd2d7b72b44820e0ffb2 |
10-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set HWEncoding field of registers. Use delete function
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsBaseInfo.h
CTargetDesc/MipsMCCodeEmitter.cpp
ipsAsmPrinter.cpp
ipsCodeEmitter.cpp
ipsRegisterInfo.td
|
| 60608b924da8b5c6681e9c113dfdfc4a0d95d278 |
10-Dec-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
[CMake] Update dependencies to intrinsics_gen corresponding to r169711.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169724 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/CMakeLists.txt
|
| 06180bf3f25f2a9828e4c39f63a883aaa6c9452d |
07-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the new MIBundleBuilder class in the Mips target.
This is the preferred way of creating bundled machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169585 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
ipsLongBranch.cpp
|
| f3c0c77bc34706cc3c2bbc5e4aaae984f52d01a7 |
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete nodes and instructions for dynamic alloca that are no longer in
use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169580 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsISelLowering.cpp
ipsInstrInfo.td
|
| 249330eadb9d1d4835d6b55146147840492e5d13 |
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Shorten predicate name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169579 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsCondMov.td
ipsInstrFPU.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| 64ed8e97f75b498a1ba13e08d6c633c75b7f05ec |
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unused sub-target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169578 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsSubtarget.cpp
ipsSubtarget.h
|
| ab9705f8fa48f1f00f159746139509faab919ee2 |
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove unnecessary predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169577 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsCondMov.td
ipsInstrInfo.td
|
| a1514e24cc24b050f53a12650e047799358833a1 |
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.h
ipsAsmPrinter.h
ipsMachineFunction.h
ipsSubtarget.h
ipsTargetMachine.h
|
| ff0b2cfa3b97e3aae384622464deeb7ab93bafc5 |
04-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Classic JIT is still being supported by MIPS, along with MCJIT.
This change adds endian-awareness to MipsJITInfo and emitWordLE in
MipsCodeEmitter has become emitWord now to support both endianness.
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169177 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
ipsJITInfo.cpp
ipsJITInfo.h
|
| 25752e7be73d53ded2643f90d4344463c2cbf222 |
03-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are dead
code. Removing it.
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169174 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
isassembler/MipsDisassembler.cpp
CTargetDesc/MipsMCTargetDesc.cpp
ips16FrameLowering.cpp
ips16InstrInfo.cpp
ips16RegisterInfo.cpp
ipsAsmPrinter.cpp
ipsCodeEmitter.cpp
ipsDelaySlotFiller.cpp
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsInstrInfo.cpp
ipsJITInfo.cpp
ipsLongBranch.cpp
ipsMCInstLower.cpp
ipsMachineFunction.cpp
ipsRegisterInfo.cpp
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
ipsSERegisterInfo.cpp
ipsTargetMachine.cpp
ipsTargetObjectFile.cpp
|
| 4334dd96a9e622fdcf2825a8f73a2d941d67be72 |
30-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.
Rationale:
1) This was the name in the comment block. ;]
2) It matches Clang's __has_feature naming convention.
3) It matches other compiler-feature-test conventions.
Sorry for the noise. =]
I've also switch the comment block to use a \brief tag and not duplicate
the name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168996 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 198ad916d736047f8a439f19dee25cee917df8a9 |
22-Nov-2012 |
Jack Carter <jcarter@mips.com> |
Mips direct object xgot support
This patch provides support for the MIPS relocations:
*) R_MIPS_GOT_HI16
*) R_MIPS_GOT_LO16
*) R_MIPS_CALL_HI16
*) R_MIPS_CALL_LO16
These are used for large GOT instruction sequences.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168471 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
|
| f09a03776dbbc882c9b15eeccb8ec847058fbfa0 |
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Generate big GOT code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
ips64InstrInfo.td
ipsISelLowering.cpp
ipsInstrInfo.td
ipsMCInstLower.cpp
|
| d43e06de594e734513eb4e24193eb2dd5288c0c4 |
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper
functions added in r168456.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168458 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 6b28b80791c742f4c561eeeae399338a8903dd6d |
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add helper functions that create nodes for computing address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168456 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 81784cb374d7e3cbcd86f19315052d30cb7c49f9 |
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add command line option "-mxgot".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168455 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 59be760f61d54e24bae70c4465021a6f0746d278 |
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] When a node which loads from a GOT is created, pass a MachinePointerInfo
referring to a GOT entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168453 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 26e6ad7b290abd4e5dcae1c6fbd5cae77a4beffe |
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add target operand flag enums for big GOT relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168450 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsBaseInfo.h
|
| 94e472832f30320d273f5630044c6bbd626e9949 |
17-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Initial implementation of MipsTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| a032dbd62f46a40b2cf759ce0dd0ebd41ef0614c |
16-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 0301bc54ad23c9dff0370dffaf6eb3eabba42cc4 |
15-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add predicate HasFPIdx for floating-point indexed load instruction
support and use it in place of HasMips32r2Or64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsISelDAGToDAG.cpp
ipsInstrFPU.td
ipsInstrInfo.td
ipsSubtarget.cpp
ipsSubtarget.h
|
| c984657c7461ce28b25ca91fdc6caaf2860127fd |
15-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add assertions in MipsLongBranch which check the size of basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168078 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| e90a3bcae1cd936aa760cffe5607266279b210d1 |
07-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 7085221a593ac5cb2478a4f81e0f7212616a9afb |
07-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete MipsFunctionInfo::NextStackOffset. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167546 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsMachineFunction.h
|
| 3c77033a902af3185aa9a759c4a845fa359a475c |
03-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set flag neverHasSideEffects flag on floating point conversion
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167348 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFPU.td
ipsInstrInfo.td
|
| 3c9c1ab7b7549dfaf22456d89bd241a5e8dfc0a4 |
03-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set flag isAsCheapAsAMove flag on instruction LUi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167345 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 11a45c214c26bdc49ef58c0eb214df5200867cee |
03-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| da15a0ed4cd74f767cc124b65b7b7d9482969318 |
03-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not reserve all 64-bit registers, but only the ones which need to be
reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly
returns an empty set of integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167335 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
|
| 5c87b732f2bb25e43b8faf90f43bb38d607fc8ec |
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use register number instead of name to print register $AT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167315 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| 265f191b57a4e359bc44a51602c9d2a4ee6af96b |
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add function MipsFrameLowering::estimateStackSize.
This function estimates stack size and will be called before
PrologEpilogInserter scans the callee-saved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167313 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
ipsFrameLowering.h
|
| 294166d541fd634fea09fb1fe48457536ef43ed0 |
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the size
of the incoming argument area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167312 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsMachineFunction.h
|
| 173192fa71a45ee87479c0eb7753bf116bce36b8 |
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directive
"set .noat" so that the assembler doesn't issue warnings when register $AT is
used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167310 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsLongBranch.cpp
ipsMachineFunction.h
ipsSEInstrInfo.cpp
ipsSERegisterInfo.cpp
|
| 497204a94b6ebe94b0cc9b9ef11eee7baf1df53b |
31-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
re-materialization of immediate loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167153 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 9441125d636dee246acf9cb6c8f264edda92c335 |
31-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16InstrInfo.td
ips16RegisterInfo.cpp
ips16RegisterInfo.h
|
| 2f34d754d00fbe2e4a98762d71d0fae5f4b0cf45 |
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Allow tail-call optimization for vararg functions and functions which
use the caller's stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167048 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| b33b34a7dc447cf52702b8892c9829344e81f73a |
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add code for saving formal argument information to MipsFunctionInfo. This
information will be used by IsEligibleForTailCallOptimization to determine
whether a call can be tail-call optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167043 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsMachineFunction.h
|
| 7d71209912bb55856f34df7013382e6dd310983b |
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of function MipsTargetLowering::passArgOnStack which emits nodes
for passing a function call argument on a stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167041 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| e7b406d7ac150189522f0a139f1a2f76bde2cb26 |
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not do tail-call optimization if target is mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167039 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| c09856b5357af621fcb84a7b2b6bfbf630c244ef |
30-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Change mips16 delay slot jumps to non delay slot forms by default.
We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166990 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| 576b1dbbef3c85df7245ebd9c1064c2083a4e4a1 |
29-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement patterns for extloadi8 and extloadi16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166960 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 8834a20d5dcb905d454321bb0668f1e086563212 |
29-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Expand all atomic ops for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166935 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 3a9f4568fbb974844afacd12ab9b62e8844fd8ad |
29-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement brind operator for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166903 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 0d91c0b519e0053931bf9502ebeaf44d397812f0 |
28-Oct-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove TargetELFWriterInfo.
All the credit goes to Jan Voung for noticing it was dead!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ipsELFWriterInfo.cpp
ipsELFWriterInfo.h
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5 |
28-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.
The Mips16InstrInfo.td has been updated to use addr16 instead of addr.
The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16InstrInfo.td
ips16RegisterInfo.cpp
ipsISelDAGToDAG.cpp
ipsMachineFunction.cpp
ipsMachineFunction.h
ipsRegisterInfo.cpp
|
| 7797e8f9019d304e394a6ad3bf72a200473d0747 |
27-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement MipsHi for mips16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166852 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 21a9a98b77c48fb5084d3ef470083704d13c3929 |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not tail-call optimize vararg functions or functions with byval
arguments.
This is rather conservative and should be fixed later to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166851 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 4618e0b574bf879d062a39b5867d9c314a4639e0 |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the
previous iteration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166850 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| fe30a9be40a6bc22ccfab96915f4a71966f53023 |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Use the methods and classes that were added to simplify LowerCall and
LowerFormalArguments in MipsTargetLowering.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166846 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCallingConv.td
ipsISelLowering.cpp
|
| f084847373210540f345698295af333834493322 |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers
of vararg functions back to the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166844 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| db40edeb11f4f97c8de5428a84346834deaa2a47 |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add method MipsTargetLowering::passByValArg.
This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166843 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| eb98ae46bca786f033f8f4ab5f89ac046bd9f28e |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add method MipsTargetLowering::copyByValRegs.
This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166841 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 7887c90a7b80b994a51a2a3b88eef3643473e67c |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add class MipsCC which provides methods used to analyze formal and call
arguments and inquire about calling convention information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166840 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 3649255e14e369aa70bf1122cd5b0e1a92431662 |
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete MipsFunctionInfo::InArgFIRange.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166837 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsMachineFunction.h
|
| 25424154f4670c71150120416ff26300e46d393b |
27-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
implement mips16 tls global addr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166827 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| eac3b65b00883ff8edaf0fbc4b973d5a3a9c455d |
26-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166780 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| a81be80b0eabfc8b5e590a10471c66dadf6ded6f |
26-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement carry for subtract/add for mips16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166755 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsISelDAGToDAG.cpp
|
| 28a6214b59c0896695e478c57c485cc85f436528 |
26-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
implement large (>16 bit) constant loading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166749 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 4c5a6dab17c4a1ea3b970219a817d503ce108e86 |
25-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
implement mips16 patterns for select nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166721 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 6a020a71173a3ea7738a9df69982e85ddbfe0303 |
25-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for creating AsmRewrites in the target specific
AsmParser logic. To be used/tested in a subsequent commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166714 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 270483466124fe1e19d5439e958fef63cebd43cd |
24-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 2ef5bd3ba685704bc9c0d03654cb0b7fd1b071e6 |
24-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure sret argument is returned in register V0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166539 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 293e5d0e0a4abce2c79a6bde338325ca1df0edab |
23-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
implement setXX patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166459 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 30580cea43ac9108627e0616df6a30518ee7c0ef |
20-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use 64-bit registers to return an sret pointer if target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166344 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 2b861be96ef18174c201ce6a94c5130445bc5b40 |
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add code to do tail call optimization.
Currently, it is enabled only if option "enable-mips-tail-calls" is given and
all of the callee's arguments are passed in registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166342 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| e050902ca7b2976fff845b55d7fb2ccba9d37892 |
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix TAILCALL's operand node type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166341 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| e06ce4c2c48351d6d74ac2f81e72e17e5ec9fdc7 |
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166339 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsMachineFunction.h
|
| 01a75c46e3292c1a66b577b5a6b7510a1867afdd |
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add tail call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166338 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| 1f027135a89f6673d48e709ec5053809ab157bc3 |
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make the branch nodes used in jump instructions a template parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166337 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 58d1e3f72a61b5f8ace620c9e16baaecbb3f53f1 |
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add node and enum for mips tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166318 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrInfo.td
|
| cbd9a19b5d6ff93efa82c467508ede78b8af3bac |
19-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 3b9a911efcf280950f878a050728450423875639 |
18-Oct-2012 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang. I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.
This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 95a2bb4cdf48fb927c1c7c640012118c455b6727 |
18-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Add conditional branch instructions and their patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166134 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| 84125ca43c758fd21fdab2b05196e0df57c55c96 |
13-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Remove the MatchInstruction() function. Previously, this was
the interface between the front-end and the MC layer when parsing inline
assembly. Unfortunately, this is too deep into the parsing stack. Specifically,
we're unable to handle target-independent assembly (i.e., assembly directives,
labels, etc.). Note the MatchAndEmitInstruction() isn't the correct
abstraction either. I'll be exposing target-independent hooks shortly, so this
is really just a cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165858 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 6e006d3de882784527d4d9cc92b1a91f6773505e |
13-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Use the new API introduced in r165830 in lieu of the
MapAndConstraints vector. Also remove the unused Kind argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 7d90d4d709b9053f7214203c34b8be9dbd311ace |
12-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Div, Rem int/unsigned int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165783 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| aa5b393c69cf24d47a5727d15584f3daeba1aead |
11-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Expose move to/from coprocessor instructions in MIPS64 mode.
Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode. We should ensure that this is easy to
do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
|
| 6f9e66e1be19db4e88b0fda1ece0d2cd46de4064 |
11-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Add getters for the MIPS TargetTransform classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165670 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.h
|
| d140af6c2374e29ab29caef11d888a358717572c |
11-Oct-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unused member variable introduced in r165665.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165669 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.h
|
| e3d0e86919730784faaddcb5d9b0257c39b0804b |
11-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| a5971e8c004c588a8dfa90da49986af60620189e |
10-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Reorder some parts of the td file to by in alphabetical order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165590 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 97d9f081a92c18bb4fd1c069dccde7c99301150a |
10-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsTargetLowering::CanLowerReturn.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165585 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 2f68b311a1b0efb3cafeca3780f5c3d09a762a50 |
10-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Initial assembler implementation of Mips load address macro
This patch provides initial implementation of load address
macro instruction for Mips. We have implemented two kinds
of expansions with their variations depending on the size
of immediate operand:
1) load address with immediate value directly:
* la d,j => addiu d,$zero,j (for -32768 <= j <= 65535)
* la d,j => lui d,hi16(j)
ori d,d,lo16(j) (for any other 32 bit value of j)
2) load load address with register offset value
* la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535)
* la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j)
ori d,d,lo16(j)
addu d,d,s
This patch does not cover the case when the address is loaded
from the value of the label or function.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsInstrInfo.td
|
| 572e1bd109518f80b54d229de10699c4603944c3 |
09-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Improvements to MIPS64 assembler:
- Teach it about dadd[i] instructions and move pseudo-instruction
- Make it parse the register names correctly (for N32 / N64)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165506 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ips64InstrInfo.td
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ipsAsmPrinter.cpp
ipsCodeEmitter.cpp
ipsELFWriterInfo.cpp
ipsFrameLowering.cpp
ipsSEFrameLowering.cpp
ipsTargetMachine.cpp
ipsTargetMachine.h
ipsTargetObjectFile.cpp
|
| de3322746280b957d552cc5e69e121b38c07406c |
06-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Adding support for instructions mfc0, mfc2, mtc0, mtc2
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| 2490dc650895149423bb59538dc03ca352222702 |
06-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Minor changes based on post commit review:
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165350 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 10d5ff6b1dceec77c23cd200ef200e2e9dec4c85 |
06-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Minor changes based on post commit review:
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165346 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 9ba9d4d76bfa8de2b05cbce02a5a3ff7d46cb331 |
05-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add a few typedefs to simplify future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| dfb8dbb4fd97140aa9bf6b9dadbca25665144c09 |
05-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Patch for integer multiply, signed/unsigned, long/long long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165322 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
|
| 9d577c861414c28967d77c2a1edf64b68efdeaee |
04-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
ipsInstrFormats.td
ipsInstrInfo.td
|
| 30116cd2e24a4a2b6c2771ef2665d655de93b984 |
04-Oct-2012 |
Jack Carter <jcarter@mips.com> |
This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options
at - lets the assembler use the $at register for macros,
but generates warnings if the source program uses $at
noat - let source programs use $at without issuingwarnings.
noreorder - prevents the assembler from reordering machine
language instructions.
nomacro - causes the assembler to print a warning whenever
an assembler operation generates more than one
machine language instruction.
macro - lets the assembler generate multiple machine instructions
from a single assembler instruction
reorder - lets the assembler reorder machine language
instructions to improve performance
The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.
Following options are not implemented yet:
nomips16
nomicromips
move
nomove
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165194 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 42faefc11da326f10a4a52d72953318921d9e43d |
03-Oct-2012 |
Jack Carter <jcarter@mips.com> |
This patch moves from using a hard coded number (4)
for the number of bytes in a particular instruction
to using
const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
Desc.getSize()
This is necessary with the advent of 16 bit instructions with
mips16 and micromips. It is also puts Mips in compliance with
the other targets for getting instruction size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165171 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 8e71e617c9b1e42737ffd00984a5025ec90c734c |
03-Oct-2012 |
Jack Carter <jcarter@mips.com> |
The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands.
If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler.
This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically.
The test cases have been checked in for a number of weeks now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165067 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/CMakeLists.txt
CTargetDesc/MipsDirectObjLower.cpp
CTargetDesc/MipsDirectObjLower.h
CTargetDesc/MipsMCCodeEmitter.cpp
ipsAsmPrinter.cpp
ipsDirectObjLower.cpp
ipsDirectObjLower.h
|
| 22685876ed7231f32f7d1698c00acab22825b74c |
02-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add the convertToMapAndConstraints() function that is used to
map constraints and MCInst operands to inline asm operands. This replaces the
getMCInstOperandNum() function.
The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164979 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 93ba059e489fd8fdf3a87db638a7283e66942a31 |
28-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: other miscellaneous instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| e91ff1d135fb6b03e8bd9c8a09a67570bae583ad |
28-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: ADDUH.QB instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| c94a38ff1732b960a551c7c1a4c50ede5c4737b4 |
28-Sep-2012 |
Reed Kotler <rkotler@mips.com> |
1. Add load/store words from the stack
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
ipsRegisterInfo.td
|
| cb39aa05afd52f017869ce5399652223626da7b7 |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: ABSQ_S.PH instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| 23bb38f034a7ff5566c2cea6b69645f4ca40307f |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: SHLL.QB instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| 833f7a5c4b77796d1ad739b8d92d824612cd819e |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| 451b0e7b8a56457114d8989ac836163d82a1cf5e |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: CMPU.EQ.QB instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| a216401621bf23a672accdf6d2d1cf46ef97b4ee |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: ADDU.QB instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
|
| 01f7089bca51744226306e09db4954e3df02b3be |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 2df483efb3a3d99dd82eb88e13490ae464bf0e43 |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: all the remaining instructions which read or write accumulators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
|
| fd89e6ffdab95ae6b4568b8a4153064952f61ea6 |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: add support for extract-word instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
ipsDSPInstrInfo.td
ipsISelLowering.cpp
ipsISelLowering.h
|
| 5e69cef21bad39f796f8b2bee4117c04a10b0238 |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: add functions which decode DSP and accumulator registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| cc46fe591af10c193c17323547a3dd7cc00c925d |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: add code necessary for pseudo instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164747 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
ipsAsmPrinter.cpp
ipsAsmPrinter.h
ipsMCInstLower.h
|
| 7e105bcc3ab0e0e8ddc7617b37a9fe9cd1d0b1bf |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: add bitcast patterns between vectors and int.
No test cases. These patterns will get tested along with dsp intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
|
| 7509ec18d100206cd44790641e012aae35714212 |
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: add vector load/store patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
ipsInstrInfo.td
|
| b500e9249af1e1104c4a599d9eafc37c307172e2 |
26-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add case clauses for returning dsp accumulator encoding values in function
getMipsRegisterNumbering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164720 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsBaseInfo.h
|
| 81571d3e0f54d5b163f5d891c33918c4b84660ac |
26-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add DSP accumulator registers and register class. Remove hi/lo registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| c878f3899c01db796d72bab8ac5156c124eb30ca |
26-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164718 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
ipsMachineFunction.h
ipsSERegisterInfo.cpp
|
| 3757ff1a68b37e622ccd98ca8bb0c22c17ac6514 |
26-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Initialize boolean variables in MipsSubtarget's constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164642 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSubtarget.cpp
|
| 289b5d7f02a442cb849d3762a78796d3355b02fc |
26-Sep-2012 |
Reed Kotler <rkotler@mips.com> |
blank line for test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164640 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
|
| 2590c2e1e9e2f2a7f28672c10c2df55566238dfa |
25-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Rather then have a wrapper function, have tblgen instantiate the implementation.
Also remove an unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 00796a1b15a83247e19c2445a6ff7a31e72299a4 |
24-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Rather then have a wrapper function, have tblgen instantiate the implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| ef5fc952e8de9c76ff00cd7638ae85cf709264bd |
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: Add immediate leaves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164435 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrInfo.td
|
| 67032b27cddbb07134e128074bd23ae95384367c |
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: Add predicates and instruction template.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164434 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDSPInstrFormats.td
|
| b430cecc0eeaa3f916b396b9f5fdee04cf306658 |
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add MIPS DSP register classes. Set actions of DSP vector operations and override
TargetLowering's callback functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164431 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 6fad5e742d0213bdd68daa7d376387bcec80b5fd |
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
SelectionDAG node enums for MIPS DSP nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164430 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 1024f290d1c81dd23ec452455eff8589a4419032 |
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add MIPS accumulator and DSP control registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
ipsRegisterInfo.td
|
| a9adbf6df7116b08cef168d5b2315b82a95075c2 |
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add flags and feature bits for mips dsp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164428 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsSubtarget.h
|
| d717a066c6ddaff401b9259579b265eeafb83b6e |
22-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| b377635592a70e5c36d1c0788a71474e55b81f49 |
21-Sep-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164354 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
|
| 0fdf3b029b35f495d7261fe78737e434edc84758 |
21-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Properly save and restore RA and Mips16 callee save registers S0,S1
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164349 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16FrameLowering.h
ips16InstrInfo.td
|
| 37236515cfac7d60a9e1ee6f734618e6939db8c5 |
18-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r164051.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164150 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
|
| 536a88ad5bf160232205192a7ce72e50bfadbded |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.
Fixes PR11212.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsMCTargetDesc.h
|
| ff1547890a5af47c215bf7e1f1da85bae6aabe4d |
17-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make sure there is enough room for RA. getStackSize needs to be cleaned up but
we will do that when we implement the full save/restore.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164051 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
|
| dd100d831bb8062b64e7037d2bbc21bf20be4f45 |
15-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unused private fields to silence -Wunused-private-field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163973 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 5a7dd43f045f2f78adc81b497c5d78bd9da0884e |
15-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ips64InstrInfo.td
ipsCodeEmitter.cpp
ipsISelDAGToDAG.cpp
ipsInstrFPU.td
ipsInstrInfo.td
|
| f934d159ae6b57f05d8163265b9deaa29315d2e7 |
15-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Handled unaligned load/stores properly in Mips16
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163956 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| c5252da873d547a19069eaf9030fec203f128f66 |
14-Sep-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Fix Doxygen issues:
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
with the rest of the codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163902 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
|
| 99258f6755a253a8b864f63dcbe9d8cbfa09f560 |
14-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
mips16 fixes.
1. Add MoveR3216
2. Correct spelling for Move32R16
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163869 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.td
|
| e6ac7d69d3308d580a87ff3e3645f98e2bc565a5 |
13-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
mips16: When copying operands in a conditional branch instruction, allow for
immediate operands to be copied.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163811 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
|
| afc945b614a2bf99014d5820c8849451030ea82b |
13-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Misc.
1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163753 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 6c7ccaa3fd1d6e96d0bf922554b09d2b17c3b0e3 |
12-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 67c8978617c3bce9d07210f93f6c64c715f77695 |
12-Sep-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
|
| 68aeecc773d36c4be9adf32d1f09ec739574c880 |
11-Sep-2012 |
Stephen Hines <srhines@google.com> |
Merge up through LLVM r163557.
Updated Android.mk source files for Analysis, CodeGen, Target/Mips,
Transforms/Instrumentation, and Transforms/Utils.
Change-Id: I232a895e3ad9ec0c4a66f4308a11bb794b67940f
ndroid.mk
|
| 1c4ad5ef4fab105f0c8af7edd026e00502fb6279 |
11-Sep-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge-2012_09_10
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/Support/DynamicLibrary.cpp
lib/Support/LockFileManager.cpp
Change-Id: I91e94c3a7a76e19c688307c5a480a640a3bd2b7e
|
| 2de0572caec55e3779857cae0bbcd962af2e495d |
10-Sep-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove redundant semicolons which are null statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 1ac4587eb32e639576973b793d465c5d9577bef7 |
10-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make helper function static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163504 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 38539ebc2b55d2decec2322efd3360bf61f31da1 |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163383 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 04376ebe9f203213ef1eb4c69396fe280dc8c8b1 |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler aliased instruction support.
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.
These changes are in the instruction td file.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| acbea45573078631e116c2aa91e57d3a9cb2dde1 |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler intial directive support.
Actually these are just stubs for parsing the directives.
Semantic support will come later.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163364 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| f740d6e328bd10904b079e1ce6583f436d6c9817 |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler fpu instruction support.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
CTargetDesc/MipsBaseInfo.h
|
| 35e3aed169aa7fc9c7118f24e5e2a07e25bef512 |
07-Sep-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unused variable introduced by r163346.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163359 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 6b96c3f71fce6b0a7c380dfc3b7ebf22c40e804b |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler memory instruction support.
This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw
Test case included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| a7570a3d8686a1fe2075b5bee01650490fa52b26 |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
There are some Mips instructions that are lowered by the
assembler such as shifts greater than 32. In the case
of direct object, the code gen needs to do this lowering
since the assembler is not involved.
With the advent of the llvm-mc assembler, it also needs
to do the same lowering.
This patch makes that specific lowering code accessible
to both the direct object output and the assembler.
This patch does not affect generated output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163287 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ipsAsmPrinter.cpp
ipsDirectObjLower.cpp
ipsDirectObjLower.h
ipsMCInstLower.cpp
ipsMCInstLower.h
|
| ad51a4a5984a365d671ddfe9eaa23d2e12ee4281 |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific llvm assembler support for branch and jump instructions.
Test case included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsMCCodeEmitter.cpp
|
| ec65be84cd630d53233e7a37f0ef9d2303ac5153 |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific llvm assembler support for ALU instructions. This includes
register support. Test case included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163268 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 59324297650c12a8dccf1a7ad650a9e895fdc17e |
06-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Stop casting away const qualifier needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| fd91d8dd7e18107b35c7332b92d636420517e3cb |
05-Sep-2012 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix UseInitArray option for MIPS target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163193 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetObjectFile.cpp
|
| 5d637d7e93c1f6058c16b41b8ac7dd36c61b4a5c |
05-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix function name per coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 2cc97def7434345e399e4f5f3f2001d6d7a93c6f |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| efeaae8578ce9173a47f9e3fa5c44b90ae60c5ab |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163123 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 038f3e31276f8cc86d91d0e4513e1a3ddb8509ba |
03-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the
MCTargetAsmParser class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/MipsAsmParser.cpp
|
| 3185f9a2ea80afec30064b7cd095f82c31dc154e |
31-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsAsmPrinter.cpp
ipsMCInstLower.cpp
ipsMCInstLower.h
|
| 714313b4828cec98b086b54b356407540aa775c4 |
28-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsAsmPrinter.cpp
ipsMCInstLower.cpp
ipsMCInstLower.h
|
| 69dba7e20476ec0e64791e47b498ae3a69619f7d |
28-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into
dsll32 if the shift value is greater than 32.
For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 4fb08317af55c97f421047f0bdbfdd320ac76936 |
28-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Follow-up patch to r162731.
Fix a couple of bugs in mips' long branch pass.
This patch was supposed to be committed along with r162731, so I don't have a
new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162777 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| 273956d8c6eed86c8b4d616ecb86f7ff17e127d4 |
28-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| 1144af3c9b4da48cd581156e05b24261c8de366a |
25-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAnalyzeImmediate.cpp
|
| 16865d06128c266b5505cc21f5d086d18173408c |
24-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Disable Mips' delay slot filler when optimization level is O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 45d8dbc92d365e9c0a08ceb0bc7a9014e6064bdb |
24-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its
second operand is MipsISD::GPRel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
|
| ea47628cbafb48bf2a51554328a6dd77be40f4df |
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing SDNPSideEffect flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| d62cdbe700ab288e9ad447824066edb7d17167d9 |
23-Aug-2012 |
Stephen Hines <srhines@google.com> |
Add new files for Mips + fixups for merge to upstream r162314.
Change-Id: Ib545c0c991575c14b0b74e3b8fd4cc8c789b25d0
ndroid.mk
smParser/Android.mk
|
| 31675153bd2d7617db8cb6aeb58054934c7b9f73 |
24-Aug-2012 |
Stephen Hines <srhines@google.com> |
Merge branch 'upstream' into merge_2
Conflicts:
lib/Target/ARM/ARMCodeEmitter.cpp
Change-Id: I6702d340c733e9721499b5d85b13b96ad9c14eb5
|
| 71eab96bfd4d57a14105324cc0e0cac8eb3f7c8e |
23-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unused private field to silence build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162426 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16RegisterInfo.cpp
ips16RegisterInfo.h
|
| fc4eafa0f490bd06d8191a2f007514b9e3ce0387 |
23-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make function loadImmediate a member of MipsSEInstrInfo and change it to return
the temporary register that was used to load the immediate. Currently, it always
returns register $at, but this will change if, in the future, we decide to use
another register.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsSERegisterInfo.cpp
|
| 91a35f03da446009cd1de4cdabaa1cdec7e74e0c |
23-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add a member of type Mips16InstrInfo/MipsSEInstrInfo to class
Mips16RegisterInfo/MipsSERegisterInfo.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162413 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| 96601ca332ab388754ca4673be8973396fea2ddd |
22-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
ipsRegisterInfo.cpp
|
| e7338cd550a4ccde6796d2987b482ea9f0e239ef |
22-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.
This bug was originally reported by Carl Norum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162340 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsRegisterInfo.cpp
ipsSubtarget.cpp
ipsSubtarget.h
ipsTargetMachine.cpp
ipsTargetObjectFile.cpp
|
| 6522a9e04bcfa447299f4fd10ee9afffd5834a47 |
22-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
default.
Patch by Carl Norum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162339 91177308-0d34-0410-b5e6-96231b3b80d8
ipsDelaySlotFiller.cpp
|
| 101771ba4d9c2421f836069fcedf9ddc8a0c9dc7 |
22-Aug-2012 |
Jack Carter <jcarter@mips.com> |
For mips64 switch statements in subroutines could generate
within the codegen EK_GPRel64BlockAddress. This was not
supported for direct object output and resulted in an assertion.
This change adds support for EK_GPRel64BlockAddress for
direct object.
One fallout from this is to turn on rela relocations
for mips64 to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162334 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFObjectWriter.cpp
|
| b862f094b78e3176813903f63c0e78b6e0e7852b |
20-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix coding style violations in 162135 and 162136.
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162213 91177308-0d34-0410-b5e6-96231b3b80d8
ipsELFWriterInfo.cpp
ipsTargetMachine.h
|
| 8188955b2bcc4555432bfaeef6d1d0488bd76a06 |
18-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder initialization list to silence -Wreorder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162165 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
|
| 3028d38f6e55ae3808f97f7b5b0d7686f6483bdb |
17-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add MipsELFWriterInfo.{h,cpp}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162136 91177308-0d34-0410-b5e6-96231b3b80d8
ipsELFWriterInfo.cpp
ipsELFWriterInfo.h
|
| b889e0cd2fea4afee623d5be603b912b955a2eca |
17-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Correct MCJIT functionality for MIPS32 architecture.
No new tests are added.
All tests in ExecutionEngine/MCJIT that have been failing pass after this patch
is applied (when "make check" is done on a mips board).
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162135 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/MipsELFObjectWriter.cpp
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 72e9b6aeb48d9496bac9db8b02c88a618b464588 |
17-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
smParser/MipsAsmParser.cpp
MakeLists.txt
akefile
ips.td
ipsInstrFPU.td
ipsInstrInfo.td
ipsRegisterInfo.td
|
| bb2e1b581ada0b748d6626512094c9500544f600 |
16-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add Android ABI to Mips backend to handle functions returning vectors of four
floats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162008 91177308-0d34-0410-b5e6-96231b3b80d8
ips.td
ipsCallingConv.td
ipsSubtarget.h
|
| c77dddcca6c18e6c41446b5d252457c7a582d5ea |
15-Aug-2012 |
jeffhao <jeffhao@google.com> |
Fix mips disassembler makefile to build for mips, not arm.
Change-Id: I3a5491781ec580669f9af48f4d181571042fa4e7
isassembler/Android.mk
|
| fc1a161d76f5cc0204bed3bce3e27cf36ac76d22 |
14-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 69a0aa87f8d64895af082cb52c7ecee0f6021d20 |
10-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't modify MO while use_iterator is still pointing to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161626 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
|
| 8d7e5efcaa5a1625e9518d090697f08d6d1110d5 |
09-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Another 32 to 64 bit sign extension bug.
The fields in the td definition were switched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
|
| 5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88 |
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The define for 64 bit sign extension neglected to
initialize fields of the class that it used.
The result was nonsense code.
Before:
0000000000000000 <foo>:
0: 00441100 0x441100
4: 03e00008 jr ra
8: 00000000 nop
After:
0000000000000000 <foo>:
0: 00041000 sll v0,a0,0x0
4: 03e00008 jr ra
8: 00000000 nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
|
| e2245bab3ca29dc2142d8f254005f4ae7c40cde2 |
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Mips relocation R_MIPS_64 relocates a 64 bit double word.
I hit this in a very large program (spirit.cpp), but
have not figured out how to make a small make check
test for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161366 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
|
| 61de70d98e1f752d5482b775f08827f799f4a53b |
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
were using a class defined for 32 bit instructions and
thus the instruction was for addiu instead of daddiu.
This was corrected by adding the instruction opcode as a
field in the base class to be filled in by the defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsInstrInfo.td
|
| fc54d9e47a1276650f14f38e7d037c9b58c8dc2d |
06-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.
These 2 relocations gain access to the
highest and the second highest 16 bits
of a 64 bit object.
R_MIPS_HIGHER %higher(A+S)
The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ].
R_MIPS_HIGHEST %highest(A+S)
The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161348 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 24e79e55daa5d2812d2a5ea0a282ebe48ef465e6 |
04-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ips16RegisterInfo.cpp
|
| c3f0e98f40f1382870c679b6aef1c5d01540637f |
03-Aug-2012 |
Shih-wei Liao <sliao@google.com> |
Apply changes to migrate to LLVM-160668-20120724.
- Update Android.mk for removed files and new files.
- llvm-ld has been removed in upstream, so we remove it as well.
Change-Id: I613ada916156a43993d4bba9cae6dcb6bf40ed2f
ndroid.mk
nstPrinter/Android.mk
|
| 7744acd1ab73b3eec6f1449f47083abe3fb1b527 |
03-Aug-2012 |
Shih-wei Liao <sliao@google.com> |
Merge with LLVM upstream r160668 (Jul 24th 2012)
Conflicts:
include/llvm/Support/ELF.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/Support/Memory.cpp
lib/Transforms/Instrumentation/AddressSanitizer.cpp
Change-Id: Iddd658cf2eadc7165b2805b446d31af2c5c9917f
|
| af2662606745bdebaa2cb43096274ce3d33b665f |
02-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Move the code that creates instances of MipsInstrInfo and MipsFrameLowering out
of MipsTargetMachine.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
ips16FrameLowering.cpp
ips16InstrInfo.cpp
ipsFrameLowering.cpp
ipsFrameLowering.h
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
ipsTargetMachine.cpp
|
| bddf83614a5e32297458e96375c533d231a5cd37 |
02-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Set transient stack alignment in constructor of MipsFrameLowering and re-enable
test o32_cc_vararg.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161189 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.h
|
| c15ad8517719a525ac3b88b6c49b451160691eaa |
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsJITInfo::replaceMachineCodeForFunction.
No new test case is added.
This patch makes test JITTest.FunctionIsRecompiledAndRelinked pass on mips
platform.
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161098 91177308-0d34-0410-b5e6-96231b3b80d8
ipsJITInfo.cpp
|
| fa566d02cce05cf8ca8d334a67e5534b379eaa3d |
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161095 91177308-0d34-0410-b5e6-96231b3b80d8
ipsSERegisterInfo.cpp
|
| 71746220d3d1c3e8efba35038ac2ff14b4a4d3ae |
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsSEFrameLowering.cpp
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| 8589010e3d1d5a902992a5039cffa9d4116982c5 |
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips16InstrInfo.cpp
ips16InstrInfo.h
ips16RegisterInfo.cpp
ips16RegisterInfo.h
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsSERegisterInfo.cpp
ipsSERegisterInfo.h
|
| cdb3ba71ce550c5a41c84c3678225a39d6f0a414 |
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering and
MipsSEFrameLowering.
Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be
reserved if there is a call with a large call frame or there are variable sized
objects on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161090 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
ips16FrameLowering.cpp
ips16FrameLowering.h
ipsFrameLowering.cpp
ipsFrameLowering.h
ipsSEFrameLowering.cpp
ipsSEFrameLowering.h
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| d5cfc0172cd50b198484ef6bbdeee523f3d205bb |
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add Mips16InstrInfo.cpp and MipsSEInstrInfo.cpp to CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161083 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),
and MipsSEInstrInfo (for mips32/64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.cpp
ips16InstrInfo.h
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsLongBranch.cpp
ipsSEInstrInfo.cpp
ipsSEInstrInfo.h
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| b4f921b1f0ae34d6cfda6034a7d32c73b0738351 |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete mips64 target machine classes. mips target machines can be used in place
of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161080 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
ipsTargetMachine.h
|
| 1d53f1bbab0573289a9856b7da5e9977cad848d4 |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Let PEI::calculateFrameObjectOffsets compute the final stack size rather than
computing it in MipsFrameLowering::emitPrologue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161078 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
ipsFrameLowering.h
|
| 1d165f1c252d1541b4788bf81092a9299cc764e5 |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161076 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
ipsMachineFunction.h
ipsRegisterInfo.cpp
|
| 603f69dc2c69ac3f4040e125febd3925dec2bcb2 |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161071 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsInstrFPU.td
ipsInstrFormats.td
ipsInstrInfo.td
|
| c4388d41994dc7e4492392f0c57c7b281ff165e6 |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Change name of class MipsInst to InstSE to distinguish it from mips16's
instruction class. SE stands for standard encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161069 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrFormats.td
ipsInstrInfo.td
|
| e2d529ac1111f153628a9c5c654f4a514e841b47 |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
When store nodes or memcpy nodes are created to copy the function call
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161068 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
ipsISelLowering.cpp
|
| 36bcc11236af961ff94820bf9817ecb4f98ace7e |
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsInstrFPU.td
|
| 480eeb54315e35b9d18213c2d56d2166e154b62d |
27-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Pass the correct call frame size to callseq_start node. This is needed to
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160841 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| e11246c64eb8ea3da0060be4ddb9596c8cc04439 |
26-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix call setup for PIC.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsISelLowering.cpp
|
| de4a1274706d7449870dac5bed05d27a6772d4ed |
25-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Eliminate the stack slot used to save the global base register.
The long branch pass (fixed in r160601) no longer uses the global base register
to compute addresses of branch destinations, so it is not necessary to reserve
a slot on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160703 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsMachineFunction.h
ipsRegisterInfo.cpp
|
| b57134523c87ee3e115fca41f58d73cb66046146 |
24-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix function MipsCodeEmitter::emitExternalSymbolAddress to pass test
ExecutionEngine/test-fp.ll.
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160653 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| 3ee306cbc0a295409c464ffaad5ef694de8eb09a |
24-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add basic ability to setup call frame, and make procedure calls.
Hello world will compile and execute with this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrFormats.td
ips16InstrInfo.td
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsMachineFunction.cpp
|
| ec5e97f5c874a82aa995cffee8c5592c6689ffb4 |
23-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add comment for relocations MO_HIGHER and HIGHEST in MipsBaseInfo.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160636 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsBaseInfo.h
|
| 60287963c7505180500d63b1c1b90f0f4b337430 |
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix Mips long branch pass.
This pass no longer requires that the global pointer value be saved to the
stack or register since it uses bal instruction to compute branch distance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160601 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
ipsLongBranch.cpp
|
| b22c9289b0dd8255f63038e9bb8229111eb082ae |
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add HIGHER and HIGHEST relocations to Mips backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160599 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
CTargetDesc/MipsBaseInfo.h
ipsMCInstLower.cpp
|
| fef904d0e824a2c587f8c1063b6c4fbf47fec898 |
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrFormats.td
ips16InstrInfo.td
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsMachineFunction.cpp
|
| b7dd9fc678ab4b4c57d333cd9940b0e0d7952ea6 |
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
Test case will be added later when long branch patch is checked in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrFormats.td
ips16InstrInfo.td
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsMachineFunction.cpp
|
| a0f14afee16ca976fef79c64df9a678e7f26cf43 |
18-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific inline asm operand modifier 'M':
Print the high order register of a double word register operand.
In 32 bit mode, a 64 bit double word integer will be represented
by 2 32 bit registers. This modifier causes the high order register
to be used in the asm expression. It is useful if you are using
doubles in assembler and continue to control register to variable
relationships.
This patch also fixes a related bug in a previous patch:
case 'D': // Second part of a double word register operand
case 'L': // Low order register of a double word register operand
case 'M': // High order register of a double word register operand
I got 'D' and 'M' confused. The second part of a double word operand
will only match 'M' for one of the endianesses. I had 'L' and 'D'
be the opposite twins when 'L' and 'M' are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| e882accb7a0e348bc86cca969e94e4c61581a4c8 |
18-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160403 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrFormats.td
ips16InstrInfo.td
|
| e035f65b16956cdb7ba29e741b7e3c04a8ce4d24 |
16-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63
Here is a description of DSLL:
Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits
Description: GPR[rd] <- GPR[rt] << (sa+32)
The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.
This patch implements the direct object output of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsAsmPrinter.cpp
ipsMCInstLower.cpp
ipsMCInstLower.h
|
| 68c10a2ff74fe882cfd789983b2d0f12e42fb0ec |
13-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove variable_ops from call instructions in most targets.
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsInstrInfo.td
|
| fd506efec628819f7e6fad8016a9dbb5d8612b8b |
13-Jul-2012 |
Jack Carter <jcarter@mips.com> |
The Mips specific relocation R_MIPS_GOT_DISP
is used in cases where global symbols are
directly represented in the GOT and we use an
offset into the global offset table.
This patch adds direct object support for R_MIPS_GOT_DISP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160183 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 1d82115042c81793cc3d807a8136f7f0f475f083 |
12-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Patch for Mips direct object generation.
When WriteFragmentData() case FT_align called
Asm.getBackend().writeNopData() is called, nothing
is done since Mips implementation of writeNopData just
returned "true".
For some reason this has not caused problems in 32 bit
mode, but in 64 bit mode it caused an assert when processing
multiple function units.
The test case included will assert without this patch. It
runs twice with different flags to prevent false positives
due to changes in code generation over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
|
| 9a1199459d54b7b3cbe444480ae75d286e362d01 |
11-Jul-2012 |
Jack Carter <jcarter@mips.com> |
This change removes an "initialization" warning.
Even though variable in question could not
be initialized before use, the code was such that
the compiler had no way of knowing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| f9fa3d8b872639d494481b43bee158c4359fc626 |
11-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In register classes in MipsRegisterInfo.td, list the registers in ascending
order of binary encoding.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.td
|
| 3fef29d88100881e7a52e570c30052e0d44c62ee |
11-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| ba584fe8feb840a82ad5966cb9eca6df0eeaafc2 |
11-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower RETURNADDR node in Mips backend.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
ipsISelLowering.cpp
ipsISelLowering.h
|
| bb78930489aceab797eecffe6771c6e52ff0c80c |
11-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2 |
10-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make register Mips::RA allocatable if not in mips16 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ips64InstrInfo.td
ipsFrameLowering.cpp
ipsFrameLowering.h
ipsISelLowering.cpp
ipsInstrInfo.cpp
ipsInstrInfo.h
ipsInstrInfo.td
ipsRegisterInfo.cpp
|
| 241b77fa451f8076e47c37212028454ad52ece15 |
09-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Reapply r158846.
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
|
| 63d10fbc89c02758cd91e3b53749e55c2bd0cf65 |
06-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
revert r159851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| e32cc0d5456eb7beb4030f0c0205c724a485ff31 |
06-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Reapply r158846.
Include file MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| 020f07f571fd1ae060becb2ecf8da2b220a9d47d |
06-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Changes per review of commit 159787
Mips specific inline asm operand modifier D.
Comment changes and predicate change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 244a84ee57cc73509a0e85cc92585cb567d0b72c |
06-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific inline asm operand modifier D.
Print the second half of a double word operand.
The include list was cleaned up a bit as well.
Also the test case was modified to test for both
big and little patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| a7e4558ec861145032865edcf56400be7558c2f8 |
05-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Enclose instruction rdhwr with directives, which are needed when target is
mips32 rev1 (the directives are emitted when target is mips32r2 too).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159770 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/MipsInstPrinter.cpp
|
| 10de025a67aa37112d5d4cd703925a7c1996422a |
03-Jul-2012 |
Jack Carter <jcarter@mips.com> |
mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 80c1b38eff2fb3200cdddb1ef6641d64de8496a8 |
03-Jul-2012 |
Eric Christopher <echristo@apple.com> |
Revert " mips32 long long register inline asm constraint support." as
it appears to be breaking the bots.
This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 1b055ce320fa13f6f1ac81670d11b45e01f79876 |
03-Jul-2012 |
Jack Carter <jcarter@mips.com> |
mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 39ae36337f87b1530c1680ae561c952c827d6e88 |
02-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Pass the correct ELFOSABI enumeration to the MipsELFObjectWriter constructor
Contributer: Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159574 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
|
| 564fbf6aff8fb95646a1290078a37c2d4dbe629f |
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add all codegen passes to the PassManager via TargetPassConfig.
This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
ipsTargetMachine.cpp
|
| f38ad8efd0f313a51307f700a2699ae57608ddd4 |
28-Jun-2012 |
Jack Carter <jcarter@mips.com> |
Changed the formatting sequence of a curly brace to
the comment per code review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159376 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 7c3cd4d24edf125bafc9aa258fc8e8ae1b00a4df |
28-Jun-2012 |
Jack Carter <jcarter@mips.com> |
The Mips specific inline asm operand modifier 'z' has the
following description in the gnu sources:
Print $0 if operand is zero otherwise print the op normally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159324 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 0bcbd1df7a204e1e512f1a27066d725309de1b13 |
28-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.
The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsRegisterInfo.cpp
|
| a6d6ef6dac9407840aadf1e657ba58989946173e |
28-Jun-2012 |
Jack Carter <jcarter@mips.com> |
This allows hello world to be compiled for Mips 64 direct object.
It takes advantage of r159299 which introduces relocation support for N64.
elf-dump needed to be upgraded to support N64 relocations as well.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159302 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| 0140e55393c4403ab240c386501cdc5e438dcc0e |
28-Jun-2012 |
Jack Carter <jcarter@mips.com> |
This allows hello world to be compiled for Mips 64 direct object.
It takes advantage of r159299 which introduces relocation support for N64.
elf-dump needed to be upgraded to support N64 relocations as well.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159301 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsFixupKinds.h
CTargetDesc/MipsMCCodeEmitter.cpp
|
| 93ee286e8d949147f8df7f093c9bd8529a99102d |
28-Jun-2012 |
Jack Carter <jcarter@mips.com> |
The ELF relocation record format is different for N64
which many Mips 64 ABIs use than for O64 which many
if not all other target ABIs use.
Most architectures have the following 64 bit relocation record format:
typedef struct
{
Elf64_Addr r_offset; /* Address of reference */
Elf64_Xword r_info; /* Symbol index and type of relocation */
} Elf64_Rel;
typedef struct
{
Elf64_Addr r_offset;
Elf64_Xword r_info;
Elf64_Sxword r_addend;
} Elf64_Rela;
Whereas N64 has the following format:
typedef struct
{
Elf64_Addr r_offset;/* Address of reference */
Elf64_Word r_sym; /* Symbol index */
Elf64_Byte r_ssym; /* Special symbol */
Elf64_Byte r_type3; /* Relocation type */
Elf64_Byte r_type2; /* Relocation type */
Elf64_Byte r_type; /* Relocation type */
} Elf64_Rel;
typedef struct
{
Elf64_Addr r_offset;/* Address of reference */
Elf64_Word r_sym; /* Symbol index */
Elf64_Byte r_ssym; /* Special symbol */
Elf64_Byte r_type3; /* Relocation type */
Elf64_Byte r_type2; /* Relocation type */
Elf64_Byte r_type; /* Relocation type */
Elf64_Sxword r_addend;
} Elf64_Rela;
The structure is the same size, but the r_info data element
is now 5 separate elements. Besides the content aspects,
endian byte reordering will be different for the area with
each element being endianized separately.
I treat this as generic and continue to pass r_type as
an integer masking and unmasking the byte sized N64
values for N64 mode. I've implemented this and it causes no
affect on other current targets.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159299 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsELFObjectWriter.cpp
|
| e246b52d2b02753a0064fb7e984148fff55d2872 |
27-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
|
| 4782a6e06ad4c6227831b70bb76165bc7b14bff3 |
27-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bug in computation of stack size in MipsFrameLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159240 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
|
| d5c407d2d01ff8797c29343e4da5f765fe52fb5f |
24-Jun-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3 |
21-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
1. fix null program output after some other changes
2. re-enable null.ll test
3. fix some minor style violations
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
ips16InstrInfo.td
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
|
| d5e11ad51a3966c0b80ce2119946cd1aa3558aec |
21-Jun-2012 |
Jack Carter <jcarter@mips.com> |
The inline asm operand modifier 'c' is suppose
to be generic across architectures. It has the
following description in the gnu sources:
Substitute immediate value without immediate syntax
Several Architectures such as x86 have local implementations
of operand modifier 'c' which go beyond the above description
slightly. To make use of the generic modifiers without overriding
local implementation one can make a call to the base class method
for AsmPrinter::PrintAsmOperand() in the locally derived method's
"default" case in the switch statement. That way if it is already
defined locally the generic version will never get called.
This change is needed when test/CodeGen/generic/asm-large-immediate.ll
failed on a native Mips board. The test was assuming a generic
implementation was in place.
Affected files:
lib/Target/Mips/MipsAsmPrinter.cpp:
Changed the default case to call the base method.
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
Added 'c' to the switch cases.
test/CodeGen/Mips/asm-large-immediate.ll
Mips compiled version of the generic one
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158925 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
|
| 02a227af91889d39f5e811e2e27ecce8144499eb |
20-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r158846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| b66510f309077d9f616462a1696f712236ce5a22 |
20-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MipsDisassembler.cpp
ipsRegisterInfo.td
|
| bde801b2a7e20f3de62cacc3ef643cf0ed6e2c27 |
19-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make MipsLongBranch::runOnMachineFunction return true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158702 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| 226ae40fc234f7deb7a605e844a84b12b2fbb8d6 |
19-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Use MachineBasicBlock::instr_iterator instead of MachineBasicBlock::iterator in
MipsCodeEmitter.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158701 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCodeEmitter.cpp
|
| 9d58f935bc95ab3f55936c7a67ff975c3d51cf75 |
16-Jun-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Mips/AsmParser/CMakeLists.txt: Fix dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158602 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
|
| 864f66085cd9543070ef01b9f7371c110ecd7898 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix coding style violations. Remove white spaces and tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/MipsAsmBackend.cpp
CTargetDesc/MipsELFObjectWriter.cpp
CTargetDesc/MipsMCCodeEmitter.cpp
ipsAsmPrinter.cpp
ipsDelaySlotFiller.cpp
ipsFrameLowering.cpp
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
ipsISelLowering.h
ipsInstrInfo.cpp
ipsJITInfo.cpp
ipsJITInfo.h
ipsMCInstLower.cpp
ipsMCInstLower.h
ipsRegisterInfo.cpp
ipsRegisterInfo.h
ipsSubtarget.cpp
ipsTargetMachine.h
|
| 14180454726bbef6bf5041ae19736933617b51dd |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
1. introduce MipsPat in place of Pat in order to exclude those from
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
ips64InstrInfo.td
ipsCondMov.td
ipsInstrFPU.td
ipsInstrInfo.td
|
| f1ece226125c9e8b0d0311cab7266391743da29b |
14-Jun-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsLongBranch.cpp: Tweak llvm::next() to appease msvc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158446 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| f4f60cbe46989f6f1b7fac97aafa3466ea92668a |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix Mips/CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158437 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a32ccf92c1d53e0f16d2f29ad1fae75c3aa013a0 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add file MipsLongBranch.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158436 91177308-0d34-0410-b5e6-96231b3b80d8
ipsLongBranch.cpp
|
| 63b37f122d592c7451090ea32281686de967fcd4 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove code in MipsAsmPrinter and MipsMCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158434 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsMCInstLower.cpp
ipsMCInstLower.h
|
| 9e97587e022ac38258cd59339b4bae66894f9bfb |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add long branch expansion pass for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158433 91177308-0d34-0410-b5e6-96231b3b80d8
ips.h
ipsTargetMachine.cpp
|
| 91625aab6057c46cb167f7ac4a487fe02993acb1 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add AT to the list of registers clobbered by branches so that it is available
as a scratch register when they are expanded to long branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158432 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.td
|
| c56a7bb0515bee54a904af529dbb0ee11ff34591 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediate
to load an immediate that does not fit into 16-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158431 91177308-0d34-0410-b5e6-96231b3b80d8
ipsRegisterInfo.cpp
|
| 84e09287cba5c29fc04d9963ace3165675d0b3fa |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediate
to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158430 91177308-0d34-0410-b5e6-96231b3b80d8
ipsFrameLowering.cpp
|
| d4b48b283c3939962f0cd3c17aedc40209d82b1a |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to
compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158429 91177308-0d34-0410-b5e6-96231b3b80d8
ipsInstrInfo.cpp
ipsInstrInfo.h
|
| 4654e58a64b9d9b5eb93befc74ca7cfecaf52ce9 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.
Long-branches need access to the global base register to get the destination
address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158428 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
|
| a76220a40c1fcb0aa986a2ea2c129b7549e84c3e |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add methods to MipsFunctionInfo for initializing and accessing the stack frame
object for the global base register.
This is the first of a series of patches which implements long branch expansion
for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158427 91177308-0d34-0410-b5e6-96231b3b80d8
ipsMachineFunction.h
|
| 158413930f25ecdd0902e1cc11bb8dc3683b94f8 |
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Bundle jump/branch instructions with the instructions in the delay slot in
delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.
This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158426 91177308-0d34-0410-b5e6-96231b3b80d8
ipsAsmPrinter.cpp
ipsDelaySlotFiller.cpp
|
| 8782707f5074ab3951eb6424394bc8d2a2fa584a |
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelDAGToDAG.cpp
ipsISelLowering.cpp
|
| e193b325837bee5f9a848a16077a6e156fe88fba |
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158414 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
ipsISelLowering.h
|
| 2bd7e532b49cb461f7e16acb01124b56aa169844 |
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158413 91177308-0d34-0410-b5e6-96231b3b80d8
ipsISelLowering.cpp
|
| 777a1202852ae3b9466c815b7e2463da3ba2f669 |
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement fastcc calling convention for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8
ipsCallingConv.td
ipsISelLowering.cpp
|
| 36c58aa4d6957a4ca3800c47fa241acc59d676c8 |
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Clean up trailing blanks in Mips16InstrFormats.td
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158382 91177308-0d34-0410-b5e6-96231b3b80d8
ips16 |