| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 1703a714954f9ef0c32415423e2a1e15b152e711 |
|
15-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range.
Since there is not direct object emitter at this time, it does not
have any material affect because the assembler sorts this out. But we
need to know for the actual constant island work. We track the difference
by putting # 16 inst in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 6c242d385b44d063a8a9d4690e5a9d8fdd72ef35 |
|
13-Nov-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Mips16InstrInfo.cpp: Use <cctype> instead of <ctype.h>
Also, prune <stdlib.h>, seems stray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 4df21b14675954ba951ad118d1dc4a4021650078 |
|
13-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Allow the code which returns the length for inline assembler to know
specifically about the .space directive. This allows us to force large
blocks of code to appear in test cases for things like constant islands
without having to make giant test cases to force things like long
branches to take effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| c6d4d667a8a56b341fac949153ec5939857445df |
|
12-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Change the default branch instruction to be the 16 bit variety for mips16.
This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 1edd1a336a79c4cb804d32cb492738549154c69c |
|
18-Aug-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove unused stdio.h includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| cbaf6d0cc3d3f363f269346817a90d3cbc8d1084 |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename HIRegs and LORegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 1858786285139b87961d9ca08de91dcd59364afb |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 8a7f9de9d42e5817167e374dd61408dcac31a102 |
|
04-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Clean up code for Mips16 large frame handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 41e632d9e1a55d36cb08b0551ad82a13d9137a5e |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 6daba286836e6fb2351e7ebc248e18a5c80e8a31 |
|
13-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename functions. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| c713e996d305df99cc7fc58c9d8dc1f5fa00518d |
|
29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| de89ecd011c453108c7641f44360f3a93af90206 |
|
25-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 29cb2591f9f7ec948e7b0e719b1db6cef99010d0 |
|
25-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make psuedo FEXT_T8I816_ins into a custom emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 459d35cb7975804048684261f2358eedbd2209c1 |
|
24-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make psuedo FEXT_T8I816_ins a custom inserter. It should be expanded
as early as possible; which means during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 65692c809efa46337bf80f12b1795e785a6e7207 |
|
20-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 8a20844e277d1f51600134589aeb9ca88d9ca25d |
|
19-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| f80167520740cbd9b73ead4fa524533532c5538e |
|
19-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| bb01b3cb936f110fc20700b4c4447e3e7214cab3 |
|
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 139748f1c180d4f2d55f31b321e9cfe87b06eb64 |
|
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| dabfebb5c61e49ab23c5828953506d965bcf7401 |
|
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudo/macro BteqzT8SltX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| a8601bb4ffc5a3d7668cfadcd884e5400c526231 |
|
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand macro/pseudo BteqzT8CmpX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| da4afa72f7cbe2801f3876eda33416aa3ba42987 |
|
18-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 2de893210b0d4178edb4e3f2a965d57e97410341 |
|
16-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
One more try to make this look nice. I have lots of pseudo lowering
as well as 16/32 bit variants to do and so I want this to look nice
when I do it. I've been experimenting with this. No new test cases
are needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 6a0da011e42e553d497fce2059f43401e854b99d |
|
16-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Use a different scheme to chose 16/32 variants. This scheme is more
consistent with how BuildMI works. No new tests needed. All should work
the same as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 6b9d4617800d9450825f8a4b122a9aeb76f2795f |
|
13-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 61b97b8c1721ba45e5c10ca307ceebe1efdf72a9 |
|
08-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| e11dda8631f1e65417971ee0c2f7a661fc7d0fd7 |
|
19-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and
blank spaces at end of lines.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| cef95f702a5586781e5f812078a5c57f6f0e962b |
|
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 9441125d636dee246acf9cb6c8f264edda92c335 |
|
31-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| c09856b5357af621fcb84a7b2b6bfbf630c244ef |
|
30-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Change mips16 delay slot jumps to non delay slot forms by default.
We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 95a2bb4cdf48fb927c1c7c640012118c455b6727 |
|
18-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Add conditional branch instructions and their patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 7d90d4d709b9053f7214203c34b8be9dbd311ace |
|
12-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Div, Rem int/unsigned int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| c94a38ff1732b960a551c7c1a4c50ede5c4737b4 |
|
28-Sep-2012 |
Reed Kotler <rkotler@mips.com> |
1. Add load/store words from the stack
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 99258f6755a253a8b864f63dcbe9d8cbfa09f560 |
|
14-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
mips16 fixes.
1. Add MoveR3216
2. Correct spelling for Move32R16
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 71eab96bfd4d57a14105324cc0e0cac8eb3f7c8e |
|
23-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unused private field to silence build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| af2662606745bdebaa2cb43096274ce3d33b665f |
|
02-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Move the code that creates instances of MipsInstrInfo and MipsFrameLowering out
of MipsTargetMachine.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 8589010e3d1d5a902992a5039cffa9d4116982c5 |
|
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|
| 0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),
and MipsSEInstrInfo (for mips32/64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
|