| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 5c042162beb3c2dd556e00aab84c4278a69cd5b1 |
|
04-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1aaf43c2a2ec0fd4c8dbfe56558237219c5f8af7 |
|
29-Oct-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2ef99c5dff1ab9612f2d65e38f725d809672d2fd |
|
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| adb1297d49dd345821d7aa91057a0b22e6209a16 |
|
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename isel nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 243702b95a471ffb7d2374dfad3d7f8b11bee7e7 |
|
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1abf0afdd4d8e9d58518a878f30b9eede81303cc |
|
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of instruction "drotr32" (double rotate right plus 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 69f8e0935af16622ca13d26e6a66464d3c1f3da4 |
|
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 77e1ebd18fc558620b97fe38f3ebbf825533655f |
|
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set instruction itineraries of loads, stores and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| bf19dba2d4c7927832d3037c15e0101afb730415 |
|
28-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up definitions of move word from/to coprocessor instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c89cb45ecb861aa599a8b1c735b0ce4cd73e1397 |
|
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove predicates that were incorrectly or unnecessarily added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| a98a486ad194c38293efcc5359d6ed2493f950dc |
|
20-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| cbaf6d0cc3d3f363f269346817a90d3cbc8d1084 |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename HIRegs and LORegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 491d04969d9f29ed891c73238648853954ba4f81 |
|
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 94a88c49b0e87ee8c911669ff6c6bbd31b912542 |
|
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete register class HWRegs64.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1858786285139b87961d9ca08de91dcd59364afb |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 6b034bb3ae3f6e1f3831bfc24f90e84b9578944c |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
instructions defined in MipsInstrInfo.td as codegen-only instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 014096e4d5e65309ca71d0e63327f5386ddf16fb |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| a1fe9ef62e18dcb30cdee62a2fad82d05791d359 |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ddbdeefa286374a1f036d5e80987306749d3f729 |
|
02-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
remove lines that are setting DecoderNamespace for pseudo atomic instructions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 782638aa0d18f7db7970eb0d8dded84fe7f0c450 |
|
31-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename instruction DANDi to ANDi64.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 52b7321a48ae6f1a4f8f56047196d49fdb19ac16 |
|
31-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define instruction itineraries IIArith and IILogic.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 0b926427670de6e0ed855ef93f220a3f51ed1eab |
|
22-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ae24f7d3c6770fb32eb1f6215bab1fc92cbe2d94 |
|
13-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add instruction itinerary classes for mult, seb and slt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| a66aacf6d7e57b21dcd9e866d28749567cfba74b |
|
02-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1d4d32398ddb19520b2a84acae3b7807ad74602b |
|
21-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add instruction selection patterns for blez and bgez.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f894199a14fff1399f6ee9d78c6a601d86649155 |
|
20-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 3209baefd4ab8242563118c37d8357bd9de6b421 |
|
16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add branch macro definitions
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c147c1b994e1187cb471cdb7ee05f5f875eff4e0 |
|
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix handling of instructions which copy to/from accumulator registers.
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f5926fd844a84adcf1ae4f193146f2877997b82c |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2cd7d3f9ce034ecc4ef4d6fa8fc7dac06f0c708f |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define pseudo instructions for spilling and copying accumulator
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| af7da5cb993d1a2afad4816fe22c497d5adbef91 |
|
29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 94fcfaf3a9f1179edb3b8053fe7b23eab6fb83bb |
|
29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs
This patch provides alias definitions in td files and test cases to show the usage.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1ae08e007784a0708d6dae9c37b84bb62d5e1282 |
|
04-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Print move instructions.
"move $4, $5" is printed instead of "or $4, $5, $zero".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 0c66403efdf88ff4f247b6a9f45339bb3a893235 |
|
07-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 37ef65b9c1b93c386d13089d9ace6a1cc00e82dc |
|
05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| e72fac60e3dbcf14ec68cedc1e86feafec1652eb |
|
18-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Removal of redundant code and formatting fixes.
Contributers: Jack Carter/Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ec3199f675b17b12fd779df557c6bff25aa4e862 |
|
12-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 71ab7a79a74ebb3dad1aac02c5a5c7c2c20b547f |
|
07-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b |
|
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f53b78f5bf28dff9536687245239f6aa200add86 |
|
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and
shift_rotate_imm64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 5f560bb2ebd9b489750fafd0c2d7c5136d18c622 |
|
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor instructions which move data from or to coprocessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| dbf51ee4596791d8cf38538b80805b2c3a577836 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| e8bc10b902f15eb4a12b810d5ab06a2755e7f990 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor SYNC and multiply/divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 6a8309e62afd88fbea4f1c39121de6dc4dc0d899 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 0a57dc1d147bbd091adf89ace10482ceb912c552 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor load/store left/right and load-link and store-conditional
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 16164657d88c50be59a3fbff035ded786a98cf7f |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 8e719fac46c3c79dedfde86bf439819444223537 |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor LUI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 35242e27c578da3915451079b5bdd7b9a89ed77c |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor count leading zero or one instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 8aaed99a99fcb879be2ed9bbc25a68c2e8558960 |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor sign-extension-in-register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 7de001b97e1087b393efc90f7b10ffedd4f66fed |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor instructions which copy from and to HI/LO registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2a732ec272e3bab004a47abb452ad47bc4eb8c7b |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor logical NOR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 9bf571fe2c24305aee6a930ed3b2561f6d4ff237 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1e7739f6140da773b6e998525d7900fa82670f00 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 5c5402564515ad87425af9881619545c096b84b9 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c4889013553a4e407e110d1f76d9b6cf1396e702 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2427773f2f18a2dd630428d7df927a5cdf4280f1 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Change the order of template parameters. Move the default parameters to
the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 0dad34a9bf850132e9ec84397f13604143c3aeff |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor shift immediate instructions. Separate encoding information
from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 23a3da0113600a2c3204f766cbc51d68a8ed4d94 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c9e30ea42c428ca3ccf9d70a88c4171c6be71f41 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f3c0c77bc34706cc3c2bbc5e4aaae984f52d01a7 |
|
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete nodes and instructions for dynamic alloca that are no longer in
use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 249330eadb9d1d4835d6b55146147840492e5d13 |
|
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Shorten predicate name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ab9705f8fa48f1f00f159746139509faab919ee2 |
|
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove unnecessary predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f09a03776dbbc882c9b15eeccb8ec847058fbfa0 |
|
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Generate big GOT code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 497204a94b6ebe94b0cc9b9ef11eee7baf1df53b |
|
31-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
re-materialization of immediate loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 01a75c46e3292c1a66b577b5a6b7510a1867afdd |
|
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add tail call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| aa5b393c69cf24d47a5727d15584f3daeba1aead |
|
11-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Expose move to/from coprocessor instructions in MIPS64 mode.
Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode. We should ensure that this is easy to
do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 572e1bd109518f80b54d229de10699c4603944c3 |
|
09-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Improvements to MIPS64 assembler:
- Teach it about dadd[i] instructions and move pseudo-instruction
- Make it parse the register names correctly (for N32 / N64)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 5a7dd43f045f2f78adc81b497c5d78bd9da0884e |
|
15-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 3185f9a2ea80afec30064b7cd095f82c31dc154e |
|
31-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 714313b4828cec98b086b54b356407540aa775c4 |
|
28-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 8d7e5efcaa5a1625e9518d090697f08d6d1110d5 |
|
09-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Another 32 to 64 bit sign extension bug.
The fields in the td definition were switched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88 |
|
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The define for 64 bit sign extension neglected to
initialize fields of the class that it used.
The result was nonsense code.
Before:
0000000000000000 <foo>:
0: 00441100 0x441100
4: 03e00008 jr ra
8: 00000000 nop
After:
0000000000000000 <foo>:
0: 00041000 sll v0,a0,0x0
4: 03e00008 jr ra
8: 00000000 nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 61de70d98e1f752d5482b775f08827f799f4a53b |
|
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
were using a class defined for 32 bit instructions and
thus the instruction was for addiu instead of daddiu.
This was corrected by adding the instruction opcode as a
field in the base class to be filled in by the defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| e035f65b16956cdb7ba29e741b7e3c04a8ce4d24 |
|
16-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63
Here is a description of DSLL:
Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits
Description: GPR[rd] <- GPR[rt] << (sa+32)
The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.
This patch implements the direct object output of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2 |
|
10-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make register Mips::RA allocatable if not in mips16 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 14180454726bbef6bf5041ae19736933617b51dd |
|
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
1. introduce MipsPat in place of Pat in order to exclude those from
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 4d70ceed33d07d88de837a80899c99ddf9c3534f |
|
02-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of 32/64-bit unaligned load/store instructions for Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 18f3c7809292fe6ebdce47d551f23d6ee216023f |
|
22-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 9853b49f6158eed882c276ced7013c31fa330f45 |
|
18-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ecdc9d5bb26936a68060f1238abc6c1d6b3c2a01 |
|
17-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add disassembler to MIPS.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 02365945a62f368c18547da57a4ef3382beb89d0 |
|
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r153924. There were buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 885020a7a7299c0cfc12f691bc298e0f41d02190 |
|
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS disassembler support.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| b2930b92d3e9734ced6679844666799648ebbd7a |
|
01-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Changes for migrating to using register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| bb481f882093fb738d2bb15610c79364bada5496 |
|
28-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 648f00c2f0eb29c0ae2a333fa0bfa55970059f08 |
|
24-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add an option to use a virtual register as the global base register instead of
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 57fa38225cfeded40a38770a2cc52e10a4e7268d |
|
25-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 5387f2e4f3b1982ee7236fa8db92f9c5152dc058 |
|
24-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit sign extension in register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2010325a11ecf06ba28a309b88f3991eb88cff2e |
|
04-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Rename immLUiOpnd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f12e702a8c14ba09c9fb69ae9c663589d18ad498 |
|
04-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
versions derive from them.
- JALR64 is not needed since N64 does not emit jal.
- Add template parameter to BranchLink that sets the rt field.
- Fix the set of temporary registers for O32 and N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 9dbeb0284d9e9a29f473bc24af91f780cd52dbbf |
|
24-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
If target ABI is N64, LEA should be daddiu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c0ea04389c9fc0b73d0cbd90ec3a5bc076d25d7b |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of DSBH (Double Swap Bytes within Halfwords) and
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ef43c2de8639689dafdb8b580e75bcaae19a8dbb |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
32-to-64-bit sext_inreg pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| acb5a06f7a44a4bf48e98a1a857be25338c1bdc3 |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add 64-bit extload patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 403992dc588da0f429c33061244c6d1c579d6b5a |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
32-to-64-bit sign extension pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f06cb2b207c9a4a99e9d8f2b45f9b48dfddc15ee |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add patterns for matching immediates whose lower 16-bit is cleared. These
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ee973147ac0aad6471f5506c3278654baec4d1c0 |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove definitions of double word shift plus 32 instructions. Assembler or
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ed538b5271b2ec11dad7af362ec76d5fbac5f6d0 |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove unused predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 6df7e23f0c9e9e4aa5560f3b0ecb2bb7d53f7d81 |
|
09-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Rename WrapperPIC. It is now used for both pic and static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| ca0747917d3daa85287fd7ea6f91349b8d5a5b29 |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement 64-bit support for thread local storage handling.
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 08a7d92da6f6fcd5879d1c8a7ab69b23e33831cb |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify class ReadHardware and add definition of 64-bit version of instruction
RDHWR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| da86fa14f0d1e8bfaede9d98fd66b64dcc3c9bc2 |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
32 to 64-bit anyext pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 0a18cdc372a4ca1bd685071d99016ad57ba9d77e |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
32 to 64-bit zext pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2c78be01f682e8b24bf5e5d4213016483a2fb54e |
|
07-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit WrapperPICPat patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 4d0eb637f0798726ef49d93ecb1e6ab371ab9ca3 |
|
07-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix 64-bit immediate patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| d6bc5237d8c961949fbc57dfa1a07f5833262388 |
|
05-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of 64-bit extract and insert instrucions and make
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 74c76347d3815b84b8fe480888fae5f975071d57 |
|
16-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 4fd40b3604cc5c7daff2ba26317314461c834aa1 |
|
16-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit jump register instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 788dc0f4e51628651850ca3c68cccd713b694052 |
|
14-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
32-to-64-bit extended load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| deab22a556195467f1c367c9623d276ace35c3cc |
|
12-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit arbitrary immediate pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 59068067cb37322c50463102bbd6929df34c039e |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit atomic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c742e4fc9016b4987dbd06af4670d7759392d08d |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 642b1097131ec8c700318f01fe2504d8d5ef4adc |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit versions of jal, jalr and bal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| d83d98d4eb9595a88b830f5e3f5c6c24fae80df1 |
|
07-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of 64-bit load upper immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 778404601266effff17d5c43d0ad08b8ca2522d0 |
|
07-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted
when shift amount is larger than 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 68698cc20d7e1fa1b45a30e7c25313796f40d5c6 |
|
07-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Make the type of shift amount i32 in order to reduce the number of shift
instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| bce22b48fee6a0b0295cc18c7994f3a515e63398 |
|
07-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add 64-bit to 32-bit trunc pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| bdfd98a080609fbc90cc3ddbc4cc6ecfd9e39587 |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Redefine count-leading 0s and 1s instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 89d306669e30077c205f60e7f3e4c233f92c9ad0 |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Redefine mfhi/lo and mthi/lo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| f1fddcd9e01ceb38ee7f2951f9e109cccb601654 |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Redefine multiply and divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2d0a61da62b19d9597d569fb99082b418e214a12 |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of a base class for logical shift/rotate instructions with two
source registers and redefine 32-bit and 64-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 363934665d84e402e2e44f59b47185b8a1a50be6 |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of a base class for logical shift/rotate immediate instructions
and have 32-bit and 64-bit instructions derive from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| a01820a50824bf592d0a2900cf17ae3adfd5575a |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 41f9a430cbb47b1d6172a91d2a70adc552b65678 |
|
12-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2dfd3a978936c39194246676af5c4791e65e5001 |
|
12-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
instructions with two register operands derive from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| c2f3ac9de2596df2af8b85245b987476a773d4ad |
|
12-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 7cc037a1371a4c4577af12fb221fda6e73ef5518 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Change the names of 64-bit logical instructions so that they match the names of
the real instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 395d76c5a3614b2d5f180182f4c897d76ece05ec |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove redundancy in setcc patterns using multiclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| b07a3d68972039426a87f1cac82e348e3bb1877b |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Use sltiu instead of sltu when a register operand and immediate are compared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 06f8231bfbdd77d68e7ec7ff2e238c45b3bec0b8 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add patterns for conditional branches with 64-bit register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 8191f34797d2e3cfedf5cff3e79947c90599f720 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit set-on-less-than instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 3e3427a5c3fe8303723129207ce1864bee8fa481 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for conditional branch instructions with 64-bit register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 1acb7df498485249d92f62febeaefd91cae3d98c |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Make changes necessary for supporting floating point load and store instructions
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| a5903acd6bc15c6aa511068f8b79c79014c1b5d4 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify lowering of GlobalAddress so that correct code is emitted when target is
Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 7bd19bd519311dacc8c00ac21f873d2cf900285e |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
zextloadi32 for which there is no corresponding pseudo or real instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| d55bb38ddcb82bce8f56ef6d4258f15ba1761ae4 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Change definitions of classes LoadM and StoreM in preparation for adding support
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 43e43f7d8bfc748973feb781fc304f8d23ab88ba |
|
03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit logical NOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| 2d57088ff015b01c8c2aa8d7844f96881e0c82ce |
|
03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit count leading ones and zeros instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|
| dda4a07cd818fdfe2b49412e32e0e12d9e566e31 |
|
03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| 04d3762ff111085e21cb8f8570e68dff7f847b6d |
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03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit integer multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| 36787939b27d9b238e10fc4ba42cb621003a5a31 |
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03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of instructions which move values between 64-bit integer
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| c7bafe9241c0742e71f7fd1b83e0c5b3acee0dac |
|
30-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of Mips64 rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| a64556ffda503a416b2594104f8f82345734b4d9 |
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30-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
isCommutable should be 0 for DSUBu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| 25a7d94e81317a5f562631906692c4761dcd2395 |
|
30-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Mips64 shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| f549ab78533cfb7a22a88216f20d69edfcee3cc9 |
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30-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Mips64 arithmetic and logical instructions with one source register and
immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| c0be26909fa47f3200601c384156f43301f0c5c2 |
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29-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Mips64 arithmetic and logical instructions with two source registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| d2d00edc0165274e308abbdb239af1b7b579623d |
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28-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Mips64 predicate definitions. Patch by Liu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
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| 8aa4b4cb6fb4c2dd91b17c115e4f0274f42b25ba |
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24-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips64InstrInfo.td
|