| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| bb47fd04c9b1616c0371eb2c488c5f0f665c25f8 |
|
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de |
|
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.
It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().
Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| c8a1fa77a73e7c885035421712ceba951f9024cb |
|
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp
This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).
There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.
compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
|
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added load/store intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| da0860f78e6e43aca3333a7815b2f9bc0f8dfac0 |
|
13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ba54bca472a15d0657e1b88776f7069042b60b4e |
|
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 6a2e7ac0b6647a409394e58b385e579ea62b5cba |
|
06-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| fee62c167b1f731998ff4d315830154d17ec6f85 |
|
11-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.
- Rename function.
- Pass iterator by value.
- Remove header include.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| cacff672dd532d882727a51e73c96f19fde45828 |
|
15-Mar-2013 |
David Blaikie <dblaikie@gmail.com> |
Remove some unused variables to clean the Clang -Werror build
(these were added in r177089)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f283512d72757aac5bedcb270f9199194e6a12c0 |
|
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename functions and variables to start with proper case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 554d9312b284265f91ac5ee5bf0351d446f669b1 |
|
14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
mips16 and MipsSEDAGToDAGISel is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ee767fe2d2d742630d2fd40f91f3c54e35cc0668 |
|
01-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:
(select (setgt a, Constant), T, F)
The pattern above effectively turns into this:
(conditional-move (setlt a, Constant + 1), F, T)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| abbf9df7f42e8e3e95b02b16ebbc6a0684bb4f6d |
|
16-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove SDNPWantParent from the list of SDNodeProperties.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dc2f79274021a590d6b72acd741117068c3e49bd |
|
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Split SelectAddr, which was used to match address patterns, into two
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0301bc54ad23c9dff0370dffaf6eb3eabba42cc4 |
|
15-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add predicate HasFPIdx for floating-point indexed load instruction
support and use it in place of HasMips32r2Or64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5 |
|
28-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.
The Mips16InstrInfo.td has been updated to use addr16 instead of addr.
The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| a81be80b0eabfc8b5e590a10471c66dadf6ded6f |
|
26-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement carry for subtract/add for mips16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dfb8dbb4fd97140aa9bf6b9dadbca25665144c09 |
|
05-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Patch for integer multiply, signed/unsigned, long/long long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 5a7dd43f045f2f78adc81b497c5d78bd9da0884e |
|
15-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 45d8dbc92d365e9c0a08ceb0bc7a9014e6064bdb |
|
24-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its
second operand is MipsISD::GPRel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 69a0aa87f8d64895af082cb52c7ecee0f6021d20 |
|
10-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't modify MO while use_iterator is still pointing to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 36bcc11236af961ff94820bf9817ecb4f98ace7e |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| de4a1274706d7449870dac5bed05d27a6772d4ed |
|
25-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Eliminate the stack slot used to save the global base register.
The long branch pass (fixed in r160601) no longer uses the global base register
to compute addresses of branch destinations, so it is not necessary to reserve
a slot on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 3ee306cbc0a295409c464ffaad5ef694de8eb09a |
|
24-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add basic ability to setup call frame, and make procedure calls.
Hello world will compile and execute with this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| fef904d0e824a2c587f8c1063b6c4fbf47fec898 |
|
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| b7dd9fc678ab4b4c57d333cd9940b0e0d7952ea6 |
|
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
Test case will be added later when long branch patch is checked in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| e246b52d2b02753a0064fb7e984148fff55d2872 |
|
27-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 4782a6e06ad4c6227831b70bb76165bc7b14bff3 |
|
27-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bug in computation of stack size in MipsFrameLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3 |
|
21-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
1. fix null program output after some other changes
2. re-enable null.ll test
3. fix some minor style violations
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 864f66085cd9543070ef01b9f7371c110ecd7898 |
|
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix coding style violations. Remove white spaces and tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 4654e58a64b9d9b5eb93befc74ca7cfecaf52ce9 |
|
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.
Long-branches need access to the global base register to get the destination
address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8782707f5074ab3951eb6424394bc8d2a2fa584a |
|
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| d9b0b025612992a0b724eeca8bdf10b1d7a5c355 |
|
02-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix typos found by http://github.com/lyda/misspell-check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 27ba61df9f9decc70124b7559f777ad596dfda29 |
|
12-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Insert instructions to the entry basic block which initializes the global
pointer register.
This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:
- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
allocator decide which register to assign to it or whether spill/reloads are
needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 3011a33a63b055fc3c0bba51728e13c8b0f1c20e |
|
12-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not replace operands of pseudo instructions with register $zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 420761a0f193e87d08ee1c51b26bba23ab4bac7f |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 56e1ed53f515704f2171155e19d1dee7990762a3 |
|
27-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add T9 to the list of live-in registers of the entry basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7065b7b20341aaeb93ac3ce09726f69657ff3da8 |
|
08-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
This patch eliminates redundant instructions that produce 0.
For example, the first instruction in the code below can be eliminated if the
use of $vr0 is replaced with $zero:
addiu $vr0, $zero, 0
add $vr2, $vr1, $vr0
add $vr2, $vr1, $zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3 |
|
01-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bugs which were introduced when support for base+index floating point loads
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| bb481f882093fb738d2bb15610c79364bada5496 |
|
28-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| b75673b6e18da3937e4cbcd944b081bdc28a6cf5 |
|
28-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not reserve $gp as a dedicated global base register if the target ABI is not O32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 44b6c715ac87505f98066fa3bf6e3e99a26b886a |
|
28-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for floating point base register + offset register addressing mode
load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 648f00c2f0eb29c0ae2a333fa0bfa55970059f08 |
|
24-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add an option to use a virtual register as the global base register instead of
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| c5707112e7635d1dd2f2cc9c4f42e79a51302cca |
|
17-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8f5e8c1cd69fa77bea20140a7132ee2dea166c6d |
|
17-Feb-2012 |
Jia Liu <proljc@gmail.com> |
add Emacs tag and fix some comment error in file headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 57fa38225cfeded40a38770a2cc52e10a4e7268d |
|
25-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| a32a08c8e26049457bd3df39bea5f4a80e308d4a |
|
06-Jan-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix uninitialized variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 2fd0475cdbf7e80d4e5097ab0ddedcce18711ec9 |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 49d534bb3d21cfefd372e7d337af41dbab6738e3 |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 990d639f552308220dae062661fa3ba074d7150c |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add code in MipsDAGToDAGISel for selecting constant +0.0.
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 05c585319b8620178d3032f74704c5be360ab7e7 |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert part of r146995 that was accidentally commmitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 403992dc588da0f429c33061244c6d1c579d6b5a |
|
20-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
32-to-64-bit sign extension pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 82099683060abb1f74453d06e78a3729a75ef7ee |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Tidy up. Simplify logic. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 89dc8d790d1ab3c903dfdf211f651350438a72fe |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove the restriction on the first operand of the add node in SelectAddr.
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 6df7e23f0c9e9e4aa5560f3b0ecb2bb7d53f7d81 |
|
09-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Rename WrapperPIC. It is now used for both pic and static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ca0747917d3daa85287fd7ea6f91349b8d5a5b29 |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement 64-bit support for thread local storage handling.
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| bd15090aa21738aa0670fc894f4b49c8fa93e3f5 |
|
07-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 3bdc03a592d886382471136f7cf0ef93ac0feae9 |
|
07-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 4d0eb637f0798726ef49d93ecb1e6ab371ab9ca3 |
|
07-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix 64-bit immediate patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 381e97dcf6852323d053122cb222751d6578534f |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 04d3762ff111085e21cb8f8570e68dff7f847b6d |
|
03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit integer multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 56633441271106376b39a47bbe5b59f85144b64d |
|
21-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change the names of functions isMips* to hasMips*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 614051a1c534aff052152b0162a414b3271e8fca |
|
16-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix handling of double precision loads and stores when Mips1 is targeted.
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0285e7d1c14746865a4ef772fec98370a3543a5b |
|
12-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
When constant double 0.0 is lowered, make sure 0 is copied directly from an
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.
- In the test case, the following code is generated before this patch is
applied:
mtc1 $zero, $f2 ; unformatted copy to $f2
mov.s $f0, $f2 ; $f0 is in single format
sdc1 $f12, 0($sp)
mov.s $f1, $f2 ; $f1 is in single format
c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double
- The following code is generated after this patch is applied:
mtc1 $zero, $f0 ; unformatted copy to $f0
mtc1 $zero, $f1 ; unformatted copy to $f1
c.eq.d $f12, $f0 ; $f0 can be interpreted as double
Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| d3ac47f80551d95c64cb41c3f94e888d7e13275b |
|
07-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8b2b713f686a6d4908b73c76759447aa87b62c4a |
|
24-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Prevent generation of redundant addiu instructions that compute address of
static variables or functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 21afc63ea7b8227ccb1b735255be55bf422136d6 |
|
21-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 6f3661fdcd10a33d225502f8b112dc5b7968ef74 |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| c53cc48ca98c86a9ccb9de632c77890c5f7ea2d5 |
|
09-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Initial support for inline asm memory operand constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| c079ad09f535925b4431f9ed9b6ae8aa33225910 |
|
07-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Put back removed line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0f843821385213b33116eaecf0c13e987139f6a5 |
|
07-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Coding style fixes.
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 5e06903e66a1f89b29a7cdf89421e3d8d12f6a77 |
|
02-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| d979686bb47f2dcdca60f0a088f59d1964346453 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 342837d0dcf4c47765bbd3f9c031418824b12747 |
|
28-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
Need this to prevent emitting illegal conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 4552c9a3b34ad9b2085635266348d0d9b95514a6 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0bf3dfbef60e36827df9c7e12b62503f1e345cd0 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f49fde28772cf73502d31e2755b7c75c0e90a05c |
|
04-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ad8ffad60ae33e834c18072a37b6b30fe45efdf6 |
|
02-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Undo changes mistakenly made in revision 128750.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dc1652fd311073492a169101b8b6e1d725dca280 |
|
02-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Insert space before ';' to prevent warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ad8180a0b85cbb66d30ba011d358279e6d461a16 |
|
01-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 38b5e86b9c67f601f354f8bcc11f5a515e200315 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Improve div/rem node handling on mips. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ca8a2aa921ec8966b1f0708d77e4dc0a6f1a32f8 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 81092dc20abe5253a5b4d48a75997baa84dde196 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8e68c3873549ca31533e2e3e40dda3a43cb79566 |
|
23-Dec-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7d5652dcd5371d086e2b24cb9c14a34b74481df8 |
|
12-Nov-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7fa846f7d92db26fc516754df5e762c36d3ed013 |
|
03-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove Predicate_* calls from Mips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7552a3df393a272f75104527161f7e171f8ade13 |
|
19-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't call Predicate_* in Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| fff916a96076e284edb043d7541cfc7902086039 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
SubRegIndex'ize Mips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7c306da505e2d7f64e160890b274a47fa0740962 |
|
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 9a720b0b0eee507bc453d0960ce7c11e7945d79c |
|
01-Feb-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
MulOp is actually a Mips specific node, so do the match using Opcode. This fixes PR6192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8c5ee7147b84f6171b51d4afd5466c59d8c84fef |
|
19-Jan-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix a bug introduced on r92564 where the name "Node" was already
in use by Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 9201b10daac2660f2f45534f12b52e3ee3501e88 |
|
19-Jan-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
On pic function calls some arguments were marked dead and
the instruction to load those args removed. This fix PR6071
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ea982789354af0d24ea55021a5fc2178d4647980 |
|
19-Jan-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
load f64 +0.0 in a cleaner way. This fix part of PR5445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| eeb3a00b84b7767d236ec8cf0619b9217fc247b9 |
|
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| d71cebf57591e2dc27930d3002848dddc76c3f92 |
|
25-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support PIC loading of constant pool entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 37fd537544769c7f4304141745ebee4a8677e783 |
|
25-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use endianess dependent offsets for load/store of doubles when
using two swc/lwc instead of sdc/ldc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 2045c47affc0d1462a815175e420f9d6bd3f35c6 |
|
19-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add sugregister logic to handle f64=(f32,f32).
- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 6e0b658dadc15aecc4e8503b39741148cf18ee1f |
|
16-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Fix a small bug while handling target constant pools (one param was missing).
- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| a8173b934fdfdc7a3ca543a0734b7c8fa1969366 |
|
13-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support fp64 immediate zero, this fixes only part of PR5445
because the testcase is triggering one more bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 73bb251cd7a535fb93bb3a52eda61555fb253f41 |
|
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| c517cb006553320875544f39655c3299124be3ea |
|
01-Sep-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply 80278
Add MO flags to simplify the printing of relocations.
Remove the support for printing large code model relocs (which
aren't supported anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0c80be59c7ccbd844b5dee71b038090052cac07b |
|
27-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert 80278 for now, it caused a lot of MIPS tests to fail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dcace5c6209bdcb66d6b030b461b07a15ee569c9 |
|
27-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revamp our friend Mips :)
Add MO flags to simplify the printing of relocations.
Remove the support for printing large code model relocs (which
aren't supported anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 43ed267db3512823a9698f810be4e64bee227270 |
|
23-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix some refactos for iostream changes (in -Asserts mode).
- The world needs better C++ refactoring tools, can I get an Amen!?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 893e1c90a03a53cf13f73849324e83612688428a |
|
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the last DOUTs from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7571eb5015ad07d4b849cd97a5f820be19523a66 |
|
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Minor code simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 9911405183f8596fe9d521467f83f6652a296cf4 |
|
03-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Convert Alpha and Mips to use a MachineFunctionInfo subclass to
carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This
eliminates the need for them to search through the
MachineRegisterInfo livein list in order to identify these
virtual registers. EmitLiveInCopies is now the only user of the
virtual register portion of MachineRegisterInfo's livein data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 69bbb4cd39e8c6d391c8424fd70866b128df5d14 |
|
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 30baa95afdf1199c2c5514310907b01ce5584cf5 |
|
14-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
silence warning when asserts disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d |
|
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 8ad4c00c00233acb8a3395098e2b575cc34de46b |
|
27-Oct-2008 |
David Greene <greened@obbligato.org> |
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f522068412218cd14b2c2df74a3437717d255381 |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| da8ac5fd9130b70b61be61e4819faa8d842d708f |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| f350b277f32d7d47f86c0e54f4aec4d470500618 |
|
23-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| ad3460c3c968e33c5b9a07104b9fe5a5c27ff55b |
|
21-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify SelectRoot's interface, and factor out some common code
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| e8be6c63915e0389f1eef6b53c64300d13b2ce99 |
|
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7b76da145be2b3b7518ca42b43a903eabd52e1b7 |
|
09-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixe typos and 80 column size problems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 1002c0203450620594a85454c6a095ca94b87cb2 |
|
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 225ca9cdd70de3d12641b0aba7daf6cb568a7ebd |
|
05-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| db8d56b825efeb576d67b9dbe39d736d93306222 |
|
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 0af5e095ad16091457c35edd015fe2931023f58b |
|
06-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added custom isel for MUL, SDIVREM, UDIVREM, SMUL_LOHI and UMUL_LOHI nodes
MUL is not anymore directly matched because its a pseudoinstruction.
LogicI class fixed to zero-extend immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 07cec75913b74d04df40ff7fecf51f87175076c1 |
|
06-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 4e3f5a4e9c13f216856515e6f000881f2c850736 |
|
05-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
|
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 753a98740bfe3164fd0961a1959306c46135cf19 |
|
12-Nov-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added JumpTable support
Fixed some AsmPrinter issues
Added GLOBAL_OFFSET_TABLE Node handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| c7db5618f9e5e708b87d9ae6595b3fd510a2a0c0 |
|
05-Nov-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for PIC code with "explicit relocations" *only*.
Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| b42abebe36f1dfbd0c779fd1471618c42ed3fec5 |
|
24-Sep-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added "LoadEffective" pattern to handle stack locations.
Fixed some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 7ff6fa25037d207e31f65bedc8616a90f61abc25 |
|
18-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress
fixed to generate instructions (add, lui) glued!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| a4e8200366805c665bb1424d8af5550f5d3d6863 |
|
12-Jul-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for Mips specific GAS directives
Fixed print immediate
Fixed Identation on MipsISelDAGToDAG.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|
| 972f5896e417d8e81cf400083fab15a37b6d4277 |
|
06-Jun-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial Mips support, here we go! =)
- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
|