| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 26651c7a6602626cf13ff3cda13f3ec2401bf790 |
|
18-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 95adf91f29980e374bf094e15bc3f2764ef9baf4 |
|
18-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| bb47fd04c9b1616c0371eb2c488c5f0f665c25f8 |
|
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| aee7825762830536956b9e634fd7ffd59396984d |
|
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| de712386cdde314ee18ea44b733d48a30d63de10 |
|
08-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 02fbffd4e8e1a28539b302e4de84203814898153 |
|
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c385709d8397ca1535481c04564b67d07c66c619 |
|
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).
These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.
bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
values is an uimm8, rather than when the condition is a uimm8 (which is
covered by bmnzi.b)
compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
is the same operation (see MSA.txt).
i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
distinguishable from bmnzi.b.
vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
MSA.txt).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de |
|
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.
It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().
Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 57cd3bc4064bd71eb6572d3cba5e23471ab25863 |
|
30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics)
splat.d is implemented but this subtest is currently disabled. This is because
it is difficult to match the appropriate IR on MIPS32. There is a patch under
review that should help with this so I hope to enable the subtest soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| f7b6bac2629c09b5dcdf9dd926c02490d2c81cd2 |
|
23-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for the LSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 09c7f4026afa46ca7ca67d47179013a340a5e944 |
|
23-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 5cb5ff8b1478ed413a9e9fae43b1496f5a97a2dc |
|
22-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).
List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 348da8d6b5e002c3698c37aca26c508bc60a05bb |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for LD/ST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| b14ad465492c472033e9ded65ab40e4a9c2c451a |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for LDI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| f6d4cff9b1cf1e3b57592d6a0e40f0026813aa7c |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for MOVE.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 006cff8d7b60ddf632f8642f01693dace7827d8b |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon
as GAS starts accepting them by name as that would make the assembly easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| cebd4010222f28bb68c217047fd0b2c90498f7ca |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of SPLAT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193077 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| f89f66e61b26974bb73b5832d5825091873b51dc |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to
slide left the source array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 52244da7f2b3def646900520668b859343b84a33 |
|
17-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added lsa instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| db8a16252b9d29bd7a3442d5c3bad0398dd85908 |
|
17-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Removed ldx.[bhwd] and stx.[bhwd].
These were present in a previous version of the MSA spec but are not
present in the published version. There is no hardware that uses these
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| ed785629be5a1ad689e2aa4e125781419d824938 |
|
17-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq.
Define these three instructions in alphabetical order (like the rest of the
file).
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 62e87cb2415b305ca9b888a2338a6af59e74005d |
|
15-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for build_vector for v4f32 and v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 9672a89c71f7b368455ed193bc23566f3bd4ed2b |
|
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| e89c50acc8312c6cd4d3bdbf50e02ba88e54a663 |
|
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 01436ba3066b99547c1138edf5c36ef2ad467e71 |
|
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 29adbe8464f74f17a7cf977ce21ef88d88d28b14 |
|
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 45ecbfc8e58923131068dced0cf89348ac61208f |
|
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 21d60f02c36c2362899109239d16824caa56d8ab |
|
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
This reverts 192447 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| abba71663eeebbea725eded5e23f273147824ed2 |
|
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
This reverts r192449 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 62a69eee5ad951502de28871ef27bb64dbf5508f |
|
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 6f36ea5c4778ac0519d821798b94aaac92ec1389 |
|
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed.
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
general purpose register. The changes to parseMSARegs reflect that requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| a6e253ddd0f757101fe97105d60a1e098ca5f33c |
|
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 4fa2c32220405ac32838e45d91392a83fae70bb0 |
|
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c879eabcc25c4099a50939ed0bca86471201b183 |
|
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| b9bee10b2158253e222eb8dd5f0ae0452740ace3 |
|
11-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 7f768e03684514ea9ebabed93694521f9ffab28f |
|
01-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| bdf8015cffb1860776e5a5f28014b023a32ab1bc |
|
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| b0247157c6d44363c36cffd0aeea0e2fa83d9335 |
|
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 70f556140fca702ef6062b0c46b032908b9ae2a5 |
|
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 2641f5e412ba84255d8b97f5098e3f57bf990ff1 |
|
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| b0922655166aeef6c54c7b4d31d1ccaecf492e2e |
|
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 37469a132988eb0c888f6a8a205b2aca510e14f8 |
|
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| b4691b495d867a863aa12de57d45bc6a93e4df78 |
|
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c8a1fa77a73e7c885035421712ceba951f9024cb |
|
27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 1327c089221da78b1bfd61067162023e520085ed |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 00a5b53e148cd0c840650504fcd6e92dee132c1a |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
This does not affect any of the existing output.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 9fa81ab83898314d1a6608e8303dc57253292796 |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| afee613bf390b255eef9cd46fd336fecc7663a1a |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
Internal changes only.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 4167b88cf5754597e5a7e53aa0cbba26c18b6162 |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 42d9ca629934d0c20ac19949399ce4faa9a7bbb3 |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.
Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 825e5583b6c3161bb02074dc48cd07dafdf9545c |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
This only changes internal encodings and doesn't affect output.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 3706eda52c4565016959902a3f5aaf7271516286 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| f515964d36834ec918fe831029bc72ccdcec34d3 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 93d995719e2459a6e9ccdb2c93a8ede8fa88c899 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 7e0df9aa2966d0462e34511524a4958e226b74ee |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp
This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).
There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.
compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 421dcc59212a73b82141caa2c94ea340a7b34deb |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)
This covers the case where fmax_a can be used to implement ISD::FABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 930f2b51084c6dac1238b8b0f8dd11f40f619694 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Line wrapping.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c998bc98439e21bc8c3838d6353475eacfb8494e |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 89d13c1b380218d381be035eb5e4d83dcbc391cc |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 38a10ff063971c2f7f7384cceba3253bca32e27a |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics)
This required correcting the definition of the bsel and bseli intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| ae1fb8fc19dcfd2f0e33a36f40d687b08dcc9a6b |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics)
MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| cfb1e1703130809043a7b020b4cdfa04b59fa8ec |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| e0187e51a17f2081d6a72a57e0fbba8ce38d9410 |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 9a1aaeb012e593fba977015c5d8b6b1aa41a908c |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| a399d698a84ffd22c7d1f121c24cbc147c6f4e06 |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 915432ca1306d10453c9eb523cbc4b257642f62a |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 4e812c1f4a723f0fa0e8714610e08be593c759b8 |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).
Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| f2eb1e4286bf397d60a37e6f288ac81e644a3258 |
|
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 2ac128292150c7ebb469d137877eaa3c6d26a8bb |
|
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| ece929d6234b73ea248b7a5e89f915613ad748ea |
|
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 68831cbd417b7e4c47b565038a4fe9a1269d5d50 |
|
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 8857294192bdc1992d60a14a6ff6c519ddee63e3 |
|
11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 436f64567ceb0b45e6b5b680fa09485002094830 |
|
10-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
The dotp_[su].b instructions never existed in any revision of the MSA spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 69f8e0935af16622ca13d26e6a66464d3c1f3da4 |
|
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| a86062c4b12fc2b9ee339ca8c54bcef3447f713c |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 5cb39b22fb248b59d7aa37603083ba7d1b0f7f2c |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 3aaa3e31aa35164fa54474bcf3a2c2df5ab8b375 |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 9e935a77a59fc14acf1936165f235342b741e34a |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| b9987d1aa14d8ee91bb0acd113ac21fb322f3efd |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 888497d8a2927ddab38667d54d574c3cadeef1e5 |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 6976d75415fdbdcd4cef52e0c9a20000dbb17db7 |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 99d02d13259620d175986bf9c7e1c07b2640163d |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| d31c238372b2ddba147a012f457cae896e6e828f |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 7d3da67611e9ce7541a8987dcb7964f69de071aa |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| bfb9bab2434e3a8c4452708995a7f5d4f5a3b20e |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| e3273b327555df6489640d2195b52b6317c88844 |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| cc538affd270c81d12285e6addcd261086beec2b |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 3f1acd55a8ad249926bc80916bb20f0b77798cb5 |
|
06-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 3c380d5e28f86984b147fcd424736c498773f37e |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.
Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added load/store intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| abbcf3bd47ad8ffa70f48ebd924f99fff5c22131 |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added move.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| a6c3a4ee76ef8464d3c83472e15af521ade7eeb4 |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added cfcmsa, and ctcmsa
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| f00539cc5a5e66ce6b7ce3779b00fd381e2d2dee |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c9617b9a9dfcb550adcf06f83a58a5e522414cc1 |
|
27-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added bitconverts for vector types for big and little-endian
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c73488a38ecb26340604706003e84cff7bd48ddf |
|
23-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c5158b869bbde7b08c486c6f326bd1c701367c98 |
|
20-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 6ef333501eb917cbd79a51c84294051a1a257a0b |
|
20-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added insve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| c149fbbe279ef623e6067304fd08dc1a62d74f7d |
|
20-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| ea549a847d87cb8ce46f6a45b24ae888db697a07 |
|
16-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Reverted test commit (r188556)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 1dbfa36ba1e2f6e4630b5f41254e307f81cece80 |
|
16-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Test commit. Just a blank line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| bd71eea899d579deb1fcee02944f955a4708091a |
|
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (madd_q to xori)
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| d0f99639c16ddad697db30e75643ae4cc52c3e80 |
|
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (fadd to ftq)
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| e2a9376b1bd2204ea6f56a35b762e28e0ef4e35a |
|
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|
| 3f70e908c3d9de7acea462719ebf36dca1560f9c |
|
13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
|