cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749. Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
006cff8d7b60ddf632f8642f01693dace7827d8b |
|
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
b00491341778776a4d994846ca2f7fafe79c161d |
|
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set HI/LO registers' HWEncoding field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
42d9ca629934d0c20ac19949399ce4faa9a7bbb3 |
|
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
e925f7dbbf497412cd0cc3f67b9b96fed0cc3712 |
|
16-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
a6c3a4ee76ef8464d3c83472e15af521ade7eeb4 |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
6d55dfaf9124c3e5e54190090478d2f6384a51d4 |
|
28-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isAllocatable and CoveredBySubRegs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
c73488a38ecb26340604706003e84cff7bd48ddf |
|
23-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
187dedf21d268aecac6d95211de0c496299fdd13 |
|
21-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it. I accidentally changed the encoding of the MSA registers to zero instead of 0 to 31. This change restores the encoding the registers had prior to r188893. This didn't show up in the existing tests because direct-object emission isn't implemented yet for MSA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
099e5328fcfae96b406782d636fe02a4ecad4552 |
|
21-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Define registers using foreach No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
3531db14c61957e7ad00ce972e9685864c3887da |
|
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define register class FGRH32 for the high half of the 64-bit floating point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
e2a9376b1bd2204ea6f56a35b762e28e0ef4e35a |
|
15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
88373c29fe9d0b498ed21c3d29129f31806d7ec8 |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use register operands instead of register classes in DSP instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
7d6355226c60cd5ac7e1c916b17fee1a2b30a871 |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename DSPRegs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
cbaf6d0cc3d3f363f269346817a90d3cbc8d1084 |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename HIRegs and LORegs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
3f70e908c3d9de7acea462719ebf36dca1560f9c |
|
13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
491d04969d9f29ed891c73238648853954ba4f81 |
|
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename accumulator register classes and FP register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
94a88c49b0e87ee8c911669ff6c6bbd31b912542 |
|
08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete register class HWRegs64. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
1858786285139b87961d9ca08de91dcd59364afb |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
a1fe9ef62e18dcb30cdee62a2fad82d05791d359 |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Replace usages of register classes with register operands. Also, remove unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print jalr InstAliases in MipsInstPrinter::printAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
8a7f9de9d42e5817167e374dd61408dcac31a102 |
|
04-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Clean up code for Mips16 large frame handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
b67775df0cc702cd94408200ff2d58cf83f1334a |
|
30-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
0fc641df377bf6ea88bbc28b377f6a0810dfa220 |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Increase the number of floating point condition code registers to eight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
d6a7ea27361a64228e5afaf99d2ef3609a63cd3e |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete register print method MipsInstPrinter::printCPURegs that is not needed. The generic method printOperand will do. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
27d0c68617dee9c60efbc179c31b4a1bd28daa34 |
|
17-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use "foreach" loop to make register definitions more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
db8e0bbedb46c9f781f8a32728b1019f34089ed8 |
|
01-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Increase the number of floating point control registers available to 32. Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
90b1086b93708149ed7a3749e2eeccea264a037d |
|
24-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
dd5fe2ffc6f564192876065d2617ecbc18d03f23 |
|
19-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
23ed37a6b76e79272194fb46597f7280661b828f |
|
01-Jun-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Make SubRegIndex size mandatory, following r183020. This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
a2b2200ff8684ba23c64b24c0128a78f4b6e3c73 |
|
03-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Split the DSP control register and define one register for each field of its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
c147c1b994e1187cb471cdb7ee05f5f875eff4e0 |
|
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix handling of instructions which copy to/from accumulator registers. Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
cd6c57917db22a3913a2cdbadfa79fed3547bdec |
|
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Instruction selection patterns for DSP-ASE vector select and compare instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
26aef5b7d64e2dd2ed49123baf1e1075b648824f |
|
18-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] DSP-ASE move from HI/LO register instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
fda56e54cd303894c8c6d4be7527d178d1a980cf |
|
29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Change type of accumulator registers to Untyped. Add two more accumulator register classes for Mips64 and DSP-ASE. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
7abc88bc83d2b1a0e576fa5cf92de5017d90a792 |
|
15-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set isAllocatable bit of unallocatable register classes to 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
c147b678206db510336ee95c3b55dc9c0ff19595 |
|
17-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
457ee1a12e2c52624af7fdb81cf938f6d8d96572 |
|
16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
reverting 172579 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
490c7d97737ea7719efcea7321d3cfa3984b0027 |
|
16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
Akira, Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
ec3199f675b17b12fd779df557c6bff25aa4e862 |
|
12-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
e8068692f924a1577075bd2d7b72b44820e0ffb2 |
|
10-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set HWEncoding field of registers. Use delete function getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
5c87b732f2bb25e43b8faf90f43bb38d607fc8ec |
|
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use register number instead of name to print register $AT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
c94a38ff1732b960a551c7c1a4c50ede5c4737b4 |
|
28-Sep-2012 |
Reed Kotler <rkotler@mips.com> |
1. Add load/store words from the stack 2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and moved other lines for FEXT_RI16 formats to be in the right place in the code. 3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment. 4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
81571d3e0f54d5b163f5d891c33918c4b84660ac |
|
26-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add DSP accumulator registers and register class. Remove hi/lo registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
1024f290d1c81dd23ec452455eff8589a4419032 |
|
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add MIPS accumulator and DSP control registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
72e9b6aeb48d9496bac9db8b02c88a618b464588 |
|
17-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add stub methods for mips assembly matcher. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
f9fa3d8b872639d494481b43bee158c4359fc626 |
|
11-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In register classes in MipsRegisterInfo.td, list the registers in ascending order of binary encoding. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
63d10fbc89c02758cd91e3b53749e55c2bd0cf65 |
|
06-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
revert r159851. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
e32cc0d5456eb7beb4030f0c0205c724a485ff31 |
|
06-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Reapply r158846. Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
02a227af91889d39f5e811e2e27ecce8144499eb |
|
20-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r158846. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
b66510f309077d9f616462a1696f712236ce5a22 |
|
20-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsDisassembler.cpp, instead of defining register class tables, use the ones that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
4a5a8949cd15bab98c6d73754b4d6376b34ee8af |
|
24-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Enable Mips16 compiler to compile a null program. First code from the Mips16 compiler. Includes trivial test program. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
66e19c3e9db6e2727be21074a52f5c9fa187050f |
|
17-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
This patch adds the register class for MIPS16 as well as the ability for llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
338607ae0ddab00e197222e769748e2e0c0b4e18 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the SubRegClasses field from RegisterClass descriptions. This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
c4a238c20ff72cac00a537a1ae5c8935e0881646 |
|
27-Feb-2012 |
Jia Liu <proljc@gmail.com> |
delete useless comment&blank git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
1ad175e7e0547520eec8ff5ec39a65ad8fba00c3 |
|
02-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add DWARF numbers of 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
31867660cb81ea2b1d1a6ffa7d09c91acb754a8b |
|
18-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveredBySubRegs property to Register descriptions. When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
f99c1e5a1954dbaece9ceb137ec8aa4dfeb33050 |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add newline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
be7b67368c3f7dec5a4b9cf512e4a2ceacb907cb |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add 64-bit HWR29 register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
b1dcff0fe372d6a691f37413a24d5a6564f1a361 |
|
23-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add definitions of 64-bit register files. Add code for returning Mips64's sets of callee-saved registers and reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
aaa9fc2e375ac92c9ff0cff5265c79045affe8ba |
|
23-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add definitions of 64-bit int registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
ebb90dbb54a3ac7062080953b8af03e9ee5e788a |
|
22-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
95a091a0b65d1b4a27eedd9a0c96da319209b686 |
|
22-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of a 64-bit integer register. Move the subreg index definitions to the beginning of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
bb7d289aebe4af489e7cb8a1e9cf82980624dbfd |
|
22-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add definition of 64-bit floating registers used for Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
588158674572502daefbae5225715070274e6482 |
|
10-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Make F31 and D15 non-reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
f28987b76e758b5f2fcc2c5d2c8e073df54ca91e |
|
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use set operations instead of plain lists to enumerate register classes. This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff |
|
09-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove custom allocation order boilerplate that is no longer needed. The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
d979686bb47f2dcdca60f0a088f59d1964346453 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
01eaf907b09828ed9fc497d7a8d48192e486849b |
|
29-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the dwarf numbers from the D registers. They don't have dwarf numbers and should probably be encoded as DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
a5e62019d771fd0b01311cc0136e64b66b299eb1 |
|
26-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix some dwarf register numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
59d266029c51faac156e1ceaabc6f1faf5f2b81b |
|
19-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Increase number of available registers when target is MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
4552c9a3b34ad9b2085635266348d0d9b95514a6 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
0bf3dfbef60e36827df9c7e12b62503f1e345cd0 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
81092dc20abe5253a5b4d48a75997baa84dde196 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
23e70ebf352ff4938210711464c68b5a6e46e61c |
|
17-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix emacs language spec's, patch by Edmund Grimley-Evans! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
ca561ffcf320e9dbfafcac5efcee81471f3259c3 |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism. A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
b555609e73f5091bf8180c0875fb1fa6c5ad0e7a |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
6a45d681e53a99b4c4f63e0b1664626a596a8151 |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism. A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
4fda9670f0a9cd448d1905ab669421316b8864c5 |
|
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove NumberHack entirely. SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
33276d95ef4191663d8e6b972481f9faf37ce541 |
|
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch SubRegSet to using symbolic SubRegIndices git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
09bc0298650c76db1a06e20ca84c1dcb34071600 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
fff916a96076e284edb043d7541cfc7902086039 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
SubRegIndex'ize Mips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
2045c47affc0d1462a815175e420f9d6bd3f35c6 |
|
19-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add sugregister logic to handle f64=(f32,f32). - Support mips1 like load/store of doubles: Instead of: sdc $f0, X($3) Generate: swc $f0, X($3) swc $f1, X+4($3) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
d3bdf19ce7a37e23a6c4d877fb681eb010be74f7 |
|
27-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for fround, fextend and FP_TO_SINT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
bdfbb74d34dafba3c5638fdddd561043823ebdd2 |
|
21-Mar-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Removed AFGR32 register class Handle odd registers allocation in FGR32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
91ef849e6cb01a019dc50ed4e95c058e01616062 |
|
02-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Improved asm inline for hi,lo results Added hi,lo registers to be used,def implicitly. This provides better handle of instructions which use hi/lo. Fixes a small BranchAnalysis bug git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
225ca9cdd70de3d12641b0aba7daf6cb568a7ebd |
|
05-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
dfac7cb3067c33b18c45ae931fa3d2eec3d4b57f |
|
07-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for FP Registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
f191c80cd79ee35e47b5a4feed98d687782dfe85 |
|
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers. This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|
972f5896e417d8e81cf400083fab15a37b6d4277 |
|
06-Jun-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsRegisterInfo.td
|