| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 09c7f4026afa46ca7ca67d47179013a340a5e944 |
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23-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 62e87cb2415b305ca9b888a2338a6af59e74005d |
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15-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for build_vector for v4f32 and v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 37469a132988eb0c888f6a8a205b2aca510e14f8 |
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27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| b4691b495d867a863aa12de57d45bc6a93e4df78 |
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27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 7e0df9aa2966d0462e34511524a4958e226b74ee |
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24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 9a1aaeb012e593fba977015c5d8b6b1aa41a908c |
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23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 |
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23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).
Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| ddfbd5805478cf108156bb0159b7495d2b236f7e |
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11-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 |
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07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 3c380d5e28f86984b147fcd424736c498773f37e |
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28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.
Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 |
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28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added load/store intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| c73488a38ecb26340604706003e84cff7bd48ddf |
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23-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| e2a9376b1bd2204ea6f56a35b762e28e0ef4e35a |
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15-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 491d04969d9f29ed891c73238648853954ba4f81 |
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08-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 4e0980af2e9eda80cbd82895167e650d83ffe087 |
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13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| bf308cedce5caca4c73e558611a1c8c48687d62e |
|
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Override TargetLoweringBase::isShuffleMaskLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| d593a77b4cf3b81cd657e351e47cad25ee037ce1 |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.
We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| f5926fd844a84adcf1ae4f193146f2877997b82c |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| cbcdcfbda5c60d5ac7a492ef8f90b325b6026bd1 |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
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| 5ac065a79767cc112eba63136183b7103765d0d3 |
|
13-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
mips16 and MipsSETargetLowering is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelLowering.h
|