| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 2ef99c5dff1ab9612f2d65e38f725d809672d2fd |
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15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 243702b95a471ffb7d2374dfad3d7f8b11bee7e7 |
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07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 |
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07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| b1f4f120a50c392c85c6b4388d63e36251fce279 |
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21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add support for mfhc1 and mthc1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 4cef3d818183aafc1b3adfad4140483d9ad1ad86 |
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11-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use function TargetInstrInfo::getRegClass.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 7462a875d9ca4cf7ab30829152175f7448757943 |
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08-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use a helper function which compares the size of the source and
destination operands of an instruction.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 02e168003f45cf8e0a277c6b8c85c1a3032b1dec |
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16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Test case for r182042. Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| ec4db6ab5f64318b1aa2351f7e710569869193e9 |
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16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
invalid instruction sequence.
Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.
mtc1 $f4, $4 # int-to-fp move instruction.
mov.s $f2, $f4 # move contents of $f4 to $f2.
cvt.s.w $f0, $f2 # int-to-fp conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 42f562a1694d24b41f36bbb4d4a086a2a470c625 |
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13-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add option -mno-ldc1-sdc1.
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 6daba286836e6fb2351e7ebc248e18a5c80e8a31 |
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13-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename functions. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| c713e996d305df99cc7fc58c9d8dc1f5fa00518d |
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29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 544cc21cf4807116251a699d8b1d3d4bace21597 |
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30-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Lower EH_RETURN.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| fc4eafa0f490bd06d8191a2f007514b9e3ce0387 |
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23-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make function loadImmediate a member of MipsSEInstrInfo and change it to return
the temporary register that was used to load the immediate. Currently, it always
returns register $at, but this will change if, in the future, we decide to use
another register.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 71746220d3d1c3e8efba35038ac2ff14b4a4d3ae |
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01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 8589010e3d1d5a902992a5039cffa9d4116982c5 |
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01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
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| 0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d |
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31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),
and MipsSEInstrInfo (for mips32/64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEInstrInfo.h
|