| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 6303ef1fb7bba4e6c6823a6732019e0996efe575 |
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22-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Remove unused prototypes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| ef0ccc93203e99077632cec7a0a15b8e1b704aee |
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28-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns
Test case is no breakage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 0ff4287fe2245f417ed78fa535fce360b8b8df23 |
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21-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Add support for selecting CUDA vs OCL mode based on triple
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 5443e7d79044f3198f2da044f1b389b40d9bea6f |
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31-May-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Re-enable support for virtual registers in the final output
Now that 3.3 is branched, we are re-enabling virtual registers to help
iron out bugs before the next release. Some of the post-RA passes do
not play well with virtual registers, so we disable them for now. The
needed functionality of the PrologEpilogInserter pass is copied to a
new backend-specific NVPTXPrologEpilog pass.
The test for this commit is not breaking the existing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| d22367559300c77c73e0ad9e193a33451bf8bf6c |
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20-May-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Add programmatic interface to NVVMReflect pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 7536ecf2916a6a986f0d328069e3a210f34d5ea7 |
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20-May-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.
The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space. Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 3639ce2575660a0e6938d2e84e8bd9a738fd7051 |
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30-Mar-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 7eacad03efda36e09ebd96e95d7891cadaaa9087 |
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12-Feb-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend. Instead,
let the target-independent code do all of the work. The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
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02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| a1514e24cc24b050f53a12650e047799358833a1 |
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04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 09b5df8996b37e61369026d50b44713984adbdc4 |
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05-Jun-2012 |
Yuan Lin <yulin@nvidia.com> |
Fix header file include order in NVPTX backend NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 917644d0c347950f8e77f52797cb89ceb771215d |
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04-May-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Fix a Clang warning in the new NVPTX backend:
In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53:
../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
default: assert(0 && "Unknown condition code");
^
1 warning generated.
The prevailing pattern in LLVM is to not use a default label, and instead to
use llvm_unreachable to denote that the switch in fact covers all return paths
from the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
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| 49683f3c961379fbc088871a5d6304950f1f1cbc |
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04-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:
nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX
The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTX.h
|