| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ef8c4ca252f1289ca8d0a1e6cfd96ca17fe3c5a8 |
|
07-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove getEHExceptionRegister and getEHHandlerRegister.
They haven't been used for a long time. Patch by MathOnNapkins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9bc94276e796d644cb425a7c7d38cc44dbf4e9c1 |
|
30-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add handling for conversions to fast-isel.
Yet another chunk of fast-isel code. This one handles various
conversions involving floating-point. (It also includes some
miscellaneous handling throughout the back end for LWA_32 and LWAX_32
that should have been part of the load-store patch.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 61fc8d670f1e991804c2ab753e567981e60962cb |
|
01-Aug-2013 |
Bill Wendling <isanbard@gmail.com> |
Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| aad2a72c285a48e34d89ba69d24eb624f2b09b0e |
|
18-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Support dynamic allocas with large alignment
Support for dynamic stack alignments in the PPC backend has been unfinished, in
part because it depends on dynamic stack realignment (which I only just
recently implemented fully). Now we can also support dynamic allocas with
higher than the default target stack alignment (16 bytes).
In order to round-up the requested size to the maximum requested alignment, we
need an additional register to hold the rounded-up size. We're already using one
scavenged register to hold the previous stack-pointer value (which needs to be
stored with the signal-safe stdux update), and so when we have dynamic allocas
and a large alignment, we allocate two emergency spill slots for the scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0541722de4beb2e53058dbf4ed1ebf0d96ddd6cb |
|
18-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add base-pointer support to builtin setjmp/longjmp
First, this changes the base-pointer implementation to remove an unnecessary
complication (and one that is incompatible with how builtin SjLj is
implemented): instead of using r31 as the base pointer when it is not needed as
a frame pointer, now the base pointer will always be r30 when needed.
Second, we introduce another pseudo register, BP, which is used just like the FP
pseudo register to refer to the base register before we know for certain what
register it will be.
Third, we now save BP into the jmp_buf, and restore r30 from that slot in
longjmp. If the function that called setjmp did not use a base pointer, then
r30 will be overwritten by the setjmp-calling-function's restore code. FP
restoration (which is restored into r31) works the same way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753d |
|
17-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Implement base pointer and stack realignment
This builds on some frame-lowering code that has existed since 2005 (r24224)
but was disabled in 2008 (r48188) because it needed base pointer support to
function correctly. This implementation follows the strategy suggested by Dale
Johannesen in r48188 where the following comment was added:
This does not currently work, because the delta between old and new stack
pointers is added to offsets that reference incoming parameters after the
prolog is generated, and the code that does that doesn't handle a variable
delta. You don't want to do that anyway; a better approach is to reserve
another register that retains to the incoming stack pointer, and reference
parameters relative to that.
And now we do exactly that. If we don't need a frame pointer, then we use r31
as a base pointer. If we do need a frame pointer, then we use r30 as a base
pointer. The base pointer retains the value of the stack pointer before it was
decremented in the prologue. We then use the base pointer to resolve all
negative frame indicies. The basic scheme follows that for base pointers in the
X86 backend.
We use a base pointer when we need to dynamically realign the incoming stack
pointer. This currently applies only to static objects (dynamic allocas with
large alignments, and base-pointer support in SjLj lowering will come in future
commits).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 33efedc0481c4b0d9866ff526eb1161372b5919f |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 965b20e39c7fd73846e9b6ed55ba90e032ae3b1b |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 75dd57a8f0407be32551cf695e63a106dd051a27 |
|
02-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:
1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.
2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).
3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.
4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.
With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 |
|
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 80ada583f3b40ffb201e54cd57c42f9518039c9e |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 347a5079e18278803bc05b197d325b8580e95610 |
|
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use true offset value in "memrix" machine operands
This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.
This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.
The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions. This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).
Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.
This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.
This change must be made simultaneously in all places that
access machine operands of this type. However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b1fd3cd78f8acd21dbf514b75fef991827c343b6 |
|
15-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f6f8198d85f278ff03aaf32c9db6ae0b3826395c |
|
09-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use virtual base registers on PPC
On PowerPC, non-vector loads and stores have r+i forms; however, in functions
with large stack frames these were not being used to access slots far from the
stack pointer because such slots were out of range for the signed 16-bit
immediate offset field. This increases register pressure because we need a
separate register for each offset (when the r+r form is used). By enabling
virtual base registers, we can deal with large stack frames without unduly
increasing register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 839b9096538f790a2bb060547df24703807cb83b |
|
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPCInstrInfo::FoldImmediate
There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a1f4290ac94f34173e3561c717390de07dccc646 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use ImmToIdxMap.count in PPCRegisterInfo
Code improvement suggested by Jakob (in review of r178450). No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4345e8040f14781d20fd5fa2f7ee3c75fa611fa1 |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8049ab15e4b638a07d6f230329945c2310eca27b |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405 |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d957f957eee12cf26a7160e6015f0a7c2629904f |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructions
There were a few places where kill flags were not being set correctly, and
where 32-bit instruction variants were being used with 64-bit registers. After
r178180, this code was being triggered causing llc to assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 240b7f3324da70937d4fe6d0bd7278ae82849114 |
|
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allocate r0 on PPC
The R0 register can now be allocated because instructions
that cannot use R0 as a GPR have been appropriately marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b7e11e400dabced046e7ec53a66926716563bb36 |
|
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't spill PPC VRSAVE on non-Darwin (even in SjLj)
As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore
VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've
added some asserts to make sure that we're not).
As it turns out, we're not currently handling the Darwin case correctly (I've
added a FIXME in the test case). I've tried adding various implied register
definitions/uses to force the spill without success, so I'll need to address
this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| aa6047d23d8ed55abd8545f5cbe82cd13cbd756a |
|
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Use HWEncoding and TRI->getEncodingValue
As pointed out by Jakob, we don't need to maintain a separate
register-numbering table. Instead we should let TableGen generate the table for
us from the information (already present) in PPCRegisterInfo.td.
TRI->getEncodingValue is now used to access register-encoding values.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 01f99d29c3010f2891e5edb78182216214017063 |
|
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use multiple virtual registers in PPC CR spilling
Now that the register scavenger can support multiple spill slots, and PEI can
use virtual-register-based scavenging for multiple simultaneous registers, we
can use a virtual register for the transfer register in the CR spilling code.
This should eliminate the last place (outside of the prologue/epilogue) where
we depend on the unconditional availability of the r0 register. We will soon be
able to allocate it (in a somewhat restricted sense) as a GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3b196f20fbd24b2c178a51e2473437655dc7066a |
|
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Update PPCRegisterInfo's use of virtual registers to be SSA
PPC's use of PEI's virtual-register-based scavenging functionality had
redefined the virtual registers (it was non-SSA). Now that PEI supports
dealing with instructions with multiple virtual registers, this can be
cleanup up to use multiple virtual registers and keep SSA form.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 02327fefd8a4b7d9f4dc90e066ba70b1d6253c27 |
|
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup some unused reg. scavenger parameters in PPCRegisterInfo
These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7697370adff8983e2a3de493362f0d8c9f9b0e17 |
|
22-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7ee74a663a3b4d4ee6b55d23362f347ed1d390c2 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions
__builtin_{setjmp/longjmp} functional on PPC platforms. The implementation
strategy is similar to that on X86, with the exception that a branch-and-link
variant is used to get the right jump address. Credit goes to Bill Schmidt for
suggesting the use of the unconditional bcl form (instead of the regular bl
instruction) to limit return-address-cache pollution.
Benchmarking the speed at -O3 of:
static jmp_buf env_sigill;
void foo() {
__builtin_longjmp(env_sigill,1);
}
main() {
...
for (int i = 0; i < c; ++i) {
if (__builtin_setjmp(env_sigill)) {
goto done;
} else {
foo();
}
done:;
}
...
}
vs. the same code using the libc setjmp/longjmp functions on a P7 shows that
this builtin implementation is ~4x faster with Altivec enabled and ~7.25x
faster with Altivec disabled. This comparison is somewhat unfair because the
libc version must also save/restore the VSX registers which we don't yet
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 10f7f2a222d0e83dc0c33ad506a7686190c2f7a2 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add support for spilling VRSAVE on PPC
Although there is only one Altivec VRSAVE register, it is a member of
a register class, and we need the ability to spill it. Because this
register is normally callee-preserved and handled by special code this
has never before been necessary. However, this capability will be required by
a forthcoming commit adding SjLj support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct PPC FRAMEADDR lowering using a pseudo-register
The old code used to lower FRAMEADDR tried to replicate the logic in the real
frame-lowering code that determines whether or not the frame pointer (r31) will
be used. When it seemed as through the frame pointer would not be used, the
stack pointer (r1) was used instead. Unfortunately, because the stack size is
not yet known, this does not work. Instead, this change introduces new
always-reserved pseudo-registers (FP and FP8) that are replaced during prologue
insertion with the real frame-pointer register (either r1 or r31).
It is important that this intrinsic always return a valid frame address because
it is used by Clang to store the frame address as part of code generation for
__builtin_setjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a548afc98fd4c61a8dfdd550ba57c37f2cfe3ed9 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 54e57f8cb79bdc23ed8289cf2a558fa7c9602972 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't reserve R31 on PPC64 unless the frame pointer is needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 324972904353594ad4a0cdfc79370f85e9fb9c8f |
|
17-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ce638c8248355452cb7892c9c27807a92176a7b2 |
|
16-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove PPC avoidWriteAfterWrite callback
As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite.
Jakob pointed out in response to r158719 that this callback is currently unused
and so this has no effect (and the speedups that I thought that I had observed
as a result of implementing this function must have been noise).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1c6c61a6089fb2bef47de5ee9a5f4acc34047600 |
|
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use frame-index scavenging for PPC register spilling
Make requiresFrameIndexScavenging return true, and create virtual registers in
the spilling code instead of using the register scavenger directly. This makes
the target-level code simpler, and importantly, delays the scavenging until
after callee-saved register processing (which will be important for later
changes).
Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with
the other related functions). This makes it clear that it always returns true.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4d53e7798c94143a22a9871261b8443592b929d5 |
|
12-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't reserve R2 on Darwin/PPC
Now that only the register-scavenger version of the CR spilling code remains,
we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in
any case where the System V ABI uses it (R0 is special architecturally, and so
is reserved under all common ABIs).
A few test cases needed to be updated to reflect the register-allocation changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7285e8d98c9a44b7efe792462188cfe713dd9641 |
|
12-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC should always use the register scavenger for CR spilling
This removes the -disable-ppc[32|64]-regscavenger options; the code
that uses the register scavenger has been working well (and has been the default)
for some time, and we don't need options to enable the old (broken) CR spilling code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4 |
|
24-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR14364.
This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot().
The proper place to save the frame index for the CR spill slot is in the
PPCFunctionInfo object, not the PPCRegisterInfo object.
No new test cases, as this just reimplements existing function. Existing
tests such as test/CodeGen/PowerPC/crsave.ll are sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
|
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 108fb3202af6f500073cdbb7be32c25d7a273a2e |
|
31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
|
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
|
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 48f63be3684213e16fb657e9bb8c37ae02788e90 |
|
16-Nov-2012 |
Joe Abbey <jabbey@arxan.com> |
Using const cast to alleviate a warning.
A PR is being filed to address some code issues here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 426c2bf5cdd2173e4a33aea8cb92cf684a724f4b |
|
01-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the majority of the next patch in the address space series:
r165941: Resubmit the changes to llvm core to update the functions to
support different pointer sizes on a per address space basis.
Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.
However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.
In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.
In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.
This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2c39b15073db81d93bb629303915b7d7e5d088dc |
|
15-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fb384d61c78b60787ed65475d8403aee65023962 |
|
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f3840d2c16a4ec4c879a8ded402835746de380f8 |
|
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
|
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
|
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6ffb4024d875570a01d6b8db900a0385a491403b |
|
16-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Change unsigned to uint32_t to match base class declaration and other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9d760ae5c6bc1d1482e2824efcf9cb11db1cc16f |
|
12-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
This patch corrects logic in PPCFrameLowering for save and restore of
nonvolatile condition register fields across calls under the SVR4 ABIs.
* With the 64-bit ABI, the save location is at a fixed offset of 8 from
the stack pointer. The frame pointer cannot be used to access this
portion of the stack frame since the distance from the frame pointer may
change with alloca calls.
* With the 32-bit ABI, the save location is just below the general
register save area, and is accessed via the frame pointer like the rest
of the save areas. This is an optional slot, so it must only be created
if any of CR2, CR3, and CR4 were modified.
* For both ABIs, save/restore logic is generated only if one of the
nonvolatile CR fields were modified.
I also took this opportunity to clean up an extra FIXME in
PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless
for the 64-bit ABI, so I removed them for correctness and efficiency.
Fixes PR13708 and partially also PR13623. It lets us enable exception handling
on PPC64.
Patch by William J. Schmidt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fe5b65827f20a61bef817c6421f32b7e05d65caf |
|
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Mark most PPC register classes to avoid write-after-write.
For processors with the G5-like instruction-grouping scheme, this helps avoid
early group termination due to a write-after-write dependency within the group.
It should also help on pipelined embedded cores.
On POWER7, over the test suite, this gives an average 0.5% speedup. The largest
speedups are:
SingleSource/Benchmarks/Stanford/Quicksort - 33%
MultiSource/Applications/d/make_dparser - 21%
MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12%
MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12%
Largest slowdowns:
SingleSource/Benchmarks/Stanford/Bubblesort - 23%
MultiSource/Benchmarks/Prolangs-C++/city/city - 21%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16%
MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ac81cc3282750d724f824547bc519caec0a01bce |
|
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
|
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
|
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f2f6182f6a88cf4b8d8cb95686d68aa14ddb6857 |
|
22-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203.
I don't have a small test case yet, but I'll try to construct one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e46137f498fa81a088f13d24c79242eed3ff45a7 |
|
06-Mar-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Convert PowerPC to register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 17d2dbd5f9dd6c0de86398178f302ef46ba6ec79 |
|
17-Jan-2012 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC RLWINM8 vs RLWINM
No test case: output assembly will be identical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2e95afa04cd1c89de7e4abaeead66cd8e51ec929 |
|
30-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup stack/frame register define/kill states. This fixes two bugs:
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fed4d19eddcedf2a210a0ff3a290f4bf70927452 |
|
10-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 234bb38d6c421ea22229087a9835afe99e531276 |
|
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6d0e014b1fecb35a06e551165614c08edc30194a |
|
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make base register selection used in eliminateFrameIndex 64-bit clean
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d21e930eac3d99dd77ee33ea5826700b4bc97ae8 |
|
06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add RESTORE_CR and support CR unspills
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 16588e794c7528c24fb15ee8e28653bffe78c3da |
|
06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
remove old FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3fd0018af1b692cabfa5a002bf41f1e756aa9dde |
|
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
enable PPC register scavenging by default (update tests and remove some FIXMEs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9489487f9863ca9f0ae9b4572d206910f1c5a581 |
|
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
don't include CR bit subregs in callee-saved list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2e313caa3631e2c94bb6d81429b77a30b116b520 |
|
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add register pressure for CR regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
|
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 768c65f677af3f05c2e94982043f90a1bfaceda5 |
|
22-Nov-2011 |
Hal Finkel <hfinkel@anl.gov> |
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 966aeb5788c242cfaca35c56c0ddc0ff778d4376 |
|
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor PPC target to separate MC routines from Target routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2d28617de2b0b731c08d1af9e830f31e14ac75b4 |
|
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
|
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6844f7bcdec8c2691c8d1067d90e4a02cf658c27 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide more details in tablegen generated MCRegisterInfo ctor function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 |
|
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d |
|
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 951cd021c10966f3ae146588b2466deaef730cb6 |
|
17-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix a few places where 32bit instructions/registerset were used on PPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6e032942cf58d1c41f88609a1cec74eb74940ecd |
|
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use the dwarf->llvm mapping to print register names in the cfi
directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 67dc11352df491a6be79b615f0920ff377bcae5d |
|
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Split ppc dwarf regnums into ppc64 and ppc32 flavours.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c8bd78c16ba0489835f2eb6101d9bdb96301cfe7 |
|
18-Dec-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Restore the behavior of frame lowering before my refactoring.
It turns out that ppc backend has really weird interdependencies
over different hooks and all stuff is fragile wrt small changes.
This should fix PR8749
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 94c5ae08750f314bc3cf1bf882b686244a3927d9 |
|
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move more PEI-related hooks to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d9e3385ced2dc887e2fe8e1c071bd2611e4d3ede |
|
19-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move getInitialFrameState() to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
|
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 33464912237efaa0ed7060829e66b59055bdd48b |
|
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a |
|
27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 38cb1381b5ec8c75242650491c2b8e7e8a302665 |
|
30-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
PPC doesn't supported VLA with large alignment. This was
formerly rejected by the FE, so asserted in the BE; now the FE only
warns, so we treat it as a legitimate fatal error in PPC BE.
This means the test for the feature won't pass, so it's xfail'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
|
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
|
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 42d075c4fb21995265961501cec9ff6e3fb497ce |
|
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the TargetRegisterClass member from CalleeSavedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6f07bd6ae8c2b11e78f351d7751d1e9b32f38a75 |
|
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5f07d5224ddc32f405d7e19de8e58e91ab2816bc |
|
20-May-2010 |
Dale Johannesen <dalej@apple.com> |
The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b92187a4103dca24c3767c380f63593d1f6161a7 |
|
14-May-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8c5358c93675b009ba2d57c3a5980f6bc58ba536 |
|
29-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Make naked functions work on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e566763b1915c7a4821ce95937b763724d271fec |
|
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 82bcd236937b378e56e46bdde9c17a3ea3377068 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
can't be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b35798347ea87b8b6d36155b211016a7769f01ab |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a267b0076e7887f5566e635ba35790f24d4524d9 |
|
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove the MMI pointer from MachineFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 34247a0f356edf45ae3ad9ce04e1f90a77c6dba7 |
|
29-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make isInt?? and isUint?? template specializations of the generic versions. This
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 63d7836267298f5b6cde43f0a89acbabfc109f48 |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
get MMI out of the label uniquing business, just go to MCContext
to get unique assembler temporary labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2e9919a5e5fe76f4b1e3290103c4bfd149ebba9c |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Now that DBG_LABEL is updated, we can finally make MachineMove
contain an MCSymbol instead of a label index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6ffcccab5191ef1dcde876800c24a1f58b3b7ad8 |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the DBG_LABEL MachineInstr to always be created
with an MCSymbol instead of an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 |
|
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ee25bc294204ef326994d4142dd6bea9605e6a63 |
|
12-Feb-2010 |
Dale Johannesen <dalej@apple.com> |
This should have gone in with 26015, see comments there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1797ed50f488f2030f9f9a0ac7426262abf5220a |
|
08-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
its current purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f7801b493ef94c3a7edf8d57cc564f08fce6e624 |
|
24-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Do not store R31 into the caller's link area on PPC.
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b60d5194f52349b74914593919764fe8f4396bdf |
|
24-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Make capitalization of names starting "is" more consistent.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b19a5e9be6097eab311678ccbd9e046c72f7e052 |
|
10-Nov-2009 |
Bill Wendling <isanbard@gmail.com> |
Modify how the prologue encoded the "move" information for the FDE. GCC
generates a sequence similar to this:
__Z4funci:
LFB2:
mflr r0
LCFI0:
stmw r30,-8(r1)
LCFI1:
stw r0,8(r1)
LCFI2:
stwu r1,-80(r1)
LCFI3:
mr r30,r1
LCFI4:
where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:
Leh_func_begin1:
mflr r0
stw r31, 20(r1)
stw r0, 8(r1)
Llabel1:
stwu r1, -80(r1)
Llabel2:
mr r31, r1
Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b58f498f7502e7e1833decbbbb4df771367c7341 |
|
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c0823fe7c679ca8f7d1667a310c2fca97b9402d5 |
|
18-Aug-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify RegScavenger::FindUnusedReg.
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6b16eff207f99bbde3c0f7340452a5287218772c |
|
15-Aug-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for the PowerPC 64-bit SVR4 ABI.
The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2cfd52c507bd5790457a171eb9bcb39019cc6860 |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6a3a1ba97e996bfdc061f9a51bd4cf4915962913 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Various small changes related to the Condition Register on PowerPC.
Don't spill to the CR save area when using the SVR4 ABI for now.
Don't rely on constants assigned for registers to be in order (they aren't assigned in order).
Make sure CR bits are mapped to the corresponding CR field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2a9ddfb903ae3baede7282348afae1f750905248 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Refactor ABI code in the PowerPC backend.
Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ffd0200abfd63177257f949a3674b91dcf87bf23 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Implement the SVR4 ABI for PowerPC.
Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d18e31ae17390d9c6f6cf93d18badf962452031d |
|
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
|
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 022a27e363dcd3b8d4f7e6426559ab29d7a86d70 |
|
26-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
fix warning in -asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0f8b53f19d29013ab18f3d444cea1e6305405611 |
|
03-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 536a2f1f8467a17f6d145bd83f25faae1f689839 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9e79091f1a2c8a4ef0d238dbddaea273d27ef404 |
|
27-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Respect the DisableRedZone flag on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b384ab9ea113ad22a9c7034b98060c7470f0dcc5 |
|
29-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add a RM pseudoreg for the rounding mode, which
allows ppcf128->int conversion to work with
DeadInstructionElimination. This is now turned
off but RM is harmless. It does not do a complete
job of modeling the rounding mode.
Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now. Eventually it should go back in and the
other problems fixed where they're broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c12e5812be4dacc30781db84b045775c46580240 |
|
24-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite logic to figure out whether LR needs to
be saved/restored in the prolog/epilog. We need
to do this iff something in the function stores
into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d5d8191b202c0f96f33c826c93d9796451ff7fca |
|
27-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 36a55023c1daae86afedf6e6672c0adad7bbe5ea |
|
26-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 014278e6a11fa0767853b831e5bf51b95bf541c5 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dc2fbddd9d204e904b8e61d1da1428579e7c55af |
|
11-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Trim unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2d97918ce9a41cbcb97ea5dfaaf740a0e833861a |
|
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Simplify this use of BuildMI. This is also in preparation for
pool-allocating MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
|
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
|
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3541af73b6b8a083cf2d7784438d60e8bcce3883 |
|
14-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Reverse sense of unwind-tables option. This means
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4e1b79459fcf72216cdc42a59953e172c60e15ca |
|
08-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Implement new llc flag -disable-required-unwind-tables.
Corresponds to -fno-unwind-tables (usually default in gcc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e00406281d94ebb9c69b7803311936f07994da43 |
|
02-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Cosmetic changes per EH patch review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1532f3ddd77c362dd5f613af06b4de636e3c5b0e |
|
02-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Recommitting EH patch; this should answer most of the
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b6d5b1439047609c050576f3dc52b722e76bd30b |
|
01-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Revert 49006 for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1544e4713be68edcf042de5aed7265dff7169d9d |
|
01-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Emit exception handling info for functions which are
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.
llvm-gcc generates nounwind in the right places; other FEs
will need to do so also. Given such a FE, -enable-eh should
no longer be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
|
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 71a2cb25ebc818383dd0f80475bc166f834e8d99 |
|
20-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
detabify llvm, patch by Mike Stump!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 82e4289fc7fed755442c215e9d3175c1badb831e |
|
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Disable prolog code that aligns the stack when a
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4a66e9a57e679b4f3243bf2061daf53c70102030 |
|
10-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0404cd97e4f6ebfe4f8057d4e21119d77654dff2 |
|
10-Mar-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Add description of individual bits in CR. This fix PR1765.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2b5fab67c1a2d3ec1184c065e0a6bdaaaec9253a |
|
05-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Removed spurious EnablePPCRS check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 880d0f6018b6928bdcad291be60c801238619955 |
|
05-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Use a command-line option to turn register scavenging on/off for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7194aaf738a1b89441635340403f1c5b06ae18ef |
|
03-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a1998d1cbab495aad05c97b36836788809903b79 |
|
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1b08bbca5592351a940bcd164bdec724ee954326 |
|
01-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| bb81d97feb396a8bb21d074db1c57e9f66525f40 |
|
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0a75538a68cda3bddbda3980ea0128d9f6e6339d |
|
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Makes the same change in ppc backend: avoid inserting prologue before debug labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5080f4d9919d39b367891dc51e739c571a66036c |
|
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename MachineInstr::setInstrDescriptor -> setDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
|
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
|
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
|
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 |
|
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d96428597b9a4bcf3c0702bbb497796b922c2e91 |
|
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
instead of:
_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
for:
void foo(void **X) {
*X = __builtin_return_address(0);
}
on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3fc027df4fca0355717515abb4d6e3753e6dee2a |
|
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
implement __builtin_return_addr(0) on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 73944fb22270697e75408cba52cca276be371a1f |
|
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it is valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5a759616b63a1e5dca76a2170ad0ba6410a11504 |
|
08-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a compilation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8c24e74b02bea8681eac497075e6c27ef15aa2ea |
|
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added canFoldMemoryOperand for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 |
|
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| aee4af68ae2016afc5b4ec0c430e539c5810a766 |
|
02-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove redundant foldMemoryOperand variants and other code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 789db09cde5f0cb2a0a5fc175c1141c760a3e807 |
|
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a crash on invalid code due to memcpy lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b97aec663b1591e71c9ddee6dbb327d1b827eda5 |
|
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3809fbe789cd8d1c5b71d9428401799564aed26c |
|
13-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Completely forgot, that we have some debug information emission on PPC. This should fix
some regressions on ppc nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f191c80cd79ee35e47b5a4feed98d687782dfe85 |
|
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f0a0cddbcda344a90b7217b744c78dccec71851c |
|
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 58184e6878fdab651bc7c9a59dab2687ca82ede2 |
|
18-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f602a2566845dc57444b9d40538c947b5ed23111 |
|
16-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a bug handling frame references in ppc inline asm when the frame offset
doesn't fit into 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 66f0f640820b61cf9db814b6d187bae9faf7279c |
|
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9efce638d307b2c71bd7f0258d47501661434c27 |
|
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fdd9f006bceaa4f24a969d1411917b9558cd156d |
|
14-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 82d25148a7aab0b7e048ab9b774207b3766d1bbf |
|
08-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Add missing index versions of instructions to the map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 64d80e3387f328d21cd9cc06464b5de7861e3f27 |
|
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
|
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 97de9138217d6f76f25100df272ec1a3c4d31aad |
|
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
eliminateFrameIndex() change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6c087e5585b227f3c1d8278304c7cfbc7cd4f6e8 |
|
26-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Match MachineFunction::UsedPhysRegs changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ec58d9f9ddfbfe16ea40822164f340b256c89191 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| cfcd8da70b33118ab3765ed54d63f497321932ce |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Addition to the previous commit for getCalleeSavedRegClasses:
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ef3c030e0e08b7d9446445823f4972fcf18c1ce1 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 82d4264c1fe71480bcaa63235e385a01e38dbe8c |
|
21-Mar-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Protect R31's frame offset from being used by callee-saved registers, when R31
is the frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| bf2c8b3c96f5c885095a10b0fcb29438f92d73c2 |
|
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added MRegisterInfo hook to re-materialize an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 28b3c45109153bc50d3d9e97dccb25ffd043fa50 |
|
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor interface change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5e6df4647e15c50daea9a8a4e7f4f417a266335c |
|
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d313a9b1484c52e3f784de5064ce86bdbd9b26dc |
|
27-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Duplicate use of LR, take 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3d3d6275134f3c6d35a97a028a8556fd2e62243a |
|
27-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9f0bc659c8d2f1e401a9690e4900b0fd2a70bdfe |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
implement support for the linux/ppc function call ABI. Patch by
Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2a27a7598b90359696e31cb665914206f369d1f0 |
|
23-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Don't spill LR as a callee saved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0fa1b6d1b1ce5437c30585baddcba20e691d31e0 |
|
23-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
By default, spills kills the register being stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
|
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b371f457b0ea4a652a9f526ba4375c80ae542252 |
|
19-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a284cbf667e11660840dc7bae3ee9eeaa3c7cbd2 |
|
19-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1207:
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| eceada67286f0d8081c23aedd242f4deeffa85ad |
|
17-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added getReservedRegs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b82313fdc21e8190768addf0f16710b94f0e1441 |
|
01-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support for non-landing pad exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9aa2895360bd3951fc4f204d8699b84fd9ea6ba5 |
|
01-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e078d1a14a2633d5fe5b5b9d9dec90669f5c7082 |
|
30-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Only gather frame info if debug or eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 072200c36dd96b94e772029fd72edf9fa120c467 |
|
29-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Landing pad-less eh for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 44c3b9fdd416c79f4b67cde1aecfced5921efd81 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
for debugging and exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| fab0439c62984b3dc851eb99c31c4f6edda092a1 |
|
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 99403b6964aead64c1039a8f4007437ef96dfd88 |
|
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Tell PEI that PPC will handle stack frame rounding itself.
- Do not round up to max. alignment of stack object if it is > stack alignment.
It will have to be handled with dynamic aligning code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5e73d5bd2e98afda12fa69a7ea83050c69be0d34 |
|
24-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dc77540d9506dc151d79b94bae88bd841880ef37 |
|
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c2b861da18c54a4252fecba866341e1513fa18cc |
|
02-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c88fa749eb85371f54917446b69eb89527fd12b7 |
|
07-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
fix CodeGen/PowerPC/2006-12-07-LargeAlloca.ll on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 51fe9d9aa432cbde6497cad4ea5c8f0276c67b82 |
|
06-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Make it easier for gdb to find the return address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 12a447898a3c68c1a9489f71b82650b46244d00a |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| bdc571b7d578091059aa7bc5c3a190ceb70f9542 |
|
20-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
r13 is the thread pointer on darwin/ppc64, don't allocate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d6fa8c166ace05779ebefe511c615223b12fe7db |
|
17-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Assert unhandled case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2ff5cdb16cea04f562402c2a33732840857a66e2 |
|
17-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Ignore the -disable-fp-elim when the routine is a leaf.
2. Offsets on 64-bit stores are still in bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173 |
|
16-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
This is a general clean up of the PowerPC ABI. Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5e797a5b1c05147bd68c989e8c9b9de37ee06243 |
|
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix ppc64 epilog bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6ce7dc2a97260eea5fba414332796464912b9359 |
|
15-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Properly transfer kill / dead info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5e14b821cdab1fa42baeb2ed1f663597d8345824 |
|
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the PPC regressions last night
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31752 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6a5339ba656805a9cd3bf7d884f99bb87ec84e98 |
|
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 |
|
14-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dfc55885e257f0c73eccadf257814dc2221f10fe |
|
11-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Make sure stack link is set in 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement proper PPC64 prolog/epilog codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4bfd1e9b43f589c7a2e2d45baa226496bb46d865 |
|
11-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Running with frame pointers prevented debugging, external probes and
potentially some system calls/exception handling from working. TOS must always
link to previous frame. This is a short term workaround until alloca scheme is
reworked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3ed469ccd7b028a030b550d84b7336d146f5d8fa |
|
02-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 09e460662a8d7328da1b938d5581a6ef3740b51d |
|
05-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Completely eliminate def&use operands. Now a register operand is EITHER a
def operand or a use operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ce50a165c784d71abf1b2f981be18f867787d972 |
|
29-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Handle callee saved registers in dwarf frame info (lead up to exception
handling.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4c2c9031acd1314440cdd0952182fa39b4efe90d |
|
25-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Fix some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| be6a039ad4c6314176b0834c341a25504fded32e |
|
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
The PPC64 JIT needs register numbers to encode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 804e06704261f233111913a047ef7f7dec1b8725 |
|
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7ffa9abdadd7e51726240b6a8352abda8edde869 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
the offset two bits to the left.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b410dc99774d52b4491750dab10b91cca1d661d8 |
|
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e67304fb7880bd55d194d68b827c0eb2366c0a91 |
|
13-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b47e0897a090d31d952957ba873db6c1e487b50e |
|
12-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix spilling and reloading of CR regs to reload the right values. This fixes
Olden/power (and probably others) with -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0f3ac8d8d4ce23eb2ae6f9d850f389250874eea5 |
|
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3e6a35076ed072525d3eda1945033863b613aef8 |
|
10-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e53f4a055f74bded20d6129b4724ddd17fd199f6 |
|
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Move some methods out of MachineInstr into MachineOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 63b3d7113d93fda622c4954c6b1d046ce029044e |
|
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
There shalt be only one "immediate" operand type!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e45aa737ba902a5caf2f259b3116bfc7d29b2990 |
|
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 426cd7c25fc3f5d064f9e88af0ecad26c836135a |
|
02-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Since we don't handle callee-save CRs right yet, don't allocate them. Also
don't step on R11 in the middle of a function when saving and restoring CRs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f9568d8700d5389799796262cde313bb5c7d588a |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Don't diddle VRSAVE if no registers need to be added/removed from it. This
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
instead of:
_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr
Testcase here: CodeGen/PowerPC/vec_vrsave.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 402504b1ba250839102ba384be0210d248b6e3e8 |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 369503f8412bba4a0138074c97107c09cc4513e0 |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move some knowledge about registers out of the code emitter into the register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f7d2372b7407c7f8966df39a2b5a067c72bd6b9b |
|
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Use a small table instead of macros to do this conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 218629813a47d3e398f37b5be284e179a0ec855f |
|
11-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix SingleSource/UnitTests/Vector/sumarray-dbl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 030514cd96e9b8bb08fd9585d890bd7a5f0dbb77 |
|
11-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix PR727, correctly handling large stack aligments on ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 52fa2449c9c1c8f8373faccb8968588211101e68 |
|
11-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Suppress debug label when not debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4188699f80c233a20b6ddc61570a8a8c1804cb85 |
|
07-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Foundation for call frame information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27491 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4f91a4c497fb1032550b7f163004efc5fce1d7f1 |
|
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Force use of a frame-pointer if there is anything on the stack that is aligned
more than the OS keeps the stack aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4 |
|
28-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Expose base register for DwarfWriter. Refactor code accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 414e682bac7c7fb618aef6bb0caf8ae501f7a2ed |
|
27-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Translate llvm target registers to dwarf register numbers properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f1d78e83356a412e525c30ac90dabf090a8cfc99 |
|
23-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Add support to locate local variables in frames (early version.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ecfe55e65b6a72fddd543c42f2e2df4c96c647ba |
|
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| e261c474cac3fe1ca5bb8528c150095ffb81bbca |
|
17-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 9c09c9ec9dab61450800b42cbf746164aa076b88 |
|
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
teach the ppc backend how to spill/reload vector regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8aa777d5ea8e73e2edf79fd35fd6b5c4e9949ca7 |
|
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
in functions that use a lot of callee saved regs, this can be more than
5 instructions away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 335fd3c7c2057b4e5fedb3161df44d7bc1759791 |
|
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for copying registers. still needed: spilling and reloading them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1877ec9b02511e111998596b9ba9c3a2275d6a92 |
|
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 408396014742a05cad1c91949d2226169e3f9d80 |
|
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ba625726a1fc3b18b6a5386978d33f1943f5df84 |
|
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix an off-by-one error that Nate's eagle eyes caught
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c6d48d36a349f593aab2194c141a1e24da1aec3e |
|
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
functionality change, just code cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 64da172b1435d132ce867dcd5c652577664b55a3 |
|
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
If a function has a non-zero sized frame, use an add to adjust the stack
pointer in the epilog, not a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6da8d99f70826552b3a4e7bd5d1376881574b4b1 |
|
09-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
hasInFlag, hasOutFlag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 171049d10f71fdeffdfd9592243d7af40db86c71 |
|
23-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| ae232e7a1055033436370c0b3aecf054fa44d5e7 |
|
06-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 841d12d9ac489ec33d933af96d77dd4fc2a4cee2 |
|
18-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix the JIT encoding of LWA, LD, STD, and STDU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 |
|
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
|
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 16e71f2f70811c69c56052dd146324fe20e31db5 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PPC32*.h to PPC*.h
This completes the grand PPC file renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2668959b8879097db368aec7d76c455260abc75b |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.h to PPC*.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 26bd0d48a164c419462133270e3ec1c2401a34d7 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPCInstrBuilder.h -> PPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 4c7b43b43fdf943c7298718e15ab5d6dfe345be7 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b91956e7f80141c198d3348f06164b6990913233 |
|
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
like the comment says, enable this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 919c032fa4511468aadc6f50d6ed9c50890710b3 |
|
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 2b5e66fc6e3a72ea1e832a51d0d4aab5eb519065 |
|
30-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove some now-dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5802be13e0eb0f6730b75fee2ea0b3cf6cb148a4 |
|
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
constant fold these calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b48d2cf5eb4a2576314490e43bef0ac0d87732b2 |
|
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
pass extra args
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 6a78c2157ad1ca9608ebdb33a8cc9f86f4a74f2c |
|
17-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement hook for ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| c9fe7508a5e072479d4ab5711c60aa5142c64f10 |
|
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
I forgot that we always spill fp values as 64-bits. Implement spill folding
for FP as well. This triggers a couple dozen times on 177.mesa (for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f38df04c3a0c2aa766fa50b254d2d0fc743f8152 |
|
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem that Nate noticed, where spill code was not getting coallesced
with copies, leading to code like this:
lwz r4, 380(r1)
or r10, r4, r4 ;; Last use of r4
By teaching the PPC backend how to fold spills into copies, we now get this
code:
lwz r10, 380(r1)
wow. :)
This reduces a testcase nate sent me from 1505 instructions to 1484.
Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1463019e84cea6857914cea30c0180ec7289f09f |
|
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
code cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 82972705df381178eea94121dacb6576f6bc9e30 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
teach getClass what a condition reg is
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5087daac23d841a5acb3b6d5a3e7857129ce558c |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Minor cleanups:
* avoid calling getClass() multiple times (it is relatively expensive)
* Allow -disable-fp-elim to turn of frame pointer elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 0b1e641b8217e10b04e767bd0b70933c70cc17d3 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Now that the simple isels are dead, so is this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3f852b45fcfb0dde647eff77f9186378c3f0448a |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
MFLR doesn't take an operand, the LR register is implicit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3d72d148871918cfdd930919cb11767a8c2bb7e6 |
|
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Use the new subtarget support to automatically choose the correct ABI
and asm printer for PowerPC if one is not specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| d29b6aa608d69f19b57ebd2ae630b040b1c4951d |
|
30-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Keep tabs and trailing spaces out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 3dee17581c38ce598376e83666c54a6b5d96ef05 |
|
28-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22530 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 54eed36da595f09c46a46b2b0b15757ea486b4c1 |
|
27-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement the optimization for the Red Zone on Darwin. This removes the
unnecessary SP manipulation in leaf routines that don't need it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7847fcac174bdda94373447676526af1bb1bc630 |
|
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0 |
|
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 7af0248af47fbd86ec65d308adda22ec367accc4 |
|
12-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Initial support for allocation condition registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 340f2907839cc5ecb34c5045cb24ef31588f2a39 |
|
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
have to inform the register allocator it might be stepped on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 04ec80173beda1e4309678b7ff32a5d984fa51cb |
|
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove unnecessary register copy now that regalloc is fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| dfd0e7bc342f1252a2d2088ca5a759b6f04a65d7 |
|
26-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Eliminate usage of MRegisterInfo::getRegClass(physreg)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| da721e74f87c3098bdb1373a7a1c7aef4cf7d574 |
|
27-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Correct some BuildMI arguments for the upcoming simple scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 551ccae044b0ff658fe629dd67edd5ffe75d10e8 |
|
02-Sep-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Changes For Bug 352
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 5709998993cade99e4aeda1c9d44a1bdf54aa720 |
|
27-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Register sizes are in bits, not bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 1f4a132599974d448cbaa4519006d38ce9b1bf16 |
|
22-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Don't hard code the offset of the saved R31 in functions with frame pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| 8edcd8465361f3aa29082e1b1f2a1c88afc0836a |
|
21-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Reduce uses of getRegClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
| f2ccb77ee9d8ab35866dae111fa36929689c7511 |
|
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
|