| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 985ce242a74adf6519609782acbdce2d5464fc22 |
|
16-Oct-2013 |
Eric Christopher <echristo@gmail.com> |
Add support for the VSX target attribute. No functional change
as we don't actually use it to emit any code yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| c0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842 |
|
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark PPC MFTB and DST (and friends) as deprecated
Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| b7fbc5baad87eb5cc143193e66139824993883d3 |
|
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores
For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 953a78084b85ea88cd2b208153a72df70e27133f |
|
19-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| f38cc38fa647d4e72c053c39bbe0cdec1342535f |
|
26-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Support powerpc64le as a syntax-checking target.
This patch provides basic support for powerpc64le as an LLVM target.
However, use of this target will not actually generate little-endian
code. Instead, use of the target will cause the correct little-endian
built-in defines to be generated, so that code that tests for
__LITTLE_ENDIAN__, for example, will be correctly parsed for
syntax-only testing. Code generation will otherwise be the same as
powerpc64 (big-endian), for now.
The patch leaves open the possibility of creating a little-endian
PowerPC64 back end, but there is no immediate intent to create such a
thing.
The LLVM portions of this patch simply add ppc64le coverage everywhere
that ppc64 coverage currently exists. There is nothing of any import
worth testing until such time as little-endian code generation is
implemented. In the corresponding Clang patch, there is a new test
case variant to ensure that correct built-in defines for little-endian
code are generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| a44c37f880c8ca84b7388dd52fb2708495697a18 |
|
16-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Refactoring to support subtarget feature changing
This change mirrors the changes that were made to the X86 and ARM targets to
support subtarget feature changing. As indicated in r182899, the mechanism is
still undergoing revision, and so as with the X86 and ARM targets, there is no
test case yet (there is no effective functionality change).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 1666c6a8c38a2bb2535fe667023b3f0537e03eb1 |
|
03-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] FreeBSD does not require f128 in its data layout string.
Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 827307b95fa909e35a3ddef612f9f50ffcf0963a |
|
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use PPC reciprocal estimates with Newton iteration in fast-math mode
When unsafe FP math operations are enabled, we can use the fre[s] and
frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together
with some Newton iteration, in order to quickly generate floating-point
division and sqrt results. All of these instructions are separately optional,
and so each has its own feature flag (except for the Altivec instructions,
which are covered under the existing Altivec flag). Doing this is not only
faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these
computations to be pipelined with other computations in order to hide their
overall latency.
I've also added a couple of missing fnmsub patterns which turned out to be
missing (but are necessary for good code generation of the Newton iterations).
Altivec needs a similar fix, but that will probably be more complicated because
fneg is expanded for Altivec's v4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 46479197843ecb651adc9417c49bbd1b00acfcb6 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 8049ab15e4b638a07d6f230329945c2310eca27b |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| f5d5c434606161fb017a34cb656fa4aa5a3e076b |
|
29-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| efdd4673d6e78f3d406c5d1f44316aef8a5a9a48 |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| cdc3b74cfb8a1fb3d053106cd8843a39fbb5e2e5 |
|
01-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
LLVM enablement for some older PowerPC CPUs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 5bb16fdbb363abee2b9495116ff1a97568460cae |
|
30-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add definitions for the PPC a2q core marked as having QPX available
This is the first commit of a large series which will add support for the
QPX vector instruction set to the PowerPC backend. This instruction set is
used on the IBM Blue Gene/Q supercomputers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| d3427d3f4094767884f3eafdef3d60c7f5038197 |
|
29-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add isBGQ method to PPCSubtarget
This function will be used in future commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| a1514e24cc24b050f53a12650e047799358833a1 |
|
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| baafdeae0b1551c73f1a0052414530e061029e14 |
|
29-Oct-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCSubtarget.h: Add explicit braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 19ad3e2fa7cee27dd712157f5515c178a27bde8b |
|
29-Oct-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCSubtarget.h: Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 01d013ec043407a558b8b87f75ec207336e8a4ae |
|
29-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch adds alignment information for long double to the 64-bit PowerPC
ELF subtarget.
The existing logic is used as a fallback to avoid any changes to the Darwin
ABI. PPC64 ELF now has two possible data layout strings: one for FreeBSD,
which requires 8-byte alignment, and a default string that requires
16-byte alignment.
I've added a test for PPC64 Linux to verify the 16-byte alignment. If
somebody wants to add a separate test for FreeBSD, that would be great.
Note that there is a companion patch to update the alignment information
in Clang, which I am committing now as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 621b77ade2ff46d1d8594bddee6931b2f4a14706 |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 009f7afbeb77d1cc8e962bac7057b73b6d39d62f |
|
23-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for the PPC isel instruction.
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| bd5cafd9bbba2180e7179436fb29071201d5ea9f |
|
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 622382fc5effb34ccad6e029c9612c598a3dc050 |
|
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add POWER6 and POWER7 CPU types to the PPC backend.
No functional change; these will be used by upcoming scheduler enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 70272aac56830dc4a86de7bf12e591c812ee285b |
|
02-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
The binutils for the IBM BG/P are too old to support CFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 4d989ac93ce608057fb6b13a4068264ab037ecd5 |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 64c34e253563a8ba6b41fbce2bb020632cf65961 |
|
02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
update PPC 940 hazard rec. to function in postRA mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 |
|
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC 440 scheduler and some associated tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| b272332e6120413b13dcaef7a5415783a99df073 |
|
03-Jul-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Make the i64 and f64 be 64bit ABI aligned in the target description.
This is what both the ABI and clang says.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 385e930d55f3ecd3c9538823dfa5896a12461845 |
|
02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
|
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| ab8be96fd30ca9396e6b84fdddf1ac6208984cad |
|
29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 558692fd0a31d4d3ae4fd09a3a02f80da2e44e5c |
|
20-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 18a0929a7a0b87cc50565250e33c33925a57d498 |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/PPC: Kill off DarwinVers, which is now dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 869eca129b2560a59b8aa0e8fd57b5d8f7de1f96 |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/PPC: Add a TargetTriple field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 0e3a1a8f8fbe34d47c83d19c8b11a3bfdcacad00 |
|
04-Aug-2010 |
Torok Edwin <edwintorok@gmail.com> |
Use indirect calls in PowerPC JIT.
See PR5201. There is no way to know if direct calls will be within the allowed
range for BL. Hence emit all calls as indirect when in JIT mode.
Without this long-running applications will fail to JIT on PowerPC with a
relocation failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 59a9178fbedb88427c8ff9e5fa7a8f2038f80a2e |
|
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
indicate what the native integer types for the target are.
Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 6b16eff207f99bbde3c0f7340452a5287218772c |
|
15-Aug-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for the PowerPC 64-bit SVR4 ABI.
The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 74da671c36cdaa6bea3fa7889dc9aeab572b609c |
|
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate asmflavor from subtarget, PPCTAI is the only client
and each callee knows that it returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 3be03406c9c3b2075d5ae416499af2f15f703d6f |
|
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 2a9ddfb903ae3baede7282348afae1f750905248 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Refactor ABI code in the PowerPC backend.
Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 41a024385f1220eadc48b48cb4c044a5fbc1b361 |
|
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| ded2b20e7e5399c90ee7cb560e70ab92ba620dcd |
|
27-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Alignment values for i64 and f64 on ppc64 were wrong,
possibly for the reason suggested by the comment.
No wonder it didn't work very well. This unblocks
bootstrap with assertions on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 2f6fea90a54787d873cfc25f33668cb4cc7d6e1e |
|
19-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3202.
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| db01c8ba26f288636d3f574a96af3499ee6d2579 |
|
15-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite tblgen handling of subtarget features so
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to. Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 564da5d646dfeb56df931b42fefa7c5f2591057e |
|
02-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
leopard and above support alignment for common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 8c1e6a119a68b258365677a9ee5176af3525a26f |
|
03-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
long double patch 2 of N. Handle it in TargetData.
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| ec58d9f9ddfbfe16ea40822164f340b256c89191 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 456bc87e78af18331b9579069a059c723da517d9 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Improve JIT support for linux/ppc: Patch by Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| d2b7cec527a0efa552628378ebca7a8ca63bb45d |
|
14-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Generalize TargetData strings, to support more interesting forms of data.
Patch by Scott Michel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 74fc22d484f053908c12861bae82a6460b00326c |
|
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Double and long preferred alignment set to 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| bd92d81d22c90433e968077aa0a4157d631d6365 |
|
19-Jan-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Needed to build on PPC Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| cb9009993b20ab41fab56518d666ba69533db4b3 |
|
16-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Instead of yet another enum indicating the "assembly language flavor",
just use the one that's in the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| c35010d3a44397dd04ed3bff5287f9c718dacd4a |
|
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Honor cpu directive, take two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 57fc62c8d2bf056b0d2a0e3d1b82b3b787b899f8 |
|
12-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Another step forward in PPC64 JIT support: we now no-longer need stubs
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 442b9a69811b68bc169b3eb9305fca7adfb325eb |
|
11-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
getInstrItineraryData shouldn't copy the itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| ba4733d901b1c2b994f66707657342b8c81c92bc |
|
15-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Remove what little AIX support we have. It has never been tested and isn't
complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 7c1fb5f08c7c1e9550b7eb2d8d32c93648a6d08e |
|
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Document the subtarget features better, make sure that 64-bit mode, 64-bit
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| a7a5854f1c3710f4bedf069be4771b81e449f2a3 |
|
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 94de9a8951339536af1cc0ca947bc1005eb8f5f3 |
|
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
that is currently just like ppc32 :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| bf751e2d6f3779b78c9a00fb9887e1b25faa880c |
|
28-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 6cee630070b1a7183ed56a8404e812629f5ca538 |
|
01-Nov-2005 |
Jim Laskey <jlaskey@mac.com> |
Allow itineraries to be passed through the Target Machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 2cbc207c76f10716b61c466f56b5b9fccbb80f4e |
|
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Typo made worse x 2 - take 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| ff2fcee846addcb64b6fad0efa339949d26b7390 |
|
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Typo x 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 581a8f79bc1ac3cbe5d621f0b4a0252ab2890bc1 |
|
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Give full control of subtarget features over to table generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 9d2b817fcbad2ee615be323c38f1ed66d81964dc |
|
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Do the right thing and enable 64 bit regs under the control of a subtarget
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
|
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 68fd4866ded709e53672cfc303e8303e212e3fba |
|
29-Sep-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
copy and paste error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| d401dff7966ca3ac644cddcda4f1e6d30074923e |
|
06-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Add accessor for 64bit flag, so that we can tell when it is safe to
generate the fun in-register fp<->long instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 1e9de3ed2db440fac99e5cc85b7d98b0a23a2727 |
|
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
Remove the -enable-gpopt option which is subsumed by feature flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| b1e1180ca0b32f37aa74d7ad703eeaf91e66c8fa |
|
01-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Use SubtargetFeatures in llc/lli.
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 3c304a3ba18a040d3c3dbd15ab69da5543cdbd54 |
|
06-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|
| 8c00f8cdc7ae0cdd18d91b3a31a70da0f78aa04f |
|
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add Subtarget support to PowerPC. Next up, using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCSubtarget.h
|