| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| b570599c8f048c2eda78edb9304bd8e283fb6908 |
|
18-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Enable the IR structurizer by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| ef37e453c407675ab5934d2f6bcec706b7810878 |
|
18-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add a SubtargetFeatture for disabling the ifcvt pass.
This is useful when writing test cases for the AMDIL structurizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| f95b1621887e3409ceec2db47e1b44271d934735 |
|
23-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Fix handling of vector kernel arguments
The SelectionDAGBuilder was promoting vector kernel arguments to legal
types, but this won't work for R600 and SI since kernel arguments are
stored in memory and can't be promoted. In order to handle vector
arguments correctly we need to look at the original types from the LLVM IR
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 04c559569f87d755c3f2828a765f5eb7308e6753 |
|
22-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Simplify handling of private address space
The AMDGPUIndirectAddressing pass was previously responsible for
lowering private loads and stores to indirect addressing instructions.
However, this pass was buggy and way too complicated. The only
advantage it had over the new simplified code was that it saved one
instruction per direct write to private memory. This optimization
likely has a minimal impact on performance, and we may be able
to duplicate it using some other transformation.
For the private address space, we now:
1. Lower private loads/store to Register(Load|Store) instructions
2. Reserve part of the register file as 'private memory'
3. After regalloc lower the Register(Load|Store) instructions to
MOV instructions that use indirect addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 36d96337f7bf17a35c44403ca5df4023be7f0157 |
|
13-Oct-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600/SI: Add SinkingPass before ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| de28bdadff78ceea6bb05e23dc3b4cc92fa359ed |
|
10-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Use StructurizeCFGPass for non SI targets
StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
shader from shadertoy (which exhibits complex control flow constructs) to works
correctly with respect to CFG handling (and allow us to detect potential bug in
other part of the backend).
We provide a cmd line argument to disable the pass for debug purpose.
Patch by: Vincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| dfef7cbfc6a96d129b99750f554c7dbc000d3228 |
|
01-Oct-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: add a pass that merges clauses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| f45edcc3818757234c20d4d5975c0b992bf1f95e |
|
20-Sep-2013 |
Andrew Trick <atrick@apple.com> |
Allow subtarget selection of the default MachineScheduler and document the interface.
The global registry is used to allow command line override of the
scheduler selection, but does not work well as the normal selection
API. For example, the same LLVM process should be able to target
multiple targets or subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 68db37b952be497c94c7aa98cf26f3baadb5afd3 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Convert v16i8 resource descriptors to i128
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.
This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:
https://bugs.freedesktop.org/show_bug.cgi?id=66805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 3492eefa4b2509c87598678a6977074a3f6a50e6 |
|
07-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use VSrc_* register classes as the default classes for types
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:
SGPR = COPY VGPR
Will now be emitted like this:
VSrC = COPY VGPR
This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur. Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 01d7203ef8316fdd71c3cec59f8e68fb869e0dbf |
|
06-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Factor FlattenCFG out from SimplifyCFG
Patch by: Mei Ye
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 57e6b2d1f3de0bf459e96f7038e692d624f7e580 |
|
27-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
Merge consecutive if-regions if they contain identical statements.
Both transformations reduce number of branches. The transformation
is guarded by a target-hook, and is currently enabled only for +R600,
but the correctness has been tested on X86 target using a variety of
CPU benchmarks.
Patch by: Mei Ye
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 12140450fa9c768f022946e2f355816ba8cca31d |
|
19-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Simplify AMDILCFGStructurize by removing templates and assuming single exit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| f2cfef8172fd2eceb036b8caff50623a189ba2ff |
|
09-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Do not predicated basic block with multiple alu clause
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.
NOTE: This is a candidate for the stable branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| ad966ea7a81a538425d5319f6d8568e460639e54 |
|
19-Jun-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Move StructurizeCFG out of R600 to generic Transforms.
Register it with PassManager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 3ff0abfaabc2c7f604d490be587b9c27e7c91ac0 |
|
07-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Rework subtarget info and remove AMDILDevice classes
This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| f3d6e32c09ac73b49628f5ec7066af5eca2737b5 |
|
05-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Add a pass that merge Vector Register
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 6afb65c2b709cfa078d0f6f6c5feceb2abab8036 |
|
05-Jun-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| bbbdba891b8a90d676fd251f2a4bae3bef061550 |
|
05-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Add a pass that merge Vector Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 5110102f9f7e7ddcd74d3bce1e5de3f898ba5e7f |
|
23-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix a leak on the r600 backend.
This should bring the valgrind bot back to life.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| d3293b49f9c7af741d2edd3062499fb50db0e89b |
|
17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Improve texture handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
|
13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 58e87a68a8593b0ae133d0bac17ae2027519a204 |
|
10-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.
https://bugs.freedesktop.org/show_bug.cgi?id=64201
Reviewed-by: Christian König <christian.koenig@amd.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 25f259cde28860ea76c2f5628010968945a28edb |
|
30-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Packetize instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 08001a5a1565adb8ce18b97537dd75075992d09a |
|
01-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Add support for native control flow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 8e59191eb8033133f5b2923d2056d4362af913ce |
|
01-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Emit CF_ALU and use true kcache register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| cc22640c4c8f0bc5d1e37b4ddcdf9e7c873e4383 |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: rework input interpolation v2
v2: update CMakeLists.txt as well
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 62f38ca141f87ff3ed9334fbe6a5e1c45d40ca86 |
|
05-Mar-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: initial scheduler code
This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently
it only tries to expose more parallelism for ALU instructions (this also
makes the distribution of GPR channels more uniform and increases the
chances of ALU instructions to be packed together in a single VLIW group).
Also it tries to reduce clause switching by grouping instruction of the
same kind (ALU/FETCH/CF) together.
Vincent Lejeune:
- Support for VLIW4 Slot assignement
- Recomputation of ScheduleDAG to get more parallelism opportunities
Tom Stellard:
- Fix assertion failure when trying to determine an instruction's slot
based on its destination register's class
- Fix some compiler warnings
Vincent Lejeune: [v2]
- Remove recomputation of ScheduleDAG (will be provided in a later patch)
- Improve estimation of an ALU clause size so that heuristic does not emit cf
instructions at the wrong position.
- Make schedule heuristic smarter using SUnit Depth
- Take constant read limitations into account
Vincent Lejeune: [v3]
- Fix some uninitialized values in ConstPair
- Add asserts to ensure an ALU slot is always populated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| d4c3e566922e04296c29cc4a1695e06a2b53bcb7 |
|
05-Mar-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.
Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case
and taking them in account for scheduling is difficult for no real benefit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| e25e490793241e471036c3e2f969ce6a068e5ce1 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use V_ADD_F32_e64
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 |
|
06-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Support for indirect addressing v4
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| cc38cad53cfebcdfc3b4fbdd924c2a92cd9dacc0 |
|
05-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Fold remaining CONST_COPY after expand pseudo inst
Patch by: Vincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 9f7818d9bdfce2e9c7a2cbe31490a135aa6d1211 |
|
23-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: rework handling of the constants
Remove Cxxx registers, add new special register - "ALU_CONST" and new
operand for each alu src - "sel". ALU_CONST is used to designate that the
new operand contains the value to override src.sel, src.kc_bank, src.chan
for constants in the driver.
Patch by: Vadim Girlin
Vincent Lejeune:
- Use pointers for constants
- Fold CONST_ADDRESS when possible
Tom Stellard:
- Give CONSTANT_BUFFER_0 its own address space
- Use integer types for constant loads
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 82d3d4524f2595b2dce617e963b6d67876b4f9ba |
|
18-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Proper insert S_WAITCNT instructions
Some instructions like memory reads/writes are executed
asynchronously, so we need to insert S_WAITCNT instructions
to block before accessing their results. Previously we have
just inserted S_WAITCNT instructions after each async
instruction, this patch fixes this and adds a prober
insertion pass.
Patch by: Christian König
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| 6b7d99d47321ebb478b22afd2e317fe89d2149db |
|
19-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
R600: New control flow for SI v2
This patch replaces the control flow handling with a new
pass which structurize the graph before transforming it to
machine instruction. This has a couple of different advantages
and currently fixes 20 piglit tests without a single regression.
It is now a general purpose transformation that could be not
only be used for SI/R6xx, but also for other hardware
implementations that use a form of structurized control flow.
v2: further cleanup, fixes and documentation
Patch by: Christian König
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|
| f98f2ce29e6e2996fa58f38979143eceaa818335 |
|
11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
|