| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| c3cee57f7d20f69a84fd88464ed8cf050e63c7ad |
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09-Sep-2013 |
Bill Wendling <isanbard@gmail.com> |
Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.
Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.
<rdar://problem/13623355>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| 879b071bf539163f90a5ef449d3e6a9ec73faa2f |
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23-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
R600: Hide symbols of implementation details.
Also removes an unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| 3a63bf27c54e0975a219f723381494f2be52c7e2 |
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15-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Emit ELF formatted code rather than raw ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| 251040bc18eedfa56d01fe92836e55cfd8c5d990 |
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08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| 3ee6391e0cddf8d94e2fa441d661c23e494a8489 |
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17-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
R600: BB operand support for SI
Patch by: Christian König
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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| f98f2ce29e6e2996fa58f38979143eceaa818335 |
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11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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