| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/R600Defines.h
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| 8e78012457682d335ee97cf2859dfe03b7e2ae93 |
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26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for i8 and i16 local memory stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| e7ac2ed1c268891a856ab38db1e34372a79da86a |
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16-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add IsExport bit to TableGen instruction definitions
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| e3d4cbc7d25061441adafa47450a31571c87bf85 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| 7e9381951eb4dadf9c59257786416ac51a6a6c09 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add ALUInst bit to tablegen definitions v2
v2:
- Remove functions left over from a previous rebase.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| 5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0 |
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25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Use new getNamedOperandIdx function generated by TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| 4ed9917147b1d1f2616f7c941bbe6999b979f510 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| 32c76107d029c1cad5935d08cdcde6139cf874bb |
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06-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Remove dead code from the CodeEmitter v2
v2:
- Replace switch statement with TSFlags query
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| f07b5373d7493d29cd758ababf135c2d0d8da127 |
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06-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Emit config values in register / value pairs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| e332e3559b5c09040de1528920006756e0962d6a |
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30-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Add a Bank Swizzle operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| 631591e6f3e5119d8a8b1c853279bc4ac7ace4a0 |
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30-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 |
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06-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Support for indirect addressing v4
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| 9f7818d9bdfce2e9c7a2cbe31490a135aa6d1211 |
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23-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: rework handling of the constants
Remove Cxxx registers, add new special register - "ALU_CONST" and new
operand for each alu src - "sel". ALU_CONST is used to designate that the
new operand contains the value to override src.sel, src.kc_bank, src.chan
for constants in the driver.
Patch by: Vadim Girlin
Vincent Lejeune:
- Use pointers for constants
- Fold CONST_ADDRESS when possible
Tom Stellard:
- Give CONSTANT_BUFFER_0 its own address space
- Use integer types for constant loads
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
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| f98f2ce29e6e2996fa58f38979143eceaa818335 |
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11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Defines.h
|