cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749. Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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04c559569f87d755c3f2828a765f5eb7308e6753 |
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22-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Simplify handling of private address space The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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de28bdadff78ceea6bb05e23dc3b4cc92fa359ed |
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10-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Use StructurizeCFGPass for non SI targets StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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ac779b8494ad3d2f2ea40cb566552c0fb1b17363 |
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12-Sep-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Don't use trans slot for instructions that read LDS source registers This fixes some regressions in the piglit local memory store tests introduced by recent commits which made the scheduler aware of the trans slot. It's not possible to test this using lit, because there is no way to determine from the assembly dumps whether or not an instruction is in the trans slot. Even if this were possible, the test would be highly sensitive to changes in the scheduler and might generate confusing false negatives. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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bb25a01d232257b134f1f6a5810116cbb04b95b1 |
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04-Sep-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Non vector only instruction can be scheduled on trans unit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 |
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31-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Revert "R600: Non vector only instruction can be scheduled on trans unit" This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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98ce62780ea7185ba710868bf83c8077e8d7f6d6 |
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31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Non vector only instruction can be scheduled on trans unit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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a92f8ee2f3ee12d26f6ed0720c763021cfa22ca8 |
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31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Don't mix LDS and non-LDS instructions in the same group There are a lot of restrictions on instruction groups that contain LDS instructions, so for now we will be conservative and not packetize anything else with them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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f2cfef8172fd2eceb036b8caff50623a189ba2ff |
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09-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Do not predicated basic block with multiple alu clause Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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8f9fbd67c3f803f7397843fdf4b2a7b7ca10189e |
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29-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Support schedule and packetization of trans-only inst git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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e3d4cbc7d25061441adafa47450a31571c87bf85 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add local memory support via LDS Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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cedcfee405a22b245e869abe8609f094df34085a |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for GROUP_BARRIER instruction Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0 |
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25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Use new getNamedOperandIdx function generated by TableGen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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0c922879854f5a6ee60283b99c68089f76f94778 |
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03-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: 3 op instructions have no write bit but the result are store in PV git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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5c35290fa35ae234fed02496404cb0fc37e1c8a5 |
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23-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move passes from namespace llvm into anonymous namespaces. Sort includes while there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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4ed9917147b1d1f2616f7c941bbe6999b979f510 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Relax some vector constraints on Dot4. Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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25c209e9a262b623deca60fb6b886907e22c941b |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Some factorization git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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152ebee8f3e8506dbf693ecdb2d8ab335eeae4d9 |
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02-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: If previous bundle is dot4, PV valid chan is always X git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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25f259cde28860ea76c2f5628010968945a28edb |
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30-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Packetize instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600Packetizer.cpp
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