| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
|
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| adadf887cb57f8281ec23f846a946fb59bd0a0d7 |
|
19-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
X86: FrameIndex addressing modes do have a base register.
When selecting the DAG (add (WrapperRIP ...), (FrameIndex ...)), X86 code had
spotted the FrameIndex possibility and was working out whether it could fold
the WrapperRIP into this.
The test for forming a %rip version is notionally whether we already have a
base or index register (%rip precludes both), but we were forgetting to account
for the register that would be inserted later to access the frame.
rdar://problem/15024520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 07ad0c4c99cb704d4f3e1bc1ba3bb1b194efe572 |
|
15-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Use MVT instead of EVT in X86ISelDAGToDAG since all the types should be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5a0910b34959fa8e0b5a49908f51a15bc3a48069 |
|
15-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 842b1bdd940e365898581d6ff54794b8fa1a13c9 |
|
09-Jul-2013 |
Jim Grosbach <grosbach@apple.com> |
X86: Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 872bb3681009ab31965228305bc0452e84569355 |
|
27-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't cast away constness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ba54bca472a15d0657e1b88776f7069042b60b4e |
|
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e5609f37323b105c7720d5d423a9203d1e869c29 |
|
10-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
X86: Stop LEA64_32r doing unspeakable things to its arguments.
Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.
This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6a2e7ac0b6647a409394e58b385e579ea62b5cba |
|
06-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9a508ef64a194f0f4a3362c55a6e33bec18b7554 |
|
05-Jun-2013 |
Michael Liao <michael.liao@intel.com> |
[PATCH] Fix VGATHER* operand constraints
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."
---
[1] http://software.intel.com/sites/default/files/319433-014.pdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3ba14fab1b653015428055ddce4205682885ff3f |
|
01-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
Revert r183069: "TMP: LEA64_32r fixing"
Very sorry, it was committed from the wrong branch by mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4d3ace4da0a000428ad5baea72c82e585fcd531c |
|
01-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
TMP: LEA64_32r fixing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 85c622d6b6633c19d2729e82453c6c7f56ee7cd9 |
|
01-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.
This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 34431085def8f67db07ccb7485138176bba5a90a |
|
01-Jun-2013 |
Eric Christopher <echristo@gmail.com> |
Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it
seems to have caused PR16192 and other JIT related failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 43887bf3e62daab1c8571be8a73741c9275f866a |
|
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it was
allocated as setting a GR64, but the eventual instruction ("movl") only set a
GR32. This converts it into a so-called "MOV32ri64" which still accepts a
(appropriate) 64-bit immediate but defines a GR32. This is then converted to
the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 15983b80a0ceb224b74d2ee5ef53d3eed37dc03b |
|
30-May-2013 |
Tim Northover <tnorthover@apple.com> |
X86: use sub-register sequences for MOV*r0 operations
Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions,
it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg")
and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is
smaller and partial register updates can sometimes be avoided.
Until recently, this sequence was a barrier to rematerialization though. That
should now be fixed so it's an appropriate time to make the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dd0fb018a7cd2214c7bc5c6c767f626f99b47ba9 |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 3/4.
Remove the old IR ordering mechanism and switch to new one. Fix unit
test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
|
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c706dc7ae7b50920b863af47634078482de75b26 |
|
13-Apr-2013 |
Andrew Trick <atrick@apple.com> |
Catch another case where SD fails to propagate node order.
I need to handle this for the test case in my following scheduler
commit.
Work is already under way to redesign the mechanism for node order
propagation because this case by case approach is unmaintainable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 816f6d0ac76c0ffb2ea9ecb72349d5d7d0fa8d1a |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Skip moving call address loading into callseq when targets prefer register indirect call.
To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.
To prevent that, such moving is disabled when target favors register
indirect call.
Previous workaround disabling CALL32m/CALL64m insn selection is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 608e3554847ef35995b7310ba8acd43ab861e3f0 |
|
19-Feb-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Add obvious constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 50c023d4960ee492014391b6b84a259e1e02da82 |
|
13-Jan-2013 |
Nick Lewycky <nicholas@mxc.ca> |
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 700843ec2c4cb4aa442377809c6ebb3ae3030c61 |
|
06-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR14739. It's not safe to fold a load into a call across a store. Thanks to Nick Lewycky for the initial patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 18d0f12aa8761fab3ac83376b14d0b16b4e5e934 |
|
05-Jan-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Move 'break' to the right place to prevent fallthru. There is no test-case
because conditions in the next case prevented from doing anything nasty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
|
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
|
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3427f0aa7ca6979c8646a9b18c1bdab41dcb6eb0 |
|
15-Nov-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Remove unneeded #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9c7ae01f390b3d7c0fab562e69aba253d28a6dfb |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6c0e04c823cf4034214b050e338c99a401edd2ac |
|
16-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add __builtin_setjmp/_longjmp supprt in X86 backend
- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also
used as a light-weight replacement of setjmp/longjmp which are used to
implementation continuation, user-level threading, and etc. The support added
in this patch ONLY addresses this usage and is NOT intended to support SjLj
exception handling as zero-cost DWARF exception handling is used by default
in X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
|
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2a2947885aea4e96eb6b776c1558f625506a26d2 |
|
05-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r165072. Try a different approach: only move the load when it's going to be folded into the call. rdar://12437604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2b87e06d265e83d61873075e8f8e9c51430ff332 |
|
03-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a serious X86 instruction selection bug. In
X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside
callseq_start / callseq_end so it can be folded into a call. This can
create a cycle in the DAG when the call is glued to a copytoreg. We
have been lucky this hasn't caused too many issues because the pre-ra
scheduler has special handling of call sequences. However, it has
caused a crash in a specific tailcall case.
rdar://12393897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bc96bcdaf9bd4d61cae955cf7b54c108947208cd |
|
28-Sep-2012 |
Manman Ren <mren@apple.com> |
X86: when replacing SUB with TEST in ISelDAGToDAG, only replace uses of the
second output of SUB with first output of TEST.
PR13966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
|
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0832a72a662043efad72f090023a19156974fc0c |
|
26-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add MULX code generation support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e5e8f7656a3b37c4c0c7936f78fa2586f06fbb9a |
|
25-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add missing i64 max/min/umax/umin on 32-bit target
- Turn on atomic6432.ll and add specific test case as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cd9ede9fc00be3f13e6f450b63419ed80f225d48 |
|
19-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArith
- Merge the processing of LOAD_ADD with other atomic load-arith
operations
- Separate the logic getting target constant for atomic-load-op and add
an optimization for atomic-load-add on i16 with negative value
- Optimize a minor case for atomic-fetch-add i16 with negative operand. Test
case is revised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0767dc546ec94f46b5c4292645dbf096fe3100cf |
|
13-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r163761 "Don't fold indexed loads into TCRETURNmi64."
The patch caused "Wrong topological sorting" assertions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| aa0cfea9a439cb8de1ff288bd6db9b4a86c4da7b |
|
13-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't fold indexed loads into TCRETURNmi64.
We don't have enough GR64_TC registers when calling a varargs function
with 6 arguments. Since %al holds the number of vector registers used,
only %r11 is available as a scratch register.
This means that addressing modes using both base and index registers
can't be folded into TCRETURNmi64.
<rdar://problem/12282281>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6c7ccaa3fd1d6e96d0bf922554b09d2b17c3b0e3 |
|
12-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b720be6a50f4e1b3280d2b029ee38dda14577525 |
|
12-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"
No functional change. Update r163339.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 77e300e8f0b8db8eec448cae9c87d7c5bfad9757 |
|
06-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with "ifndef NDEBUG"
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1144af3c9b4da48cd581156e05b24261c8de366a |
|
25-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2865422a4d03f3676545825142f8a262084c5f47 |
|
11-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a couple default: llvm_unreachable() to some switch statements. Fix a bad message in an existing llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 39ad568c62f5120faec29f69d3d614303a1f992d |
|
08-Aug-2012 |
Manman Ren <mren@apple.com> |
X86: enable CSE between CMP and SUB
We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.
Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.
rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4feb647283db0ea4660941d3ac4202947b1ce196 |
|
06-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a20e1e7ef596842127794372244fd5c646f71296 |
|
01-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 23a62cbaf5ea046c8f6e5581c460f8618396d6eb |
|
24-Jul-2012 |
David Chisnall <csdavec@swan.ac.uk> |
ELF does not imply GNU/Linux. Do not assume GNU conventions just because we
are targeting an ELF platform. Only fold gs-relative (and fs-relative) loads
if it is actually sensible to do so for the target platform.
This fixes PR13438.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5aba78bd8056dc407bcbce4080ffcd12b13c7342 |
|
12-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 51e89c0d6ab7ec7d6c816c845447b1c3267775a3 |
|
01-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Reduce code size by using a second switch statement to avoid extra calls to SelectAtomic64. Also catch cases where SelectAtomic64 fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 65b382cf9172c76f09695b9dbae25ddf094e97c9 |
|
01-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a break to the end of case statement missed in r159501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 15d39adbcaf5e9e779e66ebd252502142c683e18 |
|
01-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Fix a crash on release builds if gather intrinsics are passed a non-constant value for the last argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| de6e484c15e71d4ed6a1ece3537daf78721d07a3 |
|
01-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Use a second switch statement to reduce number of calls to SelectGather in code. Reduces code size a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 40307c7dbe2d104784763c28697d7926793674af |
|
29-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add more GATHER intrinsics in LLVM
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 |
|
26-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 88097819fca78aa9f5d1607d0e6271a096c5bd07 |
|
23-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6100366c2f543ea1bc26b3c22b7543237bd79274 |
|
16-May-2012 |
Evan Cheng <evan.cheng@apple.com> |
Avoid creating a cycle when folding load / op with flag / store. PR11451474. rdar://11451474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f0bcecc0d59455add4367204a198949d807fe1da |
|
12-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Generalize r153635 to deal with TokenFactor chains; also clean up the logic and fix the tests. rdar://11069732, rdar://11236106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ab5a55e11870c8f5aaa8e4b973092bf66f9d6742 |
|
09-Apr-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Cleanup and relax a restriction on the matching of global offsets into
x86 addressing modes. This allows PIE-based TLS offsets to fit directly
into an addressing mode immediate offset, which is the last remaining
code quality issue from PR12380. With this patch, that PR is completely
fixed.
To understand why this patch is correct to match these offsets into
addressing mode immediates, break it down by cases:
1) 32-bit is trivially correct, and unmodified here.
2) 64-bit non-small mode is unchanged and never matches.
3) 64-bit small PIC code which is RIP-relative is handled specially in
the match to try to fit RIP into the base register. If it fails, it
now early exits. This behavior is unchanged by the patch.
4) 64-bit small non-PIC code which is not RIP-relative continues to work
as it did before. The reason these immediates are safe is because the
ABI ensures they fit in small mode. This behavior is unchanged.
5) 64-bit small PIC code which is *not* using RIP-relative addressing.
This is the only case changed by the patch, and the primary place you
see it is in TLS, either the win64 section offset TLS or Linux
local-exec TLS model in a PIC compilation. Here the ABI again ensures
that the immediates fit because we are in small mode, and any other
operations required due to the PIC relocation model have been handled
externally to the Wrapper node (extra loads etc are made around the
wrapper node in ISelLowering).
I've tested this as much as I can comparing it with GCC's output, and
everything appears safe. I discussed this with Anton and it made sense
to him at least at face value. That said, if there are issues with PIC
code after this patch, yell and we can revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 73478404af7f6b6e64bdda5920ebaede6a4e7a14 |
|
29-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace assert(0) with llvm_unreachable to avoid warnings about dropping off the end of a non-void function in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 76d03106df93665503f5fe75e2974f2d08c447e4 |
|
29-Mar-2012 |
Joel Jones <joel_k_jones@apple.com> |
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
This is a code change to add support for changing instruction sequences of the form:
load
inc/dec of 8/16/32/64 bits
store
into the appropriate X86 inc/dec through memory instruction:
inc[qlwb] / dec[qlwb]
The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f75f4271f43ddff0be588fe3bf782de61d36e034 |
|
29-Mar-2012 |
Joel Jones <joel_k_jones@apple.com> |
Reverted to revision 153616 to unblock build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c367a3eb7376c37c50f0313063481f5b5bb04f04 |
|
29-Mar-2012 |
Joel Jones <joel_k_jones@apple.com> |
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
This is a code change to add support for changing instruction sequences of the form:
load
inc/dec of 8/16/32/64 bits
store
into the appropriate X86 inc/dec through memory instruction:
inc[qlwb] / dec[qlwb]
The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4e02f23de24375294005f88b5254a3775d39fcb2 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 72051bf629087bb7d7e68aa4d553be8137098056 |
|
09-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store opcodes in static tables in X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c528e462a18bea90d8680a96d44c6df1cd3e030a |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 527a08b253795cf09de41c289c9dc071f00b1d4a |
|
16-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the same CALL instructions for Windows as for everything else.
The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9989a63818581bcfeed730e42055af425fdf9353 |
|
15-Feb-2012 |
Pete Cooper <peter_cooper@apple.com> |
Stop custom lowering forr x86 DEC64m from happening if the load in the lowered sequence has more than 1 user
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ce3900849a3b5d43d27ad0fa4d94ff6c12afc9f0 |
|
13-Feb-2012 |
Pete Cooper <peter_cooper@apple.com> |
Fixed bug when custom lowering DEC64m on x86.
If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.
Fixes PR11964.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0fe9a92b33269d005253a2ed47d55dba48929c48 |
|
12-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Switch all of the uses of my InsertDAGNode helper to follow the exact
same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.
I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.
I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 11f0e7b158d669a8c630068a0d8bdd107caef487 |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert r147945 which disabled an addressing mode transformation. I had
hoped this would revive one of the llvm-gcc selfhost build bots, but it
didn't so it doesn't appear that my transform is the culprit.
If anyone else is seeing failures, please let me know!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147957 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e4bc80a14be77c232e1c4e1f30308a72d5cec05a |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Disable the transformation I added in r147936 to see if it fixes some
strange build bot failures that look like a miscompile into an infloop.
I'll investigate this tomorrow, but I'd both like to know whether my
patch is the culprit, and get the bots back to green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d65a9106cd31d0564c093a4a40f7772f80797296 |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Hoist a really redundant code pattern into a helper function, and delete
lots of lines of code. No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 93b7358fc9657cbe4c82f750bac5b9d259923e04 |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Simplify the AND-rooted mask+shift checking code to match that of the
SRL-rooted code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dddcd78e24babb4ca6b35d99abe40bdedde71fab |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Unify the interface of the three mask+shift transform helpers, and
factor the differences that were hiding in one of them into its other
caller, the SRL handling code. No change in behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fde2c1a4c67c8a858b08785bc34aadf07f5c1a44 |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Clarify and make explicit some of the requirements for transforming
mask+shift pairs at the beginning of the ISD::AND case block, and then
hoist the final pattern into a helper function, simplifying and
reflowing it appropriately. This should have no observable behavior
change, but several simplifications fell out of this such as directly
computing the new mask constant, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6ae18e5092553cc58ecdf9aaad4a0e1590ed4626 |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Hoist the logic to transform shift+mask combinations into sub-register
extracts and scaled addressing modes into its own helper function. No
functionality changed here, just hoisting and layout fixes falling out
of that hoisting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f103b3d1b99db0ae314c36d8b4ae71427816379e |
|
11-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Teach the X86 instruction selection to do some heroic transforms to
detect a pattern which can be implemented with a small 'shl' embedded in
the addressing mode scale. This happens in real code as follows:
unsigned x = my_accelerator_table[input >> 11];
Here we have some lookup table that we look into using the high bits of
'input'. Each entity in the table is 4-bytes, which means this
implicitly gets turned into (once lowered out of a GEP):
*(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2));
The shift right followed by a shift left is canonicalized to a smaller
shift right and masking off the low bits. That hides the shift right
which x86 has an addressing mode designed to support. We now detect
masks of this form, and produce the longer shift right followed by the
proper addressing mode. In addition to saving a (rather large)
instruction, this also reduces stalls in Intel chips on benchmarks I've
measured.
In order for all of this to work, one part of the DAG needs to be
canonicalized *still further* than it currently is. This involves
removing pointless 'trunc' nodes between a zextload and a zext. Without
that, we end up generating spurious masks and hiding the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4e3a40293f2e6f04396d2c7d355c5f2a03488c87 |
|
09-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Don't rely on the fact that shift values are never very large, and thus
this substraction will result in small negative numbers at worst which
become very large positive numbers on assignment and are thus caught by
the <=4 check on the next line. The >0 check clearly intended to catch
these as negative numbers.
Spotted by inspection, and impossible to trigger given the shift widths
that can be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cd75e44173d970058520503ed0c156e5072965ca |
|
16-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added missing comment about new custom lowering of DEC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2d496897934adfc0e3e1563dd64d9a7122971e22 |
|
15-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 65fd6564b8aedd053845c81ede1ac594acb470e4 |
|
03-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6f3ddef7c51f03945644ad0e69068dfb24d4b092 |
|
29-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Revert r143206, as there are still some failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bf923b815d6da97367e3eedab69230918bf128a3 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 62c1d00dfd38996f381edae55e1028b8e52a1107 |
|
28-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2ba60e593012ba9b2a9d20b86733eadca288bcb2 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ed744827041a97336461abdc91b43fd0eafb869c |
|
08-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| aed890bee04cce1896a4230cd493774c9700f545 |
|
01-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Teach PreprocessISelDAG to be aware of vector types and to not process them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2a01946de4e510e42691f8dc5e7331fcecb67432 |
|
13-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4977eb5eb53a28208a1e5ccdc26f62cd6948eeca |
|
13-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress.
Part of <rdar://problem/9763308>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e3997d40de141519434a9720d11879610262f708 |
|
02-Jul-2011 |
Eric Christopher <echristo@apple.com> |
TargetConstant immediates won't be placed into registers so tighten
up the valid constant check earlier.
rdar://9692967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5d8aa345dd8f92d572a3c639ee7c6f5a7a932384 |
|
30-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Fix a small thinko for constant i64 lock/orq optimization where we
we didn't have an opcode for 64-bit constant or expressions.
Fixes rdar://9692967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0e29ed081b24359978916b997e91e3e1e2293915 |
|
20-May-2011 |
Stuart Hastings <stuart@apple.com> |
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
rdar://problem/8614450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6abb7bae10736316fdf377ddbfff29960674c96a |
|
17-May-2011 |
Eric Christopher <echristo@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c324f72ab722a852d65fa1f1a45c1de678b0e9a6 |
|
17-May-2011 |
Eric Christopher <echristo@apple.com> |
Support XOR and AND optimization with no return value.
Finishes off rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 811c2b7110105c4c8cd3649f66a3c83b3afec864 |
|
17-May-2011 |
Eric Christopher <echristo@apple.com> |
Couple less magic numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8102bf003eeb066cace2d5941871dec0f5ea1685 |
|
17-May-2011 |
Eric Christopher <echristo@apple.com> |
Make this code a little less magic number laden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c493a1f317a3f5b260f9747f29cea556da52cf73 |
|
11-May-2011 |
Eric Christopher <echristo@apple.com> |
Turn this into a table, this will make more sense shortly.
Part of rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b38fe4b52de05a35c0693f4fd117f908a2abadb7 |
|
11-May-2011 |
Eric Christopher <echristo@apple.com> |
Optimize atomic lock or that doesn't use the result value.
Next up: xor and and.
Part of rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 20115617d4979d5efa5b7741d5ab7a0978a9eb22 |
|
23-Apr-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Silence an overzealous uninitialized variable warning from GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b20a8fc8a6bf57dbde0e9238cf535abb4326dc80 |
|
22-Apr-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a901129169194881a78b7fd8953e09f55b846d10 |
|
16-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods. Radar 9002173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0a9481f44fe4fc76e59109992940a76b2a3f9b3b |
|
13-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
Enhance ComputeMaskedBits to know that aligned frameindexes
have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.
Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 40ccb798ccac6bc3f2c819828a249cc186932a3f |
|
27-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64.
CALL64 marks %xmm* as dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dec28ceb028372c82eae1de7d381d601c3ce0130 |
|
16-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
fix PR8514, a bug where the "heroic" transformation of shift/and
into and/shift would cause nodes to move around and a dangling pointer
to happen. The code tried to avoid this with a HandleSDNode, but
got the details wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d7f696edecd6f015acbea97257653662378a15b7 |
|
14-Jan-2011 |
Ted Kremenek <kremenek@apple.com> |
'HiReg' is written but never read. Nuke its
declaration and its assignments.
Found by clang static analyzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 78d15761e40a542b992ac811b4e3909c33d1513a |
|
06-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
PR8918 - When used with MinGW64, LLVM generates a "calll __main" at the
beginning of the "main" function. The assembler complains about the invalid
suffix for the 'call' instruction. The right instruction is "callq __main".
Patch by KS Sreeram!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b20e0b1fddfd9099e12b84a71fbc8ccff5a12b10 |
|
05-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1de4aa904e9672abfc2e755d798c926d324e2d36 |
|
27-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 25cbf504fe803a0b57e877c6f83aed5aa48e7ec7 |
|
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Use #NAME# to have the CMOV multiclass define things with the same names as before
(e.g. CMOVBE16rr instead of CMOVBErr16).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d350e4757e649dce07f7492115bd9d19c71426bf |
|
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
switch CMOVBE to the multipattern:
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 56a8b817b103dbbcb404705cbb9dabab6049ba7d |
|
22-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Temporarily work around new address lowering while I figure out what
needs to happen for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f93b90c5dfe98958eb43715a6e674565ab162502 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 492a43e6f64997a0ab26ef047dced193931fda85 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the last 4 X86ISD nodes that should have memoperands to have them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2156b79c493751f165d445535f8b598b4769b3e8 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
can access the stack due to how it is generated though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0729093cd7e15ed6469e50b74f0edd7f205b50ff |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
used with stack slots, but hey, lets be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8864155a35eb59fbebfd1822aaf224128b5c5d23 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give VZEXT_LOAD a memory operand, it now works with segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0b79cfee1518b67f1da5cb95a44bb01fa4fad6c6 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
revert r114386 now that address modes work correctly, we get a nice
call through gs-relative memory now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 93c4a5bef780e43552d3b9d702756d3acb7801d2 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b86faa17a4e574580ad029a8082a27ead2fa6013 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement support for GS and FS relative address space matching
by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.
This makes FS and GS relative accesses *far* more predictable and
work much better. It also simplifies the X86 backend a bit, more
to come.
There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114491 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 701cd622978ffe8c3197c0c465b97c5f2aeb8346 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
even though I'm about to rip it out, simplify the address mode stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3d6ccfba314ed38e4506dae2781a060e9a3e07ac |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
propagate MachinePointerInfo through various uses of the old
SelectionDAG::getExtLoad overload, and eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 08bad54baf244ea0d0835b729db2b3754156683d |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8453210, a crash handling a call through a GS relative load.
For now, just disable folding the load into the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 17aa68055beed6faa48ca3a995c5b6fdf5092fd4 |
|
04-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3061c4442ec9d15d0e38d1cf2841e8a21938cf5e |
|
03-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't call Predicate_* from X86 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fc19695c9a6d87b26461c72f30af22026bf0326e |
|
25-Aug-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove dead recursive function. Yay for clang -Wunused-function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7752442bfa1213b302d421988813e3b1cec6b796 |
|
05-Aug-2010 |
Eli Friedman <eli.friedman@gmail.com> |
PR7814: Truncates cannot be ignored for signed comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 599b531a960833719f607d66c97871f1f5ad12c0 |
|
09-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Change LEA to have 5 operands for its memory operand, just
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bcc8017c738e92d9c1af221b11c4916cb524184e |
|
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
|
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4f5d84e4adfe2fd972e20e1e9104fbacf8d63512 |
|
26-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 027657db7cf60bcbf40403496d7e4a170f9ce1ec |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Change UpdateNodeOperands' operand and return value from SDValue to
SDNode *, since it doesn't care about the ResNo value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e54081088e82813b5ab36d3a797172f3455c68ba |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Don't maintain a set of deleted nodes; instead, use a HandleSDNode
to track a node over CSE events. This fixes PR7368.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 30ef0e5658b0b8b04437f73f74162d5d72923f29 |
|
03-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Add first pass at darwin tls compiler support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3458e9e4dfc8689179a74e954aad78d3a4b564ff |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename X86 subregister indices to something shorter.
Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ffce6f134386e757b10fcab96309ae3a8e421fd5 |
|
30-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Don't leave Base.FrameIndex uninitialized, so that it doesn't
print randomly in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2bce5f4b56ac0ea8e452a79e13abba1deca9b7b6 |
|
28-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable i16 to i32 promotion by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d6139425f5f5c303d5ae6a2202fb40a8f6dde9a6 |
|
21-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
teach the x86 address matching stuff to handle
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6465265ae1b9d2d9ffb6cfcebf4b46ad97914aa7 |
|
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Delete unneeeded arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f3caa525cc887b696df8e8a8d9ddb03515d1695a |
|
18-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
X86 address mode matching code MatchAddressRecursively does some aggressive hack which require doing a RAUW. It may end up deleting some SDNode up stream. It should avoid referencing deleted nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f48ef0365545b6160836e3f4b4a210d1e21f1881 |
|
14-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 97d853451ec22e123b4cc28523d2495370d8ac8a |
|
04-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1840991d54247c32cbf12245b50dcaf023cec7c4 |
|
03-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
factor the 'sign extended from 8 bit' patterns better so
that they are not destination type specific. This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fb444af5c9901271dc115a3197d7fa9ef4187fdd |
|
03-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
merge two loops over all nodes in the graph into one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 98d45790ae087d4a38767c256f5bb06d78dd8b4b |
|
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate PreprocessForRMW now that isel handles it.
We still preprocess calls and fp return stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d1b738298359846b9cccaa0931e6ec1fc59a6d87 |
|
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Fix some issues in WalkChainUsers dealing with
CopyToReg/CopyFromReg/INLINEASM. These are annoying because
they have the same opcode before an after isel. Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.
With that done, give IsLegalToFold a new flag that causes it to
ignore chains. This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing. This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.
I currently #if out the dead code in the X86 backend and MSP
backend, I'll remove it for real in a follow-on patch.
The testcase changes are:
test/CodeGen/X86/sse3.ll: we generate better code
test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was
miscompiling this before, we now generate correct code
Convert it to filecheck while I'm at it.
test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
folding to make anton happy. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7c306da505e2d7f64e160890b274a47fa0740962 |
|
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e60f7b4412409f2ba641dd85c3aa1d06e005380d |
|
01-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
remove a little hack I did for the old isel, not needed
now that it is gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 31c020a147edafc36d7d913ebb16020c574cdac3 |
|
01-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
remove a terrible hack that disabled assertions from this file because of build time
problems. rdar://7697850.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 652b7e488d78fe4d3697d2aaf7734422650fd7d0 |
|
23-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
no need to override IsLegalToFold, the base implementation
disables load folding at -O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f1c6428164f6f5e07cbc88c1c1440efbf29c0d5f |
|
21-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix and un-xfail X86/vec_ss_load_fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a170b5e818bef4841084297960334eaea64e7081 |
|
21-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
rename SelectScalarSSELoad -> SelectScalarSSELoadXXX and rewrite
it to follow the mode needed by the new isel. Instead of returning
the input and output chains, it just returns the (currently only one,
which is a silly limitation) node that has input and output chains.
Since we want the old thing to still work, add a new
SelectScalarSSELoad to emulate the old interface. The XXX suffix
and the wrapper will eventually go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 64b4986c94076690d64e6d0561b9c291d8f7f674 |
|
17-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
rename and document some arguments so I don't have to keep
reverse engineering what they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 92d3ada814f33e3e1d10f0e5e3a15333b0cca849 |
|
16-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7653908, a crash on a case where we would fold a load
into a roundss intrinsic, producing a cyclic dag. The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection. Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 014bf215c3457bb34fee348265e8f63a70b4d503 |
|
15-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| db8d989ed598da345f07a33cf7a578d9ec57d475 |
|
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bd13fb62541136a4891d702feec8b7aba5bf695a |
|
11-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor the conditional jump instructions in the .td file to
use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a10756ee657a4d43a48cca5c166919093930ed6b |
|
21-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Re-implement the main strength-reduction portion of LoopStrengthReduction.
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cf495bc2e505e52ad018da55bed11c7b8bc97db5 |
|
20-Jan-2010 |
David Greene <greened@obbligato.org> |
When XDEBUG is enabled, check for SelectionDAG cycles at some key
points. This will help us find future problems like the one
described in PR6019.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ee9c595885636ccec635a82ffd49c5ab825c7839 |
|
16-Jan-2010 |
David Greene <greened@obbligato.org> |
Fix PR6019. A load has more than one use if it feeds a bitconvert that
has more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f1b4d26e674a067b9f5c8622ad79c95d1e094046 |
|
12-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 05920b8146558f5e3141a886cd2a00281b10222a |
|
11-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 93158. It's breaking quite a few x86_64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 71c25b7d7bdf9b49dd70965c7486ce930b846aac |
|
11-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Re-instate MOV64r0 and MOV16r0, with adjustments to work with the
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d7f4f24d3f880d0d44d96bf200871768ec3240d9 |
|
05-Jan-2010 |
David Greene <greened@obbligato.org> |
Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| eeb3a00b84b7767d236ec8cf0619b9217fc247b9 |
|
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9ef51c801152084239feae34be87c55c60b168df |
|
04-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Flags-producing add, and, or, etc. have the same profibility
rules as normal add, and, or, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9e3238303c2f3d3936828705b23b3efc0e3b1321 |
|
23-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
completely eliminate the MOV16r0 'instruction'. The only
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c7928f8f4eb5d15b70337fd8a6527fd6c4ed7893 |
|
18-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 91623 now that I actually know what I was trying to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 08ce53996e944927699dd6e98839deb9d9d4c092 |
|
17-Dec-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Revert r91623 to unbreak the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 73ebbd8aac979cd6a62f15434f0e5423306f82dd |
|
17-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove an unused option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
|
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 253e9b2990b090162e389475c4ef419ff7e2c5d1 |
|
11-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-gcc/clang don't (won't?) need this hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5da58851e55beb97de0c88286c10431f9b5cd141 |
|
10-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add a monstrous hack to improve X86ISelDAGToDAG compile time.
- Force NDEBUG on in any Release build. This drops the compile time to ~100s
from ~600s, in Release mode.
- This may just be a temporary workaround, I don't know the true nature of the
gcc-4.2 compile time performance problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7289ed2ee7828ce52ddf37284da5f60190db3086 |
|
06-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Use SUBREG_TO_REG instead of INSERT_SUBREG to model x86-64's
implicit zero-extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 73bb251cd7a535fb93bb3a52eda61555fb253f41 |
|
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 43f44aa16099d94402862f20eea10f405a7e6029 |
|
01-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
improve x86 codegen support for blockaddress. We now compile
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 11596ed43c5eb3b8a49f563abdbdb7ea54fec991 |
|
09-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Fix the x86 test-shrink optimization so that it doesn't shrink comparisons
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 206a357684ec4f9159905eb7293bfb2221af0e14 |
|
16-Sep-2009 |
Nate Begeman <natebegeman@mac.com> |
Do not try and sink a load whose chain result has more than one use, when
trying to create RMW opportunities in the x86 backend. This can cause a
cycle to appear in the graph, since the other uses may eventually feed into
the TokenFactor we are sinking the load below.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1e038a8494c9b363cd03a1e239d3a6817d7edec3 |
|
15-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Don't pull a load through a callseq_start if the load's chain
has multiple uses, as one of the other uses may be on a path
to a different node above the callseq_start, because that
leads to a cyclic graph. This problem is exposed when
-combiner-global-alias-analysis is used. This fixes PR4880.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 79b765d0575c5ffdb377c27823e640443a8e7ac6 |
|
25-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Use X86II::MO_NO_FLAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 072a56e37de0e4872ce0340b0bd5585ba15fd0c3 |
|
23-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove Streams.h from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
|
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 25f1aa04ff27ddc3de9154ee58e64a96849ff66c |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ef74e9bf2af0f7443e85111adb497afd8802975a |
|
20-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix an x86 code size regression: prefer RIP-relative addressing
over absolute addressing even in non-PIC mode (unless the address
has an index or something else incompatible), because it has a
smaller encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6bd4aca29f2133bcb789bba3f36afe5cf33ae687 |
|
19-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Remove temporary testing code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6a402dc952ccad3f8fd0d9e272dbdd261f50854e |
|
19-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Add an x86 peep that narrows TEST instructions to forms that use
a smaller encoding. These kinds of patterns are very frequent in
sqlite3, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1232167ce3c6efbdc5647ebaa23863a3157e36e3 |
|
07-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reformatting of lines. Put multiple DEBUG statements under one DEBUG statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| aae317ac32c63a4cfea9925afa9cbd7a6cf1af77 |
|
06-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bug in x86's PreprocessForRMW logic that was exposed
by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b5e01724057e6eabc45da75df3037af4ad29248c |
|
06-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Better handle kernel code model. Also, generalize the things and fix one
subtle bug with small code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0ea8bf3590d7553179f95e4b0fc47c02f066fcfb |
|
03-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- s/DOUT/DEBUG(errs()/g
- Tidy up some headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7267734c3944582c8ceffddaec84fff70c929a62 |
|
02-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7571eb5015ad07d4b849cd97a5f820be19523a66 |
|
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Minor code simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 37b7387da90ffd42d28ad0f08fca00b684294b2c |
|
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch.
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 41d0b9d952c1d329c80e091160e71a21570ef18c |
|
23-Jul-2009 |
Dan Gohman <gohman@apple.com> |
x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9ac7542bab447299fc5d67c756e75e44502fc87e |
|
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
reapply r75408, which eliminates MOV64r0 in favor of using
MOV32r0 + subregs to do the same thing. This should work now
that PR4544 is fixed. Thanks Evan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 69600cae95b93dd8e3fc869a630b007f1c648d43 |
|
12-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r75408. It appears to break the Apple-style builds:
x86_64-apple-darwin10-gcc -c -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Wold-style-definition -Wmissing-format-attribute -mdynamic-no-pic -DHAVE_CONFIG_H -I. -I. -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~obj/src/include -DENABLE_LLVM -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DLLVM_VERSION_INFO='"9999"' -DBUILD_LLVM_APPLE_STYLE /Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/tree-ssa-alias.c -o tree-ssa-alias.o
/var/tmp//ccJQ2JBT.s:4134:Incorrect register `%rcx' used with `l' suffix
make[2]: *** [tree-ssa-live.o] Error 1
make[2]: *** Waiting for unfinished jobs....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a6d16ae432f7ca11e888b216bde08d0097bcf441 |
|
12-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate MOV64r0 in favor of a Pat<> pattern. This is only nontrivial because
the div lowering code explicitly references it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 14f7511f46ed61b0dbaaf566e1170f40b9663924 |
|
12-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix a bug in my cleanup patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2514278b833a0ca95869bae633099d86dd39550d |
|
12-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
comment cleanup, reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 18c5987fa33ba9d57ea597e3131f664443765f4e |
|
27-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ba8ef45d12be2f63107dc69c3581ba8c49a9bcd2 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
make sure to propagate operand flags in SelectTLSADDRAddr properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0b0deab4648c3b5c3db9fbd4a7b1653be1e1b9cc |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
fix a pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b8afeb99e91f02c0ddd1864504e14ac198e9ede8 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
propagate target operand flags through addressing mode selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5c0b16d0c40bb95e572e5d24db587ed8ca4bde71 |
|
20-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
change TLS_ADDR lowering to lower to a real mem operand, instead of matching as
a global with that gets printed with the :mem modifier. All operands to lea's
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this. There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).
This also makes the use of EBX explicit in the operand list in the 32-bit,
instead of implicit in the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c553462c2989bbcbd9a911f7a5d56e76883d3038 |
|
03-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Remove the redundant TM member from X86DAGToDAGISel; replace it
with an accessor method which simply casts the parent class
SelectionDAGISel's TM to the target-specific type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3cd90a18bb862b9115b69a031282925f8c1afcfc |
|
11-May-2009 |
Dan Gohman <gohman@apple.com> |
Convert a subtract into a negate and an add when it helps x86
address folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c1c6ef8f74fc550f29cfec1f2fb699dd8c2fb94e |
|
08-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out cycle-finder code and make it generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 98a366d547772010e94609e4584489b3e5ce0043 |
|
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b |
|
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c69d56f1154342a57c9bdd4c17a10333e3520127 |
|
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2e9d5f912a9841d3685ba0241abe1131943fed29 |
|
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7c36683fa33afe91da0b5e08ca3064c633dc3f77 |
|
16-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix PR3995. A scale must be 1, 2, 4 or 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 62ad138d7033e207842337c9fb909f70e32b14ea |
|
15-Apr-2009 |
Dan Gohman <gohman@apple.com> |
For the h-register addressing-mode trick, use the correct value for
any non-address uses of the address value. This fixes 186.crafty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 21e3dfbc86955cf46a362e8ed36b5b73b42961c9 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8433df36fb9566a00e643a6cb8f5e77af453ea81 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Remove x86's special-case handling for ISD::TRUNCATE and
ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3cd0aa3260c3e97cadd66b9b00ed724821b87f67 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7ff5bff45eaa1fabf8bb910daf2907cf981cbf3d |
|
13-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
X86-64 TLS support for local exec and initial exec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b215776fa1ee3f1fc389eadc843688c5a0c79a2d |
|
13-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
only if symbolic addresses are RIP relatives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 49a168daae8148d3b94788671605aab2a2b155ad |
|
12-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
refactor some code into X86DAGToDAGISel::MatchWrapper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dbcfb3080a1e208aef8e4f13a94ce3aa8309643f |
|
10-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't fold a load if the other operand is a TLS address.
With this we generate
movl %gs:0, %eax
leal i@NTPOFF(%eax), %eax
instead of
movl $i@NTPOFF, %eax
addl %gs:0, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 094fad37b90946c91a09eb9270a0dbe800f49d87 |
|
08-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 044b5344c4a97b3c709a05b9c5f9296656477652 |
|
08-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 |
|
07-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 523249f8562c2a4b2a72fdac52666a08aff797dc |
|
31-Mar-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
remove unused arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4d9523246999531db52312c6eef6af705a5a692e |
|
31-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 73f24c9f0d9afd1fd65d544f2b7b7b7c77fc2238 |
|
30-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a0a4f07fb67d120f00cff053056f644b4d1c14f6 |
|
28-Mar-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use array_lengthof
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e4d5d34cfcde3c5df4af502ced717c6e01268cd1 |
|
27-Mar-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use less hard coded constants to make the code less brittle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9a49d31b6f94febb408b5d25d3e768c04292cf10 |
|
14-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Don't forego folding of loads into 64-bit adds when the other
operand is a signed 32-bit immediate. Unlike with the 8-bit
signed immediate case, it isn't actually smaller to fold a
32-bit signed immediate instead of a load. In fact, it's
larger in the case of 32-bit unsigned immediates, because
they can be materialized with movl instead of movq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 77502c93442c5953c05e39fcd4c17d9e2aca766f |
|
13-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Enhance address-mode folding of ISD::ADD to handle cases where the
operands can't both be fully folded at the same time. For example,
in the included testcase, a global variable is being added with
an add of two values. The global variable wants RIP-relative
addressing, so it can't share the address with another base
register, but it's still possible to fold the initial add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8d13f8f1043d8b47940ecab7bac838ff1e8166f8 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of BuildMI from X86.
There were some that might even matter in X86FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1823c92aa711e38577d135461fba200423114ed8 |
|
12-Feb-2009 |
Chris Lattner <sabre@nondot.org> |
fix the X86 backend to just drop llvm.declare nodes for VLAs instead of
leaving them in the DAG and then getting selection errors. This is a
fix for PR3538.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6f38cb61a94b3abab70f0ee463bdcf55d86d334e |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2d0a1cc4161b4616b725d9f28c4492f5e4de5260 |
|
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Refactor some repeated logic into a separate function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dd64c417c0ef73345222eca60154289c1ad62a09 |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Patch up omissions in DebugLoc propagation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d839254888b1a2cc63c4a3336488ce3d3c05052d |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
DebugLoc propgation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c03e9a1040a975670a9c94e94d37dd3a940e0cd5 |
|
27-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Simplify findNonImmUse; return the result using the return value
instead of via a by-reference argument. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e8ecf4876adf7fde02c744ca37a399b9c90eb105 |
|
27-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Eliminate unnecessary operands-list traversals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5b2e5893c62cac7f349b348400c669d40e2eeca2 |
|
26-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1ef4d8f7ee60f724eff2175ed22f75a60eb8d50d |
|
21-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Fix a recent regression. ClrOpcode is not set for i8; for i8, if
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2722e7b1394e675114d2338ce61a92814d66d126 |
|
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8e278266494c71471bfd7c29cccfcdcef433a4ba |
|
17-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f2accb5c9eae69bce73a338680825a229f23ae5a |
|
10-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6bb14ca775b4cea4543ceb482e09a1b92aee80a5 |
|
10-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Some code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 884c70c912b699a4d14d05dcac1ac4f2d47c0f9a |
|
27-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size.
e.g.
movl 4(%esp), %eax
addl $4, %eax
is 2 bytes shorter than
movl $4, %eax
addl 4(%esp), %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bc5cbb8be9d935240be5a57a8f37c5258a9d0563 |
|
12-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Move the code that inserts X87 FP_REG_KILL instructions from a
special-purpose hook to a new pass. Also, add check to see if any
x87 virtual registers are used, to avoid doing any work in the
common case that no x87 code is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 27cae7b01b2102ce06c355701987eafb5047a2c0 |
|
11-Nov-2008 |
Dan Gohman <gohman@apple.com> |
The 32-bit displacement field in an x86 address is signed. Arrange for it
to be sign-extended when it is promoted to 64 bits for intermediate
offset calculations. The offset calculations are done as uint64_t so that
overflow conditions are well defined.
This fixes a problem which is currently hidden by the x86 AsmPrinter but
which was exposed by r58917 (which is temporarily reverted). See PR3027
for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d |
|
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f6503a031e2459be63ebc688d32577d9f70da354 |
|
04-Nov-2008 |
Dan Gohman <gohman@apple.com> |
The ANDMask node folds to a constant, and isn't the node that needs to
have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8ad4c00c00233acb8a3395098e2b575cc34de46b |
|
27-Oct-2008 |
David Greene <greened@obbligato.org> |
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6520e20e4fb31f2e65e25c38b372b19d33a83df4 |
|
18-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f522068412218cd14b2c2df74a3437717d255381 |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 552e3be775c3ed9ff79e3002b369c5267633f72b |
|
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7b8e96401ca2859d0c9fd4962c3e3da9973eb443 |
|
13-Oct-2008 |
Dan Gohman <gohman@apple.com> |
When doing the very-late shift-and address-mode optimization,
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.
If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.
This fixes PR2849.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e76225a4c1f185e7a00f790f956bd3ff0e017c90 |
|
06-Oct-2008 |
Devang Patel <dpatel@apple.com> |
It is possible that all functions in one module are not being
optimized for size. Set OptForSize for each function separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 880ae364ba4ed3d63542a2ef934980c70e8bb9d7 |
|
04-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Make atomic Swap work, 64-bit on x86-32.
Make it all work in non-pic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1b54c7fe9b034a6450af8596231ad5368b617725 |
|
03-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Pass MemOperand through for 64-bit atomics on 32-bit,
incidentally making the case where the memop is a
pointer deref work. Fix cmp-and-swap regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| da8ac5fd9130b70b61be61e4819faa8d842d708f |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 38217fef57de72064ba74a165cf100d785dfcad0 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Remove an unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 48c1bc2ace6481d3272ab5c18e1f19352c563be8 |
|
02-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Handle some 64-bit atomics on x86-32, some of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4ae641f4d12c60ee1aaca5e42b6de231c6a02c40 |
|
02-Oct-2008 |
Devang Patel <dpatel@apple.com> |
Remove OptimizeForSize global. Use function attribute optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f06c835f769aa1cf67801ed1f6bd366a447c18b1 |
|
30-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Optimize SelectionDAG's AssignTopologicalOrder even further.
Completely eliminate the TopOrder std::vector. Instead, sort
the AllNodes list in place. This also eliminates the need to
call AllNodes.size(), a linear-time operation, before
performing the sort.
Also, eliminate the Sources temporary std::vector, since it
essentially duplicates the sorted result as it is being
built.
This also changes the direction of the topological sort
from bottom-up to top-down. The AllNodes list starts out in
roughly top-down order, so this reduces the amount of
reordering needed. Top-down is also more convenient for
Legalize, and ISel needed only minor adjustments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56867 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 57c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37c |
|
30-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 02a4da2c2212652d29feef3c1426c47e2ccb323c |
|
27-Sep-2008 |
Daniel Dunbar <daniel@zuster.org> |
Unbreak build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b7a75a5a541a836d07cfc5ccebd70bb5e42f797f |
|
27-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7810bfed5570c192e0714a8fd0e5130a0c38dd2e |
|
26-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 97135e1ee51357245561a5108f90a8a1161431a1 |
|
26-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Factor out the code for determining when symblic addresses
require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
|
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fe29e770e603d1b2118b55958bb45f58009124ea |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Delete an unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8b746969baee26237e4c52de9862d06795eabcda |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Move the code for initializing the global base reg out of
X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 682d5a88341ebcb1ba4edad7f8df069e33e78b01 |
|
17-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw
up some new ascii art to illustrate what it does. This change
currently has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 93c53e5583427ee567293a9a21c6c76fccf218ca |
|
31-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
fix a bunch of 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
|
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ab6c3bb44d254d1b3c9dcce74ba3a917558feab3 |
|
25-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f350b277f32d7d47f86c0e54f4aec4d470500618 |
|
23-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ad3460c3c968e33c5b9a07104b9fe5a5c27ff55b |
|
21-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify SelectRoot's interface, and factor out some common code
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0bfa1bfbff1ddc5a85494c9e2b1f985f145dc8a6 |
|
20-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.
Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0ac3fc2a61f77af74ccde3dcd437d0f72b736b8f |
|
17-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ea9587bf41ab9b3de3846ab7de797a5d9bbdeec7 |
|
13-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Oops, check in these files too, for the FastISel -> Fast rename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 50dd1d028021bd7fd8bca3f33633ea59577c9d5e |
|
12-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Some fixes for x86-64 JIT. Make it use small code
model, except for external calls; this makes
addressing modes PC-relative. Incomplete.
The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8968450305c28444edc3c272d8752a8db0c2f34a |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Tidy SDNode::use_iterator, and complete the transition to have it
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 462dc7f4960e5074ddf4769ec8b2ef1ba7a4d2c8 |
|
21-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add titles to the various SelectionDAG viewGraph calls
that include useful information like the name of the
block being viewed and the current phase of compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e8be6c63915e0389f1eef6b53c64300d13b2ce99 |
|
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2fbdf0e711697666d231ce7369a3966721e85c54 |
|
16-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Fix the result type of X86's truncate to i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4576f6d7a9c0f2c6a3b6c5d4d8a3063bbf763ae5 |
|
01-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Do not use computationally expensive scheduling heuristics with -fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| db8d56b825efeb576d67b9dbe39d736d93306222 |
|
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fab8387384c6866730147a78347705987b57a14b |
|
18-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak DECLARE isel in pic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 851bc0453350254cd45a91b6af9592003562d707 |
|
17-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rather than avoiding to wrap ISD::DECLARE GV operand in X86ISD::Wrapper, simply handle it at dagisel time with x86 specific isel code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d35121ad00667d93ea779a722dbee7d022410815 |
|
29-May-2008 |
Dan Gohman <gohman@apple.com> |
Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.
This fixes "rdar://5791600", whatever that is ;-).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cd0baf21a1f3582ada94d11cf1ccbf342b504077 |
|
23-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Use movlps / movhps to modify low / high half of 16-byet memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d880b97257c7f8ec4e94948874cb87c865d9f96f |
|
09-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle a few more cases of folding load i64 into xmm and zero top bits.
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7e2ff77ef05c23db6b9c82bc7a4110e170d7f94c |
|
08-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 419ace9bda6abaaa65560708064b210b4e48880f |
|
25-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Not checking for intrinsics which do not have a chain operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cdda25d22b348b0e8ef14a5e5e7d3e5f1d41c690 |
|
25-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Switch from std::set to SmallPtrSet.
- Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 25453ea49e30e4e22e072153832158a6b0ee0390 |
|
25-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
Loosen up an assertion to allow intrinsics. I really have no
idea what this code (findNonImmUse) does, so I'm only guessing
that this is the right thing. It would be really really nice
if this had comments and perhaps switched to SmallPtrSet
(hint hint) :)
This fixes rdar://5886601, a crash on gcc.target/i386/sse4_1-pblendw.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dc1adac582fa120861f18ae7221bfe1421fea59f |
|
07-Apr-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 90ce87b5bde326634bc0edddd74a426f11b7fe97 |
|
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6397c64441ddce3822ab0e712f224a11bd75811c |
|
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Backing out 48222 temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e326332acd5fefb9854118603b4d07d4e44b64c5 |
|
26-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Use a linked data structure for the uses lists of an SDNode, just like
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 920c37afc5896201ec014041cbd270289baa25c0 |
|
21-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
remove Evan's "ugly hack" that sorta attempted to get
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c9298235251b014e86a7368d92b589d093acb64a |
|
16-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6634e26aa11b0e2eabde8b3b463bb943364f8d9d |
|
13-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1fab4a6bbb6eb5d44d35c8aade2493143b44d288 |
|
11-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Recommitting parts of r48130. These do not appear to cause the observed failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 447ff68c08bc01aa040ae6d0291af69b55bb8e57 |
|
11-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Change the model for FP Stack return to use fp operands on the
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 03fdec04d1f179f32047aa6752aa59f2674c9894 |
|
11-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Don't emit FP_REG_KILL into a block that just returns. Nothing
can be live out of the block anyway, so it isn't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4499e495eabe8de7d595416a03c56af4688df507 |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3feb0170a8d65984ce5c01a85e7dfd4005f8bb35 |
|
10-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6fa2f9c63688ff240d58c80bc0e433bb27a53c85 |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 07b7ea1a48a89675c22d66943b8458ebb59d8e4a |
|
04-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove -always-fold-and-in-test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e526d8a95568f356d68b601f6037125dde8078ed |
|
28-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Set to default: x86 no longer fold and into test if it has more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 545914311ad85a9b326deacc34f57b85b90216b5 |
|
25-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Revert the assert for MUL_LOHI with an unused high result; Chris
pointed out that this isn't correct at -O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c2d9b5fcdfcfaa40b8d8b85b3ff46ab0dfebd619 |
|
25-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Add an assert to verify that we don't see an
{S,U}MUL_LOHI with an unused high value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fcf81db600385be24baae2dd1c1994150e409a7b |
|
25-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Remove the hack that turned an {S,U}MUL_LOHI with an unused high
result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2e68b6f52d0979575b2f02ed29717d907ba0684c |
|
25-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert MaskedValueIsZero and all its users to use APInt. Also add
a SignBitIsZero function to simplify a common use case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3738f2d59fe0f040b18dfe2f0d5b110be3a02b69 |
|
20-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Poorly named option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 79964fdbaf11877c463d081ae3ffdc7a540f54c2 |
|
20-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Disable for now. This is pessimizing code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e9c608d6ccf0fae87982c7510835b8f2f99353ff |
|
20-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9f143ce9894a053d0338f3fdfefe4cd067213422 |
|
12-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Only using x86-64 rip relative addressing in non-staic mode?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| be3bf423315394f15f0c71afdaed26e5cfbcad4a |
|
07-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4e3f5a4e9c13f216856515e6f000881f2c850736 |
|
05-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
|
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0d9e976ad2c5479f3d67f8cb09a5908cfc29985c |
|
29-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
Status: This only works for direct calls, and only the caller side is done. Disabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d43d00cf3ae44b94162552b19e4cf2491bc0533e |
|
24-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b1a9aec515125d88a53cdd1d229905da6ee75dee |
|
08-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a x86-64 static codegen bug. This fixes a lot of x86-64 jit failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0475ab58b8e92fa8e8b90ddbf023bc60587c5e25 |
|
05-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Combine MovePCtoStack + POP32r into one instruction MOVPC32r so it can be moved if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f02ca69951dcd1a984083c5f3f3ca6a49e34fa8f |
|
22-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix JIT code emission of X86::MovePCtoStack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1314b00cf2edc49c24c814e66f3fad62a5da40e8 |
|
13-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fold some and + shift in x86 addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5aaddaa7b8d52eec58f6eec0a4a897a03b517ca4 |
|
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
aesthetic changes, no functionality change. Evan, it's not clear
what 'Available' is, please add a comment near it and rename it
if appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8a594489bf2e4b533f6403549afb7d5de417c9e4 |
|
25-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0d642871f512fa9bb83eca5f5b0176e9e42a339a |
|
01-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Silence, accersed warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8368805e255d53a68f89e341b69ed0f7022509c4 |
|
22-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Fix the folding of multiplication into addresses on x86, which was broken
by the recent {U,S}MUL_LOHI changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 96aaa545298b6b95d5a83cc5b62af14ca8968ed4 |
|
12-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 74f87a63b6f5ea3325641b531bbe8d104d23e796 |
|
09-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Fix grammar in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 525178cdbf00720ea8bce297a7d65b0cca0ab439 |
|
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2fe1259d0ab75fdc49bc368cfa62f3260dc3a2df |
|
25-Sep-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Partly revert invalid r41774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a37c9f7506af622b9f29a35466b33c650c75e9f7 |
|
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
When both x/y and x%y are needed (x and y both scalar integer), compute
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 48d1e4517e6cdbbcdacae6e555a0aefa6bc3975c |
|
25-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
When mixing SSE and x87 codegen, it's possible to
have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them. To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL. PR 1697. (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ef61ed350737c860ddff4107a7a32ade82d5bfb8 |
|
08-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
TableGen no longer emit CopyFromReg nodes for implicit results in physical
registers. The scheduler is now responsible for emitting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cdd509aecdf14ebb18ecd6844462084698b65c4e |
|
07-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Apply feedback from previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| eaf089430e7681fcddc3465c3b33b9645273ab02 |
|
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| badb2d23d1042a991b8c6e31ff19ffd3f6712570 |
|
13-Aug-2007 |
Dan Gohman <gohman@apple.com> |
When x86 addresses matching exceeds its recursion limit, check to
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a1eb155e521e06d2b3e33699a4cf87ae5d012087 |
|
11-Aug-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Use subregs to improve any_extend code generation when feasible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c59e52108bbfca50b23c5d10706484d4b012c344 |
|
10-Aug-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f7ef26e7012fdf0ec6366489d269997f2ed1ba97 |
|
09-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cdbe4d3ebe50bd3709b08ee59bb09ccf3a1fbd47 |
|
07-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Long double patch 8 of N: make it partially work in
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40906 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6a30811d5c3484883cbcbbda1140f2ac36f7c09c |
|
06-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Get X86 long double calling convention to work
(on Darwin, anyway). Fix some table omissions for
LD arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7afa166c7663269824c3a164a3909ec5f97ed26a |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Switch some multiplication instructions over to the new scheme for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f6844ca0e4a02fae3b100db7b0c62170d05e5b53 |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mac OS X X86-64 low 4G address not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2dc6dc619c89c739550a0fcab96a9f7eac3d9f15 |
|
29-Jul-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cf5543c47e082fa1d2b6b67973018774dd0ef0cd |
|
26-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40535 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 518143d7950fb02683b9675e94d42c112ed599c4 |
|
26-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Same goes for constantpool, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a49ed78c2793c52d89a780c1f71c4fca0602eb66 |
|
26-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mac OS X x86-64 lower 4G address is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| dc9b3d0bb5ed3a3f59cad61e264f0ec43c946459 |
|
25-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 849f214a4e3676e41168b0c5398165c4d4fb99f8 |
|
03-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants. Some factoring
improvments forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
|
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a1b253f58e0adc809450d9fd4941539259dddd20 |
|
12-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f6e9353e1a922643b88dfea6763b0453727aa5c2 |
|
28-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Oops :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 33bf8c44dd53090e61e57683b4382b734dc53b61 |
|
28-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Don't allow MatchAddress recurse too much. This trims exponential
behaviour in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a16b7cb1d3a482a28bc8f73433f0034d8d8673d7 |
|
20-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2, #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6241226b097f1a71c25e2e30272aa508abaafc6d |
|
04-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a miscompilation in the addr mode code trying to implement X | C and
X + C to promote LEA formation. We would incorrectly apply it in some cases
(test) and miss it in others.
This fixes CodeGen/X86/2007-02-04-OrAddrMode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 706535db86868d710ad10ddad4adc4bc8b838f10 |
|
22-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Linux GOT indirect reference is only necessary in PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7aa8a459227ea02263d92e48ef109da3c0e0a5fb |
|
13-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Adjust #includes to compensate for lost of DerivedTypes.h in
TargetLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7f70559bc47877bafc6dfa92b7df6b64650445fb |
|
12-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
* PIC codegen for X86/Linux has been implemented
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 317848f4a11f7fe55afdd6d90ded8444069b56fb |
|
03-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Really big cleanup.
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 95b2c7da5e83670881270c1cd231a240be0556d9 |
|
19-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
eliminate static ctors for Statistic objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a70d14bd16dbd528f6271a5160173d8b80c61ed2 |
|
19-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR1062 by Dan Gohman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ac0b6ae358944ae8b2b5a11dc08f52c3ed89f2da |
|
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Detemplatize the Statistic class. The only type it is instantiated with
is 'unsigned'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 953fa0455e1917e2d91a5bfdad246d75831c5f29 |
|
05-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Revert an unintended change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 28b51439f3b99bac332f32778ef26d000dc85301 |
|
05-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Switch X86-64 JIT to large code size model.
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 19f2ffce4598c4c70f32eed7c6740b43185200b1 |
|
05-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0085a28d13f86b09ba0c83e8dce81de3ba15ca2d |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use a different wrapper node for RIP-relative GV, etc.
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4946399b6432db1cacb647cbca25178ca2a5f02b |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d0ff02cf6ff3019dc97d49636a055e13d20a0774 |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR1018 - Better support for X86-64 Linux in small code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b1409ce7ba3cea5e75fd205d4c037638d93cfeaf |
|
17-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6345d75729392d9b50383f1b5c7f92d477572290 |
|
17-Nov-2006 |
Bill Wendling <isanbard@gmail.com> |
Removed even more std::cerr and #include <iostream> things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 |
|
14-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5cd3e9f4b7caa5a79c6c05633b11144d0ae41771 |
|
11-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add implicit use / def operands to created MI's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 490ce1ea6f85395127f62ba521ce9d20d1f569fe |
|
11-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add all implicit defs to FP_REG_KILL mi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d6373bcd8232fe40fc4296a6f5e2d374b196bc6c |
|
10-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0d53826f3653a789cf1491c3c40a1f4a993992b6 |
|
08-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d41b30def3181bce4bf87e8bde664d15663165d0 |
|
05-Nov-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Unbreak VC++ build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 15092547e495c6d01a9aeb6d16c527d92c859749 |
|
03-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
silence warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 07e4b00a1a2d28985307c0e04e7508879b4ca270 |
|
16-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
SelectScalarSSELoad should call CanBeFoldedBy as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 27e1fe9dab89388dfcb3985128d000e632fdc5f6 |
|
14-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Corrected load folding check. We need to start from the root of the sub-dag
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
|
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 494cec6e5888ee8dc697f95f0806813fb0f08a57 |
|
12-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Doh. This wasn't causing problems by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f78ae9eb8ac39ac5ad99e749152887d168b0ceaa |
|
12-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
fix compilation failure of smg2000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4fe4f254ce677e49448ab22cf83a25729e5b9634 |
|
12-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 82a9164fb4b86164b642d76584a6efdc8bafccca |
|
11-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a275ecbd10b95878dd25333843cdd19e714c3640 |
|
10-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
More isel time load folding checking for nodes that produce flag values.
See comment in CanBeFoldedBy() for detailed explanation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 466685d41a9ea4905b9486fea38e83802e46f196 |
|
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3a7cd951c12dfafa9c182b2a027a283c63cdb4d0 |
|
07-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
completely disable folding of loads into scalar sse instructions and provide
a framework for doing it right. This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.
Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 71f84de79b824d2b3c3c6fa1ce6627540b79671e |
|
30-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bcb9770efe409f3291ce21269904744e7bf3397b |
|
17-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Added some eye-candy for Subtarget type checking
Added X86 StdCall & FastCall calling conventions. Codegen will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c45a2c72ccf57e84a18beb898740fe5b8fe0d2c8 |
|
15-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove a unnecessary check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0f27fc34f7e6f12069527b209127424416d941f3 |
|
13-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a regression in the 32-bit port from the 64-bit port landing.
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c356a572e34131bf767f35e3fecefae36fab744a |
|
12-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects MachineConstantPoolEntry changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 1453de5aa93c48779e1a5cdedec6e1493f6988eb |
|
02-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen.
Suppose the TokenFactor can reach the Op:
[Load chain]
^
|
[Load]
^ ^
| |
/ \-
/ |
/ [Op]
/ ^ ^
| .. |
| / |
[TokenFactor] |
^ |
| |
\ /
\ /
[Store]
If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4a888584eaa61a12505baa2e70152f9b76f6bb27 |
|
29-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 780413d4622e3977227c8e11ef27ba53bdee0d94 |
|
29-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't performance load/op/store transformation if op produces a floating point
or vector result. X86 does not have load/mod/store variants of those
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29957 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e50794adda9256d6fe2f378c01ee3c44e1fbd86c |
|
29-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Enable x86 isel preprocessing by default unless -fast is specified.
- Also disable isel load folding if -fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 82a35b34fbf66acc18b9e2d6b46604a3e9a8a2c9 |
|
29-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Avoid making unneeded load/mod/store transformation which can hurt performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 70e674e95e73c33e747b2c0d97a40e3b06d163de |
|
28-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a4f0b3a084d120cfc5b5bb06f64b222f5cb72740 |
|
27-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0b828e08f94459ac0046b864871d92fed4aaef7c |
|
27-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 95514bae7309ffacfc0a79b267159dcfde2b7720 |
|
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
SelectNodeTo now returns a SDNode*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9ade218533429146731213eacb7e12060e65ff58 |
|
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Select() no longer require Result operand by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0469990e790b6947bf3d9e5c84586d7e082185d9 |
|
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblgen changes; clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| eb8730d131be888ba93f7dfc2e5457375190107e |
|
17-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 23329f5e0366af7cd9a96572ed8d6322696e5846 |
|
16-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
SelectNodeTo() may return a SDOperand that is different from the input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 64a752f7c7cf160f2887d0a16d5922359832c9c2 |
|
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f4b4c416d361e0f4523200a60d5fc290da1e8319 |
|
08-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate reachability matrix. It has to be calculated before any instruction
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29559 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2ef88a09b71f458ad415b35a1fb431c3d15d7eb1 |
|
08-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen isel changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4876dc5b137a19039182bd4cfe2100917cbd468f |
|
03-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflect change to AssignTopologicalOrder().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 686c4a18f1e9f1decdb2d95a2d0f6bf925d55d93 |
|
02-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use of vector<bool> causes some horrendous compile time regression (2x)!
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| db3cc3d7d663a8dc2063d1bb581851e5e66f269d |
|
01-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Factor topological order code to SelectionDAG. Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 37e1803a66a56593efef9df306a3ed437a2bb80c |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Can't spell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ba27731f35d60f8fa9959d346b4336d0d00a9ccb |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Some clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f2dfafcbc1026b22442acbcddebf4039e4354918 |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename IsFoldableBy to CanBeFoldedleBy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2584d93acf7cdfabc815a6bbc5597e4dd46d8f2c |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Node selected into address mode cannot be folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 63ce5682e29f62d5c779e54a6362ba8ff038d350 |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Another duh. Determine topological order before any target node is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0e2c36fcc22be3435b2aa5b0e0b1824a2b3a969e |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Brain cramp..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b3c334674ddf4671c22d750a612e91e481a33ac8 |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Allocating too large an array for ReachibilityMatrix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5fa5de80e21a49f9f2be8a22a9e12443321fc812 |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Calculate the portion of reachbility matrix on demand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8cbc93aadbf88cdfc5aab865c71d34bb11241245 |
|
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
isNonImmUse is replaced by IsFoldableBy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a8df1b4296470de77426cb781ae53691d2811f5f |
|
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use reachbility information to determine whether a node can be folded into another during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2c79de8018bb8c77a245d4ccb740affbf1f52319 |
|
29-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Hide x86 symbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28976 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c0bad5706eff2dec7304b9266657ffdded0628d9 |
|
08-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for "m" inline asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3649b0efa5e663aba9596a0225c34f82de1d95b7 |
|
03-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Cygwin support. Patch by Anton Korobeynikov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| aede9b9598a49da48478c889a8f4412a8b32bcf4 |
|
02-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use xor to clear a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| eaf1e3177518d2eaaf636b0e4ace8c60c794c72c |
|
30-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove bogus comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e6ad27e9173e15e4954d96ef3b1e8efa6c032d87 |
|
30-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
A addressing mode folding enhancement:
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
return (x << 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6a3d5a62f09d4093468525a07a0143cae0e9df41 |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Assert if InflightSet is not cleared after instruction selecting a BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| afe358e7d46da9d29ba02fbbf81bdfb4ac4a4520 |
|
24-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3c380e71e1de8c6adfb428e86aca0899e8906838 |
|
21-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Back out indirect branch load folding hack. It broke some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 4f7f71de43f2b9981e6e9df97f7b4f296b31a69f |
|
20-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use of load's chain result should be redirected to load's chain operand.
If it reads the chain result of the call, then the use, callseq_start,
and call would form a cycle!
- Don't forget handle node replacement!
- There could also be a TokenFactor between the load and the callseq_start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 6b2e254437589d705c704d1f4b7643443dc16a6b |
|
20-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Missing break statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fb914c43bae0f75743b3a84ae1add4c0060ef0f5 |
|
20-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove unused patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b245d92328a7ad050a7ee099de99da8f249b2a91 |
|
20-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle indirect call which folds a load manually. This never matches by
the TableGen generated code since the load's chain result is read by
the callseq_start node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 069287d460321af43b7c88b816da5c778e5f46d1 |
|
16-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0bbac9ffd17280baa780e248911d4cd05870536b |
|
12-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 403be7eafc8922c20d7e8253bc8d6d0abd0448cb |
|
08-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8f7f7125e95e4fce29a4b8acbc88f708e7fae42f |
|
05-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Better implementation of truncate. ISel matches it to a pseudo instruction
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 420736dc85c01702bb7bc40495f8a4be5e5f8a6c |
|
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
#include Intrinsics.h into all dag isels
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c4c6257c1a154279bf10e9498d46d6c1793dbaa7 |
|
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8c03fe4acaef1a797047ec370da7fbc5d723db3e |
|
28-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't match x << 1 to LEAL. It's better to emit x + x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 51a9ed9b41c881bd485ce76834352eb82c38ee5b |
|
25-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 020d2e8e7aa36692af13c1215fdd6248a6d9e950 |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a0ea0539e359f6d82218e5aa4cdf3b50b17d6fbd |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 224ec39cab5298cfd196c0b5d2ac4825f8e2ab12 |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 codegen tweak to use lea in another case:
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7ccced634ae0ecdc1c4f599fd3abf188c367e231 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 / Darwin PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2486af1b53615288e7b884cbb7501d7b957c3af7 |
|
11-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Prevent certain nodes that have already been selected from being folded into
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 23addc061c63cd4df6674548d3152e597f286a0a |
|
10-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Nicer code. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f597dc78f818a226fa7760286e053fc966c593f3 |
|
10-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added X86 isel debugging stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7d82d607c566b7a5465586f8143e6f889d104b37 |
|
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblgen change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7e9b26fc73425ae215fbc9c8010cb53059a93b3a |
|
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 34167215a8da717b21e44f1b834dc34d15279bf1 |
|
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 5e35168b11e2ca083308f93876daa0f1d795158a |
|
06-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Update load folding checks to match those auto-generated by tblgen.
- Manually select SDOperand's returned by TryFoldLoad which make up the
load address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ba2f0a9ee53512ce840aca34281e126802a125d1 |
|
05-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use SelectRoot() as entry of any tblgen based isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7dd281b3e5b53390ccf3a689ef8a4397210ef75d |
|
05-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit the last bit of change that was backed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b46ef676794879efc4b79fb36ec606d0ceb83f42 |
|
04-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Temporarily revert this patch, which probably breaks with the
tblgen patch reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 9c4815a0362575bcd207619188156b5fad73c2bc |
|
04-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Complex pattern's custom matcher should not call Select() on any operands.
Select them afterwards if it returns true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 223547ab3101f32252cb704a67bd757e00fdbd16 |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
- Use XORP* to implement fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 559806f575297866609c7bef0e5c1084dcdda9a5 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 2c2c6c61f100bc7c3df873b11203fcea1b5e18fe |
|
23-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add explicit #includes of <iostream>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d9c45e9af96c3ec5d8228b05908d1465cb3fdbea |
|
19-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Didn't mean to check that in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b7b5706340785a97d4c59559adba1a8784d8102d |
|
19-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
A obvious typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0cc3945efe8702c1244a31d2d355b4b64e25a8b7 |
|
16-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix FP_TO_INT**_IN_MEM lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e112552b5a5c1086aeabe590ab651cbf1178393f |
|
15-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b47fad9892a2b73252b05aa809b2de1af89a1d3d |
|
14-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
silence a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 38262cad0a13d1b7f4daa2422072da8f97545d26 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Select DYNAMIC_STACKALLOC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8700e14ba10abeef4a8a2cf396e5e98ff81b9de3 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Add special entry code main() (to set x87 to 64-bit precision).
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 92cb0af6754b0d20b9eda4b459a5a27578bfd9ae |
|
11-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
implement FP_REG_KILL insertion for the dag-dag instruction selector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| a2b694ce3522eb8ebe60748dd5021b27472fc68f |
|
11-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fit into 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| aaca22ca918585173f55e926bc050fb0696fc28b |
|
10-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
FP_TO_INT*_IN_MEM and x87 FP Select support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 510e478098aa939044959aed6770a3f17bff303e |
|
10-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Added undef patterns.
* Some reorg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 948f343a2f3ec8fc75401ea2465262dd7f43edf7 |
|
07-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Added integer div / rem.
* Fixed a load folding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 0114e949034dd3032599799fda9dc9d62aa60088 |
|
06-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
ISEL code for MULHU, MULHS, and UNDEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| da95a84a11e684072ea25fbb9830e769039fd985 |
|
06-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
fold (shl x, 1) -> (add x, x)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 650d688db671068a9cd8cd66dbc30c5c4810a025 |
|
05-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added ConstantFP patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| d90eb7fb2435e2abedb4694edc44fa45642edbe9 |
|
05-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
DAG based isel call support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 3a03ebb37747c2b3fd9b4f8b44f1124f53727894 |
|
22-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 8263c5e9209760146e3f28b632431c2373dd343f |
|
21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Remove ISD::RET select code. Now tblgen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b077b842b64af39c8e2e9aaad327b3be446790dd |
|
21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added lowering hook for external weak global address. It inserts a load
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| fcaa9957c9181e1de8c82f2cd808e3c457acc7ba |
|
19-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
It's essential we clear CodeGenMap after isel every basic block!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24867 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bdce7b4090b59f650933896b9db36638c5a58dd4 |
|
17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Darwin API issue: indirect load of external and weak symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 45f37bc5275762ea61d680a040fa36f06468ffc7 |
|
17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added truncate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| aed7c721dfd6a3a27d07f582cb0057e64385ba45 |
|
17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added support for cmp, test, and conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cb17bac3a39546a186e0b0eb53b5916dff54c564 |
|
15-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| def941b41ff41cfb92ada3f217f9f194659de642 |
|
15-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Handling zero extension of 1 bit value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| e5280536a3b9f7169b3a5ef3460c8ee4bd324709 |
|
12-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
base or index operands being selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| cbd6ed4d6bd4b48a4344691ad60d441382f85b37 |
|
12-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| b51a059b2c47b91a66230ce53410303bacb79a69 |
|
10-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added X86 store patterns.
* Added X86 dec patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| ec693f77c03f5511001bfcac8180de6b551f7b1d |
|
08-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added intelligence to X86 LEA addressing mode matching routine so it returns
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 640f299b44a35ed628a58f9c0c948067d629aa0c |
|
01-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Proper support for shifts with register shift value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24559 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 350d22e14d889e5874a9465d2a4c724c6e91dadb |
|
30-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
SelectNodeTo now returns its result, we must pay attention to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| bd3d25c6b1fb60f72122d2f87c16135c683c356f |
|
30-Nov-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added support to STORE and shifts to DAG to DAG isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| f9ce9fb49bebe48c55b3f373c95393ce9257f3f9 |
|
19-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add load and other support to the dag-dag isel. Patch contributed by Evan
Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| 7a125378439bb51a57e552915c261ce5ede282f8 |
|
16-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add patterns for several simple instructions that take i32 immediates.
Patch contributed by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|
| c961eea6cb8d0a2d75fa074832f5c797f90330ef |
|
16-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
|