| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| faf1415c4fa88b6233bca488b8ac3bb8e6a73c72 |
|
24-Oct-2013 |
Yaron Keren <yaron.keren@gmail.com> |
(this is a corrected patch)
Calling _chkstk is required on ELF as well as COFF on Windows. Without
_chkstk, functions requiring large stack crash in initialization code.
Previous code tested for COFF format but not Mach-O and this patch modifies
the code to test for Windows OS (both Windows target and MingW target)
but not Mach-O object format: Looks like macho environment was used to
build some EFI code.
Credits to Andrew MacPherson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 615f561407c83e29356f34c057279e87d903c9f1 |
|
23-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Calling _chkstk is required on ELF as well as COFF on Windows. Without _chkstk functions requiring large stack crash in initialization code. Previous code tested for COFF format but not Mach-O and this patch modifies the code to test for Windows."
This reverts commit r193263.
It is causing CodeGen/X86/mingw-alloca.ll to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1e0437804c084dabda8894508f5867fdfb4df915 |
|
23-Oct-2013 |
Yaron Keren <yaron.keren@gmail.com> |
Calling _chkstk is required on ELF as well as COFF on Windows.
Without _chkstk functions requiring large stack crash in
initialization code. Previous code tested for COFF format but
not Mach-O and this patch modifies the code to test for Windows.
Credits to Andrew MacPherson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6a7770b7ae43d784dec6f4d3c73ffed6166f3882 |
|
16-Oct-2013 |
Andrew Trick <atrick@apple.com> |
Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.
Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.
On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.
Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.
The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.
Unit tests are updated so they don't depend on SD scheduling heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 4da61345ec553a4f3ab3cedf6f21452374f1fda1 |
|
24-Sep-2013 |
Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> |
Adding a feature flag to the llvm backend for x86 TBM instruction set.
Adding TBM feature to bdver2 processor; piledriver supports this instruction set
according to the following document:
http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 94dc6540a8f3aaadb43dda50e49fc79141fae8ed |
|
13-Sep-2013 |
Preston Gurd <preston.gurd@intel.com> |
Adds support for Atom Silvermont (SLM) - -march=slm
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.
Auto detects SLM.
Turns on post RA scheduler when generating code for SLM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f |
|
12-Sep-2013 |
Ben Langmuir <ben.langmuir@intel.com> |
Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 441c557708b5dbe91f1799baf790ad418c23ea70 |
|
29-Aug-2013 |
Cameron Esfahani <dirty@apple.com> |
Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6a15b6a269e79a8382348812ac32221fdc25b7ca |
|
28-Aug-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
X86Subtarget.h: Recognize x86_64-cygwin.
In the LLVM side, x86_64-cygwin is almost as same as x86_64-mingw32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 33b5fe7f160886a0718e8cad4ac0d896d5d5c46f |
|
21-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e3809eed34f000581a464689596eefde2a6d1f24 |
|
24-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ac226bbf457f6b5e5210a4a82b1ce678298b2d89 |
|
12-Jul-2013 |
Charles Davis <cdavis5x@gmail.com> |
Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.
Summary:
This patch adds explicit calling convention types for the Win64 and
System V/x86-64 ABIs. This allows code to override the default, and use
the Win64 convention on a target that wants to use SysV (and
vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU
attributes.
Reviewers:
CC:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| b2b5dc642cbbe781f73b9da83874d4005c50bd8e |
|
25-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Revert "Temporarily enable MI-Sched on X86."
This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 98a9b72e8c56dc13a2617de84503a3d78352789c |
|
24-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d6ac8e9a03d8fa7115079d86192bc4529e8281aa |
|
25-Apr-2013 |
Preston Gurd <preston.gurd@intel.com> |
This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c26392aa5d9c2dbca2909d6874d181455f8aeb8f |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1edadea42f6f5c393b4fdb9d7ce1cf7eb9c24ab4 |
|
27-Mar-2013 |
Preston Gurd <preston.gurd@intel.com> |
For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.
This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.
Patch by Sriram Murali.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0ca1a7f177ffd29c0af49f23cc7bd5f0b56a60d0 |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add HLE target feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 675eb3b9ac547119f6db676ebdd172d40a797b1c |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 901d80065c9afa0ba33e8546c2e1e99a00aceb14 |
|
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget so that they can be reset with the new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ba6867d0ce3de9b7b4385f98d215edfcd36c4b32 |
|
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Temporary revert of 175320.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 9be8b4fc92e1ace819a78db512c1f945c1471be7 |
|
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 789cb5df9ca61f8a3794a4fbde7cc020fd00a02a |
|
15-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.
If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 7b672ed380cf44894f8b96c52558dcfc136af383 |
|
14-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a5597f0eaf1f93c6d0bc641a0cc54ecffb33955a |
|
25-Jan-2013 |
Eli Bendersky <eliben@google.com> |
In this patch, we teach X86_64TargetMachine that it has a ILP32
(defined by the x32 ABI) mode, in which case its pointers are 32-bits
in size. This knowledge is also added to X86RegisterInfo that now
returns the appropriate registers in getPointerRegClass.
There are many outcomes to this change. In order to keep the patches
separate and manageable, we start by focusing on some simple testable
cases. The patch adds a test with passing a pointer to a function -
focusing on the difference between the two data models for x86-64.
Another test is added for handling of 'sret' arguments (and
functionality is added in X86ISelLowering to make it work).
A note on naming: the "x32 ABI" document refers to the AMD64
architecture (in LLVM it's distinguished by being is64Bits() in the
x86 subtarget) with two variations: the LP64 (default) data model, and
the ILP32 data model. This patch adds predicates to the subtarget
which are consistent with this naming scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c7b902e7fe3498503efbfd98cabb1b1c67cadda6 |
|
08-Jan-2013 |
Preston Gurd <preston.gurd@intel.com> |
Pad Short Functions for Intel Atom
The current Intel Atom microarchitecture has a feature whereby
when a function returns early then it is slightly faster to execute
a sequence of NOP instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction until
the return address is ready.
When compiling for X86 Atom only, this patch will run a pass,
called "X86PadShortFunction" which will add NOP instructions where less
than four cycles elapse between function entry and return.
It includes tests.
This patch has been updated to address Nadav's review comments
- Optimize only at >= O1 and don't do optimization if -Os is set
- Stores MachineBasicBlock* instead of BBNum
- Uses DenseMap instead of std::map
- Fixes placement of braces
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 5d1f5c17377e56d88a525cf82d02e6e5df254580 |
|
05-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Revert revision 171524. Original message:
URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev
Log:
The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP
instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction
until the return address is ready.
When compiling for X86 Atom only, this patch will run a pass, called
"X86PadShortFunction" which will add NOP instructions where less than four
cycles elapse between function entry and return.
It includes tests.
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| dd30b471750aca5c652873f9a8972df162b7e5eb |
|
04-Jan-2013 |
Preston Gurd <preston.gurd@intel.com> |
The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP
instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction
until the return address is ready.
When compiling for X86 Atom only, this patch will run a pass, called
"X86PadShortFunction" which will add NOP instructions where less than four
cycles elapse between function entry and return.
It includes tests.
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| f659c0de6c7a4684a2a30c344ce6827ea87032d8 |
|
04-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Make NaCl naming consistent. The triple OSType is called NaCl and is represented
textually as NativeClient. Also added a link to the native client project for
readers unfamiliar with it.
A Clang patch will follow shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a1514e24cc24b050f53a12650e047799358833a1 |
|
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 8564dc67b5840da1633e29bade33185f4a36bb2d |
|
29-Nov-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in X86IselLowering.cpp.
The logic was not changed, only names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
|
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 39817f9d393fdc29ec35fc8626d8b372415df414 |
|
08-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: remove the unused getSpecialAddressLatency hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 7bbd6e366b39157445cc921024a987e61ea68c00 |
|
02-Oct-2012 |
Andrew Kaylor <andrew.kaylor@intel.com> |
Support for generating ELF objects on Windows.
This adds 'elf' as a recognized target triple environment value and overrides the default generated object format on Windows platforms if that value is present. This patch also enables MCJIT tests on Windows using the new environment value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d48bb9316ddaacb695d896a67f35fef024a0b76a |
|
26-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove hasNoAVX method. Can just invert hasAVX instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 2e2efd960056bbb7e4bbd843c8de55116d52aa7d |
|
04-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder, or both.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a03c44117b83b745068385625b4d30e73b4e113c |
|
30-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0e292376d09223d791ed2ccc8935e98cbd36f1f8 |
|
24-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Custom lower FMA intrinsics to target specific nodes and remove the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 9b54141cae0d3f429c414f28cd8c3dc1e819eb92 |
|
23-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Favor FMA3 over FMA4 if both are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a20e1e7ef596842127794372244fd5c646f71296 |
|
01-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a15f9d53114a86005b260cbc451b0c63aa92bc1d |
|
03-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c8e340da823e8ff10b947429ef99e34ffc3067d8 |
|
31-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Rename the CLMUL target feature to PCLMUL.
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
|
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 44de83a7f6c814cf534b2bb58042035a778da5a8 |
|
19-Feb-2012 |
Jia Liu <proljc@gmail.com> |
some comment fix for X86 and ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| de1df103b9c578d0a1609054a5944342c5d0ba23 |
|
07-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 69f44692bf5fea1d908fc06487e173837d06ea58 |
|
05-Feb-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Begin fleshing out more convenience predicates in llvm::Triple and
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.
This round of predicates is focused on OS-categorization predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 922d314e8f9f0d8e447c055485a2969ee9cf2dd2 |
|
02-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1accb7ed98d823c291a4d5df172d0538451aba9e |
|
10-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d0a31177684eddd44eedb05839195820e84a9b54 |
|
10-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c6d59954d8b4bc63aa8e6333d902a3fffc774189 |
|
10-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 16de4632bb263d7e0def43ebc13af5077726f067 |
|
09-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 85abb2700d7791bcfa022fe8765df72929256d20 |
|
09-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove hasSSE1orAVX(). It's the same as hasXMM().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 2f435511e98299f61093b46e479dfdb5a904a066 |
|
08-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ce25d26b400d25c9e20ac9fe2d5b0cafb9d7fa15 |
|
02-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Add XOP feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c0d82857e095de15b31b0d654856aebea60dd339 |
|
22-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e7b05504faa86a5c0b80a62ddb60cbb0cf163d5d |
|
30-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 928698b14e4bcd0f231dc28e246920a242d81fc1 |
|
18-Oct-2011 |
David Meyer <pdox@google.com> |
Remove NaClMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 909652f6876a97d63db20606cd1b37e95d016caf |
|
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1203fe7fc80d0fe16a30ae3ddb9b0823b17f39ce |
|
13-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141854 because it was causing failures:
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 8ab1d1e900a5346db019b6a038e3f497bcfb506e |
|
13-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 37f2167f15608ff56d202ff21954a456aab6e534 |
|
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 LZCNT instruction. Including instruction selection support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| da394041c409cb06008e60b9f9f845e845215b03 |
|
09-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 581fe82c84839f769a7275cf4cde7ea209f5ed04 |
|
03-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1fac6b50ea720d75fc2bf01a288e99f239869e90 |
|
05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 43f51aeca8367ea35adad963c00bd2bc5b8d1391 |
|
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e3345c4e4a9d9afe43bad24d287d44baa1a5dc9a |
|
20-Jul-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 4d1a8dde2d9eea508f66d51428b4f155fa6a6756 |
|
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Restore old behavior. Always auto-detect features unless cpu or features are specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 18fb1d35db9e2160be3a5bd2950f7e0d206bdbb8 |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 385e930d55f3ecd3c9538823dfa5896a12461845 |
|
02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
|
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ef41ff618f2537539b538e6c7bf471c753391f92 |
|
23-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetOptions.h dependency from X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 912225e18559a73228099330a4c253fdccf9fa3d |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 2cf711f1e69dc1d00d57814478c8eb12d97ce3a8 |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/X86: Eliminate uses of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 24cfd06d031da285286a330c1fbc61127643dd2d |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/X86: Add getTargetTriple() accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 4c3ab58c4766bb48526523b000fa54186c97877e |
|
22-Feb-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Stack alignment is 16 bytes on FreeBSD/i386 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 7331ca853af405460960d7cc07f48fd01fb58acf |
|
21-Feb-2011 |
Duncan Sands <baldrick@free.fr> |
The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6904f05e607b6bbdfa96a2ebb628ebf3a1f21455 |
|
17-Feb-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e310b3a2a32d356f3f890fb138b1694b53d15f4e |
|
17-Feb-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 2bffee2ee725047137d2523e31db9ecc7b246cbb |
|
01-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Patches to build EFI with Clang/LLVM. By Carl Norum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 2ea8ee7c76b8d8754d81072e691caf25d23289e3 |
|
10-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1292c226458b68a119d3a387a0527f453b2065c2 |
|
04-Dec-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add patterns for the x86 popcnt instruction.
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
supports SSE4.2 (nehalem) or SSE4A (barcelona).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0febc4657b0edbf16b55ca5365d2b6aab45be7c5 |
|
03-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| cd458be04761f4a4dfb0881847a2acb4dc2d0609 |
|
18-Sep-2010 |
NAKAMURA Takumi <geek4civic@gmail.com> |
X86Subtarget.h: Fix Cygwin's TD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ace53f2fbc65f1e26c084c733ffbdbe3516580a6 |
|
03-Sep-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| cdae7e8244e37f539a5f1c9b780de7817b40de52 |
|
23-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add x86 CLMUL (Carry-less multiplication) cpu feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 62f35a2c133cd7de818dfc366a393282f01b111c |
|
05-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Have the X86 backend use Triple instead of a string and some enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 4d3d6e1a0c99e2212953a90185a8d027c595bf5a |
|
27-May-2010 |
Dan Gohman <gohman@apple.com> |
FastISel doesn't yet handle callee-pop functions.
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 2bce5f4b56ac0ea8e452a79e13abba1deca9b7b6 |
|
28-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable i16 to i32 promotion by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 5528e7bcb1209094a68bbf6d1efeefc3ca34774f |
|
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6d1cd1cd04abb1828a14980e15252985c8c728b2 |
|
02-Apr-2010 |
Eric Christopher <echristo@apple.com> |
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 48c58bb8610cd475d1acb073694e0d2b4dd7cc8c |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Nehalem unaligned memory access is fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| bdc652bab899d86f2181ed30caf689e43237ffb3 |
|
18-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Turning off post-ra scheduling for x86. It isn't a consistent win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 314a11318404569efaee74b7208d4b8ab1f64510 |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add support for pentium class CPUs which do not have cmov,
PR4841. Patch by Craig Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 5d96eb867196d8e0b70266fb5eebd9b754c90d9b |
|
28-Feb-2010 |
Mikhail Glushenkov <foldr@codedgers.com> |
80-col violations/trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ebb0c2b2874e38918e6af07fcafe296c3a5666c5 |
|
12-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Setup correct data layout to match gcc's expectations on mingw32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 990c4b87e37d394565a2e1a207ecac69b90fd90a |
|
12-Jan-2010 |
Duncan Sands <baldrick@free.fr> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e2de606e0b1c061ed88fa144d1ab503c52200f33 |
|
12-Jan-2010 |
Duncan Sands <baldrick@free.fr> |
Tweak commit 91745, which changed target data for both Mingw and Cygwin,
to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size. Patch by Aaron Gray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 95eb2eeea65fbae223ffd517f3984f14b034fcb8 |
|
11-Jan-2010 |
David Greene <greened@obbligato.org> |
Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| b1f49813334278094b1ecd7ad920f5c276f7b3e6 |
|
22-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e9ec6ad1ba5fd9ad70f5d0c059c5a5aa44f501f7 |
|
19-Dec-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Bump alignment requirements for windows targets to achieve compartibility with vcpp.
Based on patch by Michael Beck!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 400073d5467b79534d8c63b0d996a55e4252ff4b |
|
18-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
On recent Intel u-arch's, folding loads into some unary SSE instructions can
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
|
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 |
|
13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0855dee564f80160abf95497475306af38ab7f84 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 59a9178fbedb88427c8ff9e5fa7a8f2038f80a2e |
|
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
indicate what the native integer types for the target are.
Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| c869d063d47c382eb5574cdfa3a1666bde48d0a2 |
|
23-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
X86 needs critical path anti-dependency breaking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 4c3715c2e5e17d7216a96ac2baf9720630f04408 |
|
23-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d36076e4a3a57f55c044cd1cf21a39abe1edf2de |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turn on post-alloc scheduling for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| eb6e1daa4379f5d2a27ba487cbd6c5fc8d125d71 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| fa16354e0370fe884830286923352268b036737d |
|
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 79f7400e4f98929571431f4e8c21f6ef52c63f6b |
|
15-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove X86Subtarget::IsLinux. It's no longer being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a76e3fc131792fa6a88807c3120c59c8632bfb9e |
|
16-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
rearrange X86ATTAsmPrinter::doFinalization, making a scan of
the global variable list only happen for COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 848113833fc51bdd170cdce17abe7783ca52a34a |
|
03-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Make these functions static and local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d0da6ff3ad761dc5eb00cbe32b850de7b0bf27b6 |
|
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 700841617a9cfdc08323449ab14f42513c106430 |
|
02-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Add support for modeling whether or not the processor has support for
conditional moves as a subtarget feature. This is the easy part of
PR4841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ce914b8f945bdd42126991a7fda8984681c2c067 |
|
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
change the -x86-asm-syntax=intel/att flag to be in X86TAI
instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 3be03406c9c3b2075d5ae416499af2f15f703d6f |
|
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e2c920845a407957b8ae2600feae1f4c85a0d4d0 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove the now-dead TM argument to these methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 8097b65c432c3cc39339b6bb0ead9e1e09232ff7 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make PIC vs DynamicNoPIC be explicit in PICStyles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 3b67e9ba015624a9904a41d6d0fd61cac1b02055 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 0d786dd954622b8e7981eee32e9d585ee067d9c5 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify fast isel by using ClassifyGlobalReference. This
elimiantes the last use of GVRequiresExtraLoad, so delete it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| dfed413ef6bfb05754ee5a9f3a3c7f98c764a374 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate GVRequiresRegister, replacing it with predicates we
need for other purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d392bd97c8203ab4a770dfdd0a5565ac6cd6cacd |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move some classification logic around. Now GVRequiresExtraLoad
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ed0dca6a5dfa26e63c5636eb092640159182df89 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 754b7650c20a0fa3a9df3f067dc02a0905992325 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
more complex and slow than just directly testing what we care about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e6c07b52e76b19d83338901b2e103bd8cbabd42f |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
There is only one case where GVRequiresExtraLoad returns true for calls:
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 04b304caf633a471946c59c7d313e1560c5d07a5 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| e4df756289b6d80dcfd67b9f97fd464f62fd4902 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
When in -static mode, force the PIC style to none. Doing this requires fixing
code which conflated RIPRel PIC with x86-64. Fix these to just check for X86-64
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 640a0c147795b79d28c411883d6c89d051908e39 |
|
29-Jun-2009 |
David Greene <greened@obbligato.org> |
Fix a subtarget feature bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 343dadbb368ec4de546c2cc3ffb1dac4cdbe14b9 |
|
27-Jun-2009 |
David Greene <greened@obbligato.org> |
Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| aecaa1f143b21894ab61616bdbf67e8f450dfc7a |
|
21-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 8cf5ab153d3873d8565d5433527bd0219f7b8043 |
|
26-May-2009 |
Stefanus Du Toit <stefanus.dutoit@rapidmind.com> |
Update CPU capabilities for AMD machines
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 41a024385f1220eadc48b48cb4c044a5fbc1b361 |
|
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d7f666a869966a22b0b8f9fcd5056c1d475039cc |
|
20-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Try again. Allow call to immediate address for ELF or when in static relocation mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
|
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| ccb6976a69a6e146db049fff8e6338e31c91b6f8 |
|
02-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 8749b61178228ba1fb2668034d79da1b247173d7 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 368eb2b22d014cd312e1314b678258fea2e5084b |
|
05-Dec-2008 |
Dale Johannesen <dalej@apple.com> |
Forgot a file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| f9a67a894366482cb2aa70a0e4dfeb5d76f91988 |
|
28-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Fix build with gcc-4.4: it doesn't like PICStyle
being both a namespace and a variable name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6e08738d4b1bb6c087d81bca656c24cdc1d504f8 |
|
01-Oct-2008 |
Bill Wendling <isanbard@gmail.com> |
Just don't transform this memset into "bzero" if no-builtin is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 6f287b22d2e57600b4cd5dc209d0d869e7736c0b |
|
30-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 600bf16cf7b1667f85c8531432aae0dd23d553ab |
|
05-May-2008 |
Dan Gohman <gohman@apple.com> |
Use a dedicated IsLinux flag instead of an ELFLinux TargetType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| a779a9899a5e23bd5198973f4709d66cb4bc2e64 |
|
05-May-2008 |
Dan Gohman <gohman@apple.com> |
Add AsmPrinter support for emitting a directive to declare that
the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 43b7ca15a3f5c80847e078d2201e935ffc3e0e4a |
|
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable SSE4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| b4e56d4a2bc5a18507b2d255abf75f7850f41c04 |
|
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily disabling SSE4 until we fix the encoding issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 68d599df37218452acd5a680d5360d3caaa1623c |
|
01-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Speculatively micro-optimize memory-zeroing calls on Darwin 10.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 1a979d9eab68b353208cdff87b09ff703d5bf15d |
|
22-Mar-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add convenient helper for win64 check. Simplify things slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| add251754cd18f4ef9f4eb1ead16a0c98887066e |
|
12-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| be3bf423315394f15f0c71afdaed26e5cfbcad4a |
|
07-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 63ec90a6a8e0e441a1560f4386c5b6d538ad6583 |
|
03-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
SSE 4.1 Intrinsics and detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 7ad92d81e2c2d1fe8ae89e5638fc57925d747429 |
|
02-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
darwin9 and above support aligned common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| fc05f402ea22e8a9ae465d209b65be7e857a89ff |
|
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 588af2fb99bf255c350fcfc582e475cf4840c606 |
|
07-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for having different alignment for objects on call frames.
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 29d62bebd91fbd8a79996c3983dcd567c30c112c |
|
04-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mac OS X X86-64 ABI is same as the standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 7240ae3cac925ea3cface5982d75aa19c1d7c4b7 |
|
31-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Align i64 and f64 at 8 byte on x86-64.
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 9989a65693c357809e8e131b0a4ff1285b5e968a |
|
07-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Replace 4-line function with 10-line version per review comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 27f92be8b7e83d3fe612ecf28393a9ce8334898a |
|
06-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Move lengthy conditional down 1 level per review comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| f6844ca0e4a02fae3b100db7b0c62170d05e5b53 |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mac OS X X86-64 low 4G address not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| bb1ee05253d965e0944351a21e9970c02b1aebfe |
|
11-Apr-2007 |
Bill Wendling <isanbard@gmail.com> |
Add support for our first SSSE3 instruction "pmulhrsw".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 26aa785942fa43eac68ec9a7592ab49df5d1dc57 |
|
16-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
document some subtlety
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| cb9009993b20ab41fab56518d666ba69533db4b3 |
|
16-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Instead of yet another enum indicating the "assembly language flavor",
just use the one that's in the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 7f70559bc47877bafc6dfa92b7df6b64650445fb |
|
12-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
* PIC codegen for X86/Linux has been implemented
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 317848f4a11f7fe55afdd6d90ded8444069b56fb |
|
03-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Really big cleanup.
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 2b2bc688849234b9ee5e0c8704a2984f0e9cbba3 |
|
22-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactored JIT codegen for mingw32. Now we're using standart relocation
type for distinguish JIT & non-JIT instead of "dirty" hacks :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 15fccf1d9395ccf3f60404e71dc9db029d04f910 |
|
20-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fixed dllimported symbols support during JIT'ing. JIT on mingw32
platform should be more or less workable. At least, sim is running fine
under lli :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 7784ebc239202bba4859855c3f438319144535f0 |
|
30-Nov-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out GVRequiresExtraLoad() from .h to .cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 12c49af81e370df835ca1b72cdcefcadafcede4b |
|
21-Nov-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactored *GVRequiresExtraLoad() to Subtarget method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 751c0e12dbabe90c98f1f050baea714e79c837d6 |
|
16-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| a26eb5e1a7e36521caff281da687764a0c43e428 |
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06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Still need to support -mcpu=<> or cross compilation will fail. Doh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| abc346ceda2374971513535f21cea5fcb4b7cf46 |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| b74ed07bfd3af42331b1964c24c39912610a08f4 |
|
14-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Adding dllimport, dllexport and external weak linkage types.
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 2dd538c2d27ac6ff4dbbe221a6199a1f8e12c8bc |
|
08-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
add a new value for the command line optn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 05a059d5d8d039dbbec3607b313c38fba14f972e |
|
07-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Make the x86 asm flavor part of the subtarget info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| dd842e12e1a054256314d36f3cab3d59da39fc68 |
|
04-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Add accessor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 7ccced634ae0ecdc1c4f599fd3abf188c367e231 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 / Darwin PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 18a8452f3d2cc0bbfea427b10e2c7dccc86f2188 |
|
16-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
A bit more memset / memcpy optimization.
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 259e97cc725011a3c138563d421a4654b082a64c |
|
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
* Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 559806f575297866609c7bef0e5c1084dcdda9a5 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 97c7fc351e4dd73041bc7e47c8a144216a50a648 |
|
26-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added preliminary x86 subtarget support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| d460f57d65ce7d1d0db6f0183d31eae1ecdb8788 |
|
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify the subtarget info, allow the asmwriter to do some target sensing
based on TargetType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| e5600e5509be43097e5f3b7e0f5d33305dc77630 |
|
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin,
or native Win32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| b1e1180ca0b32f37aa74d7ad703eeaf91e66c8fa |
|
01-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Use SubtargetFeatures in llc/lli.
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| 8c00f8cdc7ae0cdd18d91b3a31a70da0f78aa04f |
|
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add Subtarget support to PowerPC. Next up, using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|
| 9eb59ec548b861d6ede05b4e6dc22aabf645e665 |
|
27-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Eliminate tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| b151acadc85011961e24d98fa6ce626ea45cd074 |
|
12-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Minor changes to improve comments and fix the build on _WIN32 systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
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| fb5792f416089d8d8d0c6ee62c1f41a55d2cf75d |
|
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement Subtarget support
Implement the X86 Subtarget.
This consolidates the checks for target triple, and setting options based
on target triple into one place. This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.
This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin. Next up is to convert over the asm printers
to use this new interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22389 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.h
|